1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Samsung CSIS MIPI CSI-2 receiver driver.
4  *
5  * The Samsung CSIS IP is a MIPI CSI-2 receiver found in various NXP i.MX7 and
6  * i.MX8 SoCs. The i.MX7 features version 3.3 of the IP, while i.MX8 features
7  * version 3.6.3.
8  *
9  * Copyright (C) 2019 Linaro Ltd
10  * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. All Rights Reserved.
11  * Copyright (C) 2011 - 2013 Samsung Electronics Co., Ltd.
12  *
13  */
14 
15 #include <linux/clk.h>
16 #include <linux/debugfs.h>
17 #include <linux/delay.h>
18 #include <linux/errno.h>
19 #include <linux/interrupt.h>
20 #include <linux/io.h>
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/mutex.h>
24 #include <linux/of.h>
25 #include <linux/of_device.h>
26 #include <linux/platform_device.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/regulator/consumer.h>
29 #include <linux/reset.h>
30 #include <linux/spinlock.h>
31 
32 #include <media/v4l2-common.h>
33 #include <media/v4l2-device.h>
34 #include <media/v4l2-fwnode.h>
35 #include <media/v4l2-mc.h>
36 #include <media/v4l2-subdev.h>
37 
38 #define CSIS_DRIVER_NAME			"imx-mipi-csis"
39 
40 #define CSIS_PAD_SINK				0
41 #define CSIS_PAD_SOURCE				1
42 #define CSIS_PADS_NUM				2
43 
44 #define MIPI_CSIS_DEF_PIX_WIDTH			640
45 #define MIPI_CSIS_DEF_PIX_HEIGHT		480
46 
47 /* Register map definition */
48 
49 /* CSIS version */
50 #define MIPI_CSIS_VERSION			0x00
51 #define MIPI_CSIS_VERSION_IMX7D			0x03030505
52 #define MIPI_CSIS_VERSION_IMX8MP		0x03060301
53 
54 /* CSIS common control */
55 #define MIPI_CSIS_CMN_CTRL			0x04
56 #define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW	BIT(16)
57 #define MIPI_CSIS_CMN_CTRL_INTER_MODE		BIT(10)
58 #define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL	BIT(2)
59 #define MIPI_CSIS_CMN_CTRL_RESET		BIT(1)
60 #define MIPI_CSIS_CMN_CTRL_ENABLE		BIT(0)
61 
62 #define MIPI_CSIS_CMN_CTRL_LANE_NR_OFFSET	8
63 #define MIPI_CSIS_CMN_CTRL_LANE_NR_MASK		(3 << 8)
64 
65 /* CSIS clock control */
66 #define MIPI_CSIS_CLK_CTRL			0x08
67 #define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH3(x)	((x) << 28)
68 #define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH2(x)	((x) << 24)
69 #define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH1(x)	((x) << 20)
70 #define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH0(x)	((x) << 16)
71 #define MIPI_CSIS_CLK_CTRL_CLKGATE_EN_MSK	(0xf << 4)
72 #define MIPI_CSIS_CLK_CTRL_WCLK_SRC		BIT(0)
73 
74 /* CSIS Interrupt mask */
75 #define MIPI_CSIS_INT_MSK			0x10
76 #define MIPI_CSIS_INT_MSK_EVEN_BEFORE		BIT(31)
77 #define MIPI_CSIS_INT_MSK_EVEN_AFTER		BIT(30)
78 #define MIPI_CSIS_INT_MSK_ODD_BEFORE		BIT(29)
79 #define MIPI_CSIS_INT_MSK_ODD_AFTER		BIT(28)
80 #define MIPI_CSIS_INT_MSK_FRAME_START		BIT(24)
81 #define MIPI_CSIS_INT_MSK_FRAME_END		BIT(20)
82 #define MIPI_CSIS_INT_MSK_ERR_SOT_HS		BIT(16)
83 #define MIPI_CSIS_INT_MSK_ERR_LOST_FS		BIT(12)
84 #define MIPI_CSIS_INT_MSK_ERR_LOST_FE		BIT(8)
85 #define MIPI_CSIS_INT_MSK_ERR_OVER		BIT(4)
86 #define MIPI_CSIS_INT_MSK_ERR_WRONG_CFG		BIT(3)
87 #define MIPI_CSIS_INT_MSK_ERR_ECC		BIT(2)
88 #define MIPI_CSIS_INT_MSK_ERR_CRC		BIT(1)
89 #define MIPI_CSIS_INT_MSK_ERR_UNKNOWN		BIT(0)
90 
91 /* CSIS Interrupt source */
92 #define MIPI_CSIS_INT_SRC			0x14
93 #define MIPI_CSIS_INT_SRC_EVEN_BEFORE		BIT(31)
94 #define MIPI_CSIS_INT_SRC_EVEN_AFTER		BIT(30)
95 #define MIPI_CSIS_INT_SRC_EVEN			BIT(30)
96 #define MIPI_CSIS_INT_SRC_ODD_BEFORE		BIT(29)
97 #define MIPI_CSIS_INT_SRC_ODD_AFTER		BIT(28)
98 #define MIPI_CSIS_INT_SRC_ODD			(0x3 << 28)
99 #define MIPI_CSIS_INT_SRC_NON_IMAGE_DATA	(0xf << 28)
100 #define MIPI_CSIS_INT_SRC_FRAME_START		BIT(24)
101 #define MIPI_CSIS_INT_SRC_FRAME_END		BIT(20)
102 #define MIPI_CSIS_INT_SRC_ERR_SOT_HS		BIT(16)
103 #define MIPI_CSIS_INT_SRC_ERR_LOST_FS		BIT(12)
104 #define MIPI_CSIS_INT_SRC_ERR_LOST_FE		BIT(8)
105 #define MIPI_CSIS_INT_SRC_ERR_OVER		BIT(4)
106 #define MIPI_CSIS_INT_SRC_ERR_WRONG_CFG		BIT(3)
107 #define MIPI_CSIS_INT_SRC_ERR_ECC		BIT(2)
108 #define MIPI_CSIS_INT_SRC_ERR_CRC		BIT(1)
109 #define MIPI_CSIS_INT_SRC_ERR_UNKNOWN		BIT(0)
110 #define MIPI_CSIS_INT_SRC_ERRORS		0xfffff
111 
112 /* D-PHY status control */
113 #define MIPI_CSIS_DPHY_STATUS			0x20
114 #define MIPI_CSIS_DPHY_STATUS_ULPS_DAT		BIT(8)
115 #define MIPI_CSIS_DPHY_STATUS_STOPSTATE_DAT	BIT(4)
116 #define MIPI_CSIS_DPHY_STATUS_ULPS_CLK		BIT(1)
117 #define MIPI_CSIS_DPHY_STATUS_STOPSTATE_CLK	BIT(0)
118 
119 /* D-PHY common control */
120 #define MIPI_CSIS_DPHY_CMN_CTRL			0x24
121 #define MIPI_CSIS_DPHY_CMN_CTRL_HSSETTLE(n)	((n) << 24)
122 #define MIPI_CSIS_DPHY_CMN_CTRL_HSSETTLE_MASK	GENMASK(31, 24)
123 #define MIPI_CSIS_DPHY_CMN_CTRL_CLKSETTLE(n)	((n) << 22)
124 #define MIPI_CSIS_DPHY_CMN_CTRL_CLKSETTLE_MASK	GENMASK(23, 22)
125 #define MIPI_CSIS_DPHY_CMN_CTRL_DPDN_SWAP_CLK	BIT(6)
126 #define MIPI_CSIS_DPHY_CMN_CTRL_DPDN_SWAP_DAT	BIT(5)
127 #define MIPI_CSIS_DPHY_CMN_CTRL_ENABLE_DAT	BIT(1)
128 #define MIPI_CSIS_DPHY_CMN_CTRL_ENABLE_CLK	BIT(0)
129 #define MIPI_CSIS_DPHY_CMN_CTRL_ENABLE		(0x1f << 0)
130 
131 /* D-PHY Master and Slave Control register Low */
132 #define MIPI_CSIS_DPHY_BCTRL_L			0x30
133 #define MIPI_CSIS_DPHY_BCTRL_L_USER_DATA_PATTERN_LOW(n)		(((n) & 3U) << 30)
134 #define MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_715MV		(0 << 28)
135 #define MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_724MV		(1 << 28)
136 #define MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_733MV		(2 << 28)
137 #define MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_706MV		(3 << 28)
138 #define MIPI_CSIS_DPHY_BCTRL_L_BGR_CHOPPER_FREQ_3MHZ		(0 << 27)
139 #define MIPI_CSIS_DPHY_BCTRL_L_BGR_CHOPPER_FREQ_1_5MHZ		(1 << 27)
140 #define MIPI_CSIS_DPHY_BCTRL_L_VREG12_EXTPWR_EN_CTL		BIT(26)
141 #define MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_2V		(0 << 24)
142 #define MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_23V		(1 << 24)
143 #define MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_17V		(2 << 24)
144 #define MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_26V		(3 << 24)
145 #define MIPI_CSIS_DPHY_BCTRL_L_REG_1P2_LVL_SEL			BIT(23)
146 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_80MV		(0 << 21)
147 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_100MV		(1 << 21)
148 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_120MV		(2 << 21)
149 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_140MV		(3 << 21)
150 #define MIPI_CSIS_DPHY_BCTRL_L_VREF_SRC_SEL			BIT(20)
151 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_715MV		(0 << 18)
152 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_743MV		(1 << 18)
153 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_650MV		(2 << 18)
154 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_682MV		(3 << 18)
155 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_PULSE_REJECT		BIT(17)
156 #define MIPI_CSIS_DPHY_BCTRL_L_MSTRCLK_LP_SLEW_RATE_DOWN_0	(0 << 15)
157 #define MIPI_CSIS_DPHY_BCTRL_L_MSTRCLK_LP_SLEW_RATE_DOWN_15P	(1 << 15)
158 #define MIPI_CSIS_DPHY_BCTRL_L_MSTRCLK_LP_SLEW_RATE_DOWN_30P	(3 << 15)
159 #define MIPI_CSIS_DPHY_BCTRL_L_MSTRCLK_LP_SLEW_RATE_UP		BIT(14)
160 #define MIPI_CSIS_DPHY_BCTRL_L_LP_CD_HYS_60MV			(0 << 13)
161 #define MIPI_CSIS_DPHY_BCTRL_L_LP_CD_HYS_70MV			(1 << 13)
162 #define MIPI_CSIS_DPHY_BCTRL_L_BGR_CHOPPER_EN			BIT(12)
163 #define MIPI_CSIS_DPHY_BCTRL_L_ERRCONTENTION_LP_EN		BIT(11)
164 #define MIPI_CSIS_DPHY_BCTRL_L_TXTRIGGER_CLK_EN			BIT(10)
165 #define MIPI_CSIS_DPHY_BCTRL_L_B_DPHYCTRL(n)			(((n) * 25 / 1000000) << 0)
166 
167 /* D-PHY Master and Slave Control register High */
168 #define MIPI_CSIS_DPHY_BCTRL_H			0x34
169 /* D-PHY Slave Control register Low */
170 #define MIPI_CSIS_DPHY_SCTRL_L			0x38
171 /* D-PHY Slave Control register High */
172 #define MIPI_CSIS_DPHY_SCTRL_H			0x3c
173 
174 /* ISP Configuration register */
175 #define MIPI_CSIS_ISP_CONFIG_CH(n)		(0x40 + (n) * 0x10)
176 #define MIPI_CSIS_ISPCFG_MEM_FULL_GAP_MSK	(0xff << 24)
177 #define MIPI_CSIS_ISPCFG_MEM_FULL_GAP(x)	((x) << 24)
178 #define MIPI_CSIS_ISPCFG_PIXEL_MODE_SINGLE	(0 << 12)
179 #define MIPI_CSIS_ISPCFG_PIXEL_MODE_DUAL	(1 << 12)
180 #define MIPI_CSIS_ISPCFG_PIXEL_MODE_QUAD	(2 << 12)	/* i.MX8M[MNP] only */
181 #define MIPI_CSIS_ISPCFG_PIXEL_MASK		(3 << 12)
182 #define MIPI_CSIS_ISPCFG_ALIGN_32BIT		BIT(11)
183 #define MIPI_CSIS_ISPCFG_FMT(fmt)		((fmt) << 2)
184 #define MIPI_CSIS_ISPCFG_FMT_MASK		(0x3f << 2)
185 
186 /* ISP Image Resolution register */
187 #define MIPI_CSIS_ISP_RESOL_CH(n)		(0x44 + (n) * 0x10)
188 #define CSIS_MAX_PIX_WIDTH			0xffff
189 #define CSIS_MAX_PIX_HEIGHT			0xffff
190 
191 /* ISP SYNC register */
192 #define MIPI_CSIS_ISP_SYNC_CH(n)		(0x48 + (n) * 0x10)
193 #define MIPI_CSIS_ISP_SYNC_HSYNC_LINTV_OFFSET	18
194 #define MIPI_CSIS_ISP_SYNC_VSYNC_SINTV_OFFSET	12
195 #define MIPI_CSIS_ISP_SYNC_VSYNC_EINTV_OFFSET	0
196 
197 /* ISP shadow registers */
198 #define MIPI_CSIS_SDW_CONFIG_CH(n)		(0x80 + (n) * 0x10)
199 #define MIPI_CSIS_SDW_RESOL_CH(n)		(0x84 + (n) * 0x10)
200 #define MIPI_CSIS_SDW_SYNC_CH(n)		(0x88 + (n) * 0x10)
201 
202 /* Debug control register */
203 #define MIPI_CSIS_DBG_CTRL			0xc0
204 #define MIPI_CSIS_DBG_INTR_MSK			0xc4
205 #define MIPI_CSIS_DBG_INTR_MSK_DT_NOT_SUPPORT	BIT(25)
206 #define MIPI_CSIS_DBG_INTR_MSK_DT_IGNORE	BIT(24)
207 #define MIPI_CSIS_DBG_INTR_MSK_ERR_FRAME_SIZE	BIT(20)
208 #define MIPI_CSIS_DBG_INTR_MSK_TRUNCATED_FRAME	BIT(16)
209 #define MIPI_CSIS_DBG_INTR_MSK_EARLY_FE		BIT(12)
210 #define MIPI_CSIS_DBG_INTR_MSK_EARLY_FS		BIT(8)
211 #define MIPI_CSIS_DBG_INTR_MSK_CAM_VSYNC_FALL	BIT(4)
212 #define MIPI_CSIS_DBG_INTR_MSK_CAM_VSYNC_RISE	BIT(0)
213 #define MIPI_CSIS_DBG_INTR_SRC			0xc8
214 #define MIPI_CSIS_DBG_INTR_SRC_DT_NOT_SUPPORT	BIT(25)
215 #define MIPI_CSIS_DBG_INTR_SRC_DT_IGNORE	BIT(24)
216 #define MIPI_CSIS_DBG_INTR_SRC_ERR_FRAME_SIZE	BIT(20)
217 #define MIPI_CSIS_DBG_INTR_SRC_TRUNCATED_FRAME	BIT(16)
218 #define MIPI_CSIS_DBG_INTR_SRC_EARLY_FE		BIT(12)
219 #define MIPI_CSIS_DBG_INTR_SRC_EARLY_FS		BIT(8)
220 #define MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_FALL	BIT(4)
221 #define MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_RISE	BIT(0)
222 
223 #define MIPI_CSIS_FRAME_COUNTER_CH(n)		(0x0100 + (n) * 4)
224 
225 /* Non-image packet data buffers */
226 #define MIPI_CSIS_PKTDATA_ODD			0x2000
227 #define MIPI_CSIS_PKTDATA_EVEN			0x3000
228 #define MIPI_CSIS_PKTDATA_SIZE			SZ_4K
229 
230 #define DEFAULT_SCLK_CSIS_FREQ			166000000UL
231 
232 /* MIPI CSI-2 Data Types */
233 #define MIPI_CSI2_DATA_TYPE_YUV420_8		0x18
234 #define MIPI_CSI2_DATA_TYPE_YUV420_10		0x19
235 #define MIPI_CSI2_DATA_TYPE_LE_YUV420_8		0x1a
236 #define MIPI_CSI2_DATA_TYPE_CS_YUV420_8		0x1c
237 #define MIPI_CSI2_DATA_TYPE_CS_YUV420_10	0x1d
238 #define MIPI_CSI2_DATA_TYPE_YUV422_8		0x1e
239 #define MIPI_CSI2_DATA_TYPE_YUV422_10		0x1f
240 #define MIPI_CSI2_DATA_TYPE_RGB565		0x22
241 #define MIPI_CSI2_DATA_TYPE_RGB666		0x23
242 #define MIPI_CSI2_DATA_TYPE_RGB888		0x24
243 #define MIPI_CSI2_DATA_TYPE_RAW6		0x28
244 #define MIPI_CSI2_DATA_TYPE_RAW7		0x29
245 #define MIPI_CSI2_DATA_TYPE_RAW8		0x2a
246 #define MIPI_CSI2_DATA_TYPE_RAW10		0x2b
247 #define MIPI_CSI2_DATA_TYPE_RAW12		0x2c
248 #define MIPI_CSI2_DATA_TYPE_RAW14		0x2d
249 #define MIPI_CSI2_DATA_TYPE_USER(x)		(0x30 + (x))
250 
251 struct mipi_csis_event {
252 	bool debug;
253 	u32 mask;
254 	const char * const name;
255 	unsigned int counter;
256 };
257 
258 static const struct mipi_csis_event mipi_csis_events[] = {
259 	/* Errors */
260 	{ false, MIPI_CSIS_INT_SRC_ERR_SOT_HS,		"SOT Error" },
261 	{ false, MIPI_CSIS_INT_SRC_ERR_LOST_FS,		"Lost Frame Start Error" },
262 	{ false, MIPI_CSIS_INT_SRC_ERR_LOST_FE,		"Lost Frame End Error" },
263 	{ false, MIPI_CSIS_INT_SRC_ERR_OVER,		"FIFO Overflow Error" },
264 	{ false, MIPI_CSIS_INT_SRC_ERR_WRONG_CFG,	"Wrong Configuration Error" },
265 	{ false, MIPI_CSIS_INT_SRC_ERR_ECC,		"ECC Error" },
266 	{ false, MIPI_CSIS_INT_SRC_ERR_CRC,		"CRC Error" },
267 	{ false, MIPI_CSIS_INT_SRC_ERR_UNKNOWN,		"Unknown Error" },
268 	{ true, MIPI_CSIS_DBG_INTR_SRC_DT_NOT_SUPPORT,	"Data Type Not Supported" },
269 	{ true, MIPI_CSIS_DBG_INTR_SRC_DT_IGNORE,	"Data Type Ignored" },
270 	{ true, MIPI_CSIS_DBG_INTR_SRC_ERR_FRAME_SIZE,	"Frame Size Error" },
271 	{ true, MIPI_CSIS_DBG_INTR_SRC_TRUNCATED_FRAME,	"Truncated Frame" },
272 	{ true, MIPI_CSIS_DBG_INTR_SRC_EARLY_FE,	"Early Frame End" },
273 	{ true, MIPI_CSIS_DBG_INTR_SRC_EARLY_FS,	"Early Frame Start" },
274 	/* Non-image data receive events */
275 	{ false, MIPI_CSIS_INT_SRC_EVEN_BEFORE,		"Non-image data before even frame" },
276 	{ false, MIPI_CSIS_INT_SRC_EVEN_AFTER,		"Non-image data after even frame" },
277 	{ false, MIPI_CSIS_INT_SRC_ODD_BEFORE,		"Non-image data before odd frame" },
278 	{ false, MIPI_CSIS_INT_SRC_ODD_AFTER,		"Non-image data after odd frame" },
279 	/* Frame start/end */
280 	{ false, MIPI_CSIS_INT_SRC_FRAME_START,		"Frame Start" },
281 	{ false, MIPI_CSIS_INT_SRC_FRAME_END,		"Frame End" },
282 	{ true, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_FALL,	"VSYNC Falling Edge" },
283 	{ true, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_RISE,	"VSYNC Rising Edge" },
284 };
285 
286 #define MIPI_CSIS_NUM_EVENTS ARRAY_SIZE(mipi_csis_events)
287 
288 enum mipi_csis_clk {
289 	MIPI_CSIS_CLK_PCLK,
290 	MIPI_CSIS_CLK_WRAP,
291 	MIPI_CSIS_CLK_PHY,
292 	MIPI_CSIS_CLK_AXI,
293 };
294 
295 static const char * const mipi_csis_clk_id[] = {
296 	"pclk",
297 	"wrap",
298 	"phy",
299 	"axi",
300 };
301 
302 enum mipi_csis_version {
303 	MIPI_CSIS_V3_3,
304 	MIPI_CSIS_V3_6_3,
305 };
306 
307 struct mipi_csis_info {
308 	enum mipi_csis_version version;
309 	unsigned int num_clocks;
310 };
311 
312 struct mipi_csis_device {
313 	struct device *dev;
314 	void __iomem *regs;
315 	struct clk_bulk_data *clks;
316 	struct reset_control *mrst;
317 	struct regulator *mipi_phy_regulator;
318 	const struct mipi_csis_info *info;
319 
320 	struct v4l2_subdev sd;
321 	struct media_pad pads[CSIS_PADS_NUM];
322 	struct v4l2_async_notifier notifier;
323 	struct v4l2_subdev *src_sd;
324 
325 	struct v4l2_mbus_config_mipi_csi2 bus;
326 	u32 clk_frequency;
327 	u32 hs_settle;
328 	u32 clk_settle;
329 
330 	spinlock_t slock;	/* Protect events */
331 	struct mipi_csis_event events[MIPI_CSIS_NUM_EVENTS];
332 	struct dentry *debugfs_root;
333 	struct {
334 		bool enable;
335 		u32 hs_settle;
336 		u32 clk_settle;
337 	} debug;
338 };
339 
340 /* -----------------------------------------------------------------------------
341  * Format helpers
342  */
343 
344 struct csis_pix_format {
345 	u32 code;
346 	u32 output;
347 	u32 data_type;
348 	u8 width;
349 };
350 
351 static const struct csis_pix_format mipi_csis_formats[] = {
352 	/* YUV formats. */
353 	{
354 		.code = MEDIA_BUS_FMT_UYVY8_1X16,
355 		.output = MEDIA_BUS_FMT_UYVY8_1X16,
356 		.data_type = MIPI_CSI2_DATA_TYPE_YUV422_8,
357 		.width = 16,
358 	},
359 	/* RGB formats. */
360 	{
361 		.code = MEDIA_BUS_FMT_RGB565_1X16,
362 		.output = MEDIA_BUS_FMT_RGB565_1X16,
363 		.data_type = MIPI_CSI2_DATA_TYPE_RGB565,
364 		.width = 16,
365 	}, {
366 		.code = MEDIA_BUS_FMT_BGR888_1X24,
367 		.output = MEDIA_BUS_FMT_RGB888_1X24,
368 		.data_type = MIPI_CSI2_DATA_TYPE_RGB888,
369 		.width = 24,
370 	},
371 	/* RAW (Bayer and greyscale) formats. */
372 	{
373 		.code = MEDIA_BUS_FMT_SBGGR8_1X8,
374 		.output = MEDIA_BUS_FMT_SBGGR8_1X8,
375 		.data_type = MIPI_CSI2_DATA_TYPE_RAW8,
376 		.width = 8,
377 	}, {
378 		.code = MEDIA_BUS_FMT_SGBRG8_1X8,
379 		.output = MEDIA_BUS_FMT_SGBRG8_1X8,
380 		.data_type = MIPI_CSI2_DATA_TYPE_RAW8,
381 		.width = 8,
382 	}, {
383 		.code = MEDIA_BUS_FMT_SGRBG8_1X8,
384 		.output = MEDIA_BUS_FMT_SGRBG8_1X8,
385 		.data_type = MIPI_CSI2_DATA_TYPE_RAW8,
386 		.width = 8,
387 	}, {
388 		.code = MEDIA_BUS_FMT_SRGGB8_1X8,
389 		.output = MEDIA_BUS_FMT_SRGGB8_1X8,
390 		.data_type = MIPI_CSI2_DATA_TYPE_RAW8,
391 		.width = 8,
392 	}, {
393 		.code = MEDIA_BUS_FMT_Y8_1X8,
394 		.output = MEDIA_BUS_FMT_Y8_1X8,
395 		.data_type = MIPI_CSI2_DATA_TYPE_RAW8,
396 		.width = 8,
397 	}, {
398 		.code = MEDIA_BUS_FMT_SBGGR10_1X10,
399 		.output = MEDIA_BUS_FMT_SBGGR10_1X10,
400 		.data_type = MIPI_CSI2_DATA_TYPE_RAW10,
401 		.width = 10,
402 	}, {
403 		.code = MEDIA_BUS_FMT_SGBRG10_1X10,
404 		.output = MEDIA_BUS_FMT_SGBRG10_1X10,
405 		.data_type = MIPI_CSI2_DATA_TYPE_RAW10,
406 		.width = 10,
407 	}, {
408 		.code = MEDIA_BUS_FMT_SGRBG10_1X10,
409 		.output = MEDIA_BUS_FMT_SGRBG10_1X10,
410 		.data_type = MIPI_CSI2_DATA_TYPE_RAW10,
411 		.width = 10,
412 	}, {
413 		.code = MEDIA_BUS_FMT_SRGGB10_1X10,
414 		.output = MEDIA_BUS_FMT_SRGGB10_1X10,
415 		.data_type = MIPI_CSI2_DATA_TYPE_RAW10,
416 		.width = 10,
417 	}, {
418 		.code = MEDIA_BUS_FMT_Y10_1X10,
419 		.output = MEDIA_BUS_FMT_Y10_1X10,
420 		.data_type = MIPI_CSI2_DATA_TYPE_RAW10,
421 		.width = 10,
422 	}, {
423 		.code = MEDIA_BUS_FMT_SBGGR12_1X12,
424 		.output = MEDIA_BUS_FMT_SBGGR12_1X12,
425 		.data_type = MIPI_CSI2_DATA_TYPE_RAW12,
426 		.width = 12,
427 	}, {
428 		.code = MEDIA_BUS_FMT_SGBRG12_1X12,
429 		.output = MEDIA_BUS_FMT_SGBRG12_1X12,
430 		.data_type = MIPI_CSI2_DATA_TYPE_RAW12,
431 		.width = 12,
432 	}, {
433 		.code = MEDIA_BUS_FMT_SGRBG12_1X12,
434 		.output = MEDIA_BUS_FMT_SGRBG12_1X12,
435 		.data_type = MIPI_CSI2_DATA_TYPE_RAW12,
436 		.width = 12,
437 	}, {
438 		.code = MEDIA_BUS_FMT_SRGGB12_1X12,
439 		.output = MEDIA_BUS_FMT_SRGGB12_1X12,
440 		.data_type = MIPI_CSI2_DATA_TYPE_RAW12,
441 		.width = 12,
442 	}, {
443 		.code = MEDIA_BUS_FMT_Y12_1X12,
444 		.output = MEDIA_BUS_FMT_Y12_1X12,
445 		.data_type = MIPI_CSI2_DATA_TYPE_RAW12,
446 		.width = 12,
447 	}, {
448 		.code = MEDIA_BUS_FMT_SBGGR14_1X14,
449 		.output = MEDIA_BUS_FMT_SBGGR14_1X14,
450 		.data_type = MIPI_CSI2_DATA_TYPE_RAW14,
451 		.width = 14,
452 	}, {
453 		.code = MEDIA_BUS_FMT_SGBRG14_1X14,
454 		.output = MEDIA_BUS_FMT_SGBRG14_1X14,
455 		.data_type = MIPI_CSI2_DATA_TYPE_RAW14,
456 		.width = 14,
457 	}, {
458 		.code = MEDIA_BUS_FMT_SGRBG14_1X14,
459 		.output = MEDIA_BUS_FMT_SGRBG14_1X14,
460 		.data_type = MIPI_CSI2_DATA_TYPE_RAW14,
461 		.width = 14,
462 	}, {
463 		.code = MEDIA_BUS_FMT_SRGGB14_1X14,
464 		.output = MEDIA_BUS_FMT_SRGGB14_1X14,
465 		.data_type = MIPI_CSI2_DATA_TYPE_RAW14,
466 		.width = 14,
467 	},
468 	/* JPEG */
469 	{
470 		.code = MEDIA_BUS_FMT_JPEG_1X8,
471 		.output = MEDIA_BUS_FMT_JPEG_1X8,
472 		/*
473 		 * Map JPEG_1X8 to the RAW8 datatype.
474 		 *
475 		 * The CSI-2 specification suggests in Annex A "JPEG8 Data
476 		 * Format (informative)" to transmit JPEG data using one of the
477 		 * Data Types aimed to represent arbitrary data, such as the
478 		 * "User Defined Data Type 1" (0x30).
479 		 *
480 		 * However, when configured with a User Defined Data Type, the
481 		 * CSIS outputs data in quad pixel mode regardless of the mode
482 		 * selected in the MIPI_CSIS_ISP_CONFIG_CH register. Neither of
483 		 * the IP cores connected to the CSIS in i.MX SoCs (CSI bridge
484 		 * or ISI) support quad pixel mode, so this will never work in
485 		 * practice.
486 		 *
487 		 * Some sensors (such as the OV5640) send JPEG data using the
488 		 * RAW8 data type. This is usable and works, so map the JPEG
489 		 * format to RAW8. If the CSIS ends up being integrated in an
490 		 * SoC that can support quad pixel mode, this will have to be
491 		 * revisited.
492 		 */
493 		.data_type = MIPI_CSI2_DATA_TYPE_RAW8,
494 		.width = 8,
495 	}
496 };
497 
498 static const struct csis_pix_format *find_csis_format(u32 code)
499 {
500 	unsigned int i;
501 
502 	for (i = 0; i < ARRAY_SIZE(mipi_csis_formats); i++)
503 		if (code == mipi_csis_formats[i].code)
504 			return &mipi_csis_formats[i];
505 	return NULL;
506 }
507 
508 /* -----------------------------------------------------------------------------
509  * Hardware configuration
510  */
511 
512 static inline u32 mipi_csis_read(struct mipi_csis_device *csis, u32 reg)
513 {
514 	return readl(csis->regs + reg);
515 }
516 
517 static inline void mipi_csis_write(struct mipi_csis_device *csis, u32 reg,
518 				   u32 val)
519 {
520 	writel(val, csis->regs + reg);
521 }
522 
523 static void mipi_csis_enable_interrupts(struct mipi_csis_device *csis, bool on)
524 {
525 	mipi_csis_write(csis, MIPI_CSIS_INT_MSK, on ? 0xffffffff : 0);
526 	mipi_csis_write(csis, MIPI_CSIS_DBG_INTR_MSK, on ? 0xffffffff : 0);
527 }
528 
529 static void mipi_csis_sw_reset(struct mipi_csis_device *csis)
530 {
531 	u32 val = mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL);
532 
533 	mipi_csis_write(csis, MIPI_CSIS_CMN_CTRL,
534 			val | MIPI_CSIS_CMN_CTRL_RESET);
535 	usleep_range(10, 20);
536 }
537 
538 static void mipi_csis_system_enable(struct mipi_csis_device *csis, int on)
539 {
540 	u32 val, mask;
541 
542 	val = mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL);
543 	if (on)
544 		val |= MIPI_CSIS_CMN_CTRL_ENABLE;
545 	else
546 		val &= ~MIPI_CSIS_CMN_CTRL_ENABLE;
547 	mipi_csis_write(csis, MIPI_CSIS_CMN_CTRL, val);
548 
549 	val = mipi_csis_read(csis, MIPI_CSIS_DPHY_CMN_CTRL);
550 	val &= ~MIPI_CSIS_DPHY_CMN_CTRL_ENABLE;
551 	if (on) {
552 		mask = (1 << (csis->bus.num_data_lanes + 1)) - 1;
553 		val |= (mask & MIPI_CSIS_DPHY_CMN_CTRL_ENABLE);
554 	}
555 	mipi_csis_write(csis, MIPI_CSIS_DPHY_CMN_CTRL, val);
556 }
557 
558 static void __mipi_csis_set_format(struct mipi_csis_device *csis,
559 				   const struct v4l2_mbus_framefmt *format,
560 				   const struct csis_pix_format *csis_fmt)
561 {
562 	u32 val;
563 
564 	/* Color format */
565 	val = mipi_csis_read(csis, MIPI_CSIS_ISP_CONFIG_CH(0));
566 	val &= ~(MIPI_CSIS_ISPCFG_ALIGN_32BIT | MIPI_CSIS_ISPCFG_FMT_MASK
567 		| MIPI_CSIS_ISPCFG_PIXEL_MASK);
568 
569 	/*
570 	 * YUV 4:2:2 can be transferred with 8 or 16 bits per clock sample
571 	 * (referred to in the documentation as single and dual pixel modes
572 	 * respectively, although the 8-bit mode transfers half a pixel per
573 	 * clock sample and the 16-bit mode one pixel). While both mode work
574 	 * when the CSIS is connected to a receiver that supports either option,
575 	 * single pixel mode requires clock rates twice as high. As all SoCs
576 	 * that integrate the CSIS can operate in 16-bit bit mode, and some do
577 	 * not support 8-bit mode (this is the case of the i.MX8MP), use dual
578 	 * pixel mode unconditionally.
579 	 *
580 	 * TODO: Verify which other formats require DUAL (or QUAD) modes.
581 	 */
582 	if (csis_fmt->data_type == MIPI_CSI2_DATA_TYPE_YUV422_8)
583 		val |= MIPI_CSIS_ISPCFG_PIXEL_MODE_DUAL;
584 
585 	val |= MIPI_CSIS_ISPCFG_FMT(csis_fmt->data_type);
586 	mipi_csis_write(csis, MIPI_CSIS_ISP_CONFIG_CH(0), val);
587 
588 	/* Pixel resolution */
589 	val = format->width | (format->height << 16);
590 	mipi_csis_write(csis, MIPI_CSIS_ISP_RESOL_CH(0), val);
591 }
592 
593 static int mipi_csis_calculate_params(struct mipi_csis_device *csis,
594 				      const struct csis_pix_format *csis_fmt)
595 {
596 	s64 link_freq;
597 	u32 lane_rate;
598 
599 	/* Calculate the line rate from the pixel rate. */
600 	link_freq = v4l2_get_link_freq(csis->src_sd->ctrl_handler,
601 				       csis_fmt->width,
602 				       csis->bus.num_data_lanes * 2);
603 	if (link_freq < 0) {
604 		dev_err(csis->dev, "Unable to obtain link frequency: %d\n",
605 			(int)link_freq);
606 		return link_freq;
607 	}
608 
609 	lane_rate = link_freq * 2;
610 
611 	if (lane_rate < 80000000 || lane_rate > 1500000000) {
612 		dev_dbg(csis->dev, "Out-of-bound lane rate %u\n", lane_rate);
613 		return -EINVAL;
614 	}
615 
616 	/*
617 	 * The HSSETTLE counter value is document in a table, but can also
618 	 * easily be calculated. Hardcode the CLKSETTLE value to 0 for now
619 	 * (which is documented as corresponding to CSI-2 v0.87 to v1.00) until
620 	 * we figure out how to compute it correctly.
621 	 */
622 	csis->hs_settle = (lane_rate - 5000000) / 45000000;
623 	csis->clk_settle = 0;
624 
625 	dev_dbg(csis->dev, "lane rate %u, Tclk_settle %u, Ths_settle %u\n",
626 		lane_rate, csis->clk_settle, csis->hs_settle);
627 
628 	if (csis->debug.hs_settle < 0xff) {
629 		dev_dbg(csis->dev, "overriding Ths_settle with %u\n",
630 			csis->debug.hs_settle);
631 		csis->hs_settle = csis->debug.hs_settle;
632 	}
633 
634 	if (csis->debug.clk_settle < 4) {
635 		dev_dbg(csis->dev, "overriding Tclk_settle with %u\n",
636 			csis->debug.clk_settle);
637 		csis->clk_settle = csis->debug.clk_settle;
638 	}
639 
640 	return 0;
641 }
642 
643 static void mipi_csis_set_params(struct mipi_csis_device *csis,
644 				 const struct v4l2_mbus_framefmt *format,
645 				 const struct csis_pix_format *csis_fmt)
646 {
647 	int lanes = csis->bus.num_data_lanes;
648 	u32 val;
649 
650 	val = mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL);
651 	val &= ~MIPI_CSIS_CMN_CTRL_LANE_NR_MASK;
652 	val |= (lanes - 1) << MIPI_CSIS_CMN_CTRL_LANE_NR_OFFSET;
653 	if (csis->info->version == MIPI_CSIS_V3_3)
654 		val |= MIPI_CSIS_CMN_CTRL_INTER_MODE;
655 	mipi_csis_write(csis, MIPI_CSIS_CMN_CTRL, val);
656 
657 	__mipi_csis_set_format(csis, format, csis_fmt);
658 
659 	mipi_csis_write(csis, MIPI_CSIS_DPHY_CMN_CTRL,
660 			MIPI_CSIS_DPHY_CMN_CTRL_HSSETTLE(csis->hs_settle) |
661 			MIPI_CSIS_DPHY_CMN_CTRL_CLKSETTLE(csis->clk_settle));
662 
663 	val = (0 << MIPI_CSIS_ISP_SYNC_HSYNC_LINTV_OFFSET)
664 	    | (0 << MIPI_CSIS_ISP_SYNC_VSYNC_SINTV_OFFSET)
665 	    | (0 << MIPI_CSIS_ISP_SYNC_VSYNC_EINTV_OFFSET);
666 	mipi_csis_write(csis, MIPI_CSIS_ISP_SYNC_CH(0), val);
667 
668 	val = mipi_csis_read(csis, MIPI_CSIS_CLK_CTRL);
669 	val |= MIPI_CSIS_CLK_CTRL_WCLK_SRC;
670 	val |= MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH0(15);
671 	val &= ~MIPI_CSIS_CLK_CTRL_CLKGATE_EN_MSK;
672 	mipi_csis_write(csis, MIPI_CSIS_CLK_CTRL, val);
673 
674 	mipi_csis_write(csis, MIPI_CSIS_DPHY_BCTRL_L,
675 			MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_715MV |
676 			MIPI_CSIS_DPHY_BCTRL_L_BGR_CHOPPER_FREQ_3MHZ |
677 			MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_2V |
678 			MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_80MV |
679 			MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_715MV |
680 			MIPI_CSIS_DPHY_BCTRL_L_LP_CD_HYS_60MV |
681 			MIPI_CSIS_DPHY_BCTRL_L_B_DPHYCTRL(20000000));
682 	mipi_csis_write(csis, MIPI_CSIS_DPHY_BCTRL_H, 0);
683 
684 	/* Update the shadow register. */
685 	val = mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL);
686 	mipi_csis_write(csis, MIPI_CSIS_CMN_CTRL,
687 			val | MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW |
688 			MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL);
689 }
690 
691 static int mipi_csis_clk_enable(struct mipi_csis_device *csis)
692 {
693 	return clk_bulk_prepare_enable(csis->info->num_clocks, csis->clks);
694 }
695 
696 static void mipi_csis_clk_disable(struct mipi_csis_device *csis)
697 {
698 	clk_bulk_disable_unprepare(csis->info->num_clocks, csis->clks);
699 }
700 
701 static int mipi_csis_clk_get(struct mipi_csis_device *csis)
702 {
703 	unsigned int i;
704 	int ret;
705 
706 	csis->clks = devm_kcalloc(csis->dev, csis->info->num_clocks,
707 				  sizeof(*csis->clks), GFP_KERNEL);
708 
709 	if (!csis->clks)
710 		return -ENOMEM;
711 
712 	for (i = 0; i < csis->info->num_clocks; i++)
713 		csis->clks[i].id = mipi_csis_clk_id[i];
714 
715 	ret = devm_clk_bulk_get(csis->dev, csis->info->num_clocks,
716 				csis->clks);
717 	if (ret < 0)
718 		return ret;
719 
720 	/* Set clock rate */
721 	ret = clk_set_rate(csis->clks[MIPI_CSIS_CLK_WRAP].clk,
722 			   csis->clk_frequency);
723 	if (ret < 0)
724 		dev_err(csis->dev, "set rate=%d failed: %d\n",
725 			csis->clk_frequency, ret);
726 
727 	return ret;
728 }
729 
730 static void mipi_csis_start_stream(struct mipi_csis_device *csis,
731 				   const struct v4l2_mbus_framefmt *format,
732 				   const struct csis_pix_format *csis_fmt)
733 {
734 	mipi_csis_sw_reset(csis);
735 	mipi_csis_set_params(csis, format, csis_fmt);
736 	mipi_csis_system_enable(csis, true);
737 	mipi_csis_enable_interrupts(csis, true);
738 }
739 
740 static void mipi_csis_stop_stream(struct mipi_csis_device *csis)
741 {
742 	mipi_csis_enable_interrupts(csis, false);
743 	mipi_csis_system_enable(csis, false);
744 }
745 
746 static irqreturn_t mipi_csis_irq_handler(int irq, void *dev_id)
747 {
748 	struct mipi_csis_device *csis = dev_id;
749 	unsigned long flags;
750 	unsigned int i;
751 	u32 status;
752 	u32 dbg_status;
753 
754 	status = mipi_csis_read(csis, MIPI_CSIS_INT_SRC);
755 	dbg_status = mipi_csis_read(csis, MIPI_CSIS_DBG_INTR_SRC);
756 
757 	spin_lock_irqsave(&csis->slock, flags);
758 
759 	/* Update the event/error counters */
760 	if ((status & MIPI_CSIS_INT_SRC_ERRORS) || csis->debug.enable) {
761 		for (i = 0; i < MIPI_CSIS_NUM_EVENTS; i++) {
762 			struct mipi_csis_event *event = &csis->events[i];
763 
764 			if ((!event->debug && (status & event->mask)) ||
765 			    (event->debug && (dbg_status & event->mask)))
766 				event->counter++;
767 		}
768 	}
769 	spin_unlock_irqrestore(&csis->slock, flags);
770 
771 	mipi_csis_write(csis, MIPI_CSIS_INT_SRC, status);
772 	mipi_csis_write(csis, MIPI_CSIS_DBG_INTR_SRC, dbg_status);
773 
774 	return IRQ_HANDLED;
775 }
776 
777 /* -----------------------------------------------------------------------------
778  * PHY regulator and reset
779  */
780 
781 static int mipi_csis_phy_enable(struct mipi_csis_device *csis)
782 {
783 	if (csis->info->version != MIPI_CSIS_V3_3)
784 		return 0;
785 
786 	return regulator_enable(csis->mipi_phy_regulator);
787 }
788 
789 static int mipi_csis_phy_disable(struct mipi_csis_device *csis)
790 {
791 	if (csis->info->version != MIPI_CSIS_V3_3)
792 		return 0;
793 
794 	return regulator_disable(csis->mipi_phy_regulator);
795 }
796 
797 static void mipi_csis_phy_reset(struct mipi_csis_device *csis)
798 {
799 	if (csis->info->version != MIPI_CSIS_V3_3)
800 		return;
801 
802 	reset_control_assert(csis->mrst);
803 	msleep(20);
804 	reset_control_deassert(csis->mrst);
805 }
806 
807 static int mipi_csis_phy_init(struct mipi_csis_device *csis)
808 {
809 	if (csis->info->version != MIPI_CSIS_V3_3)
810 		return 0;
811 
812 	/* Get MIPI PHY reset and regulator. */
813 	csis->mrst = devm_reset_control_get_exclusive(csis->dev, NULL);
814 	if (IS_ERR(csis->mrst))
815 		return PTR_ERR(csis->mrst);
816 
817 	csis->mipi_phy_regulator = devm_regulator_get(csis->dev, "phy");
818 	if (IS_ERR(csis->mipi_phy_regulator))
819 		return PTR_ERR(csis->mipi_phy_regulator);
820 
821 	return regulator_set_voltage(csis->mipi_phy_regulator, 1000000,
822 				     1000000);
823 }
824 
825 /* -----------------------------------------------------------------------------
826  * Debug
827  */
828 
829 static void mipi_csis_clear_counters(struct mipi_csis_device *csis)
830 {
831 	unsigned long flags;
832 	unsigned int i;
833 
834 	spin_lock_irqsave(&csis->slock, flags);
835 	for (i = 0; i < MIPI_CSIS_NUM_EVENTS; i++)
836 		csis->events[i].counter = 0;
837 	spin_unlock_irqrestore(&csis->slock, flags);
838 }
839 
840 static void mipi_csis_log_counters(struct mipi_csis_device *csis, bool non_errors)
841 {
842 	unsigned int num_events = non_errors ? MIPI_CSIS_NUM_EVENTS
843 				: MIPI_CSIS_NUM_EVENTS - 8;
844 	unsigned long flags;
845 	unsigned int i;
846 
847 	spin_lock_irqsave(&csis->slock, flags);
848 
849 	for (i = 0; i < num_events; ++i) {
850 		if (csis->events[i].counter > 0 || csis->debug.enable)
851 			dev_info(csis->dev, "%s events: %d\n",
852 				 csis->events[i].name,
853 				 csis->events[i].counter);
854 	}
855 	spin_unlock_irqrestore(&csis->slock, flags);
856 }
857 
858 static int mipi_csis_dump_regs(struct mipi_csis_device *csis)
859 {
860 	static const struct {
861 		u32 offset;
862 		const char * const name;
863 	} registers[] = {
864 		{ MIPI_CSIS_CMN_CTRL, "CMN_CTRL" },
865 		{ MIPI_CSIS_CLK_CTRL, "CLK_CTRL" },
866 		{ MIPI_CSIS_INT_MSK, "INT_MSK" },
867 		{ MIPI_CSIS_DPHY_STATUS, "DPHY_STATUS" },
868 		{ MIPI_CSIS_DPHY_CMN_CTRL, "DPHY_CMN_CTRL" },
869 		{ MIPI_CSIS_DPHY_SCTRL_L, "DPHY_SCTRL_L" },
870 		{ MIPI_CSIS_DPHY_SCTRL_H, "DPHY_SCTRL_H" },
871 		{ MIPI_CSIS_ISP_CONFIG_CH(0), "ISP_CONFIG_CH0" },
872 		{ MIPI_CSIS_ISP_RESOL_CH(0), "ISP_RESOL_CH0" },
873 		{ MIPI_CSIS_SDW_CONFIG_CH(0), "SDW_CONFIG_CH0" },
874 		{ MIPI_CSIS_SDW_RESOL_CH(0), "SDW_RESOL_CH0" },
875 		{ MIPI_CSIS_DBG_CTRL, "DBG_CTRL" },
876 		{ MIPI_CSIS_FRAME_COUNTER_CH(0), "FRAME_COUNTER_CH0" },
877 	};
878 
879 	unsigned int i;
880 	u32 cfg;
881 
882 	if (!pm_runtime_get_if_in_use(csis->dev))
883 		return 0;
884 
885 	dev_info(csis->dev, "--- REGISTERS ---\n");
886 
887 	for (i = 0; i < ARRAY_SIZE(registers); i++) {
888 		cfg = mipi_csis_read(csis, registers[i].offset);
889 		dev_info(csis->dev, "%14s: 0x%08x\n", registers[i].name, cfg);
890 	}
891 
892 	pm_runtime_put(csis->dev);
893 
894 	return 0;
895 }
896 
897 static int mipi_csis_dump_regs_show(struct seq_file *m, void *private)
898 {
899 	struct mipi_csis_device *csis = m->private;
900 
901 	return mipi_csis_dump_regs(csis);
902 }
903 DEFINE_SHOW_ATTRIBUTE(mipi_csis_dump_regs);
904 
905 static void mipi_csis_debugfs_init(struct mipi_csis_device *csis)
906 {
907 	csis->debug.hs_settle = UINT_MAX;
908 	csis->debug.clk_settle = UINT_MAX;
909 
910 	csis->debugfs_root = debugfs_create_dir(dev_name(csis->dev), NULL);
911 
912 	debugfs_create_bool("debug_enable", 0600, csis->debugfs_root,
913 			    &csis->debug.enable);
914 	debugfs_create_file("dump_regs", 0600, csis->debugfs_root, csis,
915 			    &mipi_csis_dump_regs_fops);
916 	debugfs_create_u32("tclk_settle", 0600, csis->debugfs_root,
917 			   &csis->debug.clk_settle);
918 	debugfs_create_u32("ths_settle", 0600, csis->debugfs_root,
919 			   &csis->debug.hs_settle);
920 }
921 
922 static void mipi_csis_debugfs_exit(struct mipi_csis_device *csis)
923 {
924 	debugfs_remove_recursive(csis->debugfs_root);
925 }
926 
927 /* -----------------------------------------------------------------------------
928  * V4L2 subdev operations
929  */
930 
931 static struct mipi_csis_device *sd_to_mipi_csis_device(struct v4l2_subdev *sdev)
932 {
933 	return container_of(sdev, struct mipi_csis_device, sd);
934 }
935 
936 static int mipi_csis_s_stream(struct v4l2_subdev *sd, int enable)
937 {
938 	struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd);
939 	const struct v4l2_mbus_framefmt *format;
940 	const struct csis_pix_format *csis_fmt;
941 	struct v4l2_subdev_state *state;
942 	int ret;
943 
944 	if (!enable) {
945 		v4l2_subdev_call(csis->src_sd, video, s_stream, 0);
946 
947 		mipi_csis_stop_stream(csis);
948 		if (csis->debug.enable)
949 			mipi_csis_log_counters(csis, true);
950 
951 		pm_runtime_put(csis->dev);
952 
953 		return 0;
954 	}
955 
956 	state = v4l2_subdev_lock_and_get_active_state(sd);
957 
958 	format = v4l2_subdev_get_pad_format(sd, state, CSIS_PAD_SINK);
959 	csis_fmt = find_csis_format(format->code);
960 
961 	ret = mipi_csis_calculate_params(csis, csis_fmt);
962 	if (ret < 0)
963 		goto err_unlock;
964 
965 	mipi_csis_clear_counters(csis);
966 
967 	ret = pm_runtime_resume_and_get(csis->dev);
968 	if (ret < 0)
969 		goto err_unlock;
970 
971 	mipi_csis_start_stream(csis, format, csis_fmt);
972 
973 	ret = v4l2_subdev_call(csis->src_sd, video, s_stream, 1);
974 	if (ret < 0)
975 		goto err_stop;
976 
977 	mipi_csis_log_counters(csis, true);
978 
979 	v4l2_subdev_unlock_state(state);
980 
981 	return 0;
982 
983 err_stop:
984 	mipi_csis_stop_stream(csis);
985 	pm_runtime_put(csis->dev);
986 err_unlock:
987 	v4l2_subdev_unlock_state(state);
988 
989 	return ret;
990 }
991 
992 static int mipi_csis_enum_mbus_code(struct v4l2_subdev *sd,
993 				    struct v4l2_subdev_state *sd_state,
994 				    struct v4l2_subdev_mbus_code_enum *code)
995 {
996 	/*
997 	 * The CSIS can't transcode in any way, the source format is identical
998 	 * to the sink format.
999 	 */
1000 	if (code->pad == CSIS_PAD_SOURCE) {
1001 		struct v4l2_mbus_framefmt *fmt;
1002 
1003 		if (code->index > 0)
1004 			return -EINVAL;
1005 
1006 		fmt = v4l2_subdev_get_pad_format(sd, sd_state, code->pad);
1007 		code->code = fmt->code;
1008 		return 0;
1009 	}
1010 
1011 	if (code->pad != CSIS_PAD_SINK)
1012 		return -EINVAL;
1013 
1014 	if (code->index >= ARRAY_SIZE(mipi_csis_formats))
1015 		return -EINVAL;
1016 
1017 	code->code = mipi_csis_formats[code->index].code;
1018 
1019 	return 0;
1020 }
1021 
1022 static int mipi_csis_set_fmt(struct v4l2_subdev *sd,
1023 			     struct v4l2_subdev_state *sd_state,
1024 			     struct v4l2_subdev_format *sdformat)
1025 {
1026 	struct csis_pix_format const *csis_fmt;
1027 	struct v4l2_mbus_framefmt *fmt;
1028 	unsigned int align;
1029 
1030 	/*
1031 	 * The CSIS can't transcode in any way, the source format can't be
1032 	 * modified.
1033 	 */
1034 	if (sdformat->pad == CSIS_PAD_SOURCE)
1035 		return v4l2_subdev_get_fmt(sd, sd_state, sdformat);
1036 
1037 	if (sdformat->pad != CSIS_PAD_SINK)
1038 		return -EINVAL;
1039 
1040 	/*
1041 	 * Validate the media bus code and clamp and align the size.
1042 	 *
1043 	 * The total number of bits per line must be a multiple of 8. We thus
1044 	 * need to align the width for formats that are not multiples of 8
1045 	 * bits.
1046 	 */
1047 	csis_fmt = find_csis_format(sdformat->format.code);
1048 	if (!csis_fmt)
1049 		csis_fmt = &mipi_csis_formats[0];
1050 
1051 	switch (csis_fmt->width % 8) {
1052 	case 0:
1053 		align = 0;
1054 		break;
1055 	case 4:
1056 		align = 1;
1057 		break;
1058 	case 2:
1059 	case 6:
1060 		align = 2;
1061 		break;
1062 	default:
1063 		/* 1, 3, 5, 7 */
1064 		align = 3;
1065 		break;
1066 	}
1067 
1068 	v4l_bound_align_image(&sdformat->format.width, 1,
1069 			      CSIS_MAX_PIX_WIDTH, align,
1070 			      &sdformat->format.height, 1,
1071 			      CSIS_MAX_PIX_HEIGHT, 0, 0);
1072 
1073 	fmt = v4l2_subdev_get_pad_format(sd, sd_state, sdformat->pad);
1074 
1075 	fmt->code = csis_fmt->code;
1076 	fmt->width = sdformat->format.width;
1077 	fmt->height = sdformat->format.height;
1078 	fmt->field = V4L2_FIELD_NONE;
1079 	fmt->colorspace = sdformat->format.colorspace;
1080 	fmt->quantization = sdformat->format.quantization;
1081 	fmt->xfer_func = sdformat->format.xfer_func;
1082 	fmt->ycbcr_enc = sdformat->format.ycbcr_enc;
1083 
1084 	sdformat->format = *fmt;
1085 
1086 	/* Propagate the format from sink to source. */
1087 	fmt = v4l2_subdev_get_pad_format(sd, sd_state, CSIS_PAD_SOURCE);
1088 	*fmt = sdformat->format;
1089 
1090 	/* The format on the source pad might change due to unpacking. */
1091 	fmt->code = csis_fmt->output;
1092 
1093 	return 0;
1094 }
1095 
1096 static int mipi_csis_get_frame_desc(struct v4l2_subdev *sd, unsigned int pad,
1097 				    struct v4l2_mbus_frame_desc *fd)
1098 {
1099 	struct v4l2_mbus_frame_desc_entry *entry = &fd->entry[0];
1100 	const struct csis_pix_format *csis_fmt;
1101 	const struct v4l2_mbus_framefmt *fmt;
1102 	struct v4l2_subdev_state *state;
1103 
1104 	if (pad != CSIS_PAD_SOURCE)
1105 		return -EINVAL;
1106 
1107 	state = v4l2_subdev_lock_and_get_active_state(sd);
1108 	fmt = v4l2_subdev_get_pad_format(sd, state, CSIS_PAD_SOURCE);
1109 	csis_fmt = find_csis_format(fmt->code);
1110 	v4l2_subdev_unlock_state(state);
1111 
1112 	if (!csis_fmt)
1113 		return -EPIPE;
1114 
1115 	fd->type = V4L2_MBUS_FRAME_DESC_TYPE_PARALLEL;
1116 	fd->num_entries = 1;
1117 
1118 	memset(entry, 0, sizeof(*entry));
1119 
1120 	entry->flags = 0;
1121 	entry->pixelcode = csis_fmt->code;
1122 	entry->bus.csi2.vc = 0;
1123 	entry->bus.csi2.dt = csis_fmt->data_type;
1124 
1125 	return 0;
1126 }
1127 
1128 static int mipi_csis_init_cfg(struct v4l2_subdev *sd,
1129 			      struct v4l2_subdev_state *sd_state)
1130 {
1131 	struct v4l2_subdev_format fmt = {
1132 		.pad = CSIS_PAD_SINK,
1133 	};
1134 
1135 	fmt.format.code = mipi_csis_formats[0].code;
1136 	fmt.format.width = MIPI_CSIS_DEF_PIX_WIDTH;
1137 	fmt.format.height = MIPI_CSIS_DEF_PIX_HEIGHT;
1138 
1139 	fmt.format.colorspace = V4L2_COLORSPACE_SMPTE170M;
1140 	fmt.format.xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(fmt.format.colorspace);
1141 	fmt.format.ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(fmt.format.colorspace);
1142 	fmt.format.quantization =
1143 		V4L2_MAP_QUANTIZATION_DEFAULT(false, fmt.format.colorspace,
1144 					      fmt.format.ycbcr_enc);
1145 
1146 	return mipi_csis_set_fmt(sd, sd_state, &fmt);
1147 }
1148 
1149 static int mipi_csis_log_status(struct v4l2_subdev *sd)
1150 {
1151 	struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd);
1152 
1153 	mipi_csis_log_counters(csis, true);
1154 	if (csis->debug.enable)
1155 		mipi_csis_dump_regs(csis);
1156 
1157 	return 0;
1158 }
1159 
1160 static const struct v4l2_subdev_core_ops mipi_csis_core_ops = {
1161 	.log_status	= mipi_csis_log_status,
1162 };
1163 
1164 static const struct v4l2_subdev_video_ops mipi_csis_video_ops = {
1165 	.s_stream	= mipi_csis_s_stream,
1166 };
1167 
1168 static const struct v4l2_subdev_pad_ops mipi_csis_pad_ops = {
1169 	.init_cfg		= mipi_csis_init_cfg,
1170 	.enum_mbus_code		= mipi_csis_enum_mbus_code,
1171 	.get_fmt		= v4l2_subdev_get_fmt,
1172 	.set_fmt		= mipi_csis_set_fmt,
1173 	.get_frame_desc		= mipi_csis_get_frame_desc,
1174 };
1175 
1176 static const struct v4l2_subdev_ops mipi_csis_subdev_ops = {
1177 	.core	= &mipi_csis_core_ops,
1178 	.video	= &mipi_csis_video_ops,
1179 	.pad	= &mipi_csis_pad_ops,
1180 };
1181 
1182 /* -----------------------------------------------------------------------------
1183  * Media entity operations
1184  */
1185 
1186 static int mipi_csis_link_setup(struct media_entity *entity,
1187 				const struct media_pad *local_pad,
1188 				const struct media_pad *remote_pad, u32 flags)
1189 {
1190 	struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
1191 	struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd);
1192 	struct v4l2_subdev *remote_sd;
1193 
1194 	dev_dbg(csis->dev, "link setup %s -> %s", remote_pad->entity->name,
1195 		local_pad->entity->name);
1196 
1197 	/* We only care about the link to the source. */
1198 	if (!(local_pad->flags & MEDIA_PAD_FL_SINK))
1199 		return 0;
1200 
1201 	remote_sd = media_entity_to_v4l2_subdev(remote_pad->entity);
1202 
1203 	if (flags & MEDIA_LNK_FL_ENABLED) {
1204 		if (csis->src_sd)
1205 			return -EBUSY;
1206 
1207 		csis->src_sd = remote_sd;
1208 	} else {
1209 		csis->src_sd = NULL;
1210 	}
1211 
1212 	return 0;
1213 }
1214 
1215 static const struct media_entity_operations mipi_csis_entity_ops = {
1216 	.link_setup	= mipi_csis_link_setup,
1217 	.link_validate	= v4l2_subdev_link_validate,
1218 	.get_fwnode_pad = v4l2_subdev_get_fwnode_pad_1_to_1,
1219 };
1220 
1221 /* -----------------------------------------------------------------------------
1222  * Async subdev notifier
1223  */
1224 
1225 static struct mipi_csis_device *
1226 mipi_notifier_to_csis_state(struct v4l2_async_notifier *n)
1227 {
1228 	return container_of(n, struct mipi_csis_device, notifier);
1229 }
1230 
1231 static int mipi_csis_notify_bound(struct v4l2_async_notifier *notifier,
1232 				  struct v4l2_subdev *sd,
1233 				  struct v4l2_async_subdev *asd)
1234 {
1235 	struct mipi_csis_device *csis = mipi_notifier_to_csis_state(notifier);
1236 	struct media_pad *sink = &csis->sd.entity.pads[CSIS_PAD_SINK];
1237 
1238 	return v4l2_create_fwnode_links_to_pad(sd, sink, 0);
1239 }
1240 
1241 static const struct v4l2_async_notifier_operations mipi_csis_notify_ops = {
1242 	.bound = mipi_csis_notify_bound,
1243 };
1244 
1245 static int mipi_csis_async_register(struct mipi_csis_device *csis)
1246 {
1247 	struct v4l2_fwnode_endpoint vep = {
1248 		.bus_type = V4L2_MBUS_CSI2_DPHY,
1249 	};
1250 	struct v4l2_async_subdev *asd;
1251 	struct fwnode_handle *ep;
1252 	unsigned int i;
1253 	int ret;
1254 
1255 	v4l2_async_nf_init(&csis->notifier);
1256 
1257 	ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(csis->dev), 0, 0,
1258 					     FWNODE_GRAPH_ENDPOINT_NEXT);
1259 	if (!ep)
1260 		return -ENOTCONN;
1261 
1262 	ret = v4l2_fwnode_endpoint_parse(ep, &vep);
1263 	if (ret)
1264 		goto err_parse;
1265 
1266 	for (i = 0; i < vep.bus.mipi_csi2.num_data_lanes; ++i) {
1267 		if (vep.bus.mipi_csi2.data_lanes[i] != i + 1) {
1268 			dev_err(csis->dev,
1269 				"data lanes reordering is not supported");
1270 			ret = -EINVAL;
1271 			goto err_parse;
1272 		}
1273 	}
1274 
1275 	csis->bus = vep.bus.mipi_csi2;
1276 
1277 	dev_dbg(csis->dev, "data lanes: %d\n", csis->bus.num_data_lanes);
1278 	dev_dbg(csis->dev, "flags: 0x%08x\n", csis->bus.flags);
1279 
1280 	asd = v4l2_async_nf_add_fwnode_remote(&csis->notifier, ep,
1281 					      struct v4l2_async_subdev);
1282 	if (IS_ERR(asd)) {
1283 		ret = PTR_ERR(asd);
1284 		goto err_parse;
1285 	}
1286 
1287 	fwnode_handle_put(ep);
1288 
1289 	csis->notifier.ops = &mipi_csis_notify_ops;
1290 
1291 	ret = v4l2_async_subdev_nf_register(&csis->sd, &csis->notifier);
1292 	if (ret)
1293 		return ret;
1294 
1295 	return v4l2_async_register_subdev(&csis->sd);
1296 
1297 err_parse:
1298 	fwnode_handle_put(ep);
1299 
1300 	return ret;
1301 }
1302 
1303 /* -----------------------------------------------------------------------------
1304  * Suspend/resume
1305  */
1306 
1307 static int __maybe_unused mipi_csis_runtime_suspend(struct device *dev)
1308 {
1309 	struct v4l2_subdev *sd = dev_get_drvdata(dev);
1310 	struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd);
1311 	int ret;
1312 
1313 	ret = mipi_csis_phy_disable(csis);
1314 	if (ret)
1315 		return -EAGAIN;
1316 
1317 	mipi_csis_clk_disable(csis);
1318 
1319 	return 0;
1320 }
1321 
1322 static int __maybe_unused mipi_csis_runtime_resume(struct device *dev)
1323 {
1324 	struct v4l2_subdev *sd = dev_get_drvdata(dev);
1325 	struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd);
1326 	int ret;
1327 
1328 	ret = mipi_csis_phy_enable(csis);
1329 	if (ret)
1330 		return -EAGAIN;
1331 
1332 	ret = mipi_csis_clk_enable(csis);
1333 	if (ret) {
1334 		mipi_csis_phy_disable(csis);
1335 		return ret;
1336 	}
1337 
1338 	return 0;
1339 }
1340 
1341 static const struct dev_pm_ops mipi_csis_pm_ops = {
1342 	SET_RUNTIME_PM_OPS(mipi_csis_runtime_suspend, mipi_csis_runtime_resume,
1343 			   NULL)
1344 };
1345 
1346 /* -----------------------------------------------------------------------------
1347  * Probe/remove & platform driver
1348  */
1349 
1350 static int mipi_csis_subdev_init(struct mipi_csis_device *csis)
1351 {
1352 	struct v4l2_subdev *sd = &csis->sd;
1353 	int ret;
1354 
1355 	v4l2_subdev_init(sd, &mipi_csis_subdev_ops);
1356 	sd->owner = THIS_MODULE;
1357 	snprintf(sd->name, sizeof(sd->name), "csis-%s",
1358 		 dev_name(csis->dev));
1359 
1360 	sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1361 	sd->ctrl_handler = NULL;
1362 
1363 	sd->entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
1364 	sd->entity.ops = &mipi_csis_entity_ops;
1365 
1366 	sd->dev = csis->dev;
1367 
1368 	sd->fwnode = fwnode_graph_get_endpoint_by_id(dev_fwnode(csis->dev),
1369 						     1, 0, 0);
1370 	if (!sd->fwnode) {
1371 		dev_err(csis->dev, "Unable to retrieve endpoint for port@1\n");
1372 		return -ENOENT;
1373 	}
1374 
1375 	csis->pads[CSIS_PAD_SINK].flags = MEDIA_PAD_FL_SINK
1376 					 | MEDIA_PAD_FL_MUST_CONNECT;
1377 	csis->pads[CSIS_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE
1378 					   | MEDIA_PAD_FL_MUST_CONNECT;
1379 	ret = media_entity_pads_init(&sd->entity, CSIS_PADS_NUM, csis->pads);
1380 	if (ret)
1381 		return ret;
1382 
1383 	ret = v4l2_subdev_init_finalize(sd);
1384 	if (ret) {
1385 		media_entity_cleanup(&sd->entity);
1386 		return ret;
1387 	}
1388 
1389 	return 0;
1390 }
1391 
1392 static int mipi_csis_parse_dt(struct mipi_csis_device *csis)
1393 {
1394 	struct device_node *node = csis->dev->of_node;
1395 
1396 	if (of_property_read_u32(node, "clock-frequency",
1397 				 &csis->clk_frequency))
1398 		csis->clk_frequency = DEFAULT_SCLK_CSIS_FREQ;
1399 
1400 	return 0;
1401 }
1402 
1403 static int mipi_csis_probe(struct platform_device *pdev)
1404 {
1405 	struct device *dev = &pdev->dev;
1406 	struct mipi_csis_device *csis;
1407 	int irq;
1408 	int ret;
1409 
1410 	csis = devm_kzalloc(dev, sizeof(*csis), GFP_KERNEL);
1411 	if (!csis)
1412 		return -ENOMEM;
1413 
1414 	spin_lock_init(&csis->slock);
1415 
1416 	csis->dev = dev;
1417 	csis->info = of_device_get_match_data(dev);
1418 
1419 	memcpy(csis->events, mipi_csis_events, sizeof(csis->events));
1420 
1421 	/* Parse DT properties. */
1422 	ret = mipi_csis_parse_dt(csis);
1423 	if (ret < 0) {
1424 		dev_err(dev, "Failed to parse device tree: %d\n", ret);
1425 		return ret;
1426 	}
1427 
1428 	/* Acquire resources. */
1429 	csis->regs = devm_platform_ioremap_resource(pdev, 0);
1430 	if (IS_ERR(csis->regs))
1431 		return PTR_ERR(csis->regs);
1432 
1433 	irq = platform_get_irq(pdev, 0);
1434 	if (irq < 0)
1435 		return irq;
1436 
1437 	ret = mipi_csis_phy_init(csis);
1438 	if (ret < 0)
1439 		return ret;
1440 
1441 	ret = mipi_csis_clk_get(csis);
1442 	if (ret < 0)
1443 		return ret;
1444 
1445 	/* Reset PHY and enable the clocks. */
1446 	mipi_csis_phy_reset(csis);
1447 
1448 	ret = mipi_csis_clk_enable(csis);
1449 	if (ret < 0) {
1450 		dev_err(csis->dev, "failed to enable clocks: %d\n", ret);
1451 		return ret;
1452 	}
1453 
1454 	/* Now that the hardware is initialized, request the interrupt. */
1455 	ret = devm_request_irq(dev, irq, mipi_csis_irq_handler, 0,
1456 			       dev_name(dev), csis);
1457 	if (ret) {
1458 		dev_err(dev, "Interrupt request failed\n");
1459 		goto err_disable_clock;
1460 	}
1461 
1462 	/* Initialize and register the subdev. */
1463 	ret = mipi_csis_subdev_init(csis);
1464 	if (ret < 0)
1465 		goto err_disable_clock;
1466 
1467 	platform_set_drvdata(pdev, &csis->sd);
1468 
1469 	ret = mipi_csis_async_register(csis);
1470 	if (ret < 0) {
1471 		dev_err(dev, "async register failed: %d\n", ret);
1472 		goto err_cleanup;
1473 	}
1474 
1475 	/* Initialize debugfs. */
1476 	mipi_csis_debugfs_init(csis);
1477 
1478 	/* Enable runtime PM. */
1479 	pm_runtime_enable(dev);
1480 	if (!pm_runtime_enabled(dev)) {
1481 		ret = mipi_csis_runtime_resume(dev);
1482 		if (ret < 0)
1483 			goto err_unregister_all;
1484 	}
1485 
1486 	dev_info(dev, "lanes: %d, freq: %u\n",
1487 		 csis->bus.num_data_lanes, csis->clk_frequency);
1488 
1489 	return 0;
1490 
1491 err_unregister_all:
1492 	mipi_csis_debugfs_exit(csis);
1493 err_cleanup:
1494 	v4l2_subdev_cleanup(&csis->sd);
1495 	media_entity_cleanup(&csis->sd.entity);
1496 	v4l2_async_nf_unregister(&csis->notifier);
1497 	v4l2_async_nf_cleanup(&csis->notifier);
1498 	v4l2_async_unregister_subdev(&csis->sd);
1499 err_disable_clock:
1500 	mipi_csis_clk_disable(csis);
1501 	fwnode_handle_put(csis->sd.fwnode);
1502 
1503 	return ret;
1504 }
1505 
1506 static void mipi_csis_remove(struct platform_device *pdev)
1507 {
1508 	struct v4l2_subdev *sd = platform_get_drvdata(pdev);
1509 	struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd);
1510 
1511 	mipi_csis_debugfs_exit(csis);
1512 	v4l2_async_nf_unregister(&csis->notifier);
1513 	v4l2_async_nf_cleanup(&csis->notifier);
1514 	v4l2_async_unregister_subdev(&csis->sd);
1515 
1516 	pm_runtime_disable(&pdev->dev);
1517 	mipi_csis_runtime_suspend(&pdev->dev);
1518 	mipi_csis_clk_disable(csis);
1519 	v4l2_subdev_cleanup(&csis->sd);
1520 	media_entity_cleanup(&csis->sd.entity);
1521 	fwnode_handle_put(csis->sd.fwnode);
1522 	pm_runtime_set_suspended(&pdev->dev);
1523 }
1524 
1525 static const struct of_device_id mipi_csis_of_match[] = {
1526 	{
1527 		.compatible = "fsl,imx7-mipi-csi2",
1528 		.data = &(const struct mipi_csis_info){
1529 			.version = MIPI_CSIS_V3_3,
1530 			.num_clocks = 3,
1531 		},
1532 	}, {
1533 		.compatible = "fsl,imx8mm-mipi-csi2",
1534 		.data = &(const struct mipi_csis_info){
1535 			.version = MIPI_CSIS_V3_6_3,
1536 			.num_clocks = 4,
1537 		},
1538 	},
1539 	{ /* sentinel */ },
1540 };
1541 MODULE_DEVICE_TABLE(of, mipi_csis_of_match);
1542 
1543 static struct platform_driver mipi_csis_driver = {
1544 	.probe		= mipi_csis_probe,
1545 	.remove_new	= mipi_csis_remove,
1546 	.driver		= {
1547 		.of_match_table = mipi_csis_of_match,
1548 		.name		= CSIS_DRIVER_NAME,
1549 		.pm		= &mipi_csis_pm_ops,
1550 	},
1551 };
1552 
1553 module_platform_driver(mipi_csis_driver);
1554 
1555 MODULE_DESCRIPTION("i.MX7 & i.MX8 MIPI CSI-2 receiver driver");
1556 MODULE_LICENSE("GPL v2");
1557 MODULE_ALIAS("platform:imx-mipi-csi2");
1558