1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Samsung CSIS MIPI CSI-2 receiver driver. 4 * 5 * The Samsung CSIS IP is a MIPI CSI-2 receiver found in various NXP i.MX7 and 6 * i.MX8 SoCs. The i.MX7 features version 3.3 of the IP, while i.MX8 features 7 * version 3.6.3. 8 * 9 * Copyright (C) 2019 Linaro Ltd 10 * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. All Rights Reserved. 11 * Copyright (C) 2011 - 2013 Samsung Electronics Co., Ltd. 12 * 13 */ 14 15 #include <linux/clk.h> 16 #include <linux/debugfs.h> 17 #include <linux/delay.h> 18 #include <linux/errno.h> 19 #include <linux/interrupt.h> 20 #include <linux/io.h> 21 #include <linux/kernel.h> 22 #include <linux/module.h> 23 #include <linux/mutex.h> 24 #include <linux/of.h> 25 #include <linux/of_device.h> 26 #include <linux/platform_device.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/regulator/consumer.h> 29 #include <linux/reset.h> 30 #include <linux/spinlock.h> 31 32 #include <media/v4l2-common.h> 33 #include <media/v4l2-device.h> 34 #include <media/v4l2-fwnode.h> 35 #include <media/v4l2-mc.h> 36 #include <media/v4l2-subdev.h> 37 38 #define CSIS_DRIVER_NAME "imx-mipi-csis" 39 40 #define CSIS_PAD_SINK 0 41 #define CSIS_PAD_SOURCE 1 42 #define CSIS_PADS_NUM 2 43 44 #define MIPI_CSIS_DEF_PIX_WIDTH 640 45 #define MIPI_CSIS_DEF_PIX_HEIGHT 480 46 47 /* Register map definition */ 48 49 /* CSIS common control */ 50 #define MIPI_CSIS_CMN_CTRL 0x04 51 #define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW BIT(16) 52 #define MIPI_CSIS_CMN_CTRL_INTER_MODE BIT(10) 53 #define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL BIT(2) 54 #define MIPI_CSIS_CMN_CTRL_RESET BIT(1) 55 #define MIPI_CSIS_CMN_CTRL_ENABLE BIT(0) 56 57 #define MIPI_CSIS_CMN_CTRL_LANE_NR_OFFSET 8 58 #define MIPI_CSIS_CMN_CTRL_LANE_NR_MASK (3 << 8) 59 60 /* CSIS clock control */ 61 #define MIPI_CSIS_CLK_CTRL 0x08 62 #define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH3(x) ((x) << 28) 63 #define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH2(x) ((x) << 24) 64 #define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH1(x) ((x) << 20) 65 #define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH0(x) ((x) << 16) 66 #define MIPI_CSIS_CLK_CTRL_CLKGATE_EN_MSK (0xf << 4) 67 #define MIPI_CSIS_CLK_CTRL_WCLK_SRC BIT(0) 68 69 /* CSIS Interrupt mask */ 70 #define MIPI_CSIS_INT_MSK 0x10 71 #define MIPI_CSIS_INT_MSK_EVEN_BEFORE BIT(31) 72 #define MIPI_CSIS_INT_MSK_EVEN_AFTER BIT(30) 73 #define MIPI_CSIS_INT_MSK_ODD_BEFORE BIT(29) 74 #define MIPI_CSIS_INT_MSK_ODD_AFTER BIT(28) 75 #define MIPI_CSIS_INT_MSK_FRAME_START BIT(24) 76 #define MIPI_CSIS_INT_MSK_FRAME_END BIT(20) 77 #define MIPI_CSIS_INT_MSK_ERR_SOT_HS BIT(16) 78 #define MIPI_CSIS_INT_MSK_ERR_LOST_FS BIT(12) 79 #define MIPI_CSIS_INT_MSK_ERR_LOST_FE BIT(8) 80 #define MIPI_CSIS_INT_MSK_ERR_OVER BIT(4) 81 #define MIPI_CSIS_INT_MSK_ERR_WRONG_CFG BIT(3) 82 #define MIPI_CSIS_INT_MSK_ERR_ECC BIT(2) 83 #define MIPI_CSIS_INT_MSK_ERR_CRC BIT(1) 84 #define MIPI_CSIS_INT_MSK_ERR_UNKNOWN BIT(0) 85 86 /* CSIS Interrupt source */ 87 #define MIPI_CSIS_INT_SRC 0x14 88 #define MIPI_CSIS_INT_SRC_EVEN_BEFORE BIT(31) 89 #define MIPI_CSIS_INT_SRC_EVEN_AFTER BIT(30) 90 #define MIPI_CSIS_INT_SRC_EVEN BIT(30) 91 #define MIPI_CSIS_INT_SRC_ODD_BEFORE BIT(29) 92 #define MIPI_CSIS_INT_SRC_ODD_AFTER BIT(28) 93 #define MIPI_CSIS_INT_SRC_ODD (0x3 << 28) 94 #define MIPI_CSIS_INT_SRC_NON_IMAGE_DATA (0xf << 28) 95 #define MIPI_CSIS_INT_SRC_FRAME_START BIT(24) 96 #define MIPI_CSIS_INT_SRC_FRAME_END BIT(20) 97 #define MIPI_CSIS_INT_SRC_ERR_SOT_HS BIT(16) 98 #define MIPI_CSIS_INT_SRC_ERR_LOST_FS BIT(12) 99 #define MIPI_CSIS_INT_SRC_ERR_LOST_FE BIT(8) 100 #define MIPI_CSIS_INT_SRC_ERR_OVER BIT(4) 101 #define MIPI_CSIS_INT_SRC_ERR_WRONG_CFG BIT(3) 102 #define MIPI_CSIS_INT_SRC_ERR_ECC BIT(2) 103 #define MIPI_CSIS_INT_SRC_ERR_CRC BIT(1) 104 #define MIPI_CSIS_INT_SRC_ERR_UNKNOWN BIT(0) 105 #define MIPI_CSIS_INT_SRC_ERRORS 0xfffff 106 107 /* D-PHY status control */ 108 #define MIPI_CSIS_DPHY_STATUS 0x20 109 #define MIPI_CSIS_DPHY_STATUS_ULPS_DAT BIT(8) 110 #define MIPI_CSIS_DPHY_STATUS_STOPSTATE_DAT BIT(4) 111 #define MIPI_CSIS_DPHY_STATUS_ULPS_CLK BIT(1) 112 #define MIPI_CSIS_DPHY_STATUS_STOPSTATE_CLK BIT(0) 113 114 /* D-PHY common control */ 115 #define MIPI_CSIS_DPHY_CMN_CTRL 0x24 116 #define MIPI_CSIS_DPHY_CMN_CTRL_HSSETTLE(n) ((n) << 24) 117 #define MIPI_CSIS_DPHY_CMN_CTRL_HSSETTLE_MASK GENMASK(31, 24) 118 #define MIPI_CSIS_DPHY_CMN_CTRL_CLKSETTLE(n) ((n) << 22) 119 #define MIPI_CSIS_DPHY_CMN_CTRL_CLKSETTLE_MASK GENMASK(23, 22) 120 #define MIPI_CSIS_DPHY_CMN_CTRL_DPDN_SWAP_CLK BIT(6) 121 #define MIPI_CSIS_DPHY_CMN_CTRL_DPDN_SWAP_DAT BIT(5) 122 #define MIPI_CSIS_DPHY_CMN_CTRL_ENABLE_DAT BIT(1) 123 #define MIPI_CSIS_DPHY_CMN_CTRL_ENABLE_CLK BIT(0) 124 #define MIPI_CSIS_DPHY_CMN_CTRL_ENABLE (0x1f << 0) 125 126 /* D-PHY Master and Slave Control register Low */ 127 #define MIPI_CSIS_DPHY_BCTRL_L 0x30 128 #define MIPI_CSIS_DPHY_BCTRL_L_USER_DATA_PATTERN_LOW(n) (((n) & 3U) << 30) 129 #define MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_715MV (0 << 28) 130 #define MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_724MV (1 << 28) 131 #define MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_733MV (2 << 28) 132 #define MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_706MV (3 << 28) 133 #define MIPI_CSIS_DPHY_BCTRL_L_BGR_CHOPPER_FREQ_3MHZ (0 << 27) 134 #define MIPI_CSIS_DPHY_BCTRL_L_BGR_CHOPPER_FREQ_1_5MHZ (1 << 27) 135 #define MIPI_CSIS_DPHY_BCTRL_L_VREG12_EXTPWR_EN_CTL BIT(26) 136 #define MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_2V (0 << 24) 137 #define MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_23V (1 << 24) 138 #define MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_17V (2 << 24) 139 #define MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_26V (3 << 24) 140 #define MIPI_CSIS_DPHY_BCTRL_L_REG_1P2_LVL_SEL BIT(23) 141 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_80MV (0 << 21) 142 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_100MV (1 << 21) 143 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_120MV (2 << 21) 144 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_140MV (3 << 21) 145 #define MIPI_CSIS_DPHY_BCTRL_L_VREF_SRC_SEL BIT(20) 146 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_715MV (0 << 18) 147 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_743MV (1 << 18) 148 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_650MV (2 << 18) 149 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_682MV (3 << 18) 150 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_PULSE_REJECT BIT(17) 151 #define MIPI_CSIS_DPHY_BCTRL_L_MSTRCLK_LP_SLEW_RATE_DOWN_0 (0 << 15) 152 #define MIPI_CSIS_DPHY_BCTRL_L_MSTRCLK_LP_SLEW_RATE_DOWN_15P (1 << 15) 153 #define MIPI_CSIS_DPHY_BCTRL_L_MSTRCLK_LP_SLEW_RATE_DOWN_30P (3 << 15) 154 #define MIPI_CSIS_DPHY_BCTRL_L_MSTRCLK_LP_SLEW_RATE_UP BIT(14) 155 #define MIPI_CSIS_DPHY_BCTRL_L_LP_CD_HYS_60MV (0 << 13) 156 #define MIPI_CSIS_DPHY_BCTRL_L_LP_CD_HYS_70MV (1 << 13) 157 #define MIPI_CSIS_DPHY_BCTRL_L_BGR_CHOPPER_EN BIT(12) 158 #define MIPI_CSIS_DPHY_BCTRL_L_ERRCONTENTION_LP_EN BIT(11) 159 #define MIPI_CSIS_DPHY_BCTRL_L_TXTRIGGER_CLK_EN BIT(10) 160 #define MIPI_CSIS_DPHY_BCTRL_L_B_DPHYCTRL(n) (((n) * 25 / 1000000) << 0) 161 162 /* D-PHY Master and Slave Control register High */ 163 #define MIPI_CSIS_DPHY_BCTRL_H 0x34 164 /* D-PHY Slave Control register Low */ 165 #define MIPI_CSIS_DPHY_SCTRL_L 0x38 166 /* D-PHY Slave Control register High */ 167 #define MIPI_CSIS_DPHY_SCTRL_H 0x3c 168 169 /* ISP Configuration register */ 170 #define MIPI_CSIS_ISP_CONFIG_CH(n) (0x40 + (n) * 0x10) 171 #define MIPI_CSIS_ISPCFG_MEM_FULL_GAP_MSK (0xff << 24) 172 #define MIPI_CSIS_ISPCFG_MEM_FULL_GAP(x) ((x) << 24) 173 #define MIPI_CSIS_ISPCFG_PIXEL_MODE_SINGLE (0 << 12) 174 #define MIPI_CSIS_ISPCFG_PIXEL_MODE_DUAL (1 << 12) 175 #define MIPI_CSIS_ISPCFG_PIXEL_MODE_QUAD (2 << 12) /* i.MX8M[MNP] only */ 176 #define MIPI_CSIS_ISPCFG_PIXEL_MASK (3 << 12) 177 #define MIPI_CSIS_ISPCFG_ALIGN_32BIT BIT(11) 178 #define MIPI_CSIS_ISPCFG_FMT(fmt) ((fmt) << 2) 179 #define MIPI_CSIS_ISPCFG_FMT_MASK (0x3f << 2) 180 181 /* ISP Image Resolution register */ 182 #define MIPI_CSIS_ISP_RESOL_CH(n) (0x44 + (n) * 0x10) 183 #define CSIS_MAX_PIX_WIDTH 0xffff 184 #define CSIS_MAX_PIX_HEIGHT 0xffff 185 186 /* ISP SYNC register */ 187 #define MIPI_CSIS_ISP_SYNC_CH(n) (0x48 + (n) * 0x10) 188 #define MIPI_CSIS_ISP_SYNC_HSYNC_LINTV_OFFSET 18 189 #define MIPI_CSIS_ISP_SYNC_VSYNC_SINTV_OFFSET 12 190 #define MIPI_CSIS_ISP_SYNC_VSYNC_EINTV_OFFSET 0 191 192 /* ISP shadow registers */ 193 #define MIPI_CSIS_SDW_CONFIG_CH(n) (0x80 + (n) * 0x10) 194 #define MIPI_CSIS_SDW_RESOL_CH(n) (0x84 + (n) * 0x10) 195 #define MIPI_CSIS_SDW_SYNC_CH(n) (0x88 + (n) * 0x10) 196 197 /* Debug control register */ 198 #define MIPI_CSIS_DBG_CTRL 0xc0 199 #define MIPI_CSIS_DBG_INTR_MSK 0xc4 200 #define MIPI_CSIS_DBG_INTR_MSK_DT_NOT_SUPPORT BIT(25) 201 #define MIPI_CSIS_DBG_INTR_MSK_DT_IGNORE BIT(24) 202 #define MIPI_CSIS_DBG_INTR_MSK_ERR_FRAME_SIZE BIT(20) 203 #define MIPI_CSIS_DBG_INTR_MSK_TRUNCATED_FRAME BIT(16) 204 #define MIPI_CSIS_DBG_INTR_MSK_EARLY_FE BIT(12) 205 #define MIPI_CSIS_DBG_INTR_MSK_EARLY_FS BIT(8) 206 #define MIPI_CSIS_DBG_INTR_MSK_CAM_VSYNC_FALL BIT(4) 207 #define MIPI_CSIS_DBG_INTR_MSK_CAM_VSYNC_RISE BIT(0) 208 #define MIPI_CSIS_DBG_INTR_SRC 0xc8 209 #define MIPI_CSIS_DBG_INTR_SRC_DT_NOT_SUPPORT BIT(25) 210 #define MIPI_CSIS_DBG_INTR_SRC_DT_IGNORE BIT(24) 211 #define MIPI_CSIS_DBG_INTR_SRC_ERR_FRAME_SIZE BIT(20) 212 #define MIPI_CSIS_DBG_INTR_SRC_TRUNCATED_FRAME BIT(16) 213 #define MIPI_CSIS_DBG_INTR_SRC_EARLY_FE BIT(12) 214 #define MIPI_CSIS_DBG_INTR_SRC_EARLY_FS BIT(8) 215 #define MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_FALL BIT(4) 216 #define MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_RISE BIT(0) 217 218 #define MIPI_CSIS_FRAME_COUNTER_CH(n) (0x0100 + (n) * 4) 219 220 /* Non-image packet data buffers */ 221 #define MIPI_CSIS_PKTDATA_ODD 0x2000 222 #define MIPI_CSIS_PKTDATA_EVEN 0x3000 223 #define MIPI_CSIS_PKTDATA_SIZE SZ_4K 224 225 #define DEFAULT_SCLK_CSIS_FREQ 166000000UL 226 227 /* MIPI CSI-2 Data Types */ 228 #define MIPI_CSI2_DATA_TYPE_YUV420_8 0x18 229 #define MIPI_CSI2_DATA_TYPE_YUV420_10 0x19 230 #define MIPI_CSI2_DATA_TYPE_LE_YUV420_8 0x1a 231 #define MIPI_CSI2_DATA_TYPE_CS_YUV420_8 0x1c 232 #define MIPI_CSI2_DATA_TYPE_CS_YUV420_10 0x1d 233 #define MIPI_CSI2_DATA_TYPE_YUV422_8 0x1e 234 #define MIPI_CSI2_DATA_TYPE_YUV422_10 0x1f 235 #define MIPI_CSI2_DATA_TYPE_RGB565 0x22 236 #define MIPI_CSI2_DATA_TYPE_RGB666 0x23 237 #define MIPI_CSI2_DATA_TYPE_RGB888 0x24 238 #define MIPI_CSI2_DATA_TYPE_RAW6 0x28 239 #define MIPI_CSI2_DATA_TYPE_RAW7 0x29 240 #define MIPI_CSI2_DATA_TYPE_RAW8 0x2a 241 #define MIPI_CSI2_DATA_TYPE_RAW10 0x2b 242 #define MIPI_CSI2_DATA_TYPE_RAW12 0x2c 243 #define MIPI_CSI2_DATA_TYPE_RAW14 0x2d 244 #define MIPI_CSI2_DATA_TYPE_USER(x) (0x30 + (x)) 245 246 enum { 247 ST_POWERED = 1, 248 ST_STREAMING = 2, 249 ST_SUSPENDED = 4, 250 }; 251 252 struct mipi_csis_event { 253 bool debug; 254 u32 mask; 255 const char * const name; 256 unsigned int counter; 257 }; 258 259 static const struct mipi_csis_event mipi_csis_events[] = { 260 /* Errors */ 261 { false, MIPI_CSIS_INT_SRC_ERR_SOT_HS, "SOT Error" }, 262 { false, MIPI_CSIS_INT_SRC_ERR_LOST_FS, "Lost Frame Start Error" }, 263 { false, MIPI_CSIS_INT_SRC_ERR_LOST_FE, "Lost Frame End Error" }, 264 { false, MIPI_CSIS_INT_SRC_ERR_OVER, "FIFO Overflow Error" }, 265 { false, MIPI_CSIS_INT_SRC_ERR_WRONG_CFG, "Wrong Configuration Error" }, 266 { false, MIPI_CSIS_INT_SRC_ERR_ECC, "ECC Error" }, 267 { false, MIPI_CSIS_INT_SRC_ERR_CRC, "CRC Error" }, 268 { false, MIPI_CSIS_INT_SRC_ERR_UNKNOWN, "Unknown Error" }, 269 { true, MIPI_CSIS_DBG_INTR_SRC_DT_NOT_SUPPORT, "Data Type Not Supported" }, 270 { true, MIPI_CSIS_DBG_INTR_SRC_DT_IGNORE, "Data Type Ignored" }, 271 { true, MIPI_CSIS_DBG_INTR_SRC_ERR_FRAME_SIZE, "Frame Size Error" }, 272 { true, MIPI_CSIS_DBG_INTR_SRC_TRUNCATED_FRAME, "Truncated Frame" }, 273 { true, MIPI_CSIS_DBG_INTR_SRC_EARLY_FE, "Early Frame End" }, 274 { true, MIPI_CSIS_DBG_INTR_SRC_EARLY_FS, "Early Frame Start" }, 275 /* Non-image data receive events */ 276 { false, MIPI_CSIS_INT_SRC_EVEN_BEFORE, "Non-image data before even frame" }, 277 { false, MIPI_CSIS_INT_SRC_EVEN_AFTER, "Non-image data after even frame" }, 278 { false, MIPI_CSIS_INT_SRC_ODD_BEFORE, "Non-image data before odd frame" }, 279 { false, MIPI_CSIS_INT_SRC_ODD_AFTER, "Non-image data after odd frame" }, 280 /* Frame start/end */ 281 { false, MIPI_CSIS_INT_SRC_FRAME_START, "Frame Start" }, 282 { false, MIPI_CSIS_INT_SRC_FRAME_END, "Frame End" }, 283 { true, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_FALL, "VSYNC Falling Edge" }, 284 { true, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_RISE, "VSYNC Rising Edge" }, 285 }; 286 287 #define MIPI_CSIS_NUM_EVENTS ARRAY_SIZE(mipi_csis_events) 288 289 enum mipi_csis_clk { 290 MIPI_CSIS_CLK_PCLK, 291 MIPI_CSIS_CLK_WRAP, 292 MIPI_CSIS_CLK_PHY, 293 MIPI_CSIS_CLK_AXI, 294 }; 295 296 static const char * const mipi_csis_clk_id[] = { 297 "pclk", 298 "wrap", 299 "phy", 300 "axi", 301 }; 302 303 enum mipi_csis_version { 304 MIPI_CSIS_V3_3, 305 MIPI_CSIS_V3_6_3, 306 }; 307 308 struct mipi_csis_info { 309 enum mipi_csis_version version; 310 unsigned int num_clocks; 311 }; 312 313 struct mipi_csis_device { 314 struct device *dev; 315 void __iomem *regs; 316 struct clk_bulk_data *clks; 317 struct reset_control *mrst; 318 struct regulator *mipi_phy_regulator; 319 const struct mipi_csis_info *info; 320 321 struct v4l2_subdev sd; 322 struct media_pad pads[CSIS_PADS_NUM]; 323 struct v4l2_async_notifier notifier; 324 struct v4l2_subdev *src_sd; 325 326 struct v4l2_mbus_config_mipi_csi2 bus; 327 u32 clk_frequency; 328 u32 hs_settle; 329 u32 clk_settle; 330 331 struct mutex lock; /* Protect csis_fmt, format_mbus and state */ 332 const struct csis_pix_format *csis_fmt; 333 struct v4l2_mbus_framefmt format_mbus[CSIS_PADS_NUM]; 334 u32 state; 335 336 spinlock_t slock; /* Protect events */ 337 struct mipi_csis_event events[MIPI_CSIS_NUM_EVENTS]; 338 struct dentry *debugfs_root; 339 struct { 340 bool enable; 341 u32 hs_settle; 342 u32 clk_settle; 343 } debug; 344 }; 345 346 /* ----------------------------------------------------------------------------- 347 * Format helpers 348 */ 349 350 struct csis_pix_format { 351 u32 code; 352 u32 output; 353 u32 data_type; 354 u8 width; 355 }; 356 357 static const struct csis_pix_format mipi_csis_formats[] = { 358 /* YUV formats. */ 359 { 360 .code = MEDIA_BUS_FMT_UYVY8_1X16, 361 .output = MEDIA_BUS_FMT_UYVY8_1X16, 362 .data_type = MIPI_CSI2_DATA_TYPE_YUV422_8, 363 .width = 16, 364 }, 365 /* RGB formats. */ 366 { 367 .code = MEDIA_BUS_FMT_RGB565_1X16, 368 .output = MEDIA_BUS_FMT_RGB565_1X16, 369 .data_type = MIPI_CSI2_DATA_TYPE_RGB565, 370 .width = 16, 371 }, { 372 .code = MEDIA_BUS_FMT_BGR888_1X24, 373 .output = MEDIA_BUS_FMT_RGB888_1X24, 374 .data_type = MIPI_CSI2_DATA_TYPE_RGB888, 375 .width = 24, 376 }, 377 /* RAW (Bayer and greyscale) formats. */ 378 { 379 .code = MEDIA_BUS_FMT_SBGGR8_1X8, 380 .output = MEDIA_BUS_FMT_SBGGR8_1X8, 381 .data_type = MIPI_CSI2_DATA_TYPE_RAW8, 382 .width = 8, 383 }, { 384 .code = MEDIA_BUS_FMT_SGBRG8_1X8, 385 .output = MEDIA_BUS_FMT_SGBRG8_1X8, 386 .data_type = MIPI_CSI2_DATA_TYPE_RAW8, 387 .width = 8, 388 }, { 389 .code = MEDIA_BUS_FMT_SGRBG8_1X8, 390 .output = MEDIA_BUS_FMT_SGRBG8_1X8, 391 .data_type = MIPI_CSI2_DATA_TYPE_RAW8, 392 .width = 8, 393 }, { 394 .code = MEDIA_BUS_FMT_SRGGB8_1X8, 395 .output = MEDIA_BUS_FMT_SRGGB8_1X8, 396 .data_type = MIPI_CSI2_DATA_TYPE_RAW8, 397 .width = 8, 398 }, { 399 .code = MEDIA_BUS_FMT_Y8_1X8, 400 .output = MEDIA_BUS_FMT_Y8_1X8, 401 .data_type = MIPI_CSI2_DATA_TYPE_RAW8, 402 .width = 8, 403 }, { 404 .code = MEDIA_BUS_FMT_SBGGR10_1X10, 405 .output = MEDIA_BUS_FMT_SBGGR10_1X10, 406 .data_type = MIPI_CSI2_DATA_TYPE_RAW10, 407 .width = 10, 408 }, { 409 .code = MEDIA_BUS_FMT_SGBRG10_1X10, 410 .output = MEDIA_BUS_FMT_SGBRG10_1X10, 411 .data_type = MIPI_CSI2_DATA_TYPE_RAW10, 412 .width = 10, 413 }, { 414 .code = MEDIA_BUS_FMT_SGRBG10_1X10, 415 .output = MEDIA_BUS_FMT_SGRBG10_1X10, 416 .data_type = MIPI_CSI2_DATA_TYPE_RAW10, 417 .width = 10, 418 }, { 419 .code = MEDIA_BUS_FMT_SRGGB10_1X10, 420 .output = MEDIA_BUS_FMT_SRGGB10_1X10, 421 .data_type = MIPI_CSI2_DATA_TYPE_RAW10, 422 .width = 10, 423 }, { 424 .code = MEDIA_BUS_FMT_Y10_1X10, 425 .output = MEDIA_BUS_FMT_Y10_1X10, 426 .data_type = MIPI_CSI2_DATA_TYPE_RAW10, 427 .width = 10, 428 }, { 429 .code = MEDIA_BUS_FMT_SBGGR12_1X12, 430 .output = MEDIA_BUS_FMT_SBGGR12_1X12, 431 .data_type = MIPI_CSI2_DATA_TYPE_RAW12, 432 .width = 12, 433 }, { 434 .code = MEDIA_BUS_FMT_SGBRG12_1X12, 435 .output = MEDIA_BUS_FMT_SGBRG12_1X12, 436 .data_type = MIPI_CSI2_DATA_TYPE_RAW12, 437 .width = 12, 438 }, { 439 .code = MEDIA_BUS_FMT_SGRBG12_1X12, 440 .output = MEDIA_BUS_FMT_SGRBG12_1X12, 441 .data_type = MIPI_CSI2_DATA_TYPE_RAW12, 442 .width = 12, 443 }, { 444 .code = MEDIA_BUS_FMT_SRGGB12_1X12, 445 .output = MEDIA_BUS_FMT_SRGGB12_1X12, 446 .data_type = MIPI_CSI2_DATA_TYPE_RAW12, 447 .width = 12, 448 }, { 449 .code = MEDIA_BUS_FMT_Y12_1X12, 450 .output = MEDIA_BUS_FMT_Y12_1X12, 451 .data_type = MIPI_CSI2_DATA_TYPE_RAW12, 452 .width = 12, 453 }, { 454 .code = MEDIA_BUS_FMT_SBGGR14_1X14, 455 .output = MEDIA_BUS_FMT_SBGGR14_1X14, 456 .data_type = MIPI_CSI2_DATA_TYPE_RAW14, 457 .width = 14, 458 }, { 459 .code = MEDIA_BUS_FMT_SGBRG14_1X14, 460 .output = MEDIA_BUS_FMT_SGBRG14_1X14, 461 .data_type = MIPI_CSI2_DATA_TYPE_RAW14, 462 .width = 14, 463 }, { 464 .code = MEDIA_BUS_FMT_SGRBG14_1X14, 465 .output = MEDIA_BUS_FMT_SGRBG14_1X14, 466 .data_type = MIPI_CSI2_DATA_TYPE_RAW14, 467 .width = 14, 468 }, { 469 .code = MEDIA_BUS_FMT_SRGGB14_1X14, 470 .output = MEDIA_BUS_FMT_SRGGB14_1X14, 471 .data_type = MIPI_CSI2_DATA_TYPE_RAW14, 472 .width = 14, 473 }, 474 /* JPEG */ 475 { 476 .code = MEDIA_BUS_FMT_JPEG_1X8, 477 .output = MEDIA_BUS_FMT_JPEG_1X8, 478 /* 479 * Map JPEG_1X8 to the RAW8 datatype. 480 * 481 * The CSI-2 specification suggests in Annex A "JPEG8 Data 482 * Format (informative)" to transmit JPEG data using one of the 483 * Data Types aimed to represent arbitrary data, such as the 484 * "User Defined Data Type 1" (0x30). 485 * 486 * However, when configured with a User Defined Data Type, the 487 * CSIS outputs data in quad pixel mode regardless of the mode 488 * selected in the MIPI_CSIS_ISP_CONFIG_CH register. Neither of 489 * the IP cores connected to the CSIS in i.MX SoCs (CSI bridge 490 * or ISI) support quad pixel mode, so this will never work in 491 * practice. 492 * 493 * Some sensors (such as the OV5640) send JPEG data using the 494 * RAW8 data type. This is usable and works, so map the JPEG 495 * format to RAW8. If the CSIS ends up being integrated in an 496 * SoC that can support quad pixel mode, this will have to be 497 * revisited. 498 */ 499 .data_type = MIPI_CSI2_DATA_TYPE_RAW8, 500 .width = 8, 501 } 502 }; 503 504 static const struct csis_pix_format *find_csis_format(u32 code) 505 { 506 unsigned int i; 507 508 for (i = 0; i < ARRAY_SIZE(mipi_csis_formats); i++) 509 if (code == mipi_csis_formats[i].code) 510 return &mipi_csis_formats[i]; 511 return NULL; 512 } 513 514 /* ----------------------------------------------------------------------------- 515 * Hardware configuration 516 */ 517 518 static inline u32 mipi_csis_read(struct mipi_csis_device *csis, u32 reg) 519 { 520 return readl(csis->regs + reg); 521 } 522 523 static inline void mipi_csis_write(struct mipi_csis_device *csis, u32 reg, 524 u32 val) 525 { 526 writel(val, csis->regs + reg); 527 } 528 529 static void mipi_csis_enable_interrupts(struct mipi_csis_device *csis, bool on) 530 { 531 mipi_csis_write(csis, MIPI_CSIS_INT_MSK, on ? 0xffffffff : 0); 532 mipi_csis_write(csis, MIPI_CSIS_DBG_INTR_MSK, on ? 0xffffffff : 0); 533 } 534 535 static void mipi_csis_sw_reset(struct mipi_csis_device *csis) 536 { 537 u32 val = mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL); 538 539 mipi_csis_write(csis, MIPI_CSIS_CMN_CTRL, 540 val | MIPI_CSIS_CMN_CTRL_RESET); 541 usleep_range(10, 20); 542 } 543 544 static void mipi_csis_system_enable(struct mipi_csis_device *csis, int on) 545 { 546 u32 val, mask; 547 548 val = mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL); 549 if (on) 550 val |= MIPI_CSIS_CMN_CTRL_ENABLE; 551 else 552 val &= ~MIPI_CSIS_CMN_CTRL_ENABLE; 553 mipi_csis_write(csis, MIPI_CSIS_CMN_CTRL, val); 554 555 val = mipi_csis_read(csis, MIPI_CSIS_DPHY_CMN_CTRL); 556 val &= ~MIPI_CSIS_DPHY_CMN_CTRL_ENABLE; 557 if (on) { 558 mask = (1 << (csis->bus.num_data_lanes + 1)) - 1; 559 val |= (mask & MIPI_CSIS_DPHY_CMN_CTRL_ENABLE); 560 } 561 mipi_csis_write(csis, MIPI_CSIS_DPHY_CMN_CTRL, val); 562 } 563 564 /* Called with the csis.lock mutex held */ 565 static void __mipi_csis_set_format(struct mipi_csis_device *csis) 566 { 567 struct v4l2_mbus_framefmt *mf = &csis->format_mbus[CSIS_PAD_SINK]; 568 u32 val; 569 570 /* Color format */ 571 val = mipi_csis_read(csis, MIPI_CSIS_ISP_CONFIG_CH(0)); 572 val &= ~(MIPI_CSIS_ISPCFG_ALIGN_32BIT | MIPI_CSIS_ISPCFG_FMT_MASK 573 | MIPI_CSIS_ISPCFG_PIXEL_MASK); 574 575 /* 576 * YUV 4:2:2 can be transferred with 8 or 16 bits per clock sample 577 * (referred to in the documentation as single and dual pixel modes 578 * respectively, although the 8-bit mode transfers half a pixel per 579 * clock sample and the 16-bit mode one pixel). While both mode work 580 * when the CSIS is connected to a receiver that supports either option, 581 * single pixel mode requires clock rates twice as high. As all SoCs 582 * that integrate the CSIS can operate in 16-bit bit mode, and some do 583 * not support 8-bit mode (this is the case of the i.MX8MP), use dual 584 * pixel mode unconditionally. 585 * 586 * TODO: Verify which other formats require DUAL (or QUAD) modes. 587 */ 588 if (csis->csis_fmt->data_type == MIPI_CSI2_DATA_TYPE_YUV422_8) 589 val |= MIPI_CSIS_ISPCFG_PIXEL_MODE_DUAL; 590 591 val |= MIPI_CSIS_ISPCFG_FMT(csis->csis_fmt->data_type); 592 mipi_csis_write(csis, MIPI_CSIS_ISP_CONFIG_CH(0), val); 593 594 /* Pixel resolution */ 595 val = mf->width | (mf->height << 16); 596 mipi_csis_write(csis, MIPI_CSIS_ISP_RESOL_CH(0), val); 597 } 598 599 static int mipi_csis_calculate_params(struct mipi_csis_device *csis) 600 { 601 s64 link_freq; 602 u32 lane_rate; 603 604 /* Calculate the line rate from the pixel rate. */ 605 link_freq = v4l2_get_link_freq(csis->src_sd->ctrl_handler, 606 csis->csis_fmt->width, 607 csis->bus.num_data_lanes * 2); 608 if (link_freq < 0) { 609 dev_err(csis->dev, "Unable to obtain link frequency: %d\n", 610 (int)link_freq); 611 return link_freq; 612 } 613 614 lane_rate = link_freq * 2; 615 616 if (lane_rate < 80000000 || lane_rate > 1500000000) { 617 dev_dbg(csis->dev, "Out-of-bound lane rate %u\n", lane_rate); 618 return -EINVAL; 619 } 620 621 /* 622 * The HSSETTLE counter value is document in a table, but can also 623 * easily be calculated. Hardcode the CLKSETTLE value to 0 for now 624 * (which is documented as corresponding to CSI-2 v0.87 to v1.00) until 625 * we figure out how to compute it correctly. 626 */ 627 csis->hs_settle = (lane_rate - 5000000) / 45000000; 628 csis->clk_settle = 0; 629 630 dev_dbg(csis->dev, "lane rate %u, Tclk_settle %u, Ths_settle %u\n", 631 lane_rate, csis->clk_settle, csis->hs_settle); 632 633 if (csis->debug.hs_settle < 0xff) { 634 dev_dbg(csis->dev, "overriding Ths_settle with %u\n", 635 csis->debug.hs_settle); 636 csis->hs_settle = csis->debug.hs_settle; 637 } 638 639 if (csis->debug.clk_settle < 4) { 640 dev_dbg(csis->dev, "overriding Tclk_settle with %u\n", 641 csis->debug.clk_settle); 642 csis->clk_settle = csis->debug.clk_settle; 643 } 644 645 return 0; 646 } 647 648 static void mipi_csis_set_params(struct mipi_csis_device *csis) 649 { 650 int lanes = csis->bus.num_data_lanes; 651 u32 val; 652 653 val = mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL); 654 val &= ~MIPI_CSIS_CMN_CTRL_LANE_NR_MASK; 655 val |= (lanes - 1) << MIPI_CSIS_CMN_CTRL_LANE_NR_OFFSET; 656 if (csis->info->version == MIPI_CSIS_V3_3) 657 val |= MIPI_CSIS_CMN_CTRL_INTER_MODE; 658 mipi_csis_write(csis, MIPI_CSIS_CMN_CTRL, val); 659 660 __mipi_csis_set_format(csis); 661 662 mipi_csis_write(csis, MIPI_CSIS_DPHY_CMN_CTRL, 663 MIPI_CSIS_DPHY_CMN_CTRL_HSSETTLE(csis->hs_settle) | 664 MIPI_CSIS_DPHY_CMN_CTRL_CLKSETTLE(csis->clk_settle)); 665 666 val = (0 << MIPI_CSIS_ISP_SYNC_HSYNC_LINTV_OFFSET) 667 | (0 << MIPI_CSIS_ISP_SYNC_VSYNC_SINTV_OFFSET) 668 | (0 << MIPI_CSIS_ISP_SYNC_VSYNC_EINTV_OFFSET); 669 mipi_csis_write(csis, MIPI_CSIS_ISP_SYNC_CH(0), val); 670 671 val = mipi_csis_read(csis, MIPI_CSIS_CLK_CTRL); 672 val |= MIPI_CSIS_CLK_CTRL_WCLK_SRC; 673 val |= MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH0(15); 674 val &= ~MIPI_CSIS_CLK_CTRL_CLKGATE_EN_MSK; 675 mipi_csis_write(csis, MIPI_CSIS_CLK_CTRL, val); 676 677 mipi_csis_write(csis, MIPI_CSIS_DPHY_BCTRL_L, 678 MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_715MV | 679 MIPI_CSIS_DPHY_BCTRL_L_BGR_CHOPPER_FREQ_3MHZ | 680 MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_2V | 681 MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_80MV | 682 MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_715MV | 683 MIPI_CSIS_DPHY_BCTRL_L_LP_CD_HYS_60MV | 684 MIPI_CSIS_DPHY_BCTRL_L_B_DPHYCTRL(20000000)); 685 mipi_csis_write(csis, MIPI_CSIS_DPHY_BCTRL_H, 0); 686 687 /* Update the shadow register. */ 688 val = mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL); 689 mipi_csis_write(csis, MIPI_CSIS_CMN_CTRL, 690 val | MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW | 691 MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL); 692 } 693 694 static int mipi_csis_clk_enable(struct mipi_csis_device *csis) 695 { 696 return clk_bulk_prepare_enable(csis->info->num_clocks, csis->clks); 697 } 698 699 static void mipi_csis_clk_disable(struct mipi_csis_device *csis) 700 { 701 clk_bulk_disable_unprepare(csis->info->num_clocks, csis->clks); 702 } 703 704 static int mipi_csis_clk_get(struct mipi_csis_device *csis) 705 { 706 unsigned int i; 707 int ret; 708 709 csis->clks = devm_kcalloc(csis->dev, csis->info->num_clocks, 710 sizeof(*csis->clks), GFP_KERNEL); 711 712 if (!csis->clks) 713 return -ENOMEM; 714 715 for (i = 0; i < csis->info->num_clocks; i++) 716 csis->clks[i].id = mipi_csis_clk_id[i]; 717 718 ret = devm_clk_bulk_get(csis->dev, csis->info->num_clocks, 719 csis->clks); 720 if (ret < 0) 721 return ret; 722 723 /* Set clock rate */ 724 ret = clk_set_rate(csis->clks[MIPI_CSIS_CLK_WRAP].clk, 725 csis->clk_frequency); 726 if (ret < 0) 727 dev_err(csis->dev, "set rate=%d failed: %d\n", 728 csis->clk_frequency, ret); 729 730 return ret; 731 } 732 733 static void mipi_csis_start_stream(struct mipi_csis_device *csis) 734 { 735 mipi_csis_sw_reset(csis); 736 mipi_csis_set_params(csis); 737 mipi_csis_system_enable(csis, true); 738 mipi_csis_enable_interrupts(csis, true); 739 } 740 741 static void mipi_csis_stop_stream(struct mipi_csis_device *csis) 742 { 743 mipi_csis_enable_interrupts(csis, false); 744 mipi_csis_system_enable(csis, false); 745 } 746 747 static irqreturn_t mipi_csis_irq_handler(int irq, void *dev_id) 748 { 749 struct mipi_csis_device *csis = dev_id; 750 unsigned long flags; 751 unsigned int i; 752 u32 status; 753 u32 dbg_status; 754 755 status = mipi_csis_read(csis, MIPI_CSIS_INT_SRC); 756 dbg_status = mipi_csis_read(csis, MIPI_CSIS_DBG_INTR_SRC); 757 758 spin_lock_irqsave(&csis->slock, flags); 759 760 /* Update the event/error counters */ 761 if ((status & MIPI_CSIS_INT_SRC_ERRORS) || csis->debug.enable) { 762 for (i = 0; i < MIPI_CSIS_NUM_EVENTS; i++) { 763 struct mipi_csis_event *event = &csis->events[i]; 764 765 if ((!event->debug && (status & event->mask)) || 766 (event->debug && (dbg_status & event->mask))) 767 event->counter++; 768 } 769 } 770 spin_unlock_irqrestore(&csis->slock, flags); 771 772 mipi_csis_write(csis, MIPI_CSIS_INT_SRC, status); 773 mipi_csis_write(csis, MIPI_CSIS_DBG_INTR_SRC, dbg_status); 774 775 return IRQ_HANDLED; 776 } 777 778 /* ----------------------------------------------------------------------------- 779 * PHY regulator and reset 780 */ 781 782 static int mipi_csis_phy_enable(struct mipi_csis_device *csis) 783 { 784 if (csis->info->version != MIPI_CSIS_V3_3) 785 return 0; 786 787 return regulator_enable(csis->mipi_phy_regulator); 788 } 789 790 static int mipi_csis_phy_disable(struct mipi_csis_device *csis) 791 { 792 if (csis->info->version != MIPI_CSIS_V3_3) 793 return 0; 794 795 return regulator_disable(csis->mipi_phy_regulator); 796 } 797 798 static void mipi_csis_phy_reset(struct mipi_csis_device *csis) 799 { 800 if (csis->info->version != MIPI_CSIS_V3_3) 801 return; 802 803 reset_control_assert(csis->mrst); 804 msleep(20); 805 reset_control_deassert(csis->mrst); 806 } 807 808 static int mipi_csis_phy_init(struct mipi_csis_device *csis) 809 { 810 if (csis->info->version != MIPI_CSIS_V3_3) 811 return 0; 812 813 /* Get MIPI PHY reset and regulator. */ 814 csis->mrst = devm_reset_control_get_exclusive(csis->dev, NULL); 815 if (IS_ERR(csis->mrst)) 816 return PTR_ERR(csis->mrst); 817 818 csis->mipi_phy_regulator = devm_regulator_get(csis->dev, "phy"); 819 if (IS_ERR(csis->mipi_phy_regulator)) 820 return PTR_ERR(csis->mipi_phy_regulator); 821 822 return regulator_set_voltage(csis->mipi_phy_regulator, 1000000, 823 1000000); 824 } 825 826 /* ----------------------------------------------------------------------------- 827 * Debug 828 */ 829 830 static void mipi_csis_clear_counters(struct mipi_csis_device *csis) 831 { 832 unsigned long flags; 833 unsigned int i; 834 835 spin_lock_irqsave(&csis->slock, flags); 836 for (i = 0; i < MIPI_CSIS_NUM_EVENTS; i++) 837 csis->events[i].counter = 0; 838 spin_unlock_irqrestore(&csis->slock, flags); 839 } 840 841 static void mipi_csis_log_counters(struct mipi_csis_device *csis, bool non_errors) 842 { 843 unsigned int num_events = non_errors ? MIPI_CSIS_NUM_EVENTS 844 : MIPI_CSIS_NUM_EVENTS - 8; 845 unsigned long flags; 846 unsigned int i; 847 848 spin_lock_irqsave(&csis->slock, flags); 849 850 for (i = 0; i < num_events; ++i) { 851 if (csis->events[i].counter > 0 || csis->debug.enable) 852 dev_info(csis->dev, "%s events: %d\n", 853 csis->events[i].name, 854 csis->events[i].counter); 855 } 856 spin_unlock_irqrestore(&csis->slock, flags); 857 } 858 859 static int mipi_csis_dump_regs(struct mipi_csis_device *csis) 860 { 861 static const struct { 862 u32 offset; 863 const char * const name; 864 } registers[] = { 865 { MIPI_CSIS_CMN_CTRL, "CMN_CTRL" }, 866 { MIPI_CSIS_CLK_CTRL, "CLK_CTRL" }, 867 { MIPI_CSIS_INT_MSK, "INT_MSK" }, 868 { MIPI_CSIS_DPHY_STATUS, "DPHY_STATUS" }, 869 { MIPI_CSIS_DPHY_CMN_CTRL, "DPHY_CMN_CTRL" }, 870 { MIPI_CSIS_DPHY_SCTRL_L, "DPHY_SCTRL_L" }, 871 { MIPI_CSIS_DPHY_SCTRL_H, "DPHY_SCTRL_H" }, 872 { MIPI_CSIS_ISP_CONFIG_CH(0), "ISP_CONFIG_CH0" }, 873 { MIPI_CSIS_ISP_RESOL_CH(0), "ISP_RESOL_CH0" }, 874 { MIPI_CSIS_SDW_CONFIG_CH(0), "SDW_CONFIG_CH0" }, 875 { MIPI_CSIS_SDW_RESOL_CH(0), "SDW_RESOL_CH0" }, 876 { MIPI_CSIS_DBG_CTRL, "DBG_CTRL" }, 877 { MIPI_CSIS_FRAME_COUNTER_CH(0), "FRAME_COUNTER_CH0" }, 878 }; 879 880 unsigned int i; 881 u32 cfg; 882 883 dev_info(csis->dev, "--- REGISTERS ---\n"); 884 885 for (i = 0; i < ARRAY_SIZE(registers); i++) { 886 cfg = mipi_csis_read(csis, registers[i].offset); 887 dev_info(csis->dev, "%14s: 0x%08x\n", registers[i].name, cfg); 888 } 889 890 return 0; 891 } 892 893 static int mipi_csis_dump_regs_show(struct seq_file *m, void *private) 894 { 895 struct mipi_csis_device *csis = m->private; 896 897 return mipi_csis_dump_regs(csis); 898 } 899 DEFINE_SHOW_ATTRIBUTE(mipi_csis_dump_regs); 900 901 static void mipi_csis_debugfs_init(struct mipi_csis_device *csis) 902 { 903 csis->debug.hs_settle = UINT_MAX; 904 csis->debug.clk_settle = UINT_MAX; 905 906 csis->debugfs_root = debugfs_create_dir(dev_name(csis->dev), NULL); 907 908 debugfs_create_bool("debug_enable", 0600, csis->debugfs_root, 909 &csis->debug.enable); 910 debugfs_create_file("dump_regs", 0600, csis->debugfs_root, csis, 911 &mipi_csis_dump_regs_fops); 912 debugfs_create_u32("tclk_settle", 0600, csis->debugfs_root, 913 &csis->debug.clk_settle); 914 debugfs_create_u32("ths_settle", 0600, csis->debugfs_root, 915 &csis->debug.hs_settle); 916 } 917 918 static void mipi_csis_debugfs_exit(struct mipi_csis_device *csis) 919 { 920 debugfs_remove_recursive(csis->debugfs_root); 921 } 922 923 /* ----------------------------------------------------------------------------- 924 * V4L2 subdev operations 925 */ 926 927 static struct mipi_csis_device *sd_to_mipi_csis_device(struct v4l2_subdev *sdev) 928 { 929 return container_of(sdev, struct mipi_csis_device, sd); 930 } 931 932 static int mipi_csis_s_stream(struct v4l2_subdev *sd, int enable) 933 { 934 struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd); 935 int ret = 0; 936 937 if (enable) { 938 ret = mipi_csis_calculate_params(csis); 939 if (ret < 0) 940 return ret; 941 942 mipi_csis_clear_counters(csis); 943 944 ret = pm_runtime_resume_and_get(csis->dev); 945 if (ret < 0) 946 return ret; 947 } 948 949 mutex_lock(&csis->lock); 950 951 if (enable) { 952 if (csis->state & ST_SUSPENDED) { 953 ret = -EBUSY; 954 goto unlock; 955 } 956 957 mipi_csis_start_stream(csis); 958 ret = v4l2_subdev_call(csis->src_sd, video, s_stream, 1); 959 if (ret < 0) 960 goto unlock; 961 962 mipi_csis_log_counters(csis, true); 963 964 csis->state |= ST_STREAMING; 965 } else { 966 v4l2_subdev_call(csis->src_sd, video, s_stream, 0); 967 968 mipi_csis_stop_stream(csis); 969 csis->state &= ~ST_STREAMING; 970 if (csis->debug.enable) 971 mipi_csis_log_counters(csis, true); 972 } 973 974 unlock: 975 mutex_unlock(&csis->lock); 976 977 if (!enable || ret < 0) 978 pm_runtime_put(csis->dev); 979 980 return ret; 981 } 982 983 static struct v4l2_mbus_framefmt * 984 mipi_csis_get_format(struct mipi_csis_device *csis, 985 struct v4l2_subdev_state *sd_state, 986 enum v4l2_subdev_format_whence which, 987 unsigned int pad) 988 { 989 if (which == V4L2_SUBDEV_FORMAT_TRY) 990 return v4l2_subdev_get_try_format(&csis->sd, sd_state, pad); 991 992 return &csis->format_mbus[pad]; 993 } 994 995 static int mipi_csis_init_cfg(struct v4l2_subdev *sd, 996 struct v4l2_subdev_state *sd_state) 997 { 998 struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd); 999 struct v4l2_mbus_framefmt *fmt_sink; 1000 struct v4l2_mbus_framefmt *fmt_source; 1001 enum v4l2_subdev_format_whence which; 1002 1003 which = sd_state ? V4L2_SUBDEV_FORMAT_TRY : V4L2_SUBDEV_FORMAT_ACTIVE; 1004 fmt_sink = mipi_csis_get_format(csis, sd_state, which, CSIS_PAD_SINK); 1005 1006 fmt_sink->code = MEDIA_BUS_FMT_UYVY8_1X16; 1007 fmt_sink->width = MIPI_CSIS_DEF_PIX_WIDTH; 1008 fmt_sink->height = MIPI_CSIS_DEF_PIX_HEIGHT; 1009 fmt_sink->field = V4L2_FIELD_NONE; 1010 1011 fmt_sink->colorspace = V4L2_COLORSPACE_SMPTE170M; 1012 fmt_sink->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(fmt_sink->colorspace); 1013 fmt_sink->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(fmt_sink->colorspace); 1014 fmt_sink->quantization = 1015 V4L2_MAP_QUANTIZATION_DEFAULT(false, fmt_sink->colorspace, 1016 fmt_sink->ycbcr_enc); 1017 1018 /* 1019 * When called from mipi_csis_subdev_init() to initialize the active 1020 * configuration, cfg is NULL, which indicates there's no source pad 1021 * configuration to set. 1022 */ 1023 if (!sd_state) 1024 return 0; 1025 1026 fmt_source = mipi_csis_get_format(csis, sd_state, which, 1027 CSIS_PAD_SOURCE); 1028 *fmt_source = *fmt_sink; 1029 1030 return 0; 1031 } 1032 1033 static int mipi_csis_get_fmt(struct v4l2_subdev *sd, 1034 struct v4l2_subdev_state *sd_state, 1035 struct v4l2_subdev_format *sdformat) 1036 { 1037 struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd); 1038 struct v4l2_mbus_framefmt *fmt; 1039 1040 fmt = mipi_csis_get_format(csis, sd_state, sdformat->which, 1041 sdformat->pad); 1042 1043 mutex_lock(&csis->lock); 1044 sdformat->format = *fmt; 1045 mutex_unlock(&csis->lock); 1046 1047 return 0; 1048 } 1049 1050 static int mipi_csis_enum_mbus_code(struct v4l2_subdev *sd, 1051 struct v4l2_subdev_state *sd_state, 1052 struct v4l2_subdev_mbus_code_enum *code) 1053 { 1054 struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd); 1055 1056 /* 1057 * The CSIS can't transcode in any way, the source format is identical 1058 * to the sink format. 1059 */ 1060 if (code->pad == CSIS_PAD_SOURCE) { 1061 struct v4l2_mbus_framefmt *fmt; 1062 1063 if (code->index > 0) 1064 return -EINVAL; 1065 1066 fmt = mipi_csis_get_format(csis, sd_state, code->which, 1067 code->pad); 1068 code->code = fmt->code; 1069 return 0; 1070 } 1071 1072 if (code->pad != CSIS_PAD_SINK) 1073 return -EINVAL; 1074 1075 if (code->index >= ARRAY_SIZE(mipi_csis_formats)) 1076 return -EINVAL; 1077 1078 code->code = mipi_csis_formats[code->index].code; 1079 1080 return 0; 1081 } 1082 1083 static int mipi_csis_set_fmt(struct v4l2_subdev *sd, 1084 struct v4l2_subdev_state *sd_state, 1085 struct v4l2_subdev_format *sdformat) 1086 { 1087 struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd); 1088 struct csis_pix_format const *csis_fmt; 1089 struct v4l2_mbus_framefmt *fmt; 1090 unsigned int align; 1091 1092 /* 1093 * The CSIS can't transcode in any way, the source format can't be 1094 * modified. 1095 */ 1096 if (sdformat->pad == CSIS_PAD_SOURCE) 1097 return mipi_csis_get_fmt(sd, sd_state, sdformat); 1098 1099 if (sdformat->pad != CSIS_PAD_SINK) 1100 return -EINVAL; 1101 1102 /* 1103 * Validate the media bus code and clamp and align the size. 1104 * 1105 * The total number of bits per line must be a multiple of 8. We thus 1106 * need to align the width for formats that are not multiples of 8 1107 * bits. 1108 */ 1109 csis_fmt = find_csis_format(sdformat->format.code); 1110 if (!csis_fmt) 1111 csis_fmt = &mipi_csis_formats[0]; 1112 1113 switch (csis_fmt->width % 8) { 1114 case 0: 1115 align = 0; 1116 break; 1117 case 4: 1118 align = 1; 1119 break; 1120 case 2: 1121 case 6: 1122 align = 2; 1123 break; 1124 default: 1125 /* 1, 3, 5, 7 */ 1126 align = 3; 1127 break; 1128 } 1129 1130 v4l_bound_align_image(&sdformat->format.width, 1, 1131 CSIS_MAX_PIX_WIDTH, align, 1132 &sdformat->format.height, 1, 1133 CSIS_MAX_PIX_HEIGHT, 0, 0); 1134 1135 fmt = mipi_csis_get_format(csis, sd_state, sdformat->which, 1136 sdformat->pad); 1137 1138 mutex_lock(&csis->lock); 1139 1140 fmt->code = csis_fmt->code; 1141 fmt->width = sdformat->format.width; 1142 fmt->height = sdformat->format.height; 1143 fmt->colorspace = sdformat->format.colorspace; 1144 fmt->quantization = sdformat->format.quantization; 1145 fmt->xfer_func = sdformat->format.xfer_func; 1146 fmt->ycbcr_enc = sdformat->format.ycbcr_enc; 1147 1148 sdformat->format = *fmt; 1149 1150 /* Propagate the format from sink to source. */ 1151 fmt = mipi_csis_get_format(csis, sd_state, sdformat->which, 1152 CSIS_PAD_SOURCE); 1153 *fmt = sdformat->format; 1154 1155 /* The format on the source pad might change due to unpacking. */ 1156 fmt->code = csis_fmt->output; 1157 1158 /* Store the CSIS format descriptor for active formats. */ 1159 if (sdformat->which == V4L2_SUBDEV_FORMAT_ACTIVE) 1160 csis->csis_fmt = csis_fmt; 1161 1162 mutex_unlock(&csis->lock); 1163 1164 return 0; 1165 } 1166 1167 static int mipi_csis_log_status(struct v4l2_subdev *sd) 1168 { 1169 struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd); 1170 1171 mutex_lock(&csis->lock); 1172 mipi_csis_log_counters(csis, true); 1173 if (csis->debug.enable && (csis->state & ST_POWERED)) 1174 mipi_csis_dump_regs(csis); 1175 mutex_unlock(&csis->lock); 1176 1177 return 0; 1178 } 1179 1180 static const struct v4l2_subdev_core_ops mipi_csis_core_ops = { 1181 .log_status = mipi_csis_log_status, 1182 }; 1183 1184 static const struct v4l2_subdev_video_ops mipi_csis_video_ops = { 1185 .s_stream = mipi_csis_s_stream, 1186 }; 1187 1188 static const struct v4l2_subdev_pad_ops mipi_csis_pad_ops = { 1189 .init_cfg = mipi_csis_init_cfg, 1190 .enum_mbus_code = mipi_csis_enum_mbus_code, 1191 .get_fmt = mipi_csis_get_fmt, 1192 .set_fmt = mipi_csis_set_fmt, 1193 }; 1194 1195 static const struct v4l2_subdev_ops mipi_csis_subdev_ops = { 1196 .core = &mipi_csis_core_ops, 1197 .video = &mipi_csis_video_ops, 1198 .pad = &mipi_csis_pad_ops, 1199 }; 1200 1201 /* ----------------------------------------------------------------------------- 1202 * Media entity operations 1203 */ 1204 1205 static int mipi_csis_link_setup(struct media_entity *entity, 1206 const struct media_pad *local_pad, 1207 const struct media_pad *remote_pad, u32 flags) 1208 { 1209 struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity); 1210 struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd); 1211 struct v4l2_subdev *remote_sd; 1212 1213 dev_dbg(csis->dev, "link setup %s -> %s", remote_pad->entity->name, 1214 local_pad->entity->name); 1215 1216 /* We only care about the link to the source. */ 1217 if (!(local_pad->flags & MEDIA_PAD_FL_SINK)) 1218 return 0; 1219 1220 remote_sd = media_entity_to_v4l2_subdev(remote_pad->entity); 1221 1222 if (flags & MEDIA_LNK_FL_ENABLED) { 1223 if (csis->src_sd) 1224 return -EBUSY; 1225 1226 csis->src_sd = remote_sd; 1227 } else { 1228 csis->src_sd = NULL; 1229 } 1230 1231 return 0; 1232 } 1233 1234 static const struct media_entity_operations mipi_csis_entity_ops = { 1235 .link_setup = mipi_csis_link_setup, 1236 .link_validate = v4l2_subdev_link_validate, 1237 .get_fwnode_pad = v4l2_subdev_get_fwnode_pad_1_to_1, 1238 }; 1239 1240 /* ----------------------------------------------------------------------------- 1241 * Async subdev notifier 1242 */ 1243 1244 static struct mipi_csis_device * 1245 mipi_notifier_to_csis_state(struct v4l2_async_notifier *n) 1246 { 1247 return container_of(n, struct mipi_csis_device, notifier); 1248 } 1249 1250 static int mipi_csis_notify_bound(struct v4l2_async_notifier *notifier, 1251 struct v4l2_subdev *sd, 1252 struct v4l2_async_subdev *asd) 1253 { 1254 struct mipi_csis_device *csis = mipi_notifier_to_csis_state(notifier); 1255 struct media_pad *sink = &csis->sd.entity.pads[CSIS_PAD_SINK]; 1256 1257 return v4l2_create_fwnode_links_to_pad(sd, sink, 0); 1258 } 1259 1260 static const struct v4l2_async_notifier_operations mipi_csis_notify_ops = { 1261 .bound = mipi_csis_notify_bound, 1262 }; 1263 1264 static int mipi_csis_async_register(struct mipi_csis_device *csis) 1265 { 1266 struct v4l2_fwnode_endpoint vep = { 1267 .bus_type = V4L2_MBUS_CSI2_DPHY, 1268 }; 1269 struct v4l2_async_subdev *asd; 1270 struct fwnode_handle *ep; 1271 unsigned int i; 1272 int ret; 1273 1274 v4l2_async_nf_init(&csis->notifier); 1275 1276 ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(csis->dev), 0, 0, 1277 FWNODE_GRAPH_ENDPOINT_NEXT); 1278 if (!ep) 1279 return -ENOTCONN; 1280 1281 ret = v4l2_fwnode_endpoint_parse(ep, &vep); 1282 if (ret) 1283 goto err_parse; 1284 1285 for (i = 0; i < vep.bus.mipi_csi2.num_data_lanes; ++i) { 1286 if (vep.bus.mipi_csi2.data_lanes[i] != i + 1) { 1287 dev_err(csis->dev, 1288 "data lanes reordering is not supported"); 1289 ret = -EINVAL; 1290 goto err_parse; 1291 } 1292 } 1293 1294 csis->bus = vep.bus.mipi_csi2; 1295 1296 dev_dbg(csis->dev, "data lanes: %d\n", csis->bus.num_data_lanes); 1297 dev_dbg(csis->dev, "flags: 0x%08x\n", csis->bus.flags); 1298 1299 asd = v4l2_async_nf_add_fwnode_remote(&csis->notifier, ep, 1300 struct v4l2_async_subdev); 1301 if (IS_ERR(asd)) { 1302 ret = PTR_ERR(asd); 1303 goto err_parse; 1304 } 1305 1306 fwnode_handle_put(ep); 1307 1308 csis->notifier.ops = &mipi_csis_notify_ops; 1309 1310 ret = v4l2_async_subdev_nf_register(&csis->sd, &csis->notifier); 1311 if (ret) 1312 return ret; 1313 1314 return v4l2_async_register_subdev(&csis->sd); 1315 1316 err_parse: 1317 fwnode_handle_put(ep); 1318 1319 return ret; 1320 } 1321 1322 /* ----------------------------------------------------------------------------- 1323 * Suspend/resume 1324 */ 1325 1326 static int mipi_csis_pm_suspend(struct device *dev, bool runtime) 1327 { 1328 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1329 struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd); 1330 int ret = 0; 1331 1332 mutex_lock(&csis->lock); 1333 if (csis->state & ST_POWERED) { 1334 mipi_csis_stop_stream(csis); 1335 ret = mipi_csis_phy_disable(csis); 1336 if (ret) 1337 goto unlock; 1338 mipi_csis_clk_disable(csis); 1339 csis->state &= ~ST_POWERED; 1340 if (!runtime) 1341 csis->state |= ST_SUSPENDED; 1342 } 1343 1344 unlock: 1345 mutex_unlock(&csis->lock); 1346 1347 return ret ? -EAGAIN : 0; 1348 } 1349 1350 static int mipi_csis_pm_resume(struct device *dev, bool runtime) 1351 { 1352 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1353 struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd); 1354 int ret = 0; 1355 1356 mutex_lock(&csis->lock); 1357 if (!runtime && !(csis->state & ST_SUSPENDED)) 1358 goto unlock; 1359 1360 if (!(csis->state & ST_POWERED)) { 1361 ret = mipi_csis_phy_enable(csis); 1362 if (ret) 1363 goto unlock; 1364 1365 csis->state |= ST_POWERED; 1366 mipi_csis_clk_enable(csis); 1367 } 1368 if (csis->state & ST_STREAMING) 1369 mipi_csis_start_stream(csis); 1370 1371 csis->state &= ~ST_SUSPENDED; 1372 1373 unlock: 1374 mutex_unlock(&csis->lock); 1375 1376 return ret ? -EAGAIN : 0; 1377 } 1378 1379 static int __maybe_unused mipi_csis_suspend(struct device *dev) 1380 { 1381 return mipi_csis_pm_suspend(dev, false); 1382 } 1383 1384 static int __maybe_unused mipi_csis_resume(struct device *dev) 1385 { 1386 return mipi_csis_pm_resume(dev, false); 1387 } 1388 1389 static int __maybe_unused mipi_csis_runtime_suspend(struct device *dev) 1390 { 1391 return mipi_csis_pm_suspend(dev, true); 1392 } 1393 1394 static int __maybe_unused mipi_csis_runtime_resume(struct device *dev) 1395 { 1396 return mipi_csis_pm_resume(dev, true); 1397 } 1398 1399 static const struct dev_pm_ops mipi_csis_pm_ops = { 1400 SET_RUNTIME_PM_OPS(mipi_csis_runtime_suspend, mipi_csis_runtime_resume, 1401 NULL) 1402 SET_SYSTEM_SLEEP_PM_OPS(mipi_csis_suspend, mipi_csis_resume) 1403 }; 1404 1405 /* ----------------------------------------------------------------------------- 1406 * Probe/remove & platform driver 1407 */ 1408 1409 static int mipi_csis_subdev_init(struct mipi_csis_device *csis) 1410 { 1411 struct v4l2_subdev *sd = &csis->sd; 1412 1413 v4l2_subdev_init(sd, &mipi_csis_subdev_ops); 1414 sd->owner = THIS_MODULE; 1415 snprintf(sd->name, sizeof(sd->name), "csis-%s", 1416 dev_name(csis->dev)); 1417 1418 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 1419 sd->ctrl_handler = NULL; 1420 1421 sd->entity.function = MEDIA_ENT_F_VID_IF_BRIDGE; 1422 sd->entity.ops = &mipi_csis_entity_ops; 1423 1424 sd->dev = csis->dev; 1425 1426 csis->csis_fmt = &mipi_csis_formats[0]; 1427 mipi_csis_init_cfg(sd, NULL); 1428 1429 csis->pads[CSIS_PAD_SINK].flags = MEDIA_PAD_FL_SINK 1430 | MEDIA_PAD_FL_MUST_CONNECT; 1431 csis->pads[CSIS_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE 1432 | MEDIA_PAD_FL_MUST_CONNECT; 1433 return media_entity_pads_init(&sd->entity, CSIS_PADS_NUM, 1434 csis->pads); 1435 } 1436 1437 static int mipi_csis_parse_dt(struct mipi_csis_device *csis) 1438 { 1439 struct device_node *node = csis->dev->of_node; 1440 1441 if (of_property_read_u32(node, "clock-frequency", 1442 &csis->clk_frequency)) 1443 csis->clk_frequency = DEFAULT_SCLK_CSIS_FREQ; 1444 1445 return 0; 1446 } 1447 1448 static int mipi_csis_probe(struct platform_device *pdev) 1449 { 1450 struct device *dev = &pdev->dev; 1451 struct mipi_csis_device *csis; 1452 int irq; 1453 int ret; 1454 1455 csis = devm_kzalloc(dev, sizeof(*csis), GFP_KERNEL); 1456 if (!csis) 1457 return -ENOMEM; 1458 1459 mutex_init(&csis->lock); 1460 spin_lock_init(&csis->slock); 1461 1462 csis->dev = dev; 1463 csis->info = of_device_get_match_data(dev); 1464 1465 memcpy(csis->events, mipi_csis_events, sizeof(csis->events)); 1466 1467 /* Parse DT properties. */ 1468 ret = mipi_csis_parse_dt(csis); 1469 if (ret < 0) { 1470 dev_err(dev, "Failed to parse device tree: %d\n", ret); 1471 return ret; 1472 } 1473 1474 /* Acquire resources. */ 1475 csis->regs = devm_platform_ioremap_resource(pdev, 0); 1476 if (IS_ERR(csis->regs)) 1477 return PTR_ERR(csis->regs); 1478 1479 irq = platform_get_irq(pdev, 0); 1480 if (irq < 0) 1481 return irq; 1482 1483 ret = mipi_csis_phy_init(csis); 1484 if (ret < 0) 1485 return ret; 1486 1487 ret = mipi_csis_clk_get(csis); 1488 if (ret < 0) 1489 return ret; 1490 1491 /* Reset PHY and enable the clocks. */ 1492 mipi_csis_phy_reset(csis); 1493 1494 ret = mipi_csis_clk_enable(csis); 1495 if (ret < 0) { 1496 dev_err(csis->dev, "failed to enable clocks: %d\n", ret); 1497 return ret; 1498 } 1499 1500 /* Now that the hardware is initialized, request the interrupt. */ 1501 ret = devm_request_irq(dev, irq, mipi_csis_irq_handler, 0, 1502 dev_name(dev), csis); 1503 if (ret) { 1504 dev_err(dev, "Interrupt request failed\n"); 1505 goto disable_clock; 1506 } 1507 1508 /* Initialize and register the subdev. */ 1509 ret = mipi_csis_subdev_init(csis); 1510 if (ret < 0) 1511 goto disable_clock; 1512 1513 platform_set_drvdata(pdev, &csis->sd); 1514 1515 ret = mipi_csis_async_register(csis); 1516 if (ret < 0) { 1517 dev_err(dev, "async register failed: %d\n", ret); 1518 goto cleanup; 1519 } 1520 1521 /* Initialize debugfs. */ 1522 mipi_csis_debugfs_init(csis); 1523 1524 /* Enable runtime PM. */ 1525 pm_runtime_enable(dev); 1526 if (!pm_runtime_enabled(dev)) { 1527 ret = mipi_csis_pm_resume(dev, true); 1528 if (ret < 0) 1529 goto unregister_all; 1530 } 1531 1532 dev_info(dev, "lanes: %d, freq: %u\n", 1533 csis->bus.num_data_lanes, csis->clk_frequency); 1534 1535 return 0; 1536 1537 unregister_all: 1538 mipi_csis_debugfs_exit(csis); 1539 cleanup: 1540 media_entity_cleanup(&csis->sd.entity); 1541 v4l2_async_nf_unregister(&csis->notifier); 1542 v4l2_async_nf_cleanup(&csis->notifier); 1543 v4l2_async_unregister_subdev(&csis->sd); 1544 disable_clock: 1545 mipi_csis_clk_disable(csis); 1546 mutex_destroy(&csis->lock); 1547 1548 return ret; 1549 } 1550 1551 static int mipi_csis_remove(struct platform_device *pdev) 1552 { 1553 struct v4l2_subdev *sd = platform_get_drvdata(pdev); 1554 struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd); 1555 1556 mipi_csis_debugfs_exit(csis); 1557 v4l2_async_nf_unregister(&csis->notifier); 1558 v4l2_async_nf_cleanup(&csis->notifier); 1559 v4l2_async_unregister_subdev(&csis->sd); 1560 1561 pm_runtime_disable(&pdev->dev); 1562 mipi_csis_pm_suspend(&pdev->dev, true); 1563 mipi_csis_clk_disable(csis); 1564 media_entity_cleanup(&csis->sd.entity); 1565 mutex_destroy(&csis->lock); 1566 pm_runtime_set_suspended(&pdev->dev); 1567 1568 return 0; 1569 } 1570 1571 static const struct of_device_id mipi_csis_of_match[] = { 1572 { 1573 .compatible = "fsl,imx7-mipi-csi2", 1574 .data = &(const struct mipi_csis_info){ 1575 .version = MIPI_CSIS_V3_3, 1576 .num_clocks = 3, 1577 }, 1578 }, { 1579 .compatible = "fsl,imx8mm-mipi-csi2", 1580 .data = &(const struct mipi_csis_info){ 1581 .version = MIPI_CSIS_V3_6_3, 1582 .num_clocks = 4, 1583 }, 1584 }, 1585 { /* sentinel */ }, 1586 }; 1587 MODULE_DEVICE_TABLE(of, mipi_csis_of_match); 1588 1589 static struct platform_driver mipi_csis_driver = { 1590 .probe = mipi_csis_probe, 1591 .remove = mipi_csis_remove, 1592 .driver = { 1593 .of_match_table = mipi_csis_of_match, 1594 .name = CSIS_DRIVER_NAME, 1595 .pm = &mipi_csis_pm_ops, 1596 }, 1597 }; 1598 1599 module_platform_driver(mipi_csis_driver); 1600 1601 MODULE_DESCRIPTION("i.MX7 & i.MX8 MIPI CSI-2 receiver driver"); 1602 MODULE_LICENSE("GPL v2"); 1603 MODULE_ALIAS("platform:imx-mipi-csi2"); 1604