1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * i.MX8QXP/i.MX8QM JPEG encoder/decoder v4l2 driver 4 * 5 * Copyright 2018-2019 NXP 6 */ 7 8 #ifndef _MXC_JPEG_HW_H 9 #define _MXC_JPEG_HW_H 10 11 /* JPEG Decoder/Encoder Wrapper Register Map */ 12 #define GLB_CTRL 0x0 13 #define COM_STATUS 0x4 14 #define BUF_BASE0 0x14 15 #define BUF_BASE1 0x18 16 #define LINE_PITCH 0x1C 17 #define STM_BUFBASE 0x20 18 #define STM_BUFSIZE 0x24 19 #define IMGSIZE 0x28 20 #define STM_CTRL 0x2C 21 22 /* CAST JPEG-Decoder/Encoder Status Register Map (read-only)*/ 23 #define CAST_STATUS0 0x100 24 #define CAST_STATUS1 0x104 25 #define CAST_STATUS2 0x108 26 #define CAST_STATUS3 0x10c 27 #define CAST_STATUS4 0x110 28 #define CAST_STATUS5 0x114 29 #define CAST_STATUS6 0x118 30 #define CAST_STATUS7 0x11c 31 #define CAST_STATUS8 0x120 32 #define CAST_STATUS9 0x124 33 #define CAST_STATUS10 0x128 34 #define CAST_STATUS11 0x12c 35 #define CAST_STATUS12 0x130 36 #define CAST_STATUS13 0x134 37 /* the following are for encoder only */ 38 #define CAST_STATUS14 0x138 39 #define CAST_STATUS15 0x13c 40 #define CAST_STATUS16 0x140 41 #define CAST_STATUS17 0x144 42 #define CAST_STATUS18 0x148 43 #define CAST_STATUS19 0x14c 44 45 /* CAST JPEG-Decoder Control Register Map (write-only) */ 46 #define CAST_CTRL CAST_STATUS13 47 48 /* CAST JPEG-Encoder Control Register Map (write-only) */ 49 #define CAST_MODE CAST_STATUS0 50 #define CAST_CFG_MODE CAST_STATUS1 51 #define CAST_QUALITY CAST_STATUS2 52 #define CAST_RSVD CAST_STATUS3 53 #define CAST_REC_REGS_SEL CAST_STATUS4 54 #define CAST_LUMTH CAST_STATUS5 55 #define CAST_CHRTH CAST_STATUS6 56 #define CAST_NOMFRSIZE_LO CAST_STATUS7 57 #define CAST_NOMFRSIZE_HI CAST_STATUS8 58 #define CAST_OFBSIZE_LO CAST_STATUS9 59 #define CAST_OFBSIZE_HI CAST_STATUS10 60 61 #define MXC_MAX_SLOTS 1 /* TODO use all 4 slots*/ 62 /* JPEG-Decoder Wrapper Slot Registers 0..3 */ 63 #define SLOT_BASE 0x10000 64 #define SLOT_STATUS 0x0 65 #define SLOT_IRQ_EN 0x4 66 #define SLOT_BUF_PTR 0x8 67 #define SLOT_CUR_DESCPT_PTR 0xC 68 #define SLOT_NXT_DESCPT_PTR 0x10 69 #define MXC_SLOT_OFFSET(slot, offset) ((SLOT_BASE * ((slot) + 1)) + (offset)) 70 71 /* GLB_CTRL fields */ 72 #define GLB_CTRL_JPG_EN 0x1 73 #define GLB_CTRL_SFT_RST (0x1 << 1) 74 #define GLB_CTRL_DEC_GO (0x1 << 2) 75 #define GLB_CTRL_L_ENDIAN(le) ((le) << 3) 76 #define GLB_CTRL_SLOT_EN(slot) (0x1 << ((slot) + 4)) 77 78 /* COM_STAUS fields */ 79 #define COM_STATUS_DEC_ONGOING(r) (((r) & (1 << 31)) >> 31) 80 #define COM_STATUS_CUR_SLOT(r) (((r) & (0x3 << 29)) >> 29) 81 82 /* STM_CTRL fields */ 83 #define STM_CTRL_PIXEL_PRECISION (0x1 << 2) 84 #define STM_CTRL_IMAGE_FORMAT(img_fmt) ((img_fmt) << 3) 85 #define STM_CTRL_IMAGE_FORMAT_MASK (0xF << 3) 86 #define STM_CTRL_BITBUF_PTR_CLR(clr) ((clr) << 7) 87 #define STM_CTRL_AUTO_START(go) ((go) << 8) 88 #define STM_CTRL_CONFIG_MOD(mod) ((mod) << 9) 89 90 /* SLOT_STATUS fields for slots 0..3 */ 91 #define SLOT_STATUS_FRMDONE (0x1 << 3) 92 #define SLOT_STATUS_ENC_CONFIG_ERR (0x1 << 8) 93 94 /* SLOT_IRQ_EN fields TBD */ 95 96 #define MXC_NXT_DESCPT_EN 0x1 97 #define MXC_DEC_EXIT_IDLE_MODE 0x4 98 99 /* JPEG-Decoder Wrapper - STM_CTRL Register Fields */ 100 #define MXC_PIXEL_PRECISION(precision) ((precision) / 8 << 2) 101 enum mxc_jpeg_image_format { 102 MXC_JPEG_INVALID = -1, 103 MXC_JPEG_YUV420 = 0x0, /* 2 Plannar, Y=1st plane UV=2nd plane */ 104 MXC_JPEG_YUV422 = 0x1, /* 1 Plannar, YUYV sequence */ 105 MXC_JPEG_BGR = 0x2, /* BGR packed format */ 106 MXC_JPEG_YUV444 = 0x3, /* 1 Plannar, YUVYUV sequence */ 107 MXC_JPEG_GRAY = 0x4, /* Y8 or Y12 or Single Component */ 108 MXC_JPEG_RESERVED = 0x5, 109 MXC_JPEG_ABGR = 0x6, 110 }; 111 112 #include "mxc-jpeg.h" 113 void print_descriptor_info(struct device *dev, struct mxc_jpeg_desc *desc); 114 void print_cast_status(struct device *dev, void __iomem *reg, 115 unsigned int mode); 116 void print_wrapper_info(struct device *dev, void __iomem *reg); 117 void mxc_jpeg_sw_reset(void __iomem *reg); 118 int mxc_jpeg_enable(void __iomem *reg); 119 void wait_frmdone(struct device *dev, void __iomem *reg); 120 void mxc_jpeg_enc_mode_conf(struct device *dev, void __iomem *reg); 121 void mxc_jpeg_enc_mode_go(struct device *dev, void __iomem *reg); 122 void mxc_jpeg_dec_mode_go(struct device *dev, void __iomem *reg); 123 int mxc_jpeg_get_slot(void __iomem *reg); 124 u32 mxc_jpeg_get_offset(void __iomem *reg, int slot); 125 void mxc_jpeg_enable_slot(void __iomem *reg, int slot); 126 void mxc_jpeg_set_l_endian(void __iomem *reg, int le); 127 void mxc_jpeg_enable_irq(void __iomem *reg, int slot); 128 int mxc_jpeg_set_input(void __iomem *reg, u32 in_buf, u32 bufsize); 129 int mxc_jpeg_set_output(void __iomem *reg, u16 out_pitch, u32 out_buf, 130 u16 w, u16 h); 131 void mxc_jpeg_set_config_mode(void __iomem *reg, int config_mode); 132 int mxc_jpeg_set_params(struct mxc_jpeg_desc *desc, u32 bufsize, u16 133 out_pitch, u32 format); 134 void mxc_jpeg_set_bufsize(struct mxc_jpeg_desc *desc, u32 bufsize); 135 void mxc_jpeg_set_res(struct mxc_jpeg_desc *desc, u16 w, u16 h); 136 void mxc_jpeg_set_line_pitch(struct mxc_jpeg_desc *desc, u32 line_pitch); 137 void mxc_jpeg_set_desc(u32 desc, void __iomem *reg, int slot); 138 void mxc_jpeg_set_regs_from_desc(struct mxc_jpeg_desc *desc, 139 void __iomem *reg); 140 #endif 141