10c6dfa75SMarvin Lin /* SPDX-License-Identifier: GPL-2.0 */ 20c6dfa75SMarvin Lin /* 30c6dfa75SMarvin Lin * Register definition header for NPCM video driver 40c6dfa75SMarvin Lin * 50c6dfa75SMarvin Lin * Copyright (C) 2022 Nuvoton Technologies 60c6dfa75SMarvin Lin */ 70c6dfa75SMarvin Lin 80c6dfa75SMarvin Lin #ifndef _NPCM_REGS_H 90c6dfa75SMarvin Lin #define _NPCM_REGS_H 100c6dfa75SMarvin Lin 110c6dfa75SMarvin Lin /* VCD Registers */ 120c6dfa75SMarvin Lin #define VCD_DIFF_TBL 0x0000 130c6dfa75SMarvin Lin #define VCD_FBA_ADR 0x8000 140c6dfa75SMarvin Lin #define VCD_FBB_ADR 0x8004 150c6dfa75SMarvin Lin 160c6dfa75SMarvin Lin #define VCD_FB_LP 0x8008 170c6dfa75SMarvin Lin #define VCD_FBA_LP GENMASK(15, 0) 180c6dfa75SMarvin Lin #define VCD_FBB_LP GENMASK(31, 16) 190c6dfa75SMarvin Lin 200c6dfa75SMarvin Lin #define VCD_CAP_RES 0x800c 210c6dfa75SMarvin Lin #define VCD_CAP_RES_VERT_RES GENMASK(10, 0) 220c6dfa75SMarvin Lin #define VCD_CAP_RES_HOR_RES GENMASK(26, 16) 230c6dfa75SMarvin Lin 240c6dfa75SMarvin Lin #define VCD_MODE 0x8014 250c6dfa75SMarvin Lin #define VCD_MODE_VCDE BIT(0) 260c6dfa75SMarvin Lin #define VCD_MODE_CM565 BIT(1) 270c6dfa75SMarvin Lin #define VCD_MODE_IDBC BIT(3) 280c6dfa75SMarvin Lin #define VCD_MODE_KVM_BW_SET BIT(16) 290c6dfa75SMarvin Lin 300c6dfa75SMarvin Lin #define VCD_CMD 0x8018 310c6dfa75SMarvin Lin #define VCD_CMD_GO BIT(0) 320c6dfa75SMarvin Lin #define VCD_CMD_RST BIT(1) 330c6dfa75SMarvin Lin #define VCD_CMD_OPERATION GENMASK(6, 4) 340c6dfa75SMarvin Lin #define VCD_CMD_OPERATION_CAPTURE 0 350c6dfa75SMarvin Lin #define VCD_CMD_OPERATION_COMPARE 2 360c6dfa75SMarvin Lin 370c6dfa75SMarvin Lin #define VCD_STAT 0x801c 380c6dfa75SMarvin Lin #define VCD_STAT_DONE BIT(0) 390c6dfa75SMarvin Lin #define VCD_STAT_IFOT BIT(2) 400c6dfa75SMarvin Lin #define VCD_STAT_IFOR BIT(3) 410c6dfa75SMarvin Lin #define VCD_STAT_VHT_CHG BIT(5) 420c6dfa75SMarvin Lin #define VCD_STAT_HAC_CHG BIT(8) 430c6dfa75SMarvin Lin #define VCD_STAT_BUSY BIT(30) 440c6dfa75SMarvin Lin #define VCD_STAT_CLEAR 0x3fff 450c6dfa75SMarvin Lin 460c6dfa75SMarvin Lin #define VCD_INTE 0x8020 470c6dfa75SMarvin Lin #define VCD_INTE_DONE_IE BIT(0) 480c6dfa75SMarvin Lin #define VCD_INTE_IFOT_IE BIT(2) 490c6dfa75SMarvin Lin #define VCD_INTE_IFOR_IE BIT(3) 500c6dfa75SMarvin Lin #define VCD_INTE_VHT_IE BIT(5) 510c6dfa75SMarvin Lin #define VCD_INTE_HAC_IE BIT(8) 520c6dfa75SMarvin Lin 530c6dfa75SMarvin Lin #define VCD_RCHG 0x8028 540c6dfa75SMarvin Lin #define VCD_RCHG_IG_CHG0 GENMASK(2, 0) 550c6dfa75SMarvin Lin #define VCD_RCHG_TIM_PRSCL GENMASK(12, 9) 560c6dfa75SMarvin Lin 570c6dfa75SMarvin Lin #define VCD_VER_HI_TIM 0x8044 580c6dfa75SMarvin Lin #define VCD_VER_HI_TIME GENMASK(23, 0) 590c6dfa75SMarvin Lin 600c6dfa75SMarvin Lin #define VCD_VER_HI_LST 0x8048 610c6dfa75SMarvin Lin #define VCD_VER_HI_LAST GENMASK(23, 0) 620c6dfa75SMarvin Lin 630c6dfa75SMarvin Lin #define VCD_HOR_AC_TIM 0x804c 640c6dfa75SMarvin Lin #define VCD_HOR_AC_TIME GENMASK(13, 0) 650c6dfa75SMarvin Lin 660c6dfa75SMarvin Lin #define VCD_HOR_AC_LST 0x8050 670c6dfa75SMarvin Lin #define VCD_HOR_AC_LAST GENMASK(13, 0) 680c6dfa75SMarvin Lin 690c6dfa75SMarvin Lin #define VCD_FIFO 0x805c 700c6dfa75SMarvin Lin #define VCD_FIFO_TH 0x100350ff 710c6dfa75SMarvin Lin 720c6dfa75SMarvin Lin #define VCD_FB_SIZE 0x500000 /* support up to 1920 x 1200 */ 730c6dfa75SMarvin Lin #define VCD_KVM_BW_PCLK 120000000UL 740c6dfa75SMarvin Lin #define VCD_TIMEOUT_US 300000 750c6dfa75SMarvin Lin 760c6dfa75SMarvin Lin /* ECE Registers */ 770c6dfa75SMarvin Lin #define ECE_DDA_CTRL 0x0000 780c6dfa75SMarvin Lin #define ECE_DDA_CTRL_ECEEN BIT(0) 790c6dfa75SMarvin Lin #define ECE_DDA_CTRL_INTEN BIT(8) 800c6dfa75SMarvin Lin 810c6dfa75SMarvin Lin #define ECE_DDA_STS 0x0004 820c6dfa75SMarvin Lin #define ECE_DDA_STS_CDREADY BIT(8) 830c6dfa75SMarvin Lin #define ECE_DDA_STS_ACDRDY BIT(10) 840c6dfa75SMarvin Lin 850c6dfa75SMarvin Lin #define ECE_FBR_BA 0x0008 860c6dfa75SMarvin Lin #define ECE_ED_BA 0x000c 870c6dfa75SMarvin Lin #define ECE_RECT_XY 0x0010 880c6dfa75SMarvin Lin 890c6dfa75SMarvin Lin #define ECE_RECT_DIMEN 0x0014 900c6dfa75SMarvin Lin #define ECE_RECT_DIMEN_WR GENMASK(10, 0) 910c6dfa75SMarvin Lin #define ECE_RECT_DIMEN_WLTR GENMASK(14, 11) 920c6dfa75SMarvin Lin #define ECE_RECT_DIMEN_HR GENMASK(26, 16) 930c6dfa75SMarvin Lin #define ECE_RECT_DIMEN_HLTR GENMASK(30, 27) 940c6dfa75SMarvin Lin 950c6dfa75SMarvin Lin #define ECE_RESOL 0x001c 960c6dfa75SMarvin Lin #define ECE_RESOL_FB_LP_512 0 970c6dfa75SMarvin Lin #define ECE_RESOL_FB_LP_1024 1 980c6dfa75SMarvin Lin #define ECE_RESOL_FB_LP_2048 2 990c6dfa75SMarvin Lin #define ECE_RESOL_FB_LP_2560 3 1000c6dfa75SMarvin Lin #define ECE_RESOL_FB_LP_4096 4 1010c6dfa75SMarvin Lin 1020c6dfa75SMarvin Lin #define ECE_HEX_CTRL 0x0040 1030c6dfa75SMarvin Lin #define ECE_HEX_CTRL_ENCDIS BIT(0) 1040c6dfa75SMarvin Lin #define ECE_HEX_CTRL_ENC_GAP GENMASK(12, 8) 1050c6dfa75SMarvin Lin 1060c6dfa75SMarvin Lin #define ECE_HEX_RECT_OFFSET 0x0048 1070c6dfa75SMarvin Lin #define ECE_HEX_RECT_OFFSET_MASK GENMASK(22, 0) 1080c6dfa75SMarvin Lin 1090c6dfa75SMarvin Lin #define ECE_TILE_W 16 1100c6dfa75SMarvin Lin #define ECE_TILE_H 16 1110c6dfa75SMarvin Lin #define ECE_POLL_TIMEOUT_US 300000 1120c6dfa75SMarvin Lin 1130c6dfa75SMarvin Lin /* GCR Registers */ 1140c6dfa75SMarvin Lin #define INTCR 0x3c 1150c6dfa75SMarvin Lin #define INTCR_GFXIFDIS GENMASK(9, 8) 1160c6dfa75SMarvin Lin #define INTCR_DEHS BIT(27) 1170c6dfa75SMarvin Lin 1180c6dfa75SMarvin Lin #define INTCR2 0x60 1190c6dfa75SMarvin Lin #define INTCR2_GIRST2 BIT(2) 1200c6dfa75SMarvin Lin #define INTCR2_GIHCRST BIT(5) 1210c6dfa75SMarvin Lin #define INTCR2_GIVCRST BIT(6) 1220c6dfa75SMarvin Lin 1230c6dfa75SMarvin Lin /* GFXI Register */ 1240c6dfa75SMarvin Lin #define DISPST 0x00 1250c6dfa75SMarvin Lin #define DISPST_HSCROFF BIT(1) 1260c6dfa75SMarvin Lin #define DISPST_MGAMODE BIT(7) 1270c6dfa75SMarvin Lin 1280c6dfa75SMarvin Lin #define HVCNTL 0x10 1290c6dfa75SMarvin Lin #define HVCNTL_MASK GENMASK(7, 0) 1300c6dfa75SMarvin Lin 1310c6dfa75SMarvin Lin #define HVCNTH 0x14 1320c6dfa75SMarvin Lin #define HVCNTH_MASK GENMASK(2, 0) 1330c6dfa75SMarvin Lin 1340c6dfa75SMarvin Lin #define VVCNTL 0x20 1350c6dfa75SMarvin Lin #define VVCNTL_MASK GENMASK(7, 0) 1360c6dfa75SMarvin Lin 1370c6dfa75SMarvin Lin #define VVCNTH 0x24 1380c6dfa75SMarvin Lin #define VVCNTH_MASK GENMASK(2, 0) 1390c6dfa75SMarvin Lin 1400c6dfa75SMarvin Lin #define GPLLINDIV 0x40 1410c6dfa75SMarvin Lin #define GPLLINDIV_MASK GENMASK(5, 0) 1420c6dfa75SMarvin Lin #define GPLLINDIV_GPLLFBDV8 BIT(7) 1430c6dfa75SMarvin Lin 1440c6dfa75SMarvin Lin #define GPLLFBDIV 0x44 1450c6dfa75SMarvin Lin #define GPLLFBDIV_MASK GENMASK(7, 0) 1460c6dfa75SMarvin Lin 1470c6dfa75SMarvin Lin #define GPLLST 0x48 1480c6dfa75SMarvin Lin #define GPLLST_PLLOTDIV1 GENMASK(2, 0) 1490c6dfa75SMarvin Lin #define GPLLST_PLLOTDIV2 GENMASK(5, 3) 1500c6dfa75SMarvin Lin #define GPLLST_GPLLFBDV109 GENMASK(7, 6) 1510c6dfa75SMarvin Lin 1520c6dfa75SMarvin Lin #endif /* _NPCM_REGS_H */ 153