1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Microchip Image Sensor Controller (ISC) common driver base 4 * 5 * Copyright (C) 2016-2019 Microchip Technology, Inc. 6 * 7 * Author: Songjun Wu 8 * Author: Eugen Hristev <eugen.hristev@microchip.com> 9 * 10 */ 11 #include <linux/delay.h> 12 #include <linux/interrupt.h> 13 #include <linux/math64.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/of_graph.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/regmap.h> 20 #include <linux/videodev2.h> 21 #include <linux/atmel-isc-media.h> 22 23 #include <media/v4l2-ctrls.h> 24 #include <media/v4l2-device.h> 25 #include <media/v4l2-event.h> 26 #include <media/v4l2-image-sizes.h> 27 #include <media/v4l2-ioctl.h> 28 #include <media/v4l2-fwnode.h> 29 #include <media/v4l2-subdev.h> 30 #include <media/videobuf2-dma-contig.h> 31 32 #include "microchip-isc-regs.h" 33 #include "microchip-isc.h" 34 35 static unsigned int debug; 36 module_param(debug, int, 0644); 37 MODULE_PARM_DESC(debug, "debug level (0-2)"); 38 39 #define ISC_IS_FORMAT_RAW(mbus_code) \ 40 (((mbus_code) & 0xf000) == 0x3000) 41 42 #define ISC_IS_FORMAT_GREY(mbus_code) \ 43 (((mbus_code) == MEDIA_BUS_FMT_Y10_1X10) | \ 44 (((mbus_code) == MEDIA_BUS_FMT_Y8_1X8))) 45 46 static inline void isc_update_v4l2_ctrls(struct isc_device *isc) 47 { 48 struct isc_ctrls *ctrls = &isc->ctrls; 49 50 /* In here we set the v4l2 controls w.r.t. our pipeline config */ 51 v4l2_ctrl_s_ctrl(isc->r_gain_ctrl, ctrls->gain[ISC_HIS_CFG_MODE_R]); 52 v4l2_ctrl_s_ctrl(isc->b_gain_ctrl, ctrls->gain[ISC_HIS_CFG_MODE_B]); 53 v4l2_ctrl_s_ctrl(isc->gr_gain_ctrl, ctrls->gain[ISC_HIS_CFG_MODE_GR]); 54 v4l2_ctrl_s_ctrl(isc->gb_gain_ctrl, ctrls->gain[ISC_HIS_CFG_MODE_GB]); 55 56 v4l2_ctrl_s_ctrl(isc->r_off_ctrl, ctrls->offset[ISC_HIS_CFG_MODE_R]); 57 v4l2_ctrl_s_ctrl(isc->b_off_ctrl, ctrls->offset[ISC_HIS_CFG_MODE_B]); 58 v4l2_ctrl_s_ctrl(isc->gr_off_ctrl, ctrls->offset[ISC_HIS_CFG_MODE_GR]); 59 v4l2_ctrl_s_ctrl(isc->gb_off_ctrl, ctrls->offset[ISC_HIS_CFG_MODE_GB]); 60 } 61 62 static inline void isc_update_awb_ctrls(struct isc_device *isc) 63 { 64 struct isc_ctrls *ctrls = &isc->ctrls; 65 66 /* In here we set our actual hw pipeline config */ 67 68 regmap_write(isc->regmap, ISC_WB_O_RGR, 69 ((ctrls->offset[ISC_HIS_CFG_MODE_R])) | 70 ((ctrls->offset[ISC_HIS_CFG_MODE_GR]) << 16)); 71 regmap_write(isc->regmap, ISC_WB_O_BGB, 72 ((ctrls->offset[ISC_HIS_CFG_MODE_B])) | 73 ((ctrls->offset[ISC_HIS_CFG_MODE_GB]) << 16)); 74 regmap_write(isc->regmap, ISC_WB_G_RGR, 75 ctrls->gain[ISC_HIS_CFG_MODE_R] | 76 (ctrls->gain[ISC_HIS_CFG_MODE_GR] << 16)); 77 regmap_write(isc->regmap, ISC_WB_G_BGB, 78 ctrls->gain[ISC_HIS_CFG_MODE_B] | 79 (ctrls->gain[ISC_HIS_CFG_MODE_GB] << 16)); 80 } 81 82 static inline void isc_reset_awb_ctrls(struct isc_device *isc) 83 { 84 unsigned int c; 85 86 for (c = ISC_HIS_CFG_MODE_GR; c <= ISC_HIS_CFG_MODE_B; c++) { 87 /* gains have a fixed point at 9 decimals */ 88 isc->ctrls.gain[c] = 1 << 9; 89 /* offsets are in 2's complements */ 90 isc->ctrls.offset[c] = 0; 91 } 92 } 93 94 static int isc_queue_setup(struct vb2_queue *vq, 95 unsigned int *nbuffers, unsigned int *nplanes, 96 unsigned int sizes[], struct device *alloc_devs[]) 97 { 98 struct isc_device *isc = vb2_get_drv_priv(vq); 99 unsigned int size = isc->fmt.fmt.pix.sizeimage; 100 101 if (*nplanes) 102 return sizes[0] < size ? -EINVAL : 0; 103 104 *nplanes = 1; 105 sizes[0] = size; 106 107 return 0; 108 } 109 110 static int isc_buffer_prepare(struct vb2_buffer *vb) 111 { 112 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); 113 struct isc_device *isc = vb2_get_drv_priv(vb->vb2_queue); 114 unsigned long size = isc->fmt.fmt.pix.sizeimage; 115 116 if (vb2_plane_size(vb, 0) < size) { 117 v4l2_err(&isc->v4l2_dev, "buffer too small (%lu < %lu)\n", 118 vb2_plane_size(vb, 0), size); 119 return -EINVAL; 120 } 121 122 vb2_set_plane_payload(vb, 0, size); 123 124 vbuf->field = isc->fmt.fmt.pix.field; 125 126 return 0; 127 } 128 129 static void isc_crop_pfe(struct isc_device *isc) 130 { 131 struct regmap *regmap = isc->regmap; 132 u32 h, w; 133 134 h = isc->fmt.fmt.pix.height; 135 w = isc->fmt.fmt.pix.width; 136 137 /* 138 * In case the sensor is not RAW, it will output a pixel (12-16 bits) 139 * with two samples on the ISC Data bus (which is 8-12) 140 * ISC will count each sample, so, we need to multiply these values 141 * by two, to get the real number of samples for the required pixels. 142 */ 143 if (!ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code)) { 144 h <<= 1; 145 w <<= 1; 146 } 147 148 /* 149 * We limit the column/row count that the ISC will output according 150 * to the configured resolution that we want. 151 * This will avoid the situation where the sensor is misconfigured, 152 * sending more data, and the ISC will just take it and DMA to memory, 153 * causing corruption. 154 */ 155 regmap_write(regmap, ISC_PFE_CFG1, 156 (ISC_PFE_CFG1_COLMIN(0) & ISC_PFE_CFG1_COLMIN_MASK) | 157 (ISC_PFE_CFG1_COLMAX(w - 1) & ISC_PFE_CFG1_COLMAX_MASK)); 158 159 regmap_write(regmap, ISC_PFE_CFG2, 160 (ISC_PFE_CFG2_ROWMIN(0) & ISC_PFE_CFG2_ROWMIN_MASK) | 161 (ISC_PFE_CFG2_ROWMAX(h - 1) & ISC_PFE_CFG2_ROWMAX_MASK)); 162 163 regmap_update_bits(regmap, ISC_PFE_CFG0, 164 ISC_PFE_CFG0_COLEN | ISC_PFE_CFG0_ROWEN, 165 ISC_PFE_CFG0_COLEN | ISC_PFE_CFG0_ROWEN); 166 } 167 168 static void isc_start_dma(struct isc_device *isc) 169 { 170 struct regmap *regmap = isc->regmap; 171 u32 sizeimage = isc->fmt.fmt.pix.sizeimage; 172 u32 dctrl_dview; 173 dma_addr_t addr0; 174 175 addr0 = vb2_dma_contig_plane_dma_addr(&isc->cur_frm->vb.vb2_buf, 0); 176 regmap_write(regmap, ISC_DAD0 + isc->offsets.dma, addr0); 177 178 switch (isc->config.fourcc) { 179 case V4L2_PIX_FMT_YUV420: 180 regmap_write(regmap, ISC_DAD1 + isc->offsets.dma, 181 addr0 + (sizeimage * 2) / 3); 182 regmap_write(regmap, ISC_DAD2 + isc->offsets.dma, 183 addr0 + (sizeimage * 5) / 6); 184 break; 185 case V4L2_PIX_FMT_YUV422P: 186 regmap_write(regmap, ISC_DAD1 + isc->offsets.dma, 187 addr0 + sizeimage / 2); 188 regmap_write(regmap, ISC_DAD2 + isc->offsets.dma, 189 addr0 + (sizeimage * 3) / 4); 190 break; 191 default: 192 break; 193 } 194 195 dctrl_dview = isc->config.dctrl_dview; 196 197 regmap_write(regmap, ISC_DCTRL + isc->offsets.dma, 198 dctrl_dview | ISC_DCTRL_IE_IS); 199 spin_lock(&isc->awb_lock); 200 regmap_write(regmap, ISC_CTRLEN, ISC_CTRL_CAPTURE); 201 spin_unlock(&isc->awb_lock); 202 } 203 204 static void isc_set_pipeline(struct isc_device *isc, u32 pipeline) 205 { 206 struct regmap *regmap = isc->regmap; 207 struct isc_ctrls *ctrls = &isc->ctrls; 208 u32 val, bay_cfg; 209 const u32 *gamma; 210 unsigned int i; 211 212 /* WB-->CFA-->CC-->GAM-->CSC-->CBC-->SUB422-->SUB420 */ 213 for (i = 0; i < ISC_PIPE_LINE_NODE_NUM; i++) { 214 val = pipeline & BIT(i) ? 1 : 0; 215 regmap_field_write(isc->pipeline[i], val); 216 } 217 218 if (!pipeline) 219 return; 220 221 bay_cfg = isc->config.sd_format->cfa_baycfg; 222 223 regmap_write(regmap, ISC_WB_CFG, bay_cfg); 224 isc_update_awb_ctrls(isc); 225 isc_update_v4l2_ctrls(isc); 226 227 regmap_write(regmap, ISC_CFA_CFG, bay_cfg | ISC_CFA_CFG_EITPOL); 228 229 gamma = &isc->gamma_table[ctrls->gamma_index][0]; 230 regmap_bulk_write(regmap, ISC_GAM_BENTRY, gamma, GAMMA_ENTRIES); 231 regmap_bulk_write(regmap, ISC_GAM_GENTRY, gamma, GAMMA_ENTRIES); 232 regmap_bulk_write(regmap, ISC_GAM_RENTRY, gamma, GAMMA_ENTRIES); 233 234 isc->config_dpc(isc); 235 isc->config_csc(isc); 236 isc->config_cbc(isc); 237 isc->config_cc(isc); 238 isc->config_gam(isc); 239 } 240 241 static int isc_update_profile(struct isc_device *isc) 242 { 243 struct regmap *regmap = isc->regmap; 244 u32 sr; 245 int counter = 100; 246 247 regmap_write(regmap, ISC_CTRLEN, ISC_CTRL_UPPRO); 248 249 regmap_read(regmap, ISC_CTRLSR, &sr); 250 while ((sr & ISC_CTRL_UPPRO) && counter--) { 251 usleep_range(1000, 2000); 252 regmap_read(regmap, ISC_CTRLSR, &sr); 253 } 254 255 if (counter < 0) { 256 v4l2_warn(&isc->v4l2_dev, "Time out to update profile\n"); 257 return -ETIMEDOUT; 258 } 259 260 return 0; 261 } 262 263 static void isc_set_histogram(struct isc_device *isc, bool enable) 264 { 265 struct regmap *regmap = isc->regmap; 266 struct isc_ctrls *ctrls = &isc->ctrls; 267 268 if (enable) { 269 regmap_write(regmap, ISC_HIS_CFG + isc->offsets.his, 270 ISC_HIS_CFG_MODE_GR | 271 (isc->config.sd_format->cfa_baycfg 272 << ISC_HIS_CFG_BAYSEL_SHIFT) | 273 ISC_HIS_CFG_RAR); 274 regmap_write(regmap, ISC_HIS_CTRL + isc->offsets.his, 275 ISC_HIS_CTRL_EN); 276 regmap_write(regmap, ISC_INTEN, ISC_INT_HISDONE); 277 ctrls->hist_id = ISC_HIS_CFG_MODE_GR; 278 isc_update_profile(isc); 279 regmap_write(regmap, ISC_CTRLEN, ISC_CTRL_HISREQ); 280 281 ctrls->hist_stat = HIST_ENABLED; 282 } else { 283 regmap_write(regmap, ISC_INTDIS, ISC_INT_HISDONE); 284 regmap_write(regmap, ISC_HIS_CTRL + isc->offsets.his, 285 ISC_HIS_CTRL_DIS); 286 287 ctrls->hist_stat = HIST_DISABLED; 288 } 289 } 290 291 static int isc_configure(struct isc_device *isc) 292 { 293 struct regmap *regmap = isc->regmap; 294 u32 pfe_cfg0, dcfg, mask, pipeline; 295 struct isc_subdev_entity *subdev = isc->current_subdev; 296 297 pfe_cfg0 = isc->config.sd_format->pfe_cfg0_bps; 298 pipeline = isc->config.bits_pipeline; 299 300 dcfg = isc->config.dcfg_imode | isc->dcfg; 301 302 pfe_cfg0 |= subdev->pfe_cfg0 | ISC_PFE_CFG0_MODE_PROGRESSIVE; 303 mask = ISC_PFE_CFG0_BPS_MASK | ISC_PFE_CFG0_HPOL_LOW | 304 ISC_PFE_CFG0_VPOL_LOW | ISC_PFE_CFG0_PPOL_LOW | 305 ISC_PFE_CFG0_MODE_MASK | ISC_PFE_CFG0_CCIR_CRC | 306 ISC_PFE_CFG0_CCIR656 | ISC_PFE_CFG0_MIPI; 307 308 regmap_update_bits(regmap, ISC_PFE_CFG0, mask, pfe_cfg0); 309 310 isc->config_rlp(isc); 311 312 regmap_write(regmap, ISC_DCFG + isc->offsets.dma, dcfg); 313 314 /* Set the pipeline */ 315 isc_set_pipeline(isc, pipeline); 316 317 /* 318 * The current implemented histogram is available for RAW R, B, GB, GR 319 * channels. We need to check if sensor is outputting RAW BAYER 320 */ 321 if (isc->ctrls.awb && 322 ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code)) 323 isc_set_histogram(isc, true); 324 else 325 isc_set_histogram(isc, false); 326 327 /* Update profile */ 328 return isc_update_profile(isc); 329 } 330 331 static int isc_start_streaming(struct vb2_queue *vq, unsigned int count) 332 { 333 struct isc_device *isc = vb2_get_drv_priv(vq); 334 struct regmap *regmap = isc->regmap; 335 struct isc_buffer *buf; 336 unsigned long flags; 337 int ret; 338 339 ret = media_pipeline_start(isc->video_dev.entity.pads, &isc->mpipe); 340 if (ret) 341 goto err_pipeline_start; 342 343 /* Enable stream on the sub device */ 344 ret = v4l2_subdev_call(isc->current_subdev->sd, video, s_stream, 1); 345 if (ret && ret != -ENOIOCTLCMD) { 346 v4l2_err(&isc->v4l2_dev, "stream on failed in subdev %d\n", 347 ret); 348 goto err_start_stream; 349 } 350 351 ret = pm_runtime_resume_and_get(isc->dev); 352 if (ret < 0) { 353 v4l2_err(&isc->v4l2_dev, "RPM resume failed in subdev %d\n", 354 ret); 355 goto err_pm_get; 356 } 357 358 ret = isc_configure(isc); 359 if (unlikely(ret)) 360 goto err_configure; 361 362 /* Enable DMA interrupt */ 363 regmap_write(regmap, ISC_INTEN, ISC_INT_DDONE); 364 365 spin_lock_irqsave(&isc->dma_queue_lock, flags); 366 367 isc->sequence = 0; 368 isc->stop = false; 369 reinit_completion(&isc->comp); 370 371 isc->cur_frm = list_first_entry(&isc->dma_queue, 372 struct isc_buffer, list); 373 list_del(&isc->cur_frm->list); 374 375 isc_crop_pfe(isc); 376 isc_start_dma(isc); 377 378 spin_unlock_irqrestore(&isc->dma_queue_lock, flags); 379 380 /* if we streaming from RAW, we can do one-shot white balance adj */ 381 if (ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code)) 382 v4l2_ctrl_activate(isc->do_wb_ctrl, true); 383 384 return 0; 385 386 err_configure: 387 pm_runtime_put_sync(isc->dev); 388 err_pm_get: 389 v4l2_subdev_call(isc->current_subdev->sd, video, s_stream, 0); 390 391 err_start_stream: 392 media_pipeline_stop(isc->video_dev.entity.pads); 393 394 err_pipeline_start: 395 spin_lock_irqsave(&isc->dma_queue_lock, flags); 396 list_for_each_entry(buf, &isc->dma_queue, list) 397 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_QUEUED); 398 INIT_LIST_HEAD(&isc->dma_queue); 399 spin_unlock_irqrestore(&isc->dma_queue_lock, flags); 400 401 return ret; 402 } 403 404 static void isc_stop_streaming(struct vb2_queue *vq) 405 { 406 struct isc_device *isc = vb2_get_drv_priv(vq); 407 unsigned long flags; 408 struct isc_buffer *buf; 409 int ret; 410 411 mutex_lock(&isc->awb_mutex); 412 v4l2_ctrl_activate(isc->do_wb_ctrl, false); 413 414 isc->stop = true; 415 416 /* Wait until the end of the current frame */ 417 if (isc->cur_frm && !wait_for_completion_timeout(&isc->comp, 5 * HZ)) 418 v4l2_err(&isc->v4l2_dev, 419 "Timeout waiting for end of the capture\n"); 420 421 mutex_unlock(&isc->awb_mutex); 422 423 /* Disable DMA interrupt */ 424 regmap_write(isc->regmap, ISC_INTDIS, ISC_INT_DDONE); 425 426 pm_runtime_put_sync(isc->dev); 427 428 /* Disable stream on the sub device */ 429 ret = v4l2_subdev_call(isc->current_subdev->sd, video, s_stream, 0); 430 if (ret && ret != -ENOIOCTLCMD) 431 v4l2_err(&isc->v4l2_dev, "stream off failed in subdev\n"); 432 433 /* Stop media pipeline */ 434 media_pipeline_stop(isc->video_dev.entity.pads); 435 436 /* Release all active buffers */ 437 spin_lock_irqsave(&isc->dma_queue_lock, flags); 438 if (unlikely(isc->cur_frm)) { 439 vb2_buffer_done(&isc->cur_frm->vb.vb2_buf, 440 VB2_BUF_STATE_ERROR); 441 isc->cur_frm = NULL; 442 } 443 list_for_each_entry(buf, &isc->dma_queue, list) 444 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR); 445 INIT_LIST_HEAD(&isc->dma_queue); 446 spin_unlock_irqrestore(&isc->dma_queue_lock, flags); 447 } 448 449 static void isc_buffer_queue(struct vb2_buffer *vb) 450 { 451 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); 452 struct isc_buffer *buf = container_of(vbuf, struct isc_buffer, vb); 453 struct isc_device *isc = vb2_get_drv_priv(vb->vb2_queue); 454 unsigned long flags; 455 456 spin_lock_irqsave(&isc->dma_queue_lock, flags); 457 if (!isc->cur_frm && list_empty(&isc->dma_queue) && 458 vb2_start_streaming_called(vb->vb2_queue)) { 459 isc->cur_frm = buf; 460 isc_start_dma(isc); 461 } else { 462 list_add_tail(&buf->list, &isc->dma_queue); 463 } 464 spin_unlock_irqrestore(&isc->dma_queue_lock, flags); 465 } 466 467 static const struct vb2_ops isc_vb2_ops = { 468 .queue_setup = isc_queue_setup, 469 .wait_prepare = vb2_ops_wait_prepare, 470 .wait_finish = vb2_ops_wait_finish, 471 .buf_prepare = isc_buffer_prepare, 472 .start_streaming = isc_start_streaming, 473 .stop_streaming = isc_stop_streaming, 474 .buf_queue = isc_buffer_queue, 475 }; 476 477 static int isc_querycap(struct file *file, void *priv, 478 struct v4l2_capability *cap) 479 { 480 struct isc_device *isc = video_drvdata(file); 481 482 strscpy(cap->driver, "microchip-isc", sizeof(cap->driver)); 483 strscpy(cap->card, "Microchip Image Sensor Controller", sizeof(cap->card)); 484 snprintf(cap->bus_info, sizeof(cap->bus_info), 485 "platform:%s", isc->v4l2_dev.name); 486 487 return 0; 488 } 489 490 static int isc_enum_fmt_vid_cap(struct file *file, void *priv, 491 struct v4l2_fmtdesc *f) 492 { 493 struct isc_device *isc = video_drvdata(file); 494 u32 index = f->index; 495 u32 i, supported_index = 0; 496 struct isc_format *fmt; 497 498 /* 499 * If we are not asked a specific mbus_code, we have to report all 500 * the formats that we can output. 501 */ 502 if (!f->mbus_code) { 503 if (index >= isc->controller_formats_size) 504 return -EINVAL; 505 506 f->pixelformat = isc->controller_formats[index].fourcc; 507 508 return 0; 509 } 510 511 /* 512 * If a specific mbus_code is requested, check if we support 513 * this mbus_code as input for the ISC. 514 * If it's supported, then we report the corresponding pixelformat 515 * as first possible option for the ISC. 516 * E.g. mbus MEDIA_BUS_FMT_YUYV8_2X8 and report 517 * 'YUYV' (YUYV 4:2:2) 518 */ 519 fmt = isc_find_format_by_code(isc, f->mbus_code, &i); 520 if (!fmt) 521 return -EINVAL; 522 523 if (!index) { 524 f->pixelformat = fmt->fourcc; 525 526 return 0; 527 } 528 529 supported_index++; 530 531 /* If the index is not raw, we don't have anymore formats to report */ 532 if (!ISC_IS_FORMAT_RAW(f->mbus_code)) 533 return -EINVAL; 534 535 /* 536 * We are asked for a specific mbus code, which is raw. 537 * We have to search through the formats we can convert to. 538 * We have to skip the raw formats, we cannot convert to raw. 539 * E.g. 'AR12' (16-bit ARGB 4-4-4-4), 'AR15' (16-bit ARGB 1-5-5-5), etc. 540 */ 541 for (i = 0; i < isc->controller_formats_size; i++) { 542 if (isc->controller_formats[i].raw) 543 continue; 544 if (index == supported_index) { 545 f->pixelformat = isc->controller_formats[i].fourcc; 546 return 0; 547 } 548 supported_index++; 549 } 550 551 return -EINVAL; 552 } 553 554 static int isc_g_fmt_vid_cap(struct file *file, void *priv, 555 struct v4l2_format *fmt) 556 { 557 struct isc_device *isc = video_drvdata(file); 558 559 *fmt = isc->fmt; 560 561 return 0; 562 } 563 564 /* 565 * Checks the current configured format, if ISC can output it, 566 * considering which type of format the ISC receives from the sensor 567 */ 568 static int isc_try_validate_formats(struct isc_device *isc) 569 { 570 int ret; 571 bool bayer = false, yuv = false, rgb = false, grey = false; 572 573 /* all formats supported by the RLP module are OK */ 574 switch (isc->try_config.fourcc) { 575 case V4L2_PIX_FMT_SBGGR8: 576 case V4L2_PIX_FMT_SGBRG8: 577 case V4L2_PIX_FMT_SGRBG8: 578 case V4L2_PIX_FMT_SRGGB8: 579 case V4L2_PIX_FMT_SBGGR10: 580 case V4L2_PIX_FMT_SGBRG10: 581 case V4L2_PIX_FMT_SGRBG10: 582 case V4L2_PIX_FMT_SRGGB10: 583 case V4L2_PIX_FMT_SBGGR12: 584 case V4L2_PIX_FMT_SGBRG12: 585 case V4L2_PIX_FMT_SGRBG12: 586 case V4L2_PIX_FMT_SRGGB12: 587 ret = 0; 588 bayer = true; 589 break; 590 591 case V4L2_PIX_FMT_YUV420: 592 case V4L2_PIX_FMT_YUV422P: 593 case V4L2_PIX_FMT_YUYV: 594 case V4L2_PIX_FMT_UYVY: 595 case V4L2_PIX_FMT_VYUY: 596 ret = 0; 597 yuv = true; 598 break; 599 600 case V4L2_PIX_FMT_RGB565: 601 case V4L2_PIX_FMT_ABGR32: 602 case V4L2_PIX_FMT_XBGR32: 603 case V4L2_PIX_FMT_ARGB444: 604 case V4L2_PIX_FMT_ARGB555: 605 ret = 0; 606 rgb = true; 607 break; 608 case V4L2_PIX_FMT_GREY: 609 case V4L2_PIX_FMT_Y10: 610 case V4L2_PIX_FMT_Y16: 611 ret = 0; 612 grey = true; 613 break; 614 default: 615 /* any other different formats are not supported */ 616 v4l2_err(&isc->v4l2_dev, "Requested unsupported format.\n"); 617 ret = -EINVAL; 618 } 619 v4l2_dbg(1, debug, &isc->v4l2_dev, 620 "Format validation, requested rgb=%u, yuv=%u, grey=%u, bayer=%u\n", 621 rgb, yuv, grey, bayer); 622 623 if (bayer && 624 !ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) { 625 v4l2_err(&isc->v4l2_dev, "Cannot output RAW if we do not receive RAW.\n"); 626 return -EINVAL; 627 } 628 629 if (grey && !ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code) && 630 !ISC_IS_FORMAT_GREY(isc->try_config.sd_format->mbus_code)) { 631 v4l2_err(&isc->v4l2_dev, "Cannot output GREY if we do not receive RAW/GREY.\n"); 632 return -EINVAL; 633 } 634 635 if ((rgb || bayer || yuv) && 636 ISC_IS_FORMAT_GREY(isc->try_config.sd_format->mbus_code)) { 637 v4l2_err(&isc->v4l2_dev, "Cannot convert GREY to another format.\n"); 638 return -EINVAL; 639 } 640 641 return ret; 642 } 643 644 /* 645 * Configures the RLP and DMA modules, depending on the output format 646 * configured for the ISC. 647 * If direct_dump == true, just dump raw data 8/16 bits depending on format. 648 */ 649 static int isc_try_configure_rlp_dma(struct isc_device *isc, bool direct_dump) 650 { 651 isc->try_config.rlp_cfg_mode = 0; 652 653 switch (isc->try_config.fourcc) { 654 case V4L2_PIX_FMT_SBGGR8: 655 case V4L2_PIX_FMT_SGBRG8: 656 case V4L2_PIX_FMT_SGRBG8: 657 case V4L2_PIX_FMT_SRGGB8: 658 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT8; 659 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED8; 660 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; 661 isc->try_config.bpp = 8; 662 isc->try_config.bpp_v4l2 = 8; 663 break; 664 case V4L2_PIX_FMT_SBGGR10: 665 case V4L2_PIX_FMT_SGBRG10: 666 case V4L2_PIX_FMT_SGRBG10: 667 case V4L2_PIX_FMT_SRGGB10: 668 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT10; 669 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16; 670 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; 671 isc->try_config.bpp = 16; 672 isc->try_config.bpp_v4l2 = 16; 673 break; 674 case V4L2_PIX_FMT_SBGGR12: 675 case V4L2_PIX_FMT_SGBRG12: 676 case V4L2_PIX_FMT_SGRBG12: 677 case V4L2_PIX_FMT_SRGGB12: 678 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT12; 679 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16; 680 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; 681 isc->try_config.bpp = 16; 682 isc->try_config.bpp_v4l2 = 16; 683 break; 684 case V4L2_PIX_FMT_RGB565: 685 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_RGB565; 686 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16; 687 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; 688 isc->try_config.bpp = 16; 689 isc->try_config.bpp_v4l2 = 16; 690 break; 691 case V4L2_PIX_FMT_ARGB444: 692 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_ARGB444; 693 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16; 694 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; 695 isc->try_config.bpp = 16; 696 isc->try_config.bpp_v4l2 = 16; 697 break; 698 case V4L2_PIX_FMT_ARGB555: 699 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_ARGB555; 700 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16; 701 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; 702 isc->try_config.bpp = 16; 703 isc->try_config.bpp_v4l2 = 16; 704 break; 705 case V4L2_PIX_FMT_ABGR32: 706 case V4L2_PIX_FMT_XBGR32: 707 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_ARGB32; 708 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32; 709 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; 710 isc->try_config.bpp = 32; 711 isc->try_config.bpp_v4l2 = 32; 712 break; 713 case V4L2_PIX_FMT_YUV420: 714 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YYCC; 715 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_YC420P; 716 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PLANAR; 717 isc->try_config.bpp = 12; 718 isc->try_config.bpp_v4l2 = 8; /* only first plane */ 719 break; 720 case V4L2_PIX_FMT_YUV422P: 721 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YYCC; 722 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_YC422P; 723 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PLANAR; 724 isc->try_config.bpp = 16; 725 isc->try_config.bpp_v4l2 = 8; /* only first plane */ 726 break; 727 case V4L2_PIX_FMT_YUYV: 728 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YCYC | ISC_RLP_CFG_YMODE_YUYV; 729 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32; 730 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; 731 isc->try_config.bpp = 16; 732 isc->try_config.bpp_v4l2 = 16; 733 break; 734 case V4L2_PIX_FMT_UYVY: 735 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YCYC | ISC_RLP_CFG_YMODE_UYVY; 736 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32; 737 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; 738 isc->try_config.bpp = 16; 739 isc->try_config.bpp_v4l2 = 16; 740 break; 741 case V4L2_PIX_FMT_VYUY: 742 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YCYC | ISC_RLP_CFG_YMODE_VYUY; 743 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32; 744 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; 745 isc->try_config.bpp = 16; 746 isc->try_config.bpp_v4l2 = 16; 747 break; 748 case V4L2_PIX_FMT_GREY: 749 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DATY8; 750 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED8; 751 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; 752 isc->try_config.bpp = 8; 753 isc->try_config.bpp_v4l2 = 8; 754 break; 755 case V4L2_PIX_FMT_Y16: 756 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DATY10 | ISC_RLP_CFG_LSH; 757 fallthrough; 758 case V4L2_PIX_FMT_Y10: 759 isc->try_config.rlp_cfg_mode |= ISC_RLP_CFG_MODE_DATY10; 760 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16; 761 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; 762 isc->try_config.bpp = 16; 763 isc->try_config.bpp_v4l2 = 16; 764 break; 765 default: 766 return -EINVAL; 767 } 768 769 if (direct_dump) { 770 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT8; 771 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED8; 772 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; 773 return 0; 774 } 775 776 return 0; 777 } 778 779 /* 780 * Configuring pipeline modules, depending on which format the ISC outputs 781 * and considering which format it has as input from the sensor. 782 */ 783 static int isc_try_configure_pipeline(struct isc_device *isc) 784 { 785 switch (isc->try_config.fourcc) { 786 case V4L2_PIX_FMT_RGB565: 787 case V4L2_PIX_FMT_ARGB555: 788 case V4L2_PIX_FMT_ARGB444: 789 case V4L2_PIX_FMT_ABGR32: 790 case V4L2_PIX_FMT_XBGR32: 791 /* if sensor format is RAW, we convert inside ISC */ 792 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) { 793 isc->try_config.bits_pipeline = CFA_ENABLE | 794 WB_ENABLE | GAM_ENABLES | DPC_BLCENABLE | 795 CC_ENABLE; 796 } else { 797 isc->try_config.bits_pipeline = 0x0; 798 } 799 break; 800 case V4L2_PIX_FMT_YUV420: 801 /* if sensor format is RAW, we convert inside ISC */ 802 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) { 803 isc->try_config.bits_pipeline = CFA_ENABLE | 804 CSC_ENABLE | GAM_ENABLES | WB_ENABLE | 805 SUB420_ENABLE | SUB422_ENABLE | CBC_ENABLE | 806 DPC_BLCENABLE; 807 } else { 808 isc->try_config.bits_pipeline = 0x0; 809 } 810 break; 811 case V4L2_PIX_FMT_YUV422P: 812 /* if sensor format is RAW, we convert inside ISC */ 813 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) { 814 isc->try_config.bits_pipeline = CFA_ENABLE | 815 CSC_ENABLE | WB_ENABLE | GAM_ENABLES | 816 SUB422_ENABLE | CBC_ENABLE | DPC_BLCENABLE; 817 } else { 818 isc->try_config.bits_pipeline = 0x0; 819 } 820 break; 821 case V4L2_PIX_FMT_YUYV: 822 case V4L2_PIX_FMT_UYVY: 823 case V4L2_PIX_FMT_VYUY: 824 /* if sensor format is RAW, we convert inside ISC */ 825 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) { 826 isc->try_config.bits_pipeline = CFA_ENABLE | 827 CSC_ENABLE | WB_ENABLE | GAM_ENABLES | 828 SUB422_ENABLE | CBC_ENABLE | DPC_BLCENABLE; 829 } else { 830 isc->try_config.bits_pipeline = 0x0; 831 } 832 break; 833 case V4L2_PIX_FMT_GREY: 834 case V4L2_PIX_FMT_Y16: 835 /* if sensor format is RAW, we convert inside ISC */ 836 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) { 837 isc->try_config.bits_pipeline = CFA_ENABLE | 838 CSC_ENABLE | WB_ENABLE | GAM_ENABLES | 839 CBC_ENABLE | DPC_BLCENABLE; 840 } else { 841 isc->try_config.bits_pipeline = 0x0; 842 } 843 break; 844 default: 845 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) 846 isc->try_config.bits_pipeline = WB_ENABLE | DPC_BLCENABLE; 847 else 848 isc->try_config.bits_pipeline = 0x0; 849 } 850 851 /* Tune the pipeline to product specific */ 852 isc->adapt_pipeline(isc); 853 854 return 0; 855 } 856 857 static void isc_try_fse(struct isc_device *isc, 858 struct v4l2_subdev_state *sd_state) 859 { 860 int ret; 861 struct v4l2_subdev_frame_size_enum fse = {}; 862 863 /* 864 * If we do not know yet which format the subdev is using, we cannot 865 * do anything. 866 */ 867 if (!isc->config.sd_format) 868 return; 869 870 fse.code = isc->try_config.sd_format->mbus_code; 871 fse.which = V4L2_SUBDEV_FORMAT_TRY; 872 873 ret = v4l2_subdev_call(isc->current_subdev->sd, pad, enum_frame_size, 874 sd_state, &fse); 875 /* 876 * Attempt to obtain format size from subdev. If not available, 877 * just use the maximum ISC can receive. 878 */ 879 if (ret) { 880 sd_state->pads->try_crop.width = isc->max_width; 881 sd_state->pads->try_crop.height = isc->max_height; 882 } else { 883 sd_state->pads->try_crop.width = fse.max_width; 884 sd_state->pads->try_crop.height = fse.max_height; 885 } 886 } 887 888 static int isc_try_fmt(struct isc_device *isc, struct v4l2_format *f) 889 { 890 struct v4l2_pix_format *pixfmt = &f->fmt.pix; 891 unsigned int i; 892 893 if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) 894 return -EINVAL; 895 896 isc->try_config.fourcc = isc->controller_formats[0].fourcc; 897 898 /* find if the format requested is supported */ 899 for (i = 0; i < isc->controller_formats_size; i++) 900 if (isc->controller_formats[i].fourcc == pixfmt->pixelformat) { 901 isc->try_config.fourcc = pixfmt->pixelformat; 902 break; 903 } 904 905 isc_try_configure_rlp_dma(isc, false); 906 907 /* Limit to Microchip ISC hardware capabilities */ 908 v4l_bound_align_image(&pixfmt->width, 16, isc->max_width, 0, 909 &pixfmt->height, 16, isc->max_height, 0, 0); 910 /* If we did not find the requested format, we will fallback here */ 911 pixfmt->pixelformat = isc->try_config.fourcc; 912 pixfmt->colorspace = V4L2_COLORSPACE_SRGB; 913 pixfmt->field = V4L2_FIELD_NONE; 914 915 pixfmt->bytesperline = (pixfmt->width * isc->try_config.bpp_v4l2) >> 3; 916 pixfmt->sizeimage = ((pixfmt->width * isc->try_config.bpp) >> 3) * 917 pixfmt->height; 918 919 isc->try_fmt = *f; 920 921 return 0; 922 } 923 924 static int isc_set_fmt(struct isc_device *isc, struct v4l2_format *f) 925 { 926 isc_try_fmt(isc, f); 927 928 /* make the try configuration active */ 929 isc->config = isc->try_config; 930 isc->fmt = isc->try_fmt; 931 932 v4l2_dbg(1, debug, &isc->v4l2_dev, "ISC set_fmt to %.4s @%dx%d\n", 933 (char *)&f->fmt.pix.pixelformat, 934 f->fmt.pix.width, f->fmt.pix.height); 935 936 return 0; 937 } 938 939 static int isc_validate(struct isc_device *isc) 940 { 941 int ret; 942 int i; 943 struct isc_format *sd_fmt = NULL; 944 struct v4l2_pix_format *pixfmt = &isc->fmt.fmt.pix; 945 struct v4l2_subdev_format format = { 946 .which = V4L2_SUBDEV_FORMAT_ACTIVE, 947 .pad = isc->remote_pad, 948 }; 949 struct v4l2_subdev_pad_config pad_cfg = {}; 950 struct v4l2_subdev_state pad_state = { 951 .pads = &pad_cfg, 952 }; 953 954 /* Get current format from subdev */ 955 ret = v4l2_subdev_call(isc->current_subdev->sd, pad, get_fmt, NULL, 956 &format); 957 if (ret) 958 return ret; 959 960 /* Identify the subdev's format configuration */ 961 for (i = 0; i < isc->formats_list_size; i++) 962 if (isc->formats_list[i].mbus_code == format.format.code) { 963 sd_fmt = &isc->formats_list[i]; 964 break; 965 } 966 967 /* Check if the format is not supported */ 968 if (!sd_fmt) { 969 v4l2_err(&isc->v4l2_dev, 970 "Current subdevice is streaming a media bus code that is not supported 0x%x\n", 971 format.format.code); 972 return -EPIPE; 973 } 974 975 /* At this moment we know which format the subdev will use */ 976 isc->try_config.sd_format = sd_fmt; 977 978 /* If the sensor is not RAW, we can only do a direct dump */ 979 if (!ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) 980 isc_try_configure_rlp_dma(isc, true); 981 982 /* Limit to Microchip ISC hardware capabilities */ 983 v4l_bound_align_image(&format.format.width, 16, isc->max_width, 0, 984 &format.format.height, 16, isc->max_height, 0, 0); 985 986 /* Check if the frame size is the same. Otherwise we may overflow */ 987 if (pixfmt->height != format.format.height || 988 pixfmt->width != format.format.width) { 989 v4l2_err(&isc->v4l2_dev, 990 "ISC not configured with the proper frame size: %dx%d\n", 991 format.format.width, format.format.height); 992 return -EPIPE; 993 } 994 995 v4l2_dbg(1, debug, &isc->v4l2_dev, 996 "Identified subdev using format %.4s with %dx%d %d bpp\n", 997 (char *)&sd_fmt->fourcc, pixfmt->width, pixfmt->height, 998 isc->try_config.bpp); 999 1000 /* Reset and restart AWB if the subdevice changed the format */ 1001 if (isc->try_config.sd_format && isc->config.sd_format && 1002 isc->try_config.sd_format != isc->config.sd_format) { 1003 isc->ctrls.hist_stat = HIST_INIT; 1004 isc_reset_awb_ctrls(isc); 1005 isc_update_v4l2_ctrls(isc); 1006 } 1007 1008 /* Validate formats */ 1009 ret = isc_try_validate_formats(isc); 1010 if (ret) 1011 return ret; 1012 1013 /* Obtain frame sizes if possible to have crop requirements ready */ 1014 isc_try_fse(isc, &pad_state); 1015 1016 /* Configure ISC pipeline for the config */ 1017 ret = isc_try_configure_pipeline(isc); 1018 if (ret) 1019 return ret; 1020 1021 isc->config = isc->try_config; 1022 1023 v4l2_dbg(1, debug, &isc->v4l2_dev, "New ISC configuration in place\n"); 1024 1025 return 0; 1026 } 1027 1028 static int isc_s_fmt_vid_cap(struct file *file, void *priv, 1029 struct v4l2_format *f) 1030 { 1031 struct isc_device *isc = video_drvdata(file); 1032 1033 if (vb2_is_busy(&isc->vb2_vidq)) 1034 return -EBUSY; 1035 1036 return isc_set_fmt(isc, f); 1037 } 1038 1039 static int isc_try_fmt_vid_cap(struct file *file, void *priv, 1040 struct v4l2_format *f) 1041 { 1042 struct isc_device *isc = video_drvdata(file); 1043 1044 return isc_try_fmt(isc, f); 1045 } 1046 1047 static int isc_enum_input(struct file *file, void *priv, 1048 struct v4l2_input *inp) 1049 { 1050 if (inp->index != 0) 1051 return -EINVAL; 1052 1053 inp->type = V4L2_INPUT_TYPE_CAMERA; 1054 inp->std = 0; 1055 strscpy(inp->name, "Camera", sizeof(inp->name)); 1056 1057 return 0; 1058 } 1059 1060 static int isc_g_input(struct file *file, void *priv, unsigned int *i) 1061 { 1062 *i = 0; 1063 1064 return 0; 1065 } 1066 1067 static int isc_s_input(struct file *file, void *priv, unsigned int i) 1068 { 1069 if (i > 0) 1070 return -EINVAL; 1071 1072 return 0; 1073 } 1074 1075 static int isc_g_parm(struct file *file, void *fh, struct v4l2_streamparm *a) 1076 { 1077 struct isc_device *isc = video_drvdata(file); 1078 1079 return v4l2_g_parm_cap(video_devdata(file), isc->current_subdev->sd, a); 1080 } 1081 1082 static int isc_s_parm(struct file *file, void *fh, struct v4l2_streamparm *a) 1083 { 1084 struct isc_device *isc = video_drvdata(file); 1085 1086 return v4l2_s_parm_cap(video_devdata(file), isc->current_subdev->sd, a); 1087 } 1088 1089 static int isc_enum_framesizes(struct file *file, void *fh, 1090 struct v4l2_frmsizeenum *fsize) 1091 { 1092 struct isc_device *isc = video_drvdata(file); 1093 int ret = -EINVAL; 1094 int i; 1095 1096 if (fsize->index) 1097 return -EINVAL; 1098 1099 for (i = 0; i < isc->controller_formats_size; i++) 1100 if (isc->controller_formats[i].fourcc == fsize->pixel_format) 1101 ret = 0; 1102 1103 if (ret) 1104 return ret; 1105 1106 fsize->type = V4L2_FRMSIZE_TYPE_CONTINUOUS; 1107 1108 fsize->stepwise.min_width = 16; 1109 fsize->stepwise.max_width = isc->max_width; 1110 fsize->stepwise.min_height = 16; 1111 fsize->stepwise.max_height = isc->max_height; 1112 fsize->stepwise.step_width = 1; 1113 fsize->stepwise.step_height = 1; 1114 1115 return 0; 1116 } 1117 1118 static const struct v4l2_ioctl_ops isc_ioctl_ops = { 1119 .vidioc_querycap = isc_querycap, 1120 .vidioc_enum_fmt_vid_cap = isc_enum_fmt_vid_cap, 1121 .vidioc_g_fmt_vid_cap = isc_g_fmt_vid_cap, 1122 .vidioc_s_fmt_vid_cap = isc_s_fmt_vid_cap, 1123 .vidioc_try_fmt_vid_cap = isc_try_fmt_vid_cap, 1124 1125 .vidioc_enum_input = isc_enum_input, 1126 .vidioc_g_input = isc_g_input, 1127 .vidioc_s_input = isc_s_input, 1128 1129 .vidioc_reqbufs = vb2_ioctl_reqbufs, 1130 .vidioc_querybuf = vb2_ioctl_querybuf, 1131 .vidioc_qbuf = vb2_ioctl_qbuf, 1132 .vidioc_expbuf = vb2_ioctl_expbuf, 1133 .vidioc_dqbuf = vb2_ioctl_dqbuf, 1134 .vidioc_create_bufs = vb2_ioctl_create_bufs, 1135 .vidioc_prepare_buf = vb2_ioctl_prepare_buf, 1136 .vidioc_streamon = vb2_ioctl_streamon, 1137 .vidioc_streamoff = vb2_ioctl_streamoff, 1138 1139 .vidioc_g_parm = isc_g_parm, 1140 .vidioc_s_parm = isc_s_parm, 1141 .vidioc_enum_framesizes = isc_enum_framesizes, 1142 1143 .vidioc_log_status = v4l2_ctrl_log_status, 1144 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, 1145 .vidioc_unsubscribe_event = v4l2_event_unsubscribe, 1146 }; 1147 1148 static int isc_open(struct file *file) 1149 { 1150 struct isc_device *isc = video_drvdata(file); 1151 struct v4l2_subdev *sd = isc->current_subdev->sd; 1152 int ret; 1153 1154 if (mutex_lock_interruptible(&isc->lock)) 1155 return -ERESTARTSYS; 1156 1157 ret = v4l2_fh_open(file); 1158 if (ret < 0) 1159 goto unlock; 1160 1161 if (!v4l2_fh_is_singular_file(file)) 1162 goto unlock; 1163 1164 ret = v4l2_subdev_call(sd, core, s_power, 1); 1165 if (ret < 0 && ret != -ENOIOCTLCMD) { 1166 v4l2_fh_release(file); 1167 goto unlock; 1168 } 1169 1170 ret = isc_set_fmt(isc, &isc->fmt); 1171 if (ret) { 1172 v4l2_subdev_call(sd, core, s_power, 0); 1173 v4l2_fh_release(file); 1174 } 1175 1176 unlock: 1177 mutex_unlock(&isc->lock); 1178 return ret; 1179 } 1180 1181 static int isc_release(struct file *file) 1182 { 1183 struct isc_device *isc = video_drvdata(file); 1184 struct v4l2_subdev *sd = isc->current_subdev->sd; 1185 bool fh_singular; 1186 int ret; 1187 1188 mutex_lock(&isc->lock); 1189 1190 fh_singular = v4l2_fh_is_singular_file(file); 1191 1192 ret = _vb2_fop_release(file, NULL); 1193 1194 if (fh_singular) 1195 v4l2_subdev_call(sd, core, s_power, 0); 1196 1197 mutex_unlock(&isc->lock); 1198 1199 return ret; 1200 } 1201 1202 static const struct v4l2_file_operations isc_fops = { 1203 .owner = THIS_MODULE, 1204 .open = isc_open, 1205 .release = isc_release, 1206 .unlocked_ioctl = video_ioctl2, 1207 .read = vb2_fop_read, 1208 .mmap = vb2_fop_mmap, 1209 .poll = vb2_fop_poll, 1210 }; 1211 1212 irqreturn_t microchip_isc_interrupt(int irq, void *dev_id) 1213 { 1214 struct isc_device *isc = (struct isc_device *)dev_id; 1215 struct regmap *regmap = isc->regmap; 1216 u32 isc_intsr, isc_intmask, pending; 1217 irqreturn_t ret = IRQ_NONE; 1218 1219 regmap_read(regmap, ISC_INTSR, &isc_intsr); 1220 regmap_read(regmap, ISC_INTMASK, &isc_intmask); 1221 1222 pending = isc_intsr & isc_intmask; 1223 1224 if (likely(pending & ISC_INT_DDONE)) { 1225 spin_lock(&isc->dma_queue_lock); 1226 if (isc->cur_frm) { 1227 struct vb2_v4l2_buffer *vbuf = &isc->cur_frm->vb; 1228 struct vb2_buffer *vb = &vbuf->vb2_buf; 1229 1230 vb->timestamp = ktime_get_ns(); 1231 vbuf->sequence = isc->sequence++; 1232 vb2_buffer_done(vb, VB2_BUF_STATE_DONE); 1233 isc->cur_frm = NULL; 1234 } 1235 1236 if (!list_empty(&isc->dma_queue) && !isc->stop) { 1237 isc->cur_frm = list_first_entry(&isc->dma_queue, 1238 struct isc_buffer, list); 1239 list_del(&isc->cur_frm->list); 1240 1241 isc_start_dma(isc); 1242 } 1243 1244 if (isc->stop) 1245 complete(&isc->comp); 1246 1247 ret = IRQ_HANDLED; 1248 spin_unlock(&isc->dma_queue_lock); 1249 } 1250 1251 if (pending & ISC_INT_HISDONE) { 1252 schedule_work(&isc->awb_work); 1253 ret = IRQ_HANDLED; 1254 } 1255 1256 return ret; 1257 } 1258 EXPORT_SYMBOL_GPL(microchip_isc_interrupt); 1259 1260 static void isc_hist_count(struct isc_device *isc, u32 *min, u32 *max) 1261 { 1262 struct regmap *regmap = isc->regmap; 1263 struct isc_ctrls *ctrls = &isc->ctrls; 1264 u32 *hist_count = &ctrls->hist_count[ctrls->hist_id]; 1265 u32 *hist_entry = &ctrls->hist_entry[0]; 1266 u32 i; 1267 1268 *min = 0; 1269 *max = HIST_ENTRIES; 1270 1271 regmap_bulk_read(regmap, ISC_HIS_ENTRY + isc->offsets.his_entry, 1272 hist_entry, HIST_ENTRIES); 1273 1274 *hist_count = 0; 1275 /* 1276 * we deliberately ignore the end of the histogram, 1277 * the most white pixels 1278 */ 1279 for (i = 1; i < HIST_ENTRIES; i++) { 1280 if (*hist_entry && !*min) 1281 *min = i; 1282 if (*hist_entry) 1283 *max = i; 1284 *hist_count += i * (*hist_entry++); 1285 } 1286 1287 if (!*min) 1288 *min = 1; 1289 1290 v4l2_dbg(1, debug, &isc->v4l2_dev, 1291 "isc wb: hist_id %u, hist_count %u", 1292 ctrls->hist_id, *hist_count); 1293 } 1294 1295 static void isc_wb_update(struct isc_ctrls *ctrls) 1296 { 1297 struct isc_device *isc = container_of(ctrls, struct isc_device, ctrls); 1298 u32 *hist_count = &ctrls->hist_count[0]; 1299 u32 c, offset[4]; 1300 u64 avg = 0; 1301 /* We compute two gains, stretch gain and grey world gain */ 1302 u32 s_gain[4], gw_gain[4]; 1303 1304 /* 1305 * According to Grey World, we need to set gains for R/B to normalize 1306 * them towards the green channel. 1307 * Thus we want to keep Green as fixed and adjust only Red/Blue 1308 * Compute the average of the both green channels first 1309 */ 1310 avg = (u64)hist_count[ISC_HIS_CFG_MODE_GR] + 1311 (u64)hist_count[ISC_HIS_CFG_MODE_GB]; 1312 avg >>= 1; 1313 1314 v4l2_dbg(1, debug, &isc->v4l2_dev, 1315 "isc wb: green components average %llu\n", avg); 1316 1317 /* Green histogram is null, nothing to do */ 1318 if (!avg) 1319 return; 1320 1321 for (c = ISC_HIS_CFG_MODE_GR; c <= ISC_HIS_CFG_MODE_B; c++) { 1322 /* 1323 * the color offset is the minimum value of the histogram. 1324 * we stretch this color to the full range by substracting 1325 * this value from the color component. 1326 */ 1327 offset[c] = ctrls->hist_minmax[c][HIST_MIN_INDEX]; 1328 /* 1329 * The offset is always at least 1. If the offset is 1, we do 1330 * not need to adjust it, so our result must be zero. 1331 * the offset is computed in a histogram on 9 bits (0..512) 1332 * but the offset in register is based on 1333 * 12 bits pipeline (0..4096). 1334 * we need to shift with the 3 bits that the histogram is 1335 * ignoring 1336 */ 1337 ctrls->offset[c] = (offset[c] - 1) << 3; 1338 1339 /* 1340 * the offset is then taken and converted to 2's complements, 1341 * and must be negative, as we subtract this value from the 1342 * color components 1343 */ 1344 ctrls->offset[c] = -ctrls->offset[c]; 1345 1346 /* 1347 * the stretch gain is the total number of histogram bins 1348 * divided by the actual range of color component (Max - Min) 1349 * If we compute gain like this, the actual color component 1350 * will be stretched to the full histogram. 1351 * We need to shift 9 bits for precision, we have 9 bits for 1352 * decimals 1353 */ 1354 s_gain[c] = (HIST_ENTRIES << 9) / 1355 (ctrls->hist_minmax[c][HIST_MAX_INDEX] - 1356 ctrls->hist_minmax[c][HIST_MIN_INDEX] + 1); 1357 1358 /* 1359 * Now we have to compute the gain w.r.t. the average. 1360 * Add/lose gain to the component towards the average. 1361 * If it happens that the component is zero, use the 1362 * fixed point value : 1.0 gain. 1363 */ 1364 if (hist_count[c]) 1365 gw_gain[c] = div_u64(avg << 9, hist_count[c]); 1366 else 1367 gw_gain[c] = 1 << 9; 1368 1369 v4l2_dbg(1, debug, &isc->v4l2_dev, 1370 "isc wb: component %d, s_gain %u, gw_gain %u\n", 1371 c, s_gain[c], gw_gain[c]); 1372 /* multiply both gains and adjust for decimals */ 1373 ctrls->gain[c] = s_gain[c] * gw_gain[c]; 1374 ctrls->gain[c] >>= 9; 1375 1376 /* make sure we are not out of range */ 1377 ctrls->gain[c] = clamp_val(ctrls->gain[c], 0, GENMASK(12, 0)); 1378 1379 v4l2_dbg(1, debug, &isc->v4l2_dev, 1380 "isc wb: component %d, final gain %u\n", 1381 c, ctrls->gain[c]); 1382 } 1383 } 1384 1385 static void isc_awb_work(struct work_struct *w) 1386 { 1387 struct isc_device *isc = 1388 container_of(w, struct isc_device, awb_work); 1389 struct regmap *regmap = isc->regmap; 1390 struct isc_ctrls *ctrls = &isc->ctrls; 1391 u32 hist_id = ctrls->hist_id; 1392 u32 baysel; 1393 unsigned long flags; 1394 u32 min, max; 1395 int ret; 1396 1397 if (ctrls->hist_stat != HIST_ENABLED) 1398 return; 1399 1400 isc_hist_count(isc, &min, &max); 1401 1402 v4l2_dbg(1, debug, &isc->v4l2_dev, 1403 "isc wb mode %d: hist min %u , max %u\n", hist_id, min, max); 1404 1405 ctrls->hist_minmax[hist_id][HIST_MIN_INDEX] = min; 1406 ctrls->hist_minmax[hist_id][HIST_MAX_INDEX] = max; 1407 1408 if (hist_id != ISC_HIS_CFG_MODE_B) { 1409 hist_id++; 1410 } else { 1411 isc_wb_update(ctrls); 1412 hist_id = ISC_HIS_CFG_MODE_GR; 1413 } 1414 1415 ctrls->hist_id = hist_id; 1416 baysel = isc->config.sd_format->cfa_baycfg << ISC_HIS_CFG_BAYSEL_SHIFT; 1417 1418 ret = pm_runtime_resume_and_get(isc->dev); 1419 if (ret < 0) 1420 return; 1421 1422 /* 1423 * only update if we have all the required histograms and controls 1424 * if awb has been disabled, we need to reset registers as well. 1425 */ 1426 if (hist_id == ISC_HIS_CFG_MODE_GR || ctrls->awb == ISC_WB_NONE) { 1427 /* 1428 * It may happen that DMA Done IRQ will trigger while we are 1429 * updating white balance registers here. 1430 * In that case, only parts of the controls have been updated. 1431 * We can avoid that by locking the section. 1432 */ 1433 spin_lock_irqsave(&isc->awb_lock, flags); 1434 isc_update_awb_ctrls(isc); 1435 spin_unlock_irqrestore(&isc->awb_lock, flags); 1436 1437 /* 1438 * if we are doing just the one time white balance adjustment, 1439 * we are basically done. 1440 */ 1441 if (ctrls->awb == ISC_WB_ONETIME) { 1442 v4l2_info(&isc->v4l2_dev, 1443 "Completed one time white-balance adjustment.\n"); 1444 /* update the v4l2 controls values */ 1445 isc_update_v4l2_ctrls(isc); 1446 ctrls->awb = ISC_WB_NONE; 1447 } 1448 } 1449 regmap_write(regmap, ISC_HIS_CFG + isc->offsets.his, 1450 hist_id | baysel | ISC_HIS_CFG_RAR); 1451 1452 /* 1453 * We have to make sure the streaming has not stopped meanwhile. 1454 * ISC requires a frame to clock the internal profile update. 1455 * To avoid issues, lock the sequence with a mutex 1456 */ 1457 mutex_lock(&isc->awb_mutex); 1458 1459 /* streaming is not active anymore */ 1460 if (isc->stop) { 1461 mutex_unlock(&isc->awb_mutex); 1462 return; 1463 } 1464 1465 isc_update_profile(isc); 1466 1467 mutex_unlock(&isc->awb_mutex); 1468 1469 /* if awb has been disabled, we don't need to start another histogram */ 1470 if (ctrls->awb) 1471 regmap_write(regmap, ISC_CTRLEN, ISC_CTRL_HISREQ); 1472 1473 pm_runtime_put_sync(isc->dev); 1474 } 1475 1476 static int isc_s_ctrl(struct v4l2_ctrl *ctrl) 1477 { 1478 struct isc_device *isc = container_of(ctrl->handler, 1479 struct isc_device, ctrls.handler); 1480 struct isc_ctrls *ctrls = &isc->ctrls; 1481 1482 if (ctrl->flags & V4L2_CTRL_FLAG_INACTIVE) 1483 return 0; 1484 1485 switch (ctrl->id) { 1486 case V4L2_CID_BRIGHTNESS: 1487 ctrls->brightness = ctrl->val & ISC_CBC_BRIGHT_MASK; 1488 break; 1489 case V4L2_CID_CONTRAST: 1490 ctrls->contrast = ctrl->val & ISC_CBC_CONTRAST_MASK; 1491 break; 1492 case V4L2_CID_GAMMA: 1493 ctrls->gamma_index = ctrl->val; 1494 break; 1495 default: 1496 return -EINVAL; 1497 } 1498 1499 return 0; 1500 } 1501 1502 static const struct v4l2_ctrl_ops isc_ctrl_ops = { 1503 .s_ctrl = isc_s_ctrl, 1504 }; 1505 1506 static int isc_s_awb_ctrl(struct v4l2_ctrl *ctrl) 1507 { 1508 struct isc_device *isc = container_of(ctrl->handler, 1509 struct isc_device, ctrls.handler); 1510 struct isc_ctrls *ctrls = &isc->ctrls; 1511 1512 if (ctrl->flags & V4L2_CTRL_FLAG_INACTIVE) 1513 return 0; 1514 1515 switch (ctrl->id) { 1516 case V4L2_CID_AUTO_WHITE_BALANCE: 1517 if (ctrl->val == 1) 1518 ctrls->awb = ISC_WB_AUTO; 1519 else 1520 ctrls->awb = ISC_WB_NONE; 1521 1522 /* configure the controls with new values from v4l2 */ 1523 if (ctrl->cluster[ISC_CTRL_R_GAIN]->is_new) 1524 ctrls->gain[ISC_HIS_CFG_MODE_R] = isc->r_gain_ctrl->val; 1525 if (ctrl->cluster[ISC_CTRL_B_GAIN]->is_new) 1526 ctrls->gain[ISC_HIS_CFG_MODE_B] = isc->b_gain_ctrl->val; 1527 if (ctrl->cluster[ISC_CTRL_GR_GAIN]->is_new) 1528 ctrls->gain[ISC_HIS_CFG_MODE_GR] = isc->gr_gain_ctrl->val; 1529 if (ctrl->cluster[ISC_CTRL_GB_GAIN]->is_new) 1530 ctrls->gain[ISC_HIS_CFG_MODE_GB] = isc->gb_gain_ctrl->val; 1531 1532 if (ctrl->cluster[ISC_CTRL_R_OFF]->is_new) 1533 ctrls->offset[ISC_HIS_CFG_MODE_R] = isc->r_off_ctrl->val; 1534 if (ctrl->cluster[ISC_CTRL_B_OFF]->is_new) 1535 ctrls->offset[ISC_HIS_CFG_MODE_B] = isc->b_off_ctrl->val; 1536 if (ctrl->cluster[ISC_CTRL_GR_OFF]->is_new) 1537 ctrls->offset[ISC_HIS_CFG_MODE_GR] = isc->gr_off_ctrl->val; 1538 if (ctrl->cluster[ISC_CTRL_GB_OFF]->is_new) 1539 ctrls->offset[ISC_HIS_CFG_MODE_GB] = isc->gb_off_ctrl->val; 1540 1541 isc_update_awb_ctrls(isc); 1542 1543 mutex_lock(&isc->awb_mutex); 1544 if (vb2_is_streaming(&isc->vb2_vidq)) { 1545 /* 1546 * If we are streaming, we can update profile to 1547 * have the new settings in place. 1548 */ 1549 isc_update_profile(isc); 1550 } else { 1551 /* 1552 * The auto cluster will activate automatically this 1553 * control. This has to be deactivated when not 1554 * streaming. 1555 */ 1556 v4l2_ctrl_activate(isc->do_wb_ctrl, false); 1557 } 1558 mutex_unlock(&isc->awb_mutex); 1559 1560 /* if we have autowhitebalance on, start histogram procedure */ 1561 if (ctrls->awb == ISC_WB_AUTO && 1562 vb2_is_streaming(&isc->vb2_vidq) && 1563 ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code)) 1564 isc_set_histogram(isc, true); 1565 1566 /* 1567 * for one time whitebalance adjustment, check the button, 1568 * if it's pressed, perform the one time operation. 1569 */ 1570 if (ctrls->awb == ISC_WB_NONE && 1571 ctrl->cluster[ISC_CTRL_DO_WB]->is_new && 1572 !(ctrl->cluster[ISC_CTRL_DO_WB]->flags & 1573 V4L2_CTRL_FLAG_INACTIVE)) { 1574 ctrls->awb = ISC_WB_ONETIME; 1575 isc_set_histogram(isc, true); 1576 v4l2_dbg(1, debug, &isc->v4l2_dev, 1577 "One time white-balance started.\n"); 1578 } 1579 return 0; 1580 } 1581 return 0; 1582 } 1583 1584 static int isc_g_volatile_awb_ctrl(struct v4l2_ctrl *ctrl) 1585 { 1586 struct isc_device *isc = container_of(ctrl->handler, 1587 struct isc_device, ctrls.handler); 1588 struct isc_ctrls *ctrls = &isc->ctrls; 1589 1590 switch (ctrl->id) { 1591 /* being a cluster, this id will be called for every control */ 1592 case V4L2_CID_AUTO_WHITE_BALANCE: 1593 ctrl->cluster[ISC_CTRL_R_GAIN]->val = 1594 ctrls->gain[ISC_HIS_CFG_MODE_R]; 1595 ctrl->cluster[ISC_CTRL_B_GAIN]->val = 1596 ctrls->gain[ISC_HIS_CFG_MODE_B]; 1597 ctrl->cluster[ISC_CTRL_GR_GAIN]->val = 1598 ctrls->gain[ISC_HIS_CFG_MODE_GR]; 1599 ctrl->cluster[ISC_CTRL_GB_GAIN]->val = 1600 ctrls->gain[ISC_HIS_CFG_MODE_GB]; 1601 1602 ctrl->cluster[ISC_CTRL_R_OFF]->val = 1603 ctrls->offset[ISC_HIS_CFG_MODE_R]; 1604 ctrl->cluster[ISC_CTRL_B_OFF]->val = 1605 ctrls->offset[ISC_HIS_CFG_MODE_B]; 1606 ctrl->cluster[ISC_CTRL_GR_OFF]->val = 1607 ctrls->offset[ISC_HIS_CFG_MODE_GR]; 1608 ctrl->cluster[ISC_CTRL_GB_OFF]->val = 1609 ctrls->offset[ISC_HIS_CFG_MODE_GB]; 1610 break; 1611 } 1612 return 0; 1613 } 1614 1615 static const struct v4l2_ctrl_ops isc_awb_ops = { 1616 .s_ctrl = isc_s_awb_ctrl, 1617 .g_volatile_ctrl = isc_g_volatile_awb_ctrl, 1618 }; 1619 1620 #define ISC_CTRL_OFF(_name, _id, _name_str) \ 1621 static const struct v4l2_ctrl_config _name = { \ 1622 .ops = &isc_awb_ops, \ 1623 .id = _id, \ 1624 .name = _name_str, \ 1625 .type = V4L2_CTRL_TYPE_INTEGER, \ 1626 .flags = V4L2_CTRL_FLAG_SLIDER, \ 1627 .min = -4095, \ 1628 .max = 4095, \ 1629 .step = 1, \ 1630 .def = 0, \ 1631 } 1632 1633 ISC_CTRL_OFF(isc_r_off_ctrl, ISC_CID_R_OFFSET, "Red Component Offset"); 1634 ISC_CTRL_OFF(isc_b_off_ctrl, ISC_CID_B_OFFSET, "Blue Component Offset"); 1635 ISC_CTRL_OFF(isc_gr_off_ctrl, ISC_CID_GR_OFFSET, "Green Red Component Offset"); 1636 ISC_CTRL_OFF(isc_gb_off_ctrl, ISC_CID_GB_OFFSET, "Green Blue Component Offset"); 1637 1638 #define ISC_CTRL_GAIN(_name, _id, _name_str) \ 1639 static const struct v4l2_ctrl_config _name = { \ 1640 .ops = &isc_awb_ops, \ 1641 .id = _id, \ 1642 .name = _name_str, \ 1643 .type = V4L2_CTRL_TYPE_INTEGER, \ 1644 .flags = V4L2_CTRL_FLAG_SLIDER, \ 1645 .min = 0, \ 1646 .max = 8191, \ 1647 .step = 1, \ 1648 .def = 512, \ 1649 } 1650 1651 ISC_CTRL_GAIN(isc_r_gain_ctrl, ISC_CID_R_GAIN, "Red Component Gain"); 1652 ISC_CTRL_GAIN(isc_b_gain_ctrl, ISC_CID_B_GAIN, "Blue Component Gain"); 1653 ISC_CTRL_GAIN(isc_gr_gain_ctrl, ISC_CID_GR_GAIN, "Green Red Component Gain"); 1654 ISC_CTRL_GAIN(isc_gb_gain_ctrl, ISC_CID_GB_GAIN, "Green Blue Component Gain"); 1655 1656 static int isc_ctrl_init(struct isc_device *isc) 1657 { 1658 const struct v4l2_ctrl_ops *ops = &isc_ctrl_ops; 1659 struct isc_ctrls *ctrls = &isc->ctrls; 1660 struct v4l2_ctrl_handler *hdl = &ctrls->handler; 1661 int ret; 1662 1663 ctrls->hist_stat = HIST_INIT; 1664 isc_reset_awb_ctrls(isc); 1665 1666 ret = v4l2_ctrl_handler_init(hdl, 13); 1667 if (ret < 0) 1668 return ret; 1669 1670 /* Initialize product specific controls. For example, contrast */ 1671 isc->config_ctrls(isc, ops); 1672 1673 ctrls->brightness = 0; 1674 1675 v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BRIGHTNESS, -1024, 1023, 1, 0); 1676 v4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAMMA, 0, isc->gamma_max, 1, 1677 isc->gamma_max); 1678 isc->awb_ctrl = v4l2_ctrl_new_std(hdl, &isc_awb_ops, 1679 V4L2_CID_AUTO_WHITE_BALANCE, 1680 0, 1, 1, 1); 1681 1682 /* do_white_balance is a button, so min,max,step,default are ignored */ 1683 isc->do_wb_ctrl = v4l2_ctrl_new_std(hdl, &isc_awb_ops, 1684 V4L2_CID_DO_WHITE_BALANCE, 1685 0, 0, 0, 0); 1686 1687 if (!isc->do_wb_ctrl) { 1688 ret = hdl->error; 1689 v4l2_ctrl_handler_free(hdl); 1690 return ret; 1691 } 1692 1693 v4l2_ctrl_activate(isc->do_wb_ctrl, false); 1694 1695 isc->r_gain_ctrl = v4l2_ctrl_new_custom(hdl, &isc_r_gain_ctrl, NULL); 1696 isc->b_gain_ctrl = v4l2_ctrl_new_custom(hdl, &isc_b_gain_ctrl, NULL); 1697 isc->gr_gain_ctrl = v4l2_ctrl_new_custom(hdl, &isc_gr_gain_ctrl, NULL); 1698 isc->gb_gain_ctrl = v4l2_ctrl_new_custom(hdl, &isc_gb_gain_ctrl, NULL); 1699 isc->r_off_ctrl = v4l2_ctrl_new_custom(hdl, &isc_r_off_ctrl, NULL); 1700 isc->b_off_ctrl = v4l2_ctrl_new_custom(hdl, &isc_b_off_ctrl, NULL); 1701 isc->gr_off_ctrl = v4l2_ctrl_new_custom(hdl, &isc_gr_off_ctrl, NULL); 1702 isc->gb_off_ctrl = v4l2_ctrl_new_custom(hdl, &isc_gb_off_ctrl, NULL); 1703 1704 /* 1705 * The cluster is in auto mode with autowhitebalance enabled 1706 * and manual mode otherwise. 1707 */ 1708 v4l2_ctrl_auto_cluster(10, &isc->awb_ctrl, 0, true); 1709 1710 v4l2_ctrl_handler_setup(hdl); 1711 1712 return 0; 1713 } 1714 1715 static int isc_async_bound(struct v4l2_async_notifier *notifier, 1716 struct v4l2_subdev *subdev, 1717 struct v4l2_async_subdev *asd) 1718 { 1719 struct isc_device *isc = container_of(notifier->v4l2_dev, 1720 struct isc_device, v4l2_dev); 1721 struct isc_subdev_entity *subdev_entity = 1722 container_of(notifier, struct isc_subdev_entity, notifier); 1723 int pad; 1724 1725 if (video_is_registered(&isc->video_dev)) { 1726 v4l2_err(&isc->v4l2_dev, "only supports one sub-device.\n"); 1727 return -EBUSY; 1728 } 1729 1730 subdev_entity->sd = subdev; 1731 1732 pad = media_entity_get_fwnode_pad(&subdev->entity, asd->match.fwnode, 1733 MEDIA_PAD_FL_SOURCE); 1734 if (pad < 0) { 1735 v4l2_err(&isc->v4l2_dev, "failed to find pad for %s\n", 1736 subdev->name); 1737 return pad; 1738 } 1739 1740 isc->remote_pad = pad; 1741 1742 return 0; 1743 } 1744 1745 static void isc_async_unbind(struct v4l2_async_notifier *notifier, 1746 struct v4l2_subdev *subdev, 1747 struct v4l2_async_subdev *asd) 1748 { 1749 struct isc_device *isc = container_of(notifier->v4l2_dev, 1750 struct isc_device, v4l2_dev); 1751 mutex_destroy(&isc->awb_mutex); 1752 cancel_work_sync(&isc->awb_work); 1753 video_unregister_device(&isc->video_dev); 1754 v4l2_ctrl_handler_free(&isc->ctrls.handler); 1755 } 1756 1757 struct isc_format *isc_find_format_by_code(struct isc_device *isc, 1758 unsigned int code, int *index) 1759 { 1760 struct isc_format *fmt = &isc->formats_list[0]; 1761 unsigned int i; 1762 1763 for (i = 0; i < isc->formats_list_size; i++) { 1764 if (fmt->mbus_code == code) { 1765 *index = i; 1766 return fmt; 1767 } 1768 1769 fmt++; 1770 } 1771 1772 return NULL; 1773 } 1774 EXPORT_SYMBOL_GPL(isc_find_format_by_code); 1775 1776 static int isc_set_default_fmt(struct isc_device *isc) 1777 { 1778 struct v4l2_format f = { 1779 .type = V4L2_BUF_TYPE_VIDEO_CAPTURE, 1780 .fmt.pix = { 1781 .width = VGA_WIDTH, 1782 .height = VGA_HEIGHT, 1783 .field = V4L2_FIELD_NONE, 1784 .pixelformat = isc->controller_formats[0].fourcc, 1785 }, 1786 }; 1787 int ret; 1788 1789 ret = isc_try_fmt(isc, &f); 1790 if (ret) 1791 return ret; 1792 1793 isc->fmt = f; 1794 return 0; 1795 } 1796 1797 static int isc_async_complete(struct v4l2_async_notifier *notifier) 1798 { 1799 struct isc_device *isc = container_of(notifier->v4l2_dev, 1800 struct isc_device, v4l2_dev); 1801 struct video_device *vdev = &isc->video_dev; 1802 struct vb2_queue *q = &isc->vb2_vidq; 1803 int ret = 0; 1804 1805 INIT_WORK(&isc->awb_work, isc_awb_work); 1806 1807 ret = v4l2_device_register_subdev_nodes(&isc->v4l2_dev); 1808 if (ret < 0) { 1809 v4l2_err(&isc->v4l2_dev, "Failed to register subdev nodes\n"); 1810 return ret; 1811 } 1812 1813 isc->current_subdev = container_of(notifier, 1814 struct isc_subdev_entity, notifier); 1815 mutex_init(&isc->lock); 1816 mutex_init(&isc->awb_mutex); 1817 1818 init_completion(&isc->comp); 1819 1820 /* Initialize videobuf2 queue */ 1821 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; 1822 q->io_modes = VB2_MMAP | VB2_DMABUF | VB2_READ; 1823 q->drv_priv = isc; 1824 q->buf_struct_size = sizeof(struct isc_buffer); 1825 q->ops = &isc_vb2_ops; 1826 q->mem_ops = &vb2_dma_contig_memops; 1827 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; 1828 q->lock = &isc->lock; 1829 q->min_buffers_needed = 1; 1830 q->dev = isc->dev; 1831 1832 ret = vb2_queue_init(q); 1833 if (ret < 0) { 1834 v4l2_err(&isc->v4l2_dev, 1835 "vb2_queue_init() failed: %d\n", ret); 1836 goto isc_async_complete_err; 1837 } 1838 1839 /* Init video dma queues */ 1840 INIT_LIST_HEAD(&isc->dma_queue); 1841 spin_lock_init(&isc->dma_queue_lock); 1842 spin_lock_init(&isc->awb_lock); 1843 1844 ret = isc_set_default_fmt(isc); 1845 if (ret) { 1846 v4l2_err(&isc->v4l2_dev, "Could not set default format\n"); 1847 goto isc_async_complete_err; 1848 } 1849 1850 ret = isc_ctrl_init(isc); 1851 if (ret) { 1852 v4l2_err(&isc->v4l2_dev, "Init isc ctrols failed: %d\n", ret); 1853 goto isc_async_complete_err; 1854 } 1855 1856 /* Register video device */ 1857 strscpy(vdev->name, KBUILD_MODNAME, sizeof(vdev->name)); 1858 vdev->release = video_device_release_empty; 1859 vdev->fops = &isc_fops; 1860 vdev->ioctl_ops = &isc_ioctl_ops; 1861 vdev->v4l2_dev = &isc->v4l2_dev; 1862 vdev->vfl_dir = VFL_DIR_RX; 1863 vdev->queue = q; 1864 vdev->lock = &isc->lock; 1865 vdev->ctrl_handler = &isc->ctrls.handler; 1866 vdev->device_caps = V4L2_CAP_STREAMING | V4L2_CAP_VIDEO_CAPTURE | 1867 V4L2_CAP_IO_MC; 1868 video_set_drvdata(vdev, isc); 1869 1870 ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1); 1871 if (ret < 0) { 1872 v4l2_err(&isc->v4l2_dev, 1873 "video_register_device failed: %d\n", ret); 1874 goto isc_async_complete_err; 1875 } 1876 1877 ret = isc_scaler_link(isc); 1878 if (ret < 0) 1879 goto isc_async_complete_unregister_device; 1880 1881 ret = media_device_register(&isc->mdev); 1882 if (ret < 0) 1883 goto isc_async_complete_unregister_device; 1884 1885 return 0; 1886 1887 isc_async_complete_unregister_device: 1888 video_unregister_device(vdev); 1889 1890 isc_async_complete_err: 1891 mutex_destroy(&isc->awb_mutex); 1892 mutex_destroy(&isc->lock); 1893 return ret; 1894 } 1895 1896 const struct v4l2_async_notifier_operations microchip_isc_async_ops = { 1897 .bound = isc_async_bound, 1898 .unbind = isc_async_unbind, 1899 .complete = isc_async_complete, 1900 }; 1901 EXPORT_SYMBOL_GPL(microchip_isc_async_ops); 1902 1903 void microchip_isc_subdev_cleanup(struct isc_device *isc) 1904 { 1905 struct isc_subdev_entity *subdev_entity; 1906 1907 list_for_each_entry(subdev_entity, &isc->subdev_entities, list) { 1908 v4l2_async_nf_unregister(&subdev_entity->notifier); 1909 v4l2_async_nf_cleanup(&subdev_entity->notifier); 1910 } 1911 1912 INIT_LIST_HEAD(&isc->subdev_entities); 1913 } 1914 EXPORT_SYMBOL_GPL(microchip_isc_subdev_cleanup); 1915 1916 int microchip_isc_pipeline_init(struct isc_device *isc) 1917 { 1918 struct device *dev = isc->dev; 1919 struct regmap *regmap = isc->regmap; 1920 struct regmap_field *regs; 1921 unsigned int i; 1922 1923 /* 1924 * DPCEN-->GDCEN-->BLCEN-->WB-->CFA-->CC--> 1925 * GAM-->VHXS-->CSC-->CBC-->SUB422-->SUB420 1926 */ 1927 const struct reg_field regfields[ISC_PIPE_LINE_NODE_NUM] = { 1928 REG_FIELD(ISC_DPC_CTRL, 0, 0), 1929 REG_FIELD(ISC_DPC_CTRL, 1, 1), 1930 REG_FIELD(ISC_DPC_CTRL, 2, 2), 1931 REG_FIELD(ISC_WB_CTRL, 0, 0), 1932 REG_FIELD(ISC_CFA_CTRL, 0, 0), 1933 REG_FIELD(ISC_CC_CTRL, 0, 0), 1934 REG_FIELD(ISC_GAM_CTRL, 0, 0), 1935 REG_FIELD(ISC_GAM_CTRL, 1, 1), 1936 REG_FIELD(ISC_GAM_CTRL, 2, 2), 1937 REG_FIELD(ISC_GAM_CTRL, 3, 3), 1938 REG_FIELD(ISC_VHXS_CTRL, 0, 0), 1939 REG_FIELD(ISC_CSC_CTRL + isc->offsets.csc, 0, 0), 1940 REG_FIELD(ISC_CBC_CTRL + isc->offsets.cbc, 0, 0), 1941 REG_FIELD(ISC_SUB422_CTRL + isc->offsets.sub422, 0, 0), 1942 REG_FIELD(ISC_SUB420_CTRL + isc->offsets.sub420, 0, 0), 1943 }; 1944 1945 for (i = 0; i < ISC_PIPE_LINE_NODE_NUM; i++) { 1946 regs = devm_regmap_field_alloc(dev, regmap, regfields[i]); 1947 if (IS_ERR(regs)) 1948 return PTR_ERR(regs); 1949 1950 isc->pipeline[i] = regs; 1951 } 1952 1953 return 0; 1954 } 1955 EXPORT_SYMBOL_GPL(microchip_isc_pipeline_init); 1956 1957 static int isc_link_validate(struct media_link *link) 1958 { 1959 struct video_device *vdev = 1960 media_entity_to_video_device(link->sink->entity); 1961 struct isc_device *isc = video_get_drvdata(vdev); 1962 int ret; 1963 1964 ret = v4l2_subdev_link_validate(link); 1965 if (ret) 1966 return ret; 1967 1968 return isc_validate(isc); 1969 } 1970 1971 static const struct media_entity_operations isc_entity_operations = { 1972 .link_validate = isc_link_validate, 1973 }; 1974 1975 int isc_mc_init(struct isc_device *isc, u32 ver) 1976 { 1977 const struct of_device_id *match; 1978 int ret; 1979 1980 isc->video_dev.entity.function = MEDIA_ENT_F_IO_V4L; 1981 isc->video_dev.entity.flags = MEDIA_ENT_FL_DEFAULT; 1982 isc->video_dev.entity.ops = &isc_entity_operations; 1983 1984 isc->pads[ISC_PAD_SINK].flags = MEDIA_PAD_FL_SINK; 1985 1986 ret = media_entity_pads_init(&isc->video_dev.entity, ISC_PADS_NUM, 1987 isc->pads); 1988 if (ret < 0) { 1989 dev_err(isc->dev, "media entity init failed\n"); 1990 return ret; 1991 } 1992 1993 isc->mdev.dev = isc->dev; 1994 1995 match = of_match_node(isc->dev->driver->of_match_table, 1996 isc->dev->of_node); 1997 1998 strscpy(isc->mdev.driver_name, KBUILD_MODNAME, 1999 sizeof(isc->mdev.driver_name)); 2000 strscpy(isc->mdev.model, match->compatible, sizeof(isc->mdev.model)); 2001 snprintf(isc->mdev.bus_info, sizeof(isc->mdev.bus_info), "platform:%s", 2002 isc->v4l2_dev.name); 2003 isc->mdev.hw_revision = ver; 2004 2005 media_device_init(&isc->mdev); 2006 2007 isc->v4l2_dev.mdev = &isc->mdev; 2008 2009 return isc_scaler_init(isc); 2010 } 2011 EXPORT_SYMBOL_GPL(isc_mc_init); 2012 2013 void isc_mc_cleanup(struct isc_device *isc) 2014 { 2015 media_entity_cleanup(&isc->video_dev.entity); 2016 media_device_cleanup(&isc->mdev); 2017 } 2018 EXPORT_SYMBOL_GPL(isc_mc_cleanup); 2019 2020 /* regmap configuration */ 2021 #define MICROCHIP_ISC_REG_MAX 0xd5c 2022 const struct regmap_config microchip_isc_regmap_config = { 2023 .reg_bits = 32, 2024 .reg_stride = 4, 2025 .val_bits = 32, 2026 .max_register = MICROCHIP_ISC_REG_MAX, 2027 }; 2028 EXPORT_SYMBOL_GPL(microchip_isc_regmap_config); 2029 2030 MODULE_AUTHOR("Songjun Wu"); 2031 MODULE_AUTHOR("Eugen Hristev"); 2032 MODULE_DESCRIPTION("Microchip ISC common code base"); 2033 MODULE_LICENSE("GPL v2"); 2034