1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright (c) 2021 MediaTek Inc.
4  * Author: Yunfei Dong <yunfei.dong@mediatek.com>
5  */
6 
7 #ifndef _MTK_VCODEC_DEC_HW_H_
8 #define _MTK_VCODEC_DEC_HW_H_
9 
10 #include <linux/io.h>
11 #include <linux/platform_device.h>
12 
13 #include "mtk_vcodec_dec_drv.h"
14 
15 #define VDEC_HW_ACTIVE_ADDR 0x0
16 #define VDEC_HW_ACTIVE_MASK BIT(4)
17 #define VDEC_IRQ_CFG 0x11
18 #define VDEC_IRQ_CLR 0x10
19 #define VDEC_IRQ_CFG_REG 0xa4
20 
21 #define IS_SUPPORT_VDEC_HW_IRQ(hw_idx) ((hw_idx) != MTK_VDEC_LAT_SOC)
22 
23 /**
24  * enum mtk_vdec_hw_reg_idx - subdev hardware register base index
25  * @VDEC_HW_SYS : vdec soc register index
26  * @VDEC_HW_MISC: vdec misc register index
27  * @VDEC_HW_MAX : vdec supported max register index
28  */
29 enum mtk_vdec_hw_reg_idx {
30 	VDEC_HW_SYS,
31 	VDEC_HW_MISC,
32 	VDEC_HW_MAX
33 };
34 
35 /**
36  * struct mtk_vdec_hw_dev - vdec hardware driver data
37  * @plat_dev: platform device
38  * @main_dev: main device
39  * @reg_base: mapped address of MTK Vcodec registers.
40  *
41  * @curr_ctx: the context that is waiting for codec hardware
42  *
43  * @dec_irq : decoder irq resource
44  * @pm      : power management control
45  * @hw_idx  : each hardware index
46  */
47 struct mtk_vdec_hw_dev {
48 	struct platform_device *plat_dev;
49 	struct mtk_vcodec_dec_dev *main_dev;
50 	void __iomem *reg_base[VDEC_HW_MAX];
51 
52 	struct mtk_vcodec_dec_ctx *curr_ctx;
53 
54 	int dec_irq;
55 	struct mtk_vcodec_pm pm;
56 	int hw_idx;
57 };
58 
59 #endif /* _MTK_VCODEC_DEC_HW_H_ */
60