1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (c) 2022 MediaTek Inc.
4  * Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
5  */
6 
7 #ifndef __MTK_MDP3_VPU_H__
8 #define __MTK_MDP3_VPU_H__
9 
10 #include <linux/platform_device.h>
11 #include "mtk-img-ipi.h"
12 
13 enum mdp_ipi_result {
14 	MDP_IPI_SUCCESS	= 0,
15 	MDP_IPI_ENOMEM	= 12,
16 	MDP_IPI_EBUSY	= 16,
17 	MDP_IPI_EINVAL	= 22,
18 	MDP_IPI_EMINST	= 24,
19 	MDP_IPI_ERANGE	= 34,
20 	MDP_IPI_NR_ERRNO,
21 
22 	MDP_IPI_EOTHER	= MDP_IPI_NR_ERRNO,
23 	MDP_IPI_PATH_CANT_MERGE,
24 	MDP_IPI_OP_FAIL,
25 };
26 
27 struct mdp_ipi_init_msg {
28 	u32	status;
29 	u64	drv_data;
30 	u32	work_addr;	/* [in] working buffer address */
31 	u32	work_size;	/* [in] working buffer size */
32 } __packed;
33 
34 struct mdp_ipi_deinit_msg {
35 	u32	status;
36 	u64	drv_data;
37 	u32	work_addr;
38 } __packed;
39 
40 enum mdp_config_id {
41 	MDP_DEV_M2M = 0,
42 	MDP_CONFIG_POOL_SIZE	/* ALWAYS keep at the end */
43 };
44 
45 struct mdp_config_pool {
46 	u64			cfg_count[MDP_CONFIG_POOL_SIZE];
47 	struct img_config	configs[MDP_CONFIG_POOL_SIZE];
48 };
49 
50 struct mdp_vpu_dev {
51 	/* synchronization protect for accessing vpu working buffer info */
52 	struct mutex		*lock;
53 	struct mtk_scp		*scp;
54 	struct completion	ipi_acked;
55 	void			*work;
56 	dma_addr_t		work_addr;
57 	size_t			work_size;
58 	struct mdp_config_pool	*pool;
59 	u32			status;
60 };
61 
62 struct mdp_vpu_ctx {
63 	struct mdp_vpu_dev	*vpu_dev;
64 	u32			config_id;
65 	struct img_config	*config;
66 	u32			inst_addr;
67 };
68 
69 void mdp_vpu_shared_mem_free(struct mdp_vpu_dev *vpu);
70 int mdp_vpu_dev_init(struct mdp_vpu_dev *vpu, struct mtk_scp *scp,
71 		     struct mutex *lock /* for sync */);
72 int mdp_vpu_dev_deinit(struct mdp_vpu_dev *vpu);
73 int mdp_vpu_ctx_init(struct mdp_vpu_ctx *ctx, struct mdp_vpu_dev *vpu,
74 		     enum mdp_config_id id);
75 int mdp_vpu_ctx_deinit(struct mdp_vpu_ctx *ctx);
76 int mdp_vpu_process(struct mdp_vpu_ctx *vpu, struct img_ipi_frameparam *param);
77 
78 #endif  /* __MTK_MDP3_VPU_H__ */
79