1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022 MediaTek Inc. 4 * Author: Holmes Chiou <holmes.chiou@mediatek.com> 5 * Ping-Hsun Wu <ping-hsun.wu@mediatek.com> 6 */ 7 8 #ifndef __MTK_IMG_IPI_H__ 9 #define __MTK_IMG_IPI_H__ 10 11 #include <linux/types.h> 12 13 /* 14 * ISP-MDP generic input information 15 * MD5 of the target SCP blob: 16 * 6da52bdcf4bf76a0983b313e1d4745d6 17 */ 18 19 #define IMG_MAX_HW_INPUTS 3 20 21 #define IMG_MAX_HW_OUTPUTS 4 22 23 #define IMG_MAX_PLANES 3 24 25 #define IMG_IPI_INIT 1 26 #define IMG_IPI_DEINIT 2 27 #define IMG_IPI_FRAME 3 28 #define IMG_IPI_DEBUG 4 29 30 struct img_timeval { 31 u32 tv_sec; 32 u32 tv_usec; 33 } __packed; 34 35 struct img_addr { 36 u64 va; /* Used for Linux OS access */ 37 u32 pa; /* Used for CM4 access */ 38 u32 iova; /* Used for IOMMU HW access */ 39 } __packed; 40 41 struct tuning_addr { 42 u64 present; 43 u32 pa; /* Used for CM4 access */ 44 u32 iova; /* Used for IOMMU HW access */ 45 } __packed; 46 47 struct img_sw_addr { 48 u64 va; /* Used for APMCU access */ 49 u32 pa; /* Used for CM4 access */ 50 } __packed; 51 52 struct img_plane_format { 53 u32 size; 54 u32 stride; 55 } __packed; 56 57 struct img_pix_format { 58 u32 width; 59 u32 height; 60 u32 colorformat; /* enum mdp_color */ 61 u32 ycbcr_prof; /* enum mdp_ycbcr_profile */ 62 struct img_plane_format plane_fmt[IMG_MAX_PLANES]; 63 } __packed; 64 65 struct img_image_buffer { 66 struct img_pix_format format; 67 u32 iova[IMG_MAX_PLANES]; 68 /* enum mdp_buffer_usage, FD or advanced ISP usages */ 69 u32 usage; 70 } __packed; 71 72 #define IMG_SUBPIXEL_SHIFT 20 73 74 struct img_crop { 75 s32 left; 76 s32 top; 77 u32 width; 78 u32 height; 79 u32 left_subpix; 80 u32 top_subpix; 81 u32 width_subpix; 82 u32 height_subpix; 83 } __packed; 84 85 #define IMG_CTRL_FLAG_HFLIP BIT(0) 86 #define IMG_CTRL_FLAG_DITHER BIT(1) 87 #define IMG_CTRL_FLAG_SHARPNESS BIT(4) 88 #define IMG_CTRL_FLAG_HDR BIT(5) 89 #define IMG_CTRL_FLAG_DRE BIT(6) 90 91 struct img_input { 92 struct img_image_buffer buffer; 93 u32 flags; /* HDR, DRE, dither */ 94 } __packed; 95 96 struct img_output { 97 struct img_image_buffer buffer; 98 struct img_crop crop; 99 s32 rotation; 100 u32 flags; /* H-flip, sharpness, dither */ 101 } __packed; 102 103 struct img_ipi_frameparam { 104 u32 index; 105 u32 frame_no; 106 struct img_timeval timestamp; 107 u32 type; /* enum mdp_stream_type */ 108 u32 state; 109 u32 num_inputs; 110 u32 num_outputs; 111 u64 drv_data; 112 struct img_input inputs[IMG_MAX_HW_INPUTS]; 113 struct img_output outputs[IMG_MAX_HW_OUTPUTS]; 114 struct tuning_addr tuning_data; 115 struct img_addr subfrm_data; 116 struct img_sw_addr config_data; 117 struct img_sw_addr self_data; 118 } __packed; 119 120 struct img_sw_buffer { 121 u64 handle; /* Used for APMCU access */ 122 u32 scp_addr; /* Used for CM4 access */ 123 } __packed; 124 125 struct img_ipi_param { 126 u32 usage; 127 struct img_sw_buffer frm_param; 128 } __packed; 129 130 struct img_frameparam { 131 struct list_head list_entry; 132 struct img_ipi_frameparam frameparam; 133 } __packed; 134 135 /* ISP-MDP generic output information */ 136 137 struct img_comp_frame { 138 u32 output_disable; 139 u32 bypass; 140 u32 in_width; 141 u32 in_height; 142 u32 out_width; 143 u32 out_height; 144 struct img_crop crop; 145 u32 in_total_width; 146 u32 out_total_width; 147 } __packed; 148 149 struct img_region { 150 s32 left; 151 s32 right; 152 s32 top; 153 s32 bottom; 154 } __packed; 155 156 struct img_offset { 157 s32 left; 158 s32 top; 159 u32 left_subpix; 160 u32 top_subpix; 161 } __packed; 162 163 struct img_comp_subfrm { 164 u32 tile_disable; 165 struct img_region in; 166 struct img_region out; 167 struct img_offset luma; 168 struct img_offset chroma; 169 s32 out_vertical; /* Output vertical index */ 170 s32 out_horizontal; /* Output horizontal index */ 171 } __packed; 172 173 #define IMG_MAX_SUBFRAMES 14 174 175 struct mdp_rdma_subfrm { 176 u32 offset[IMG_MAX_PLANES]; 177 u32 offset_0_p; 178 u32 src; 179 u32 clip; 180 u32 clip_ofst; 181 } __packed; 182 183 struct mdp_rdma_data { 184 u32 src_ctrl; 185 u32 control; 186 u32 iova[IMG_MAX_PLANES]; 187 u32 iova_end[IMG_MAX_PLANES]; 188 u32 mf_bkgd; 189 u32 mf_bkgd_in_pxl; 190 u32 sf_bkgd; 191 u32 ufo_dec_y; 192 u32 ufo_dec_c; 193 u32 transform; 194 struct mdp_rdma_subfrm subfrms[IMG_MAX_SUBFRAMES]; 195 } __packed; 196 197 struct mdp_rsz_subfrm { 198 u32 control2; 199 u32 src; 200 u32 clip; 201 } __packed; 202 203 struct mdp_rsz_data { 204 u32 coeff_step_x; 205 u32 coeff_step_y; 206 u32 control1; 207 u32 control2; 208 struct mdp_rsz_subfrm subfrms[IMG_MAX_SUBFRAMES]; 209 } __packed; 210 211 struct mdp_wrot_subfrm { 212 u32 offset[IMG_MAX_PLANES]; 213 u32 src; 214 u32 clip; 215 u32 clip_ofst; 216 u32 main_buf; 217 } __packed; 218 219 struct mdp_wrot_data { 220 u32 iova[IMG_MAX_PLANES]; 221 u32 control; 222 u32 stride[IMG_MAX_PLANES]; 223 u32 mat_ctrl; 224 u32 fifo_test; 225 u32 filter; 226 struct mdp_wrot_subfrm subfrms[IMG_MAX_SUBFRAMES]; 227 } __packed; 228 229 struct mdp_wdma_subfrm { 230 u32 offset[IMG_MAX_PLANES]; 231 u32 src; 232 u32 clip; 233 u32 clip_ofst; 234 } __packed; 235 236 struct mdp_wdma_data { 237 u32 wdma_cfg; 238 u32 iova[IMG_MAX_PLANES]; 239 u32 w_in_byte; 240 u32 uv_stride; 241 struct mdp_wdma_subfrm subfrms[IMG_MAX_SUBFRAMES]; 242 } __packed; 243 244 struct isp_data { 245 u64 dl_flags; /* 1 << (enum mdp_comp_type) */ 246 u32 smxi_iova[4]; 247 u32 cq_idx; 248 u32 cq_iova; 249 u32 tpipe_iova[IMG_MAX_SUBFRAMES]; 250 } __packed; 251 252 struct img_compparam { 253 u32 type; /* enum mdp_comp_id */ 254 u32 id; /* engine alias_id */ 255 u32 input; 256 u32 outputs[IMG_MAX_HW_OUTPUTS]; 257 u32 num_outputs; 258 struct img_comp_frame frame; 259 struct img_comp_subfrm subfrms[IMG_MAX_SUBFRAMES]; 260 u32 num_subfrms; 261 union { 262 struct mdp_rdma_data rdma; 263 struct mdp_rsz_data rsz; 264 struct mdp_wrot_data wrot; 265 struct mdp_wdma_data wdma; 266 struct isp_data isp; 267 }; 268 } __packed; 269 270 #define IMG_MAX_COMPONENTS 20 271 272 struct img_mux { 273 u32 reg; 274 u32 value; 275 u32 subsys_id; 276 } __packed; 277 278 struct img_mmsys_ctrl { 279 struct img_mux sets[IMG_MAX_COMPONENTS * 2]; 280 u32 num_sets; 281 } __packed; 282 283 struct img_config { 284 struct img_compparam components[IMG_MAX_COMPONENTS]; 285 u32 num_components; 286 struct img_mmsys_ctrl ctrls[IMG_MAX_SUBFRAMES]; 287 u32 num_subfrms; 288 } __packed; 289 290 #endif /* __MTK_IMG_IPI_H__ */ 291