1dc7bbea9SMauro Carvalho Chehab /* SPDX-License-Identifier: GPL-2.0 */
2dc7bbea9SMauro Carvalho Chehab /*
3dc7bbea9SMauro Carvalho Chehab * Marvell camera core structures.
4dc7bbea9SMauro Carvalho Chehab *
5dc7bbea9SMauro Carvalho Chehab * Copyright 2011 Jonathan Corbet corbet@lwn.net
6dc7bbea9SMauro Carvalho Chehab */
7dc7bbea9SMauro Carvalho Chehab #ifndef _MCAM_CORE_H
8dc7bbea9SMauro Carvalho Chehab #define _MCAM_CORE_H
9dc7bbea9SMauro Carvalho Chehab
10dc7bbea9SMauro Carvalho Chehab #include <linux/list.h>
11dc7bbea9SMauro Carvalho Chehab #include <linux/clk-provider.h>
12dc7bbea9SMauro Carvalho Chehab #include <media/v4l2-common.h>
13dc7bbea9SMauro Carvalho Chehab #include <media/v4l2-ctrls.h>
14dc7bbea9SMauro Carvalho Chehab #include <media/v4l2-dev.h>
15dc7bbea9SMauro Carvalho Chehab #include <media/videobuf2-v4l2.h>
16dc7bbea9SMauro Carvalho Chehab
17dc7bbea9SMauro Carvalho Chehab /*
18dc7bbea9SMauro Carvalho Chehab * Create our own symbols for the supported buffer modes, but, for now,
19dc7bbea9SMauro Carvalho Chehab * base them entirely on which videobuf2 options have been selected.
20dc7bbea9SMauro Carvalho Chehab */
21dc7bbea9SMauro Carvalho Chehab #if IS_ENABLED(CONFIG_VIDEOBUF2_VMALLOC)
22dc7bbea9SMauro Carvalho Chehab #define MCAM_MODE_VMALLOC 1
23dc7bbea9SMauro Carvalho Chehab #endif
24dc7bbea9SMauro Carvalho Chehab
25dc7bbea9SMauro Carvalho Chehab #if IS_ENABLED(CONFIG_VIDEOBUF2_DMA_CONTIG)
26dc7bbea9SMauro Carvalho Chehab #define MCAM_MODE_DMA_CONTIG 1
27dc7bbea9SMauro Carvalho Chehab #endif
28dc7bbea9SMauro Carvalho Chehab
29dc7bbea9SMauro Carvalho Chehab #if IS_ENABLED(CONFIG_VIDEOBUF2_DMA_SG)
30dc7bbea9SMauro Carvalho Chehab #define MCAM_MODE_DMA_SG 1
31dc7bbea9SMauro Carvalho Chehab #endif
32dc7bbea9SMauro Carvalho Chehab
33dc7bbea9SMauro Carvalho Chehab #if !defined(MCAM_MODE_VMALLOC) && !defined(MCAM_MODE_DMA_CONTIG) && \
34dc7bbea9SMauro Carvalho Chehab !defined(MCAM_MODE_DMA_SG)
35*f068a6ceSHans Verkuil #error One of the vb2 buffer modes must be selected in the config
36dc7bbea9SMauro Carvalho Chehab #endif
37dc7bbea9SMauro Carvalho Chehab
38dc7bbea9SMauro Carvalho Chehab
39dc7bbea9SMauro Carvalho Chehab enum mcam_state {
40dc7bbea9SMauro Carvalho Chehab S_NOTREADY, /* Not yet initialized */
41dc7bbea9SMauro Carvalho Chehab S_IDLE, /* Just hanging around */
42dc7bbea9SMauro Carvalho Chehab S_FLAKED, /* Some sort of problem */
43dc7bbea9SMauro Carvalho Chehab S_STREAMING, /* Streaming data */
44dc7bbea9SMauro Carvalho Chehab S_BUFWAIT /* streaming requested but no buffers yet */
45dc7bbea9SMauro Carvalho Chehab };
46dc7bbea9SMauro Carvalho Chehab #define MAX_DMA_BUFS 3
47dc7bbea9SMauro Carvalho Chehab
48dc7bbea9SMauro Carvalho Chehab /*
49dc7bbea9SMauro Carvalho Chehab * Different platforms work best with different buffer modes, so we
50dc7bbea9SMauro Carvalho Chehab * let the platform pick.
51dc7bbea9SMauro Carvalho Chehab */
52dc7bbea9SMauro Carvalho Chehab enum mcam_buffer_mode {
53dc7bbea9SMauro Carvalho Chehab B_vmalloc = 0,
54dc7bbea9SMauro Carvalho Chehab B_DMA_contig = 1,
55dc7bbea9SMauro Carvalho Chehab B_DMA_sg = 2
56dc7bbea9SMauro Carvalho Chehab };
57dc7bbea9SMauro Carvalho Chehab
58dc7bbea9SMauro Carvalho Chehab enum mcam_chip_id {
59dc7bbea9SMauro Carvalho Chehab MCAM_CAFE,
60dc7bbea9SMauro Carvalho Chehab MCAM_ARMADA610,
61dc7bbea9SMauro Carvalho Chehab };
62dc7bbea9SMauro Carvalho Chehab
63dc7bbea9SMauro Carvalho Chehab /*
64dc7bbea9SMauro Carvalho Chehab * Is a given buffer mode supported by the current kernel configuration?
65dc7bbea9SMauro Carvalho Chehab */
mcam_buffer_mode_supported(enum mcam_buffer_mode mode)66dc7bbea9SMauro Carvalho Chehab static inline int mcam_buffer_mode_supported(enum mcam_buffer_mode mode)
67dc7bbea9SMauro Carvalho Chehab {
68dc7bbea9SMauro Carvalho Chehab switch (mode) {
69dc7bbea9SMauro Carvalho Chehab #ifdef MCAM_MODE_VMALLOC
70dc7bbea9SMauro Carvalho Chehab case B_vmalloc:
71dc7bbea9SMauro Carvalho Chehab #endif
72dc7bbea9SMauro Carvalho Chehab #ifdef MCAM_MODE_DMA_CONTIG
73dc7bbea9SMauro Carvalho Chehab case B_DMA_contig:
74dc7bbea9SMauro Carvalho Chehab #endif
75dc7bbea9SMauro Carvalho Chehab #ifdef MCAM_MODE_DMA_SG
76dc7bbea9SMauro Carvalho Chehab case B_DMA_sg:
77dc7bbea9SMauro Carvalho Chehab #endif
78dc7bbea9SMauro Carvalho Chehab return 1;
79dc7bbea9SMauro Carvalho Chehab default:
80dc7bbea9SMauro Carvalho Chehab return 0;
81dc7bbea9SMauro Carvalho Chehab }
82dc7bbea9SMauro Carvalho Chehab }
83dc7bbea9SMauro Carvalho Chehab
84dc7bbea9SMauro Carvalho Chehab /*
85dc7bbea9SMauro Carvalho Chehab * Basic frame states
86dc7bbea9SMauro Carvalho Chehab */
87dc7bbea9SMauro Carvalho Chehab struct mcam_frame_state {
88dc7bbea9SMauro Carvalho Chehab unsigned int frames;
89dc7bbea9SMauro Carvalho Chehab unsigned int singles;
90dc7bbea9SMauro Carvalho Chehab unsigned int delivered;
91dc7bbea9SMauro Carvalho Chehab };
92dc7bbea9SMauro Carvalho Chehab
93dc7bbea9SMauro Carvalho Chehab #define NR_MCAM_CLK 3
94dc7bbea9SMauro Carvalho Chehab
95dc7bbea9SMauro Carvalho Chehab /*
96dc7bbea9SMauro Carvalho Chehab * A description of one of our devices.
97dc7bbea9SMauro Carvalho Chehab * Locking: controlled by s_mutex. Certain fields, however, require
98dc7bbea9SMauro Carvalho Chehab * the dev_lock spinlock; they are marked as such by comments.
99dc7bbea9SMauro Carvalho Chehab * dev_lock is also required for access to device registers.
100dc7bbea9SMauro Carvalho Chehab */
101dc7bbea9SMauro Carvalho Chehab struct mcam_camera {
102dc7bbea9SMauro Carvalho Chehab /*
103dc7bbea9SMauro Carvalho Chehab * These fields should be set by the platform code prior to
104dc7bbea9SMauro Carvalho Chehab * calling mcam_register().
105dc7bbea9SMauro Carvalho Chehab */
106dc7bbea9SMauro Carvalho Chehab unsigned char __iomem *regs;
107dc7bbea9SMauro Carvalho Chehab unsigned regs_size; /* size in bytes of the register space */
108dc7bbea9SMauro Carvalho Chehab spinlock_t dev_lock;
109dc7bbea9SMauro Carvalho Chehab struct device *dev; /* For messages, dma alloc */
110dc7bbea9SMauro Carvalho Chehab enum mcam_chip_id chip_id;
111dc7bbea9SMauro Carvalho Chehab enum mcam_buffer_mode buffer_mode;
112dc7bbea9SMauro Carvalho Chehab
113dc7bbea9SMauro Carvalho Chehab int mclk_src; /* which clock source the mclk derives from */
114dc7bbea9SMauro Carvalho Chehab int mclk_div; /* Clock Divider Value for MCLK */
115dc7bbea9SMauro Carvalho Chehab
116dc7bbea9SMauro Carvalho Chehab enum v4l2_mbus_type bus_type;
117dc7bbea9SMauro Carvalho Chehab /* MIPI support */
118dc7bbea9SMauro Carvalho Chehab /* The dphy config value, allocated in board file
119dc7bbea9SMauro Carvalho Chehab * dphy[0]: DPHY3
120dc7bbea9SMauro Carvalho Chehab * dphy[1]: DPHY5
121dc7bbea9SMauro Carvalho Chehab * dphy[2]: DPHY6
122dc7bbea9SMauro Carvalho Chehab */
123dc7bbea9SMauro Carvalho Chehab int *dphy;
124dc7bbea9SMauro Carvalho Chehab bool mipi_enabled; /* flag whether mipi is enabled already */
125dc7bbea9SMauro Carvalho Chehab int lane; /* lane number */
126dc7bbea9SMauro Carvalho Chehab
127dc7bbea9SMauro Carvalho Chehab /* clock tree support */
128dc7bbea9SMauro Carvalho Chehab struct clk *clk[NR_MCAM_CLK];
129dc7bbea9SMauro Carvalho Chehab struct clk_hw mclk_hw;
130dc7bbea9SMauro Carvalho Chehab struct clk *mclk;
131dc7bbea9SMauro Carvalho Chehab
132dc7bbea9SMauro Carvalho Chehab /*
133dc7bbea9SMauro Carvalho Chehab * Callbacks from the core to the platform code.
134dc7bbea9SMauro Carvalho Chehab */
135dc7bbea9SMauro Carvalho Chehab int (*plat_power_up) (struct mcam_camera *cam);
136dc7bbea9SMauro Carvalho Chehab void (*plat_power_down) (struct mcam_camera *cam);
137dc7bbea9SMauro Carvalho Chehab void (*calc_dphy) (struct mcam_camera *cam);
138dc7bbea9SMauro Carvalho Chehab
139dc7bbea9SMauro Carvalho Chehab /*
140dc7bbea9SMauro Carvalho Chehab * Everything below here is private to the mcam core and
141dc7bbea9SMauro Carvalho Chehab * should not be touched by the platform code.
142dc7bbea9SMauro Carvalho Chehab */
143dc7bbea9SMauro Carvalho Chehab struct v4l2_device v4l2_dev;
144dc7bbea9SMauro Carvalho Chehab struct v4l2_ctrl_handler ctrl_handler;
145dc7bbea9SMauro Carvalho Chehab enum mcam_state state;
146dc7bbea9SMauro Carvalho Chehab unsigned long flags; /* Buffer status, mainly (dev_lock) */
147dc7bbea9SMauro Carvalho Chehab
148dc7bbea9SMauro Carvalho Chehab struct mcam_frame_state frame_state; /* Frame state counter */
149dc7bbea9SMauro Carvalho Chehab /*
150dc7bbea9SMauro Carvalho Chehab * Subsystem structures.
151dc7bbea9SMauro Carvalho Chehab */
152dc7bbea9SMauro Carvalho Chehab struct video_device vdev;
153dc7bbea9SMauro Carvalho Chehab struct v4l2_async_notifier notifier;
154dc7bbea9SMauro Carvalho Chehab struct v4l2_subdev *sensor;
155dc7bbea9SMauro Carvalho Chehab
156dc7bbea9SMauro Carvalho Chehab /* Videobuf2 stuff */
157dc7bbea9SMauro Carvalho Chehab struct vb2_queue vb_queue;
158dc7bbea9SMauro Carvalho Chehab struct list_head buffers; /* Available frames */
159dc7bbea9SMauro Carvalho Chehab
160dc7bbea9SMauro Carvalho Chehab unsigned int nbufs; /* How many are alloc'd */
161dc7bbea9SMauro Carvalho Chehab int next_buf; /* Next to consume (dev_lock) */
162dc7bbea9SMauro Carvalho Chehab
163dc7bbea9SMauro Carvalho Chehab char bus_info[32]; /* querycap bus_info */
164dc7bbea9SMauro Carvalho Chehab
165dc7bbea9SMauro Carvalho Chehab /* DMA buffers - vmalloc mode */
166dc7bbea9SMauro Carvalho Chehab #ifdef MCAM_MODE_VMALLOC
167dc7bbea9SMauro Carvalho Chehab unsigned int dma_buf_size; /* allocated size */
168dc7bbea9SMauro Carvalho Chehab void *dma_bufs[MAX_DMA_BUFS]; /* Internal buffer addresses */
169dc7bbea9SMauro Carvalho Chehab dma_addr_t dma_handles[MAX_DMA_BUFS]; /* Buffer bus addresses */
170dc7bbea9SMauro Carvalho Chehab struct tasklet_struct s_tasklet;
171dc7bbea9SMauro Carvalho Chehab #endif
172dc7bbea9SMauro Carvalho Chehab unsigned int sequence; /* Frame sequence number */
173dc7bbea9SMauro Carvalho Chehab unsigned int buf_seq[MAX_DMA_BUFS]; /* Sequence for individual bufs */
174dc7bbea9SMauro Carvalho Chehab
175dc7bbea9SMauro Carvalho Chehab /* DMA buffers - DMA modes */
176dc7bbea9SMauro Carvalho Chehab struct mcam_vb_buffer *vb_bufs[MAX_DMA_BUFS];
177dc7bbea9SMauro Carvalho Chehab
178dc7bbea9SMauro Carvalho Chehab /* Mode-specific ops, set at open time */
179dc7bbea9SMauro Carvalho Chehab void (*dma_setup)(struct mcam_camera *cam);
180dc7bbea9SMauro Carvalho Chehab void (*frame_complete)(struct mcam_camera *cam, int frame);
181dc7bbea9SMauro Carvalho Chehab
182dc7bbea9SMauro Carvalho Chehab /* Current operating parameters */
183dc7bbea9SMauro Carvalho Chehab struct v4l2_pix_format pix_format;
184dc7bbea9SMauro Carvalho Chehab u32 mbus_code;
185dc7bbea9SMauro Carvalho Chehab
186dc7bbea9SMauro Carvalho Chehab /* Locks */
187dc7bbea9SMauro Carvalho Chehab struct mutex s_mutex; /* Access to this structure */
188dc7bbea9SMauro Carvalho Chehab };
189dc7bbea9SMauro Carvalho Chehab
190dc7bbea9SMauro Carvalho Chehab
191dc7bbea9SMauro Carvalho Chehab /*
192dc7bbea9SMauro Carvalho Chehab * Register I/O functions. These are here because the platform code
193dc7bbea9SMauro Carvalho Chehab * may legitimately need to mess with the register space.
194dc7bbea9SMauro Carvalho Chehab */
195dc7bbea9SMauro Carvalho Chehab /*
196dc7bbea9SMauro Carvalho Chehab * Device register I/O
197dc7bbea9SMauro Carvalho Chehab */
mcam_reg_write(struct mcam_camera * cam,unsigned int reg,unsigned int val)198dc7bbea9SMauro Carvalho Chehab static inline void mcam_reg_write(struct mcam_camera *cam, unsigned int reg,
199dc7bbea9SMauro Carvalho Chehab unsigned int val)
200dc7bbea9SMauro Carvalho Chehab {
201dc7bbea9SMauro Carvalho Chehab iowrite32(val, cam->regs + reg);
202dc7bbea9SMauro Carvalho Chehab }
203dc7bbea9SMauro Carvalho Chehab
mcam_reg_read(struct mcam_camera * cam,unsigned int reg)204dc7bbea9SMauro Carvalho Chehab static inline unsigned int mcam_reg_read(struct mcam_camera *cam,
205dc7bbea9SMauro Carvalho Chehab unsigned int reg)
206dc7bbea9SMauro Carvalho Chehab {
207dc7bbea9SMauro Carvalho Chehab return ioread32(cam->regs + reg);
208dc7bbea9SMauro Carvalho Chehab }
209dc7bbea9SMauro Carvalho Chehab
210dc7bbea9SMauro Carvalho Chehab
mcam_reg_write_mask(struct mcam_camera * cam,unsigned int reg,unsigned int val,unsigned int mask)211dc7bbea9SMauro Carvalho Chehab static inline void mcam_reg_write_mask(struct mcam_camera *cam, unsigned int reg,
212dc7bbea9SMauro Carvalho Chehab unsigned int val, unsigned int mask)
213dc7bbea9SMauro Carvalho Chehab {
214dc7bbea9SMauro Carvalho Chehab unsigned int v = mcam_reg_read(cam, reg);
215dc7bbea9SMauro Carvalho Chehab
216dc7bbea9SMauro Carvalho Chehab v = (v & ~mask) | (val & mask);
217dc7bbea9SMauro Carvalho Chehab mcam_reg_write(cam, reg, v);
218dc7bbea9SMauro Carvalho Chehab }
219dc7bbea9SMauro Carvalho Chehab
mcam_reg_clear_bit(struct mcam_camera * cam,unsigned int reg,unsigned int val)220dc7bbea9SMauro Carvalho Chehab static inline void mcam_reg_clear_bit(struct mcam_camera *cam,
221dc7bbea9SMauro Carvalho Chehab unsigned int reg, unsigned int val)
222dc7bbea9SMauro Carvalho Chehab {
223dc7bbea9SMauro Carvalho Chehab mcam_reg_write_mask(cam, reg, 0, val);
224dc7bbea9SMauro Carvalho Chehab }
225dc7bbea9SMauro Carvalho Chehab
mcam_reg_set_bit(struct mcam_camera * cam,unsigned int reg,unsigned int val)226dc7bbea9SMauro Carvalho Chehab static inline void mcam_reg_set_bit(struct mcam_camera *cam,
227dc7bbea9SMauro Carvalho Chehab unsigned int reg, unsigned int val)
228dc7bbea9SMauro Carvalho Chehab {
229dc7bbea9SMauro Carvalho Chehab mcam_reg_write_mask(cam, reg, val, val);
230dc7bbea9SMauro Carvalho Chehab }
231dc7bbea9SMauro Carvalho Chehab
232dc7bbea9SMauro Carvalho Chehab /*
233dc7bbea9SMauro Carvalho Chehab * Functions for use by platform code.
234dc7bbea9SMauro Carvalho Chehab */
235dc7bbea9SMauro Carvalho Chehab int mccic_register(struct mcam_camera *cam);
236dc7bbea9SMauro Carvalho Chehab int mccic_irq(struct mcam_camera *cam, unsigned int irqs);
237dc7bbea9SMauro Carvalho Chehab void mccic_shutdown(struct mcam_camera *cam);
238dc7bbea9SMauro Carvalho Chehab void mccic_suspend(struct mcam_camera *cam);
239dc7bbea9SMauro Carvalho Chehab int mccic_resume(struct mcam_camera *cam);
240dc7bbea9SMauro Carvalho Chehab
241dc7bbea9SMauro Carvalho Chehab /*
242dc7bbea9SMauro Carvalho Chehab * Register definitions for the m88alp01 camera interface. Offsets in bytes
243dc7bbea9SMauro Carvalho Chehab * as given in the spec.
244dc7bbea9SMauro Carvalho Chehab */
245dc7bbea9SMauro Carvalho Chehab #define REG_Y0BAR 0x00
246dc7bbea9SMauro Carvalho Chehab #define REG_Y1BAR 0x04
247dc7bbea9SMauro Carvalho Chehab #define REG_Y2BAR 0x08
248dc7bbea9SMauro Carvalho Chehab #define REG_U0BAR 0x0c
249dc7bbea9SMauro Carvalho Chehab #define REG_U1BAR 0x10
250dc7bbea9SMauro Carvalho Chehab #define REG_U2BAR 0x14
251dc7bbea9SMauro Carvalho Chehab #define REG_V0BAR 0x18
252dc7bbea9SMauro Carvalho Chehab #define REG_V1BAR 0x1C
253dc7bbea9SMauro Carvalho Chehab #define REG_V2BAR 0x20
254dc7bbea9SMauro Carvalho Chehab
255dc7bbea9SMauro Carvalho Chehab /*
256dc7bbea9SMauro Carvalho Chehab * register definitions for MIPI support
257dc7bbea9SMauro Carvalho Chehab */
258dc7bbea9SMauro Carvalho Chehab #define REG_CSI2_CTRL0 0x100
259dc7bbea9SMauro Carvalho Chehab #define CSI2_C0_MIPI_EN (0x1 << 0)
260dc7bbea9SMauro Carvalho Chehab #define CSI2_C0_ACT_LANE(n) ((n-1) << 1)
261dc7bbea9SMauro Carvalho Chehab #define REG_CSI2_DPHY3 0x12c
262dc7bbea9SMauro Carvalho Chehab #define REG_CSI2_DPHY5 0x134
263dc7bbea9SMauro Carvalho Chehab #define REG_CSI2_DPHY6 0x138
264dc7bbea9SMauro Carvalho Chehab
265dc7bbea9SMauro Carvalho Chehab /* ... */
266dc7bbea9SMauro Carvalho Chehab
267dc7bbea9SMauro Carvalho Chehab #define REG_IMGPITCH 0x24 /* Image pitch register */
268dc7bbea9SMauro Carvalho Chehab #define IMGP_YP_SHFT 2 /* Y pitch params */
269dc7bbea9SMauro Carvalho Chehab #define IMGP_YP_MASK 0x00003ffc /* Y pitch field */
270dc7bbea9SMauro Carvalho Chehab #define IMGP_UVP_SHFT 18 /* UV pitch (planar) */
271dc7bbea9SMauro Carvalho Chehab #define IMGP_UVP_MASK 0x3ffc0000
272dc7bbea9SMauro Carvalho Chehab #define REG_IRQSTATRAW 0x28 /* RAW IRQ Status */
273dc7bbea9SMauro Carvalho Chehab #define IRQ_EOF0 0x00000001 /* End of frame 0 */
274dc7bbea9SMauro Carvalho Chehab #define IRQ_EOF1 0x00000002 /* End of frame 1 */
275dc7bbea9SMauro Carvalho Chehab #define IRQ_EOF2 0x00000004 /* End of frame 2 */
276dc7bbea9SMauro Carvalho Chehab #define IRQ_SOF0 0x00000008 /* Start of frame 0 */
277dc7bbea9SMauro Carvalho Chehab #define IRQ_SOF1 0x00000010 /* Start of frame 1 */
278dc7bbea9SMauro Carvalho Chehab #define IRQ_SOF2 0x00000020 /* Start of frame 2 */
279dc7bbea9SMauro Carvalho Chehab #define IRQ_OVERFLOW 0x00000040 /* FIFO overflow */
280dc7bbea9SMauro Carvalho Chehab #define IRQ_TWSIW 0x00010000 /* TWSI (smbus) write */
281dc7bbea9SMauro Carvalho Chehab #define IRQ_TWSIR 0x00020000 /* TWSI read */
282dc7bbea9SMauro Carvalho Chehab #define IRQ_TWSIE 0x00040000 /* TWSI error */
283dc7bbea9SMauro Carvalho Chehab #define TWSIIRQS (IRQ_TWSIW|IRQ_TWSIR|IRQ_TWSIE)
284dc7bbea9SMauro Carvalho Chehab #define FRAMEIRQS (IRQ_EOF0|IRQ_EOF1|IRQ_EOF2|IRQ_SOF0|IRQ_SOF1|IRQ_SOF2)
285dc7bbea9SMauro Carvalho Chehab #define ALLIRQS (TWSIIRQS|FRAMEIRQS|IRQ_OVERFLOW)
286dc7bbea9SMauro Carvalho Chehab #define REG_IRQMASK 0x2c /* IRQ mask - same bits as IRQSTAT */
287dc7bbea9SMauro Carvalho Chehab #define REG_IRQSTAT 0x30 /* IRQ status / clear */
288dc7bbea9SMauro Carvalho Chehab
289dc7bbea9SMauro Carvalho Chehab #define REG_IMGSIZE 0x34 /* Image size */
290dc7bbea9SMauro Carvalho Chehab #define IMGSZ_V_MASK 0x1fff0000
291dc7bbea9SMauro Carvalho Chehab #define IMGSZ_V_SHIFT 16
292dc7bbea9SMauro Carvalho Chehab #define IMGSZ_H_MASK 0x00003fff
293dc7bbea9SMauro Carvalho Chehab #define REG_IMGOFFSET 0x38 /* IMage offset */
294dc7bbea9SMauro Carvalho Chehab
295dc7bbea9SMauro Carvalho Chehab #define REG_CTRL0 0x3c /* Control 0 */
296dc7bbea9SMauro Carvalho Chehab #define C0_ENABLE 0x00000001 /* Makes the whole thing go */
297dc7bbea9SMauro Carvalho Chehab
298dc7bbea9SMauro Carvalho Chehab /* Mask for all the format bits */
299dc7bbea9SMauro Carvalho Chehab #define C0_DF_MASK 0x00fffffc /* Bits 2-23 */
300dc7bbea9SMauro Carvalho Chehab
301dc7bbea9SMauro Carvalho Chehab /* RGB ordering */
302dc7bbea9SMauro Carvalho Chehab #define C0_RGB4_RGBX 0x00000000
303dc7bbea9SMauro Carvalho Chehab #define C0_RGB4_XRGB 0x00000004
304dc7bbea9SMauro Carvalho Chehab #define C0_RGB4_BGRX 0x00000008
305dc7bbea9SMauro Carvalho Chehab #define C0_RGB4_XBGR 0x0000000c
306dc7bbea9SMauro Carvalho Chehab #define C0_RGB5_RGGB 0x00000000
307dc7bbea9SMauro Carvalho Chehab #define C0_RGB5_GRBG 0x00000004
308dc7bbea9SMauro Carvalho Chehab #define C0_RGB5_GBRG 0x00000008
309dc7bbea9SMauro Carvalho Chehab #define C0_RGB5_BGGR 0x0000000c
310dc7bbea9SMauro Carvalho Chehab
311dc7bbea9SMauro Carvalho Chehab /* Spec has two fields for DIN and DOUT, but they must match, so
312dc7bbea9SMauro Carvalho Chehab combine them here. */
313dc7bbea9SMauro Carvalho Chehab #define C0_DF_YUV 0x00000000 /* Data is YUV */
314dc7bbea9SMauro Carvalho Chehab #define C0_DF_RGB 0x000000a0 /* ... RGB */
315dc7bbea9SMauro Carvalho Chehab #define C0_DF_BAYER 0x00000140 /* ... Bayer */
316dc7bbea9SMauro Carvalho Chehab /* 8-8-8 must be missing from the below - ask */
317dc7bbea9SMauro Carvalho Chehab #define C0_RGBF_565 0x00000000
318dc7bbea9SMauro Carvalho Chehab #define C0_RGBF_444 0x00000800
319dc7bbea9SMauro Carvalho Chehab #define C0_RGB_BGR 0x00001000 /* Blue comes first */
320dc7bbea9SMauro Carvalho Chehab #define C0_YUV_PLANAR 0x00000000 /* YUV 422 planar format */
321dc7bbea9SMauro Carvalho Chehab #define C0_YUV_PACKED 0x00008000 /* YUV 422 packed */
322dc7bbea9SMauro Carvalho Chehab #define C0_YUV_420PL 0x0000a000 /* YUV 420 planar */
323dc7bbea9SMauro Carvalho Chehab /* Think that 420 packed must be 111 - ask */
324dc7bbea9SMauro Carvalho Chehab #define C0_YUVE_YUYV 0x00000000 /* Y1CbY0Cr */
325dc7bbea9SMauro Carvalho Chehab #define C0_YUVE_YVYU 0x00010000 /* Y1CrY0Cb */
326dc7bbea9SMauro Carvalho Chehab #define C0_YUVE_VYUY 0x00020000 /* CrY1CbY0 */
327dc7bbea9SMauro Carvalho Chehab #define C0_YUVE_UYVY 0x00030000 /* CbY1CrY0 */
328dc7bbea9SMauro Carvalho Chehab #define C0_YUVE_NOSWAP 0x00000000 /* no bytes swapping */
329dc7bbea9SMauro Carvalho Chehab #define C0_YUVE_SWAP13 0x00010000 /* swap byte 1 and 3 */
330dc7bbea9SMauro Carvalho Chehab #define C0_YUVE_SWAP24 0x00020000 /* swap byte 2 and 4 */
331dc7bbea9SMauro Carvalho Chehab #define C0_YUVE_SWAP1324 0x00030000 /* swap bytes 1&3 and 2&4 */
332dc7bbea9SMauro Carvalho Chehab /* Bayer bits 18,19 if needed */
333dc7bbea9SMauro Carvalho Chehab #define C0_EOF_VSYNC 0x00400000 /* Generate EOF by VSYNC */
334dc7bbea9SMauro Carvalho Chehab #define C0_VEDGE_CTRL 0x00800000 /* Detect falling edge of VSYNC */
335dc7bbea9SMauro Carvalho Chehab #define C0_HPOL_LOW 0x01000000 /* HSYNC polarity active low */
336dc7bbea9SMauro Carvalho Chehab #define C0_VPOL_LOW 0x02000000 /* VSYNC polarity active low */
337dc7bbea9SMauro Carvalho Chehab #define C0_VCLK_LOW 0x04000000 /* VCLK on falling edge */
338dc7bbea9SMauro Carvalho Chehab #define C0_DOWNSCALE 0x08000000 /* Enable downscaler */
339dc7bbea9SMauro Carvalho Chehab /* SIFMODE */
340dc7bbea9SMauro Carvalho Chehab #define C0_SIF_HVSYNC 0x00000000 /* Use H/VSYNC */
341dc7bbea9SMauro Carvalho Chehab #define C0_SOF_NOSYNC 0x40000000 /* Use inband active signaling */
342dc7bbea9SMauro Carvalho Chehab #define C0_SIFM_MASK 0xc0000000 /* SIF mode bits */
343dc7bbea9SMauro Carvalho Chehab
344dc7bbea9SMauro Carvalho Chehab /* Bits below C1_444ALPHA are not present in Cafe */
345dc7bbea9SMauro Carvalho Chehab #define REG_CTRL1 0x40 /* Control 1 */
346dc7bbea9SMauro Carvalho Chehab #define C1_CLKGATE 0x00000001 /* Sensor clock gate */
347dc7bbea9SMauro Carvalho Chehab #define C1_DESC_ENA 0x00000100 /* DMA descriptor enable */
348dc7bbea9SMauro Carvalho Chehab #define C1_DESC_3WORD 0x00000200 /* Three-word descriptors used */
349dc7bbea9SMauro Carvalho Chehab #define C1_444ALPHA 0x00f00000 /* Alpha field in RGB444 */
350dc7bbea9SMauro Carvalho Chehab #define C1_ALPHA_SHFT 20
351dc7bbea9SMauro Carvalho Chehab #define C1_DMAB32 0x00000000 /* 32-byte DMA burst */
352dc7bbea9SMauro Carvalho Chehab #define C1_DMAB16 0x02000000 /* 16-byte DMA burst */
353dc7bbea9SMauro Carvalho Chehab #define C1_DMAB64 0x04000000 /* 64-byte DMA burst */
354dc7bbea9SMauro Carvalho Chehab #define C1_DMAB_MASK 0x06000000
355dc7bbea9SMauro Carvalho Chehab #define C1_TWOBUFS 0x08000000 /* Use only two DMA buffers */
356dc7bbea9SMauro Carvalho Chehab #define C1_PWRDWN 0x10000000 /* Power down */
357dc7bbea9SMauro Carvalho Chehab
358dc7bbea9SMauro Carvalho Chehab #define REG_CLKCTRL 0x88 /* Clock control */
359dc7bbea9SMauro Carvalho Chehab #define CLK_DIV_MASK 0x0000ffff /* Upper bits RW "reserved" */
360dc7bbea9SMauro Carvalho Chehab
361dc7bbea9SMauro Carvalho Chehab /* This appears to be a Cafe-only register */
362dc7bbea9SMauro Carvalho Chehab #define REG_UBAR 0xc4 /* Upper base address register */
363dc7bbea9SMauro Carvalho Chehab
364dc7bbea9SMauro Carvalho Chehab /* Armada 610 DMA descriptor registers */
365dc7bbea9SMauro Carvalho Chehab #define REG_DMA_DESC_Y 0x200
366dc7bbea9SMauro Carvalho Chehab #define REG_DMA_DESC_U 0x204
367dc7bbea9SMauro Carvalho Chehab #define REG_DMA_DESC_V 0x208
368dc7bbea9SMauro Carvalho Chehab #define REG_DESC_LEN_Y 0x20c /* Lengths are in bytes */
369dc7bbea9SMauro Carvalho Chehab #define REG_DESC_LEN_U 0x210
370dc7bbea9SMauro Carvalho Chehab #define REG_DESC_LEN_V 0x214
371dc7bbea9SMauro Carvalho Chehab
372dc7bbea9SMauro Carvalho Chehab /*
373dc7bbea9SMauro Carvalho Chehab * Useful stuff that probably belongs somewhere global.
374dc7bbea9SMauro Carvalho Chehab */
375dc7bbea9SMauro Carvalho Chehab #define VGA_WIDTH 640
376dc7bbea9SMauro Carvalho Chehab #define VGA_HEIGHT 480
377dc7bbea9SMauro Carvalho Chehab
378dc7bbea9SMauro Carvalho Chehab #endif /* _MCAM_CORE_H */
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