1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Driver for Cadence MIPI-CSI2 RX Controller v1.3 4 * 5 * Copyright (C) 2017 Cadence Design Systems Inc. 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/delay.h> 10 #include <linux/io.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/of_graph.h> 14 #include <linux/phy/phy.h> 15 #include <linux/platform_device.h> 16 #include <linux/reset.h> 17 #include <linux/slab.h> 18 19 #include <media/v4l2-ctrls.h> 20 #include <media/v4l2-device.h> 21 #include <media/v4l2-fwnode.h> 22 #include <media/v4l2-subdev.h> 23 24 #define CSI2RX_DEVICE_CFG_REG 0x000 25 26 #define CSI2RX_SOFT_RESET_REG 0x004 27 #define CSI2RX_SOFT_RESET_PROTOCOL BIT(1) 28 #define CSI2RX_SOFT_RESET_FRONT BIT(0) 29 30 #define CSI2RX_STATIC_CFG_REG 0x008 31 #define CSI2RX_STATIC_CFG_DLANE_MAP(llane, plane) ((plane) << (16 + (llane) * 4)) 32 #define CSI2RX_STATIC_CFG_LANES_MASK GENMASK(11, 8) 33 34 #define CSI2RX_DPHY_LANE_CTRL_REG 0x40 35 #define CSI2RX_DPHY_CL_RST BIT(16) 36 #define CSI2RX_DPHY_DL_RST(i) BIT((i) + 12) 37 #define CSI2RX_DPHY_CL_EN BIT(4) 38 #define CSI2RX_DPHY_DL_EN(i) BIT(i) 39 40 #define CSI2RX_STREAM_BASE(n) (((n) + 1) * 0x100) 41 42 #define CSI2RX_STREAM_CTRL_REG(n) (CSI2RX_STREAM_BASE(n) + 0x000) 43 #define CSI2RX_STREAM_CTRL_START BIT(0) 44 45 #define CSI2RX_STREAM_DATA_CFG_REG(n) (CSI2RX_STREAM_BASE(n) + 0x008) 46 #define CSI2RX_STREAM_DATA_CFG_EN_VC_SELECT BIT(31) 47 #define CSI2RX_STREAM_DATA_CFG_VC_SELECT(n) BIT((n) + 16) 48 49 #define CSI2RX_STREAM_CFG_REG(n) (CSI2RX_STREAM_BASE(n) + 0x00c) 50 #define CSI2RX_STREAM_CFG_FIFO_MODE_LARGE_BUF (1 << 8) 51 52 #define CSI2RX_LANES_MAX 4 53 #define CSI2RX_STREAMS_MAX 4 54 55 enum csi2rx_pads { 56 CSI2RX_PAD_SINK, 57 CSI2RX_PAD_SOURCE_STREAM0, 58 CSI2RX_PAD_SOURCE_STREAM1, 59 CSI2RX_PAD_SOURCE_STREAM2, 60 CSI2RX_PAD_SOURCE_STREAM3, 61 CSI2RX_PAD_MAX, 62 }; 63 64 struct csi2rx_priv { 65 struct device *dev; 66 unsigned int count; 67 68 /* 69 * Used to prevent race conditions between multiple, 70 * concurrent calls to start and stop. 71 */ 72 struct mutex lock; 73 74 void __iomem *base; 75 struct clk *sys_clk; 76 struct clk *p_clk; 77 struct clk *pixel_clk[CSI2RX_STREAMS_MAX]; 78 struct reset_control *sys_rst; 79 struct reset_control *p_rst; 80 struct reset_control *pixel_rst[CSI2RX_STREAMS_MAX]; 81 struct phy *dphy; 82 83 u8 lanes[CSI2RX_LANES_MAX]; 84 u8 num_lanes; 85 u8 max_lanes; 86 u8 max_streams; 87 bool has_internal_dphy; 88 89 struct v4l2_subdev subdev; 90 struct v4l2_async_notifier notifier; 91 struct media_pad pads[CSI2RX_PAD_MAX]; 92 93 /* Remote source */ 94 struct v4l2_subdev *source_subdev; 95 int source_pad; 96 }; 97 98 static inline 99 struct csi2rx_priv *v4l2_subdev_to_csi2rx(struct v4l2_subdev *subdev) 100 { 101 return container_of(subdev, struct csi2rx_priv, subdev); 102 } 103 104 static void csi2rx_reset(struct csi2rx_priv *csi2rx) 105 { 106 writel(CSI2RX_SOFT_RESET_PROTOCOL | CSI2RX_SOFT_RESET_FRONT, 107 csi2rx->base + CSI2RX_SOFT_RESET_REG); 108 109 udelay(10); 110 111 writel(0, csi2rx->base + CSI2RX_SOFT_RESET_REG); 112 } 113 114 static int csi2rx_configure_ext_dphy(struct csi2rx_priv *csi2rx) 115 { 116 union phy_configure_opts opts = { }; 117 int ret; 118 119 ret = phy_power_on(csi2rx->dphy); 120 if (ret) 121 return ret; 122 123 ret = phy_configure(csi2rx->dphy, &opts); 124 if (ret) { 125 phy_power_off(csi2rx->dphy); 126 return ret; 127 } 128 129 return 0; 130 } 131 132 static int csi2rx_start(struct csi2rx_priv *csi2rx) 133 { 134 unsigned int i; 135 unsigned long lanes_used = 0; 136 u32 reg; 137 int ret; 138 139 ret = clk_prepare_enable(csi2rx->p_clk); 140 if (ret) 141 return ret; 142 143 reset_control_deassert(csi2rx->p_rst); 144 csi2rx_reset(csi2rx); 145 146 reg = csi2rx->num_lanes << 8; 147 for (i = 0; i < csi2rx->num_lanes; i++) { 148 reg |= CSI2RX_STATIC_CFG_DLANE_MAP(i, csi2rx->lanes[i]); 149 set_bit(csi2rx->lanes[i], &lanes_used); 150 } 151 152 /* 153 * Even the unused lanes need to be mapped. In order to avoid 154 * to map twice to the same physical lane, keep the lanes used 155 * in the previous loop, and only map unused physical lanes to 156 * the rest of our logical lanes. 157 */ 158 for (i = csi2rx->num_lanes; i < csi2rx->max_lanes; i++) { 159 unsigned int idx = find_first_zero_bit(&lanes_used, 160 csi2rx->max_lanes); 161 set_bit(idx, &lanes_used); 162 reg |= CSI2RX_STATIC_CFG_DLANE_MAP(i, i + 1); 163 } 164 165 writel(reg, csi2rx->base + CSI2RX_STATIC_CFG_REG); 166 167 ret = v4l2_subdev_call(csi2rx->source_subdev, video, s_stream, true); 168 if (ret) 169 goto err_disable_pclk; 170 171 /* Enable DPHY clk and data lanes. */ 172 if (csi2rx->dphy) { 173 reg = CSI2RX_DPHY_CL_EN | CSI2RX_DPHY_CL_RST; 174 for (i = 0; i < csi2rx->num_lanes; i++) { 175 reg |= CSI2RX_DPHY_DL_EN(csi2rx->lanes[i] - 1); 176 reg |= CSI2RX_DPHY_DL_RST(csi2rx->lanes[i] - 1); 177 } 178 179 writel(reg, csi2rx->base + CSI2RX_DPHY_LANE_CTRL_REG); 180 } 181 182 /* 183 * Create a static mapping between the CSI virtual channels 184 * and the output stream. 185 * 186 * This should be enhanced, but v4l2 lacks the support for 187 * changing that mapping dynamically. 188 * 189 * We also cannot enable and disable independent streams here, 190 * hence the reference counting. 191 */ 192 for (i = 0; i < csi2rx->max_streams; i++) { 193 ret = clk_prepare_enable(csi2rx->pixel_clk[i]); 194 if (ret) 195 goto err_disable_pixclk; 196 197 reset_control_deassert(csi2rx->pixel_rst[i]); 198 199 writel(CSI2RX_STREAM_CFG_FIFO_MODE_LARGE_BUF, 200 csi2rx->base + CSI2RX_STREAM_CFG_REG(i)); 201 202 writel(CSI2RX_STREAM_DATA_CFG_EN_VC_SELECT | 203 CSI2RX_STREAM_DATA_CFG_VC_SELECT(i), 204 csi2rx->base + CSI2RX_STREAM_DATA_CFG_REG(i)); 205 206 writel(CSI2RX_STREAM_CTRL_START, 207 csi2rx->base + CSI2RX_STREAM_CTRL_REG(i)); 208 } 209 210 ret = clk_prepare_enable(csi2rx->sys_clk); 211 if (ret) 212 goto err_disable_pixclk; 213 214 reset_control_deassert(csi2rx->sys_rst); 215 216 if (csi2rx->dphy) { 217 ret = csi2rx_configure_ext_dphy(csi2rx); 218 if (ret) { 219 dev_err(csi2rx->dev, 220 "Failed to configure external DPHY: %d\n", ret); 221 goto err_disable_sysclk; 222 } 223 } 224 225 clk_disable_unprepare(csi2rx->p_clk); 226 227 return 0; 228 229 err_disable_sysclk: 230 clk_disable_unprepare(csi2rx->sys_clk); 231 err_disable_pixclk: 232 for (; i > 0; i--) { 233 reset_control_assert(csi2rx->pixel_rst[i - 1]); 234 clk_disable_unprepare(csi2rx->pixel_clk[i - 1]); 235 } 236 237 err_disable_pclk: 238 clk_disable_unprepare(csi2rx->p_clk); 239 240 return ret; 241 } 242 243 static void csi2rx_stop(struct csi2rx_priv *csi2rx) 244 { 245 unsigned int i; 246 247 clk_prepare_enable(csi2rx->p_clk); 248 reset_control_assert(csi2rx->sys_rst); 249 clk_disable_unprepare(csi2rx->sys_clk); 250 251 for (i = 0; i < csi2rx->max_streams; i++) { 252 writel(0, csi2rx->base + CSI2RX_STREAM_CTRL_REG(i)); 253 254 reset_control_assert(csi2rx->pixel_rst[i]); 255 clk_disable_unprepare(csi2rx->pixel_clk[i]); 256 } 257 258 reset_control_assert(csi2rx->p_rst); 259 clk_disable_unprepare(csi2rx->p_clk); 260 261 if (v4l2_subdev_call(csi2rx->source_subdev, video, s_stream, false)) 262 dev_warn(csi2rx->dev, "Couldn't disable our subdev\n"); 263 264 if (csi2rx->dphy) { 265 writel(0, csi2rx->base + CSI2RX_DPHY_LANE_CTRL_REG); 266 267 if (phy_power_off(csi2rx->dphy)) 268 dev_warn(csi2rx->dev, "Couldn't power off DPHY\n"); 269 } 270 } 271 272 static int csi2rx_s_stream(struct v4l2_subdev *subdev, int enable) 273 { 274 struct csi2rx_priv *csi2rx = v4l2_subdev_to_csi2rx(subdev); 275 int ret = 0; 276 277 mutex_lock(&csi2rx->lock); 278 279 if (enable) { 280 /* 281 * If we're not the first users, there's no need to 282 * enable the whole controller. 283 */ 284 if (!csi2rx->count) { 285 ret = csi2rx_start(csi2rx); 286 if (ret) 287 goto out; 288 } 289 290 csi2rx->count++; 291 } else { 292 csi2rx->count--; 293 294 /* 295 * Let the last user turn off the lights. 296 */ 297 if (!csi2rx->count) 298 csi2rx_stop(csi2rx); 299 } 300 301 out: 302 mutex_unlock(&csi2rx->lock); 303 return ret; 304 } 305 306 static const struct v4l2_subdev_video_ops csi2rx_video_ops = { 307 .s_stream = csi2rx_s_stream, 308 }; 309 310 static const struct v4l2_subdev_ops csi2rx_subdev_ops = { 311 .video = &csi2rx_video_ops, 312 }; 313 314 static int csi2rx_async_bound(struct v4l2_async_notifier *notifier, 315 struct v4l2_subdev *s_subdev, 316 struct v4l2_async_connection *asd) 317 { 318 struct v4l2_subdev *subdev = notifier->sd; 319 struct csi2rx_priv *csi2rx = v4l2_subdev_to_csi2rx(subdev); 320 321 csi2rx->source_pad = media_entity_get_fwnode_pad(&s_subdev->entity, 322 asd->match.fwnode, 323 MEDIA_PAD_FL_SOURCE); 324 if (csi2rx->source_pad < 0) { 325 dev_err(csi2rx->dev, "Couldn't find output pad for subdev %s\n", 326 s_subdev->name); 327 return csi2rx->source_pad; 328 } 329 330 csi2rx->source_subdev = s_subdev; 331 332 dev_dbg(csi2rx->dev, "Bound %s pad: %d\n", s_subdev->name, 333 csi2rx->source_pad); 334 335 return media_create_pad_link(&csi2rx->source_subdev->entity, 336 csi2rx->source_pad, 337 &csi2rx->subdev.entity, 0, 338 MEDIA_LNK_FL_ENABLED | 339 MEDIA_LNK_FL_IMMUTABLE); 340 } 341 342 static const struct v4l2_async_notifier_operations csi2rx_notifier_ops = { 343 .bound = csi2rx_async_bound, 344 }; 345 346 static int csi2rx_get_resources(struct csi2rx_priv *csi2rx, 347 struct platform_device *pdev) 348 { 349 unsigned char i; 350 u32 dev_cfg; 351 int ret; 352 353 csi2rx->base = devm_platform_ioremap_resource(pdev, 0); 354 if (IS_ERR(csi2rx->base)) 355 return PTR_ERR(csi2rx->base); 356 357 csi2rx->sys_clk = devm_clk_get(&pdev->dev, "sys_clk"); 358 if (IS_ERR(csi2rx->sys_clk)) { 359 dev_err(&pdev->dev, "Couldn't get sys clock\n"); 360 return PTR_ERR(csi2rx->sys_clk); 361 } 362 363 csi2rx->p_clk = devm_clk_get(&pdev->dev, "p_clk"); 364 if (IS_ERR(csi2rx->p_clk)) { 365 dev_err(&pdev->dev, "Couldn't get P clock\n"); 366 return PTR_ERR(csi2rx->p_clk); 367 } 368 369 csi2rx->sys_rst = devm_reset_control_get_optional_exclusive(&pdev->dev, 370 "sys"); 371 if (IS_ERR(csi2rx->sys_rst)) 372 return PTR_ERR(csi2rx->sys_rst); 373 374 csi2rx->p_rst = devm_reset_control_get_optional_exclusive(&pdev->dev, 375 "reg_bank"); 376 if (IS_ERR(csi2rx->p_rst)) 377 return PTR_ERR(csi2rx->p_rst); 378 379 csi2rx->dphy = devm_phy_optional_get(&pdev->dev, "dphy"); 380 if (IS_ERR(csi2rx->dphy)) { 381 dev_err(&pdev->dev, "Couldn't get external D-PHY\n"); 382 return PTR_ERR(csi2rx->dphy); 383 } 384 385 ret = clk_prepare_enable(csi2rx->p_clk); 386 if (ret) { 387 dev_err(&pdev->dev, "Couldn't prepare and enable P clock\n"); 388 return ret; 389 } 390 391 dev_cfg = readl(csi2rx->base + CSI2RX_DEVICE_CFG_REG); 392 clk_disable_unprepare(csi2rx->p_clk); 393 394 csi2rx->max_lanes = dev_cfg & 7; 395 if (csi2rx->max_lanes > CSI2RX_LANES_MAX) { 396 dev_err(&pdev->dev, "Invalid number of lanes: %u\n", 397 csi2rx->max_lanes); 398 return -EINVAL; 399 } 400 401 csi2rx->max_streams = (dev_cfg >> 4) & 7; 402 if (csi2rx->max_streams > CSI2RX_STREAMS_MAX) { 403 dev_err(&pdev->dev, "Invalid number of streams: %u\n", 404 csi2rx->max_streams); 405 return -EINVAL; 406 } 407 408 csi2rx->has_internal_dphy = dev_cfg & BIT(3) ? true : false; 409 410 /* 411 * FIXME: Once we'll have internal D-PHY support, the check 412 * will need to be removed. 413 */ 414 if (!csi2rx->dphy && csi2rx->has_internal_dphy) { 415 dev_err(&pdev->dev, "Internal D-PHY not supported yet\n"); 416 return -EINVAL; 417 } 418 419 for (i = 0; i < csi2rx->max_streams; i++) { 420 char name[16]; 421 422 snprintf(name, sizeof(name), "pixel_if%u_clk", i); 423 csi2rx->pixel_clk[i] = devm_clk_get(&pdev->dev, name); 424 if (IS_ERR(csi2rx->pixel_clk[i])) { 425 dev_err(&pdev->dev, "Couldn't get clock %s\n", name); 426 return PTR_ERR(csi2rx->pixel_clk[i]); 427 } 428 429 snprintf(name, sizeof(name), "pixel_if%u", i); 430 csi2rx->pixel_rst[i] = 431 devm_reset_control_get_optional_exclusive(&pdev->dev, 432 name); 433 if (IS_ERR(csi2rx->pixel_rst[i])) 434 return PTR_ERR(csi2rx->pixel_rst[i]); 435 } 436 437 return 0; 438 } 439 440 static int csi2rx_parse_dt(struct csi2rx_priv *csi2rx) 441 { 442 struct v4l2_fwnode_endpoint v4l2_ep = { .bus_type = 0 }; 443 struct v4l2_async_connection *asd; 444 struct fwnode_handle *fwh; 445 struct device_node *ep; 446 int ret; 447 448 ep = of_graph_get_endpoint_by_regs(csi2rx->dev->of_node, 0, 0); 449 if (!ep) 450 return -EINVAL; 451 452 fwh = of_fwnode_handle(ep); 453 ret = v4l2_fwnode_endpoint_parse(fwh, &v4l2_ep); 454 if (ret) { 455 dev_err(csi2rx->dev, "Could not parse v4l2 endpoint\n"); 456 of_node_put(ep); 457 return ret; 458 } 459 460 if (v4l2_ep.bus_type != V4L2_MBUS_CSI2_DPHY) { 461 dev_err(csi2rx->dev, "Unsupported media bus type: 0x%x\n", 462 v4l2_ep.bus_type); 463 of_node_put(ep); 464 return -EINVAL; 465 } 466 467 memcpy(csi2rx->lanes, v4l2_ep.bus.mipi_csi2.data_lanes, 468 sizeof(csi2rx->lanes)); 469 csi2rx->num_lanes = v4l2_ep.bus.mipi_csi2.num_data_lanes; 470 if (csi2rx->num_lanes > csi2rx->max_lanes) { 471 dev_err(csi2rx->dev, "Unsupported number of data-lanes: %d\n", 472 csi2rx->num_lanes); 473 of_node_put(ep); 474 return -EINVAL; 475 } 476 477 v4l2_async_subdev_nf_init(&csi2rx->notifier, &csi2rx->subdev); 478 479 asd = v4l2_async_nf_add_fwnode_remote(&csi2rx->notifier, fwh, 480 struct v4l2_async_connection); 481 of_node_put(ep); 482 if (IS_ERR(asd)) { 483 v4l2_async_nf_cleanup(&csi2rx->notifier); 484 return PTR_ERR(asd); 485 } 486 487 csi2rx->notifier.ops = &csi2rx_notifier_ops; 488 489 ret = v4l2_async_nf_register(&csi2rx->notifier); 490 if (ret) 491 v4l2_async_nf_cleanup(&csi2rx->notifier); 492 493 return ret; 494 } 495 496 static int csi2rx_probe(struct platform_device *pdev) 497 { 498 struct csi2rx_priv *csi2rx; 499 unsigned int i; 500 int ret; 501 502 csi2rx = kzalloc(sizeof(*csi2rx), GFP_KERNEL); 503 if (!csi2rx) 504 return -ENOMEM; 505 platform_set_drvdata(pdev, csi2rx); 506 csi2rx->dev = &pdev->dev; 507 mutex_init(&csi2rx->lock); 508 509 ret = csi2rx_get_resources(csi2rx, pdev); 510 if (ret) 511 goto err_free_priv; 512 513 ret = csi2rx_parse_dt(csi2rx); 514 if (ret) 515 goto err_free_priv; 516 517 csi2rx->subdev.owner = THIS_MODULE; 518 csi2rx->subdev.dev = &pdev->dev; 519 v4l2_subdev_init(&csi2rx->subdev, &csi2rx_subdev_ops); 520 v4l2_set_subdevdata(&csi2rx->subdev, &pdev->dev); 521 snprintf(csi2rx->subdev.name, V4L2_SUBDEV_NAME_SIZE, "%s.%s", 522 KBUILD_MODNAME, dev_name(&pdev->dev)); 523 524 /* Create our media pads */ 525 csi2rx->subdev.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE; 526 csi2rx->pads[CSI2RX_PAD_SINK].flags = MEDIA_PAD_FL_SINK; 527 for (i = CSI2RX_PAD_SOURCE_STREAM0; i < CSI2RX_PAD_MAX; i++) 528 csi2rx->pads[i].flags = MEDIA_PAD_FL_SOURCE; 529 530 ret = media_entity_pads_init(&csi2rx->subdev.entity, CSI2RX_PAD_MAX, 531 csi2rx->pads); 532 if (ret) 533 goto err_cleanup; 534 535 ret = v4l2_async_register_subdev(&csi2rx->subdev); 536 if (ret < 0) 537 goto err_cleanup; 538 539 dev_info(&pdev->dev, 540 "Probed CSI2RX with %u/%u lanes, %u streams, %s D-PHY\n", 541 csi2rx->num_lanes, csi2rx->max_lanes, csi2rx->max_streams, 542 csi2rx->dphy ? "external" : 543 csi2rx->has_internal_dphy ? "internal" : "no"); 544 545 return 0; 546 547 err_cleanup: 548 v4l2_async_nf_unregister(&csi2rx->notifier); 549 v4l2_async_nf_cleanup(&csi2rx->notifier); 550 err_free_priv: 551 kfree(csi2rx); 552 return ret; 553 } 554 555 static void csi2rx_remove(struct platform_device *pdev) 556 { 557 struct csi2rx_priv *csi2rx = platform_get_drvdata(pdev); 558 559 v4l2_async_nf_unregister(&csi2rx->notifier); 560 v4l2_async_nf_cleanup(&csi2rx->notifier); 561 v4l2_async_unregister_subdev(&csi2rx->subdev); 562 kfree(csi2rx); 563 } 564 565 static const struct of_device_id csi2rx_of_table[] = { 566 { .compatible = "starfive,jh7110-csi2rx" }, 567 { .compatible = "cdns,csi2rx" }, 568 { }, 569 }; 570 MODULE_DEVICE_TABLE(of, csi2rx_of_table); 571 572 static struct platform_driver csi2rx_driver = { 573 .probe = csi2rx_probe, 574 .remove_new = csi2rx_remove, 575 576 .driver = { 577 .name = "cdns-csi2rx", 578 .of_match_table = csi2rx_of_table, 579 }, 580 }; 581 module_platform_driver(csi2rx_driver); 582 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@bootlin.com>"); 583 MODULE_DESCRIPTION("Cadence CSI2-RX controller"); 584 MODULE_LICENSE("GPL"); 585