1c1d82b89SHans Verkuil /* 2c1d82b89SHans Verkuil * Register definitions for the Atmel Image Sensor Interface. 3c1d82b89SHans Verkuil * 4c1d82b89SHans Verkuil * Copyright (C) 2011 Atmel Corporation 5c1d82b89SHans Verkuil * Josh Wu, <josh.wu@atmel.com> 6c1d82b89SHans Verkuil * 7c1d82b89SHans Verkuil * Based on previous work by Lars Haring, <lars.haring@atmel.com> 8c1d82b89SHans Verkuil * and Sedji Gaouaou 9c1d82b89SHans Verkuil * 10c1d82b89SHans Verkuil * This program is free software; you can redistribute it and/or modify 11c1d82b89SHans Verkuil * it under the terms of the GNU General Public License version 2 as 12c1d82b89SHans Verkuil * published by the Free Software Foundation. 13c1d82b89SHans Verkuil */ 14c1d82b89SHans Verkuil #ifndef __ATMEL_ISI_H__ 15c1d82b89SHans Verkuil #define __ATMEL_ISI_H__ 16c1d82b89SHans Verkuil 17c1d82b89SHans Verkuil #include <linux/types.h> 18c1d82b89SHans Verkuil 19c1d82b89SHans Verkuil /* ISI_V2 register offsets */ 20c1d82b89SHans Verkuil #define ISI_CFG1 0x0000 21c1d82b89SHans Verkuil #define ISI_CFG2 0x0004 22c1d82b89SHans Verkuil #define ISI_PSIZE 0x0008 23c1d82b89SHans Verkuil #define ISI_PDECF 0x000c 24c1d82b89SHans Verkuil #define ISI_Y2R_SET0 0x0010 25c1d82b89SHans Verkuil #define ISI_Y2R_SET1 0x0014 26c1d82b89SHans Verkuil #define ISI_R2Y_SET0 0x0018 27c1d82b89SHans Verkuil #define ISI_R2Y_SET1 0x001C 28c1d82b89SHans Verkuil #define ISI_R2Y_SET2 0x0020 29c1d82b89SHans Verkuil #define ISI_CTRL 0x0024 30c1d82b89SHans Verkuil #define ISI_STATUS 0x0028 31c1d82b89SHans Verkuil #define ISI_INTEN 0x002C 32c1d82b89SHans Verkuil #define ISI_INTDIS 0x0030 33c1d82b89SHans Verkuil #define ISI_INTMASK 0x0034 34c1d82b89SHans Verkuil #define ISI_DMA_CHER 0x0038 35c1d82b89SHans Verkuil #define ISI_DMA_CHDR 0x003C 36c1d82b89SHans Verkuil #define ISI_DMA_CHSR 0x0040 37c1d82b89SHans Verkuil #define ISI_DMA_P_ADDR 0x0044 38c1d82b89SHans Verkuil #define ISI_DMA_P_CTRL 0x0048 39c1d82b89SHans Verkuil #define ISI_DMA_P_DSCR 0x004C 40c1d82b89SHans Verkuil #define ISI_DMA_C_ADDR 0x0050 41c1d82b89SHans Verkuil #define ISI_DMA_C_CTRL 0x0054 42c1d82b89SHans Verkuil #define ISI_DMA_C_DSCR 0x0058 43c1d82b89SHans Verkuil 44c1d82b89SHans Verkuil /* Bitfields in CFG1 */ 45c1d82b89SHans Verkuil #define ISI_CFG1_HSYNC_POL_ACTIVE_LOW (1 << 2) 46c1d82b89SHans Verkuil #define ISI_CFG1_VSYNC_POL_ACTIVE_LOW (1 << 3) 47c1d82b89SHans Verkuil #define ISI_CFG1_PIXCLK_POL_ACTIVE_FALLING (1 << 4) 48c1d82b89SHans Verkuil #define ISI_CFG1_EMB_SYNC (1 << 6) 49c1d82b89SHans Verkuil #define ISI_CFG1_CRC_SYNC (1 << 7) 50c1d82b89SHans Verkuil /* Constants for FRATE(ISI_V2) */ 51c1d82b89SHans Verkuil #define ISI_CFG1_FRATE_CAPTURE_ALL (0 << 8) 52c1d82b89SHans Verkuil #define ISI_CFG1_FRATE_DIV_2 (1 << 8) 53c1d82b89SHans Verkuil #define ISI_CFG1_FRATE_DIV_3 (2 << 8) 54c1d82b89SHans Verkuil #define ISI_CFG1_FRATE_DIV_4 (3 << 8) 55c1d82b89SHans Verkuil #define ISI_CFG1_FRATE_DIV_5 (4 << 8) 56c1d82b89SHans Verkuil #define ISI_CFG1_FRATE_DIV_6 (5 << 8) 57c1d82b89SHans Verkuil #define ISI_CFG1_FRATE_DIV_7 (6 << 8) 58c1d82b89SHans Verkuil #define ISI_CFG1_FRATE_DIV_8 (7 << 8) 59c1d82b89SHans Verkuil #define ISI_CFG1_FRATE_DIV_MASK (7 << 8) 60c1d82b89SHans Verkuil #define ISI_CFG1_DISCR (1 << 11) 61c1d82b89SHans Verkuil #define ISI_CFG1_FULL_MODE (1 << 12) 62c1d82b89SHans Verkuil /* Definition for THMASK(ISI_V2) */ 63c1d82b89SHans Verkuil #define ISI_CFG1_THMASK_BEATS_4 (0 << 13) 64c1d82b89SHans Verkuil #define ISI_CFG1_THMASK_BEATS_8 (1 << 13) 65c1d82b89SHans Verkuil #define ISI_CFG1_THMASK_BEATS_16 (2 << 13) 66c1d82b89SHans Verkuil 67c1d82b89SHans Verkuil /* Bitfields in CFG2 */ 68c1d82b89SHans Verkuil #define ISI_CFG2_GRAYSCALE (1 << 13) 69c1d82b89SHans Verkuil #define ISI_CFG2_COL_SPACE_YCbCr (0 << 15) 70c1d82b89SHans Verkuil #define ISI_CFG2_COL_SPACE_RGB (1 << 15) 71c1d82b89SHans Verkuil /* Constants for YCC_SWAP(ISI_V2) */ 72c1d82b89SHans Verkuil #define ISI_CFG2_YCC_SWAP_DEFAULT (0 << 28) 73c1d82b89SHans Verkuil #define ISI_CFG2_YCC_SWAP_MODE_1 (1 << 28) 74c1d82b89SHans Verkuil #define ISI_CFG2_YCC_SWAP_MODE_2 (2 << 28) 75c1d82b89SHans Verkuil #define ISI_CFG2_YCC_SWAP_MODE_3 (3 << 28) 76c1d82b89SHans Verkuil #define ISI_CFG2_YCC_SWAP_MODE_MASK (3 << 28) 77c1d82b89SHans Verkuil #define ISI_CFG2_IM_VSIZE_OFFSET 0 78c1d82b89SHans Verkuil #define ISI_CFG2_IM_HSIZE_OFFSET 16 79c1d82b89SHans Verkuil #define ISI_CFG2_IM_VSIZE_MASK (0x7FF << ISI_CFG2_IM_VSIZE_OFFSET) 80c1d82b89SHans Verkuil #define ISI_CFG2_IM_HSIZE_MASK (0x7FF << ISI_CFG2_IM_HSIZE_OFFSET) 81c1d82b89SHans Verkuil 82c1d82b89SHans Verkuil /* Bitfields in PSIZE */ 83c1d82b89SHans Verkuil #define ISI_PSIZE_PREV_VSIZE_OFFSET 0 84c1d82b89SHans Verkuil #define ISI_PSIZE_PREV_HSIZE_OFFSET 16 85c1d82b89SHans Verkuil #define ISI_PSIZE_PREV_VSIZE_MASK (0x3FF << ISI_PSIZE_PREV_VSIZE_OFFSET) 86c1d82b89SHans Verkuil #define ISI_PSIZE_PREV_HSIZE_MASK (0x3FF << ISI_PSIZE_PREV_HSIZE_OFFSET) 87c1d82b89SHans Verkuil 88c1d82b89SHans Verkuil /* Bitfields in PDECF */ 89c1d82b89SHans Verkuil #define ISI_PDECF_DEC_FACTOR_MASK (0xFF << 0) 90c1d82b89SHans Verkuil #define ISI_PDECF_NO_SAMPLING (16) 91c1d82b89SHans Verkuil 92c1d82b89SHans Verkuil /* Bitfields in CTRL */ 93c1d82b89SHans Verkuil /* Also using in SR(ISI_V2) */ 94c1d82b89SHans Verkuil #define ISI_CTRL_EN (1 << 0) 95c1d82b89SHans Verkuil #define ISI_CTRL_CDC (1 << 8) 96c1d82b89SHans Verkuil /* Also using in SR/IER/IDR/IMR(ISI_V2) */ 97c1d82b89SHans Verkuil #define ISI_CTRL_DIS (1 << 1) 98c1d82b89SHans Verkuil #define ISI_CTRL_SRST (1 << 2) 99c1d82b89SHans Verkuil 100c1d82b89SHans Verkuil /* Bitfields in SR */ 101c1d82b89SHans Verkuil #define ISI_SR_SIP (1 << 19) 102c1d82b89SHans Verkuil /* Also using in SR/IER/IDR/IMR */ 103c1d82b89SHans Verkuil #define ISI_SR_VSYNC (1 << 10) 104c1d82b89SHans Verkuil #define ISI_SR_PXFR_DONE (1 << 16) 105c1d82b89SHans Verkuil #define ISI_SR_CXFR_DONE (1 << 17) 106c1d82b89SHans Verkuil #define ISI_SR_P_OVR (1 << 24) 107c1d82b89SHans Verkuil #define ISI_SR_C_OVR (1 << 25) 108c1d82b89SHans Verkuil #define ISI_SR_CRC_ERR (1 << 26) 109c1d82b89SHans Verkuil #define ISI_SR_FR_OVR (1 << 27) 110c1d82b89SHans Verkuil 111c1d82b89SHans Verkuil /* Bitfields in DMA_C_CTRL & in DMA_P_CTRL */ 112c1d82b89SHans Verkuil #define ISI_DMA_CTRL_FETCH (1 << 0) 113c1d82b89SHans Verkuil #define ISI_DMA_CTRL_WB (1 << 1) 114c1d82b89SHans Verkuil #define ISI_DMA_CTRL_IEN (1 << 2) 115c1d82b89SHans Verkuil #define ISI_DMA_CTRL_DONE (1 << 3) 116c1d82b89SHans Verkuil 117c1d82b89SHans Verkuil /* Bitfields in DMA_CHSR/CHER/CHDR */ 118c1d82b89SHans Verkuil #define ISI_DMA_CHSR_P_CH (1 << 0) 119c1d82b89SHans Verkuil #define ISI_DMA_CHSR_C_CH (1 << 1) 120c1d82b89SHans Verkuil 121c1d82b89SHans Verkuil /* Definition for isi_platform_data */ 122c1d82b89SHans Verkuil #define ISI_DATAWIDTH_8 0x01 123c1d82b89SHans Verkuil #define ISI_DATAWIDTH_10 0x02 124c1d82b89SHans Verkuil 125c1d82b89SHans Verkuil struct v4l2_async_subdev; 126c1d82b89SHans Verkuil 127c1d82b89SHans Verkuil struct isi_platform_data { 128c1d82b89SHans Verkuil u8 has_emb_sync; 129c1d82b89SHans Verkuil u8 hsync_act_low; 130c1d82b89SHans Verkuil u8 vsync_act_low; 131c1d82b89SHans Verkuil u8 pclk_act_falling; 132c1d82b89SHans Verkuil u8 full_mode; 133c1d82b89SHans Verkuil u32 data_width_flags; 134c1d82b89SHans Verkuil /* Using for ISI_CFG1 */ 135c1d82b89SHans Verkuil u32 frate; 136c1d82b89SHans Verkuil }; 137c1d82b89SHans Verkuil 138c1d82b89SHans Verkuil #endif /* __ATMEL_ISI_H__ */ 139