1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright 2020-2021 NXP 4 */ 5 6 #include <linux/init.h> 7 #include <linux/interconnect.h> 8 #include <linux/ioctl.h> 9 #include <linux/list.h> 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/of_device.h> 13 #include <linux/of_address.h> 14 #include <linux/platform_device.h> 15 #include <media/videobuf2-v4l2.h> 16 #include <media/videobuf2-dma-contig.h> 17 #include "vpu.h" 18 #include "vpu_rpc.h" 19 #include "vpu_defs.h" 20 #include "vpu_helpers.h" 21 #include "vpu_cmds.h" 22 #include "vpu_v4l2.h" 23 #include "vpu_imx8q.h" 24 #include "vpu_windsor.h" 25 26 #define CMD_SIZE 2560 27 #define MSG_SIZE 25600 28 #define WINDSOR_USER_DATA_WORDS 16 29 #define WINDSOR_MAX_SRC_FRAMES 0x6 30 #define WINDSOR_MAX_REF_FRAMES 0x3 31 #define WINDSOR_BITRATE_UNIT 1024 32 #define WINDSOR_H264_EXTENDED_SAR 255 33 34 enum { 35 GTB_ENC_CMD_NOOP = 0x0, 36 GTB_ENC_CMD_STREAM_START, 37 GTB_ENC_CMD_FRAME_ENCODE, 38 GTB_ENC_CMD_FRAME_SKIP, 39 GTB_ENC_CMD_STREAM_STOP, 40 GTB_ENC_CMD_PARAMETER_UPD, 41 GTB_ENC_CMD_TERMINATE, 42 GTB_ENC_CMD_SNAPSHOT, 43 GTB_ENC_CMD_ROLL_SNAPSHOT, 44 GTB_ENC_CMD_LOCK_SCHEDULER, 45 GTB_ENC_CMD_UNLOCK_SCHEDULER, 46 GTB_ENC_CMD_CONFIGURE_CODEC, 47 GTB_ENC_CMD_DEAD_MARK, 48 GTB_ENC_CMD_FIRM_RESET, 49 GTB_ENC_CMD_FW_STATUS, 50 GTB_ENC_CMD_RESERVED 51 }; 52 53 enum { 54 VID_API_EVENT_UNDEFINED = 0x0, 55 VID_API_ENC_EVENT_RESET_DONE = 0x1, 56 VID_API_ENC_EVENT_START_DONE, 57 VID_API_ENC_EVENT_STOP_DONE, 58 VID_API_ENC_EVENT_TERMINATE_DONE, 59 VID_API_ENC_EVENT_FRAME_INPUT_DONE, 60 VID_API_ENC_EVENT_FRAME_DONE, 61 VID_API_ENC_EVENT_FRAME_RELEASE, 62 VID_API_ENC_EVENT_PARA_UPD_DONE, 63 VID_API_ENC_EVENT_MEM_REQUEST, 64 VID_API_ENC_EVENT_FIRMWARE_XCPT, 65 VID_API_ENC_EVENT_RESERVED 66 }; 67 68 enum { 69 MEDIAIP_ENC_PIC_TYPE_B_FRAME = 0, 70 MEDIAIP_ENC_PIC_TYPE_P_FRAME, 71 MEDIAIP_ENC_PIC_TYPE_I_FRAME, 72 MEDIAIP_ENC_PIC_TYPE_IDR_FRAME, 73 MEDIAIP_ENC_PIC_TYPE_BI_FRAME 74 }; 75 76 struct windsor_iface { 77 u32 exec_base_addr; 78 u32 exec_area_size; 79 struct vpu_rpc_buffer_desc cmd_buffer_desc; 80 struct vpu_rpc_buffer_desc msg_buffer_desc; 81 u32 cmd_int_enable[VID_API_NUM_STREAMS]; 82 u32 fw_version; 83 u32 mvd_fw_offset; 84 u32 max_streams; 85 u32 ctrl_iface[VID_API_NUM_STREAMS]; 86 struct vpu_rpc_system_config system_config; 87 u32 api_version; 88 struct vpu_rpc_buffer_desc log_buffer_desc; 89 }; 90 91 struct windsor_ctrl_iface { 92 u32 enc_yuv_buffer_desc; 93 u32 enc_stream_buffer_desc; 94 u32 enc_expert_mode_param; 95 u32 enc_param; 96 u32 enc_mem_pool; 97 u32 enc_encoding_status; 98 u32 enc_dsa_status; 99 }; 100 101 struct vpu_enc_yuv_desc { 102 u32 frame_id; 103 u32 luma_base; 104 u32 chroma_base; 105 u32 param_idx; 106 u32 key_frame; 107 }; 108 109 struct vpu_enc_calib_params { 110 u32 use_ame; 111 112 u32 cme_mvx_max; 113 u32 cme_mvy_max; 114 u32 ame_prefresh_y0; 115 u32 ame_prefresh_y1; 116 u32 fme_min_sad; 117 u32 cme_min_sad; 118 119 u32 fme_pred_int_weight; 120 u32 fme_pred_hp_weight; 121 u32 fme_pred_qp_weight; 122 u32 fme_cost_weight; 123 u32 fme_act_thold; 124 u32 fme_sad_thold; 125 u32 fme_zero_sad_thold; 126 127 u32 fme_lrg_mvx_lmt; 128 u32 fme_lrg_mvy_lmt; 129 u32 fme_force_mode; 130 u32 fme_force4mvcost; 131 u32 fme_force2mvcost; 132 133 u32 h264_inter_thrd; 134 135 u32 i16x16_mode_cost; 136 u32 i4x4_mode_lambda; 137 u32 i8x8_mode_lambda; 138 139 u32 inter_mod_mult; 140 u32 inter_sel_mult; 141 u32 inter_bid_cost; 142 u32 inter_bwd_cost; 143 u32 inter_4mv_cost; 144 s32 one_mv_i16_cost; 145 s32 one_mv_i4x4_cost; 146 s32 one_mv_i8x8_cost; 147 s32 two_mv_i16_cost; 148 s32 two_mv_i4x4_cost; 149 s32 two_mv_i8x8_cost; 150 s32 four_mv_i16_cost; 151 s32 four_mv_i4x4_cost; 152 s32 four_mv_i8x8_cost; 153 154 u32 intra_pred_enab; 155 u32 intra_chr_pred; 156 u32 intra16_pred; 157 u32 intra4x4_pred; 158 u32 intra8x8_pred; 159 160 u32 cb_base; 161 u32 cb_size; 162 u32 cb_head_room; 163 164 u32 mem_page_width; 165 u32 mem_page_height; 166 u32 mem_total_size; 167 u32 mem_chunk_phys_addr; 168 u32 mem_chunk_virt_addr; 169 u32 mem_chunk_size; 170 u32 mem_y_stride; 171 u32 mem_uv_stride; 172 173 u32 split_wr_enab; 174 u32 split_wr_req_size; 175 u32 split_rd_enab; 176 u32 split_rd_req_size; 177 }; 178 179 struct vpu_enc_config_params { 180 u32 param_change; 181 u32 start_frame; 182 u32 end_frame; 183 u32 userdata_enable; 184 u32 userdata_id[4]; 185 u32 userdata_message[WINDSOR_USER_DATA_WORDS]; 186 u32 userdata_length; 187 u32 h264_profile_idc; 188 u32 h264_level_idc; 189 u32 h264_au_delimiter; 190 u32 h264_seq_end_code; 191 u32 h264_recovery_points; 192 u32 h264_vui_parameters; 193 u32 h264_aspect_ratio_present; 194 u32 h264_aspect_ratio_sar_width; 195 u32 h264_aspect_ratio_sar_height; 196 u32 h264_overscan_present; 197 u32 h264_video_type_present; 198 u32 h264_video_format; 199 u32 h264_video_full_range; 200 u32 h264_video_colour_descriptor; 201 u32 h264_video_colour_primaries; 202 u32 h264_video_transfer_char; 203 u32 h264_video_matrix_coeff; 204 u32 h264_chroma_loc_info_present; 205 u32 h264_chroma_loc_type_top; 206 u32 h264_chroma_loc_type_bot; 207 u32 h264_timing_info_present; 208 u32 h264_buffering_period_present; 209 u32 h264_low_delay_hrd_flag; 210 u32 aspect_ratio; 211 u32 test_mode; // Automated firmware test mode 212 u32 dsa_test_mode; // Automated test mode for the DSA. 213 u32 fme_test_mode; // Automated test mode for the fme 214 u32 cbr_row_mode; //0: FW mode; 1: HW mode 215 u32 windsor_mode; //0: normal mode; 1: intra only mode; 2: intra+0MV mode 216 u32 encode_mode; // H264, VC1, MPEG2, DIVX 217 u32 frame_width; // display width 218 u32 frame_height; // display height 219 u32 enc_frame_width; // encoding width, should be 16-pix align 220 u32 enc_frame_height; // encoding height, should be 16-pix aligned 221 u32 frame_rate_num; 222 u32 frame_rate_den; 223 u32 vi_field_source; 224 u32 vi_frame_width; 225 u32 vi_frame_height; 226 u32 crop_frame_width; 227 u32 crop_frame_height; 228 u32 crop_x_start_posn; 229 u32 crop_y_start_posn; 230 u32 mode422; 231 u32 mode_yuy2; 232 u32 dsa_luma_en; 233 u32 dsa_chroma_en; 234 u32 dsa_ext_hfilt_en; 235 u32 dsa_di_en; 236 u32 dsa_di_top_ref; 237 u32 dsa_vertf_disable; 238 u32 dsa_disable_pwb; 239 u32 dsa_hor_phase; 240 u32 dsa_ver_phase; 241 u32 dsa_iac_enable; 242 u32 iac_sc_threshold; 243 u32 iac_vm_threshold; 244 u32 iac_skip_mode; 245 u32 iac_grp_width; 246 u32 iac_grp_height; 247 u32 rate_control_mode; 248 u32 rate_control_resolution; 249 u32 buffer_size; 250 u32 buffer_level_init; 251 u32 buffer_I_bit_budget; 252 u32 top_field_first; 253 u32 intra_lum_qoffset; 254 u32 intra_chr_qoffset; 255 u32 inter_lum_qoffset; 256 u32 inter_chr_qoffset; 257 u32 use_def_scaling_mtx; 258 u32 inter_8x8_enab; 259 u32 inter_4x4_enab; 260 u32 fme_enable_qpel; 261 u32 fme_enable_hpel; 262 u32 fme_nozeromv; 263 u32 fme_predmv_en; 264 u32 fme_pred_2mv4mv; 265 u32 fme_smallsadthresh; 266 u32 ame_en_lmvc; 267 u32 ame_x_mult; 268 u32 cme_enable_4mv; 269 u32 cme_enable_1mv; 270 u32 hme_enable_16x8mv; 271 u32 hme_enable_8x16mv; 272 u32 cme_mv_weight; 273 u32 cme_mv_cost; 274 u32 ame_mult_mv; 275 u32 ame_shift_mv; 276 u32 hme_forceto1mv_en; 277 u32 hme_2mv_cost; 278 u32 hme_pred_mode; 279 u32 hme_sc_rnge; 280 u32 hme_sw_rnge; 281 u32 output_format; 282 u32 timestamp_enab; 283 u32 initial_pts_enab; 284 u32 initial_pts; 285 }; 286 287 struct vpu_enc_static_params { 288 u32 param_change; 289 u32 gop_length; 290 u32 rate_control_bitrate; 291 u32 rate_control_bitrate_min; 292 u32 rate_control_bitrate_max; 293 u32 rate_control_content_models; 294 u32 rate_control_iframe_maxsize; 295 u32 rate_control_qp_init; 296 u32 rate_control_islice_qp; 297 u32 rate_control_pslice_qp; 298 u32 rate_control_bslice_qp; 299 u32 adaptive_quantization; 300 u32 aq_variance; 301 u32 cost_optimization; 302 u32 fdlp_mode; 303 u32 enable_isegbframes; 304 u32 enable_adaptive_keyratio; 305 u32 keyratio_imin; 306 u32 keyratio_imax; 307 u32 keyratio_pmin; 308 u32 keyratio_pmax; 309 u32 keyratio_bmin; 310 u32 keyratio_bmax; 311 s32 keyratio_istep; 312 s32 keyratio_pstep; 313 s32 keyratio_bstep; 314 u32 enable_paff; 315 u32 enable_b_frame_ref; 316 u32 enable_adaptive_gop; 317 u32 enable_closed_gop; 318 u32 open_gop_refresh_freq; 319 u32 enable_adaptive_sc; 320 u32 enable_fade_detection; 321 s32 fade_detection_threshold; 322 u32 enable_repeat_b; 323 u32 enable_low_delay_b; 324 }; 325 326 struct vpu_enc_dynamic_params { 327 u32 param_change; 328 u32 rows_per_slice; 329 u32 mbaff_enable; 330 u32 dbf_enable; 331 u32 field_source; 332 u32 gop_b_length; 333 u32 mb_group_size; 334 u32 cbr_rows_per_group; 335 u32 skip_enable; 336 u32 pts_bits_0_to_31; 337 u32 pts_bit_32; 338 u32 rm_expsv_cff; 339 u32 const_ipred; 340 s32 chr_qp_offset; 341 u32 intra_mb_qp_offset; 342 u32 h264_cabac_init_method; 343 u32 h264_cabac_init_idc; 344 u32 h264_cabac_enable; 345 s32 alpha_c0_offset_div2; 346 s32 beta_offset_div2; 347 u32 intra_prefresh_y0; 348 u32 intra_prefresh_y1; 349 u32 dbg_dump_rec_src; 350 }; 351 352 struct vpu_enc_expert_mode_param { 353 struct vpu_enc_calib_params calib_param; 354 struct vpu_enc_config_params config_param; 355 struct vpu_enc_static_params static_param; 356 struct vpu_enc_dynamic_params dynamic_param; 357 }; 358 359 enum MEDIAIP_ENC_FMT { 360 MEDIAIP_ENC_FMT_H264 = 0, 361 MEDIAIP_ENC_FMT_VC1, 362 MEDIAIP_ENC_FMT_MPEG2, 363 MEDIAIP_ENC_FMT_MPEG4SP, 364 MEDIAIP_ENC_FMT_H263, 365 MEDIAIP_ENC_FMT_MPEG1, 366 MEDIAIP_ENC_FMT_SHORT_HEADER, 367 MEDIAIP_ENC_FMT_NULL 368 }; 369 370 enum MEDIAIP_ENC_PROFILE { 371 MEDIAIP_ENC_PROF_MPEG2_SP = 0, 372 MEDIAIP_ENC_PROF_MPEG2_MP, 373 MEDIAIP_ENC_PROF_MPEG2_HP, 374 MEDIAIP_ENC_PROF_H264_BP, 375 MEDIAIP_ENC_PROF_H264_MP, 376 MEDIAIP_ENC_PROF_H264_HP, 377 MEDIAIP_ENC_PROF_MPEG4_SP, 378 MEDIAIP_ENC_PROF_MPEG4_ASP, 379 MEDIAIP_ENC_PROF_VC1_SP, 380 MEDIAIP_ENC_PROF_VC1_MP, 381 MEDIAIP_ENC_PROF_VC1_AP 382 }; 383 384 enum MEDIAIP_ENC_BITRATE_MODE { 385 MEDIAIP_ENC_BITRATE_MODE_VBR = 0x00000001, 386 MEDIAIP_ENC_BITRATE_MODE_CBR = 0x00000002, 387 MEDIAIP_ENC_BITRATE_MODE_CONSTANT_QP = 0x00000004 388 }; 389 390 struct vpu_enc_memory_resource { 391 u32 phys; 392 u32 virt; 393 u32 size; 394 }; 395 396 struct vpu_enc_param { 397 enum MEDIAIP_ENC_FMT codec_mode; 398 enum MEDIAIP_ENC_PROFILE profile; 399 u32 level; 400 401 struct vpu_enc_memory_resource enc_mem_desc; 402 403 u32 frame_rate; 404 u32 src_stride; 405 u32 src_width; 406 u32 src_height; 407 u32 src_offset_x; 408 u32 src_offset_y; 409 u32 src_crop_width; 410 u32 src_crop_height; 411 u32 out_width; 412 u32 out_height; 413 u32 iframe_interval; 414 u32 bframes; 415 u32 low_latency_mode; 416 417 enum MEDIAIP_ENC_BITRATE_MODE bitrate_mode; 418 u32 target_bitrate; 419 u32 max_bitrate; 420 u32 min_bitrate; 421 u32 init_slice_qp; 422 }; 423 424 struct vpu_enc_mem_pool { 425 struct vpu_enc_memory_resource enc_frames[WINDSOR_MAX_SRC_FRAMES]; 426 struct vpu_enc_memory_resource ref_frames[WINDSOR_MAX_REF_FRAMES]; 427 struct vpu_enc_memory_resource act_frame; 428 }; 429 430 struct vpu_enc_encoding_status { 431 u32 frame_id; 432 u32 error_flag; //Error type 433 u32 mb_y; 434 u32 mb_x; 435 u32 reserved[12]; 436 437 }; 438 439 struct vpu_enc_dsa_status { 440 u32 frame_id; 441 u32 dsa_cyle; 442 u32 mb_y; 443 u32 mb_x; 444 u32 reserved[4]; 445 }; 446 447 struct vpu_enc_ctrl { 448 struct vpu_enc_yuv_desc *yuv_desc; 449 struct vpu_rpc_buffer_desc *stream_desc; 450 struct vpu_enc_expert_mode_param *expert; 451 struct vpu_enc_param *param; 452 struct vpu_enc_mem_pool *pool; 453 struct vpu_enc_encoding_status *status; 454 struct vpu_enc_dsa_status *dsa; 455 }; 456 457 struct vpu_enc_host_ctrls { 458 struct vpu_enc_ctrl ctrls[VID_API_NUM_STREAMS]; 459 }; 460 461 struct windsor_pic_info { 462 u32 frame_id; 463 u32 pic_encod_done; 464 u32 pic_type; 465 u32 skipped_frame; 466 u32 error_flag; 467 u32 psnr; 468 u32 flush_done; 469 u32 mb_y; 470 u32 mb_x; 471 u32 frame_size; 472 u32 frame_enc_ttl_cycles; 473 u32 frame_enc_ttl_frm_cycles; 474 u32 frame_enc_ttl_slc_cycles; 475 u32 frame_enc_ttl_enc_cycles; 476 u32 frame_enc_ttl_hme_cycles; 477 u32 frame_enc_ttl_dsa_cycles; 478 u32 frame_enc_fw_cycles; 479 u32 frame_crc; 480 u32 num_interrupts_1; 481 u32 num_interrupts_2; 482 u32 poc; 483 u32 ref_info; 484 u32 pic_num; 485 u32 pic_activity; 486 u32 scene_change; 487 u32 mb_stats; 488 u32 enc_cache_count0; 489 u32 enc_cache_count1; 490 u32 mtl_wr_strb_cnt; 491 u32 mtl_rd_strb_cnt; 492 u32 str_buff_wptr; 493 u32 diagnosticEvents; 494 u32 proc_iacc_tot_rd_cnt; 495 u32 proc_dacc_tot_rd_cnt; 496 u32 proc_dacc_tot_wr_cnt; 497 u32 proc_dacc_reg_rd_cnt; 498 u32 proc_dacc_reg_wr_cnt; 499 u32 proc_dacc_rng_rd_cnt; 500 u32 proc_dacc_rng_wr_cnt; 501 s32 tv_s; 502 u32 tv_ns; 503 }; 504 505 u32 vpu_windsor_get_data_size(void) 506 { 507 return sizeof(struct vpu_enc_host_ctrls); 508 } 509 510 static struct vpu_enc_yuv_desc *get_yuv_desc(struct vpu_shared_addr *shared, 511 u32 instance) 512 { 513 struct vpu_enc_host_ctrls *hcs = shared->priv; 514 515 return hcs->ctrls[instance].yuv_desc; 516 } 517 518 static struct vpu_enc_mem_pool *get_mem_pool(struct vpu_shared_addr *shared, 519 u32 instance) 520 { 521 struct vpu_enc_host_ctrls *hcs = shared->priv; 522 523 return hcs->ctrls[instance].pool; 524 } 525 526 static struct vpu_rpc_buffer_desc *get_stream_buf_desc(struct vpu_shared_addr *shared, 527 u32 instance) 528 { 529 struct vpu_enc_host_ctrls *hcs = shared->priv; 530 531 return hcs->ctrls[instance].stream_desc; 532 } 533 534 static struct vpu_enc_expert_mode_param *get_expert_param(struct vpu_shared_addr *shared, 535 u32 instance) 536 { 537 struct vpu_enc_host_ctrls *hcs = shared->priv; 538 539 return hcs->ctrls[instance].expert; 540 } 541 542 static struct vpu_enc_param *get_enc_param(struct vpu_shared_addr *shared, u32 instance) 543 { 544 struct vpu_enc_host_ctrls *hcs = shared->priv; 545 546 return hcs->ctrls[instance].param; 547 } 548 549 static u32 get_ptr(u32 ptr) 550 { 551 return (ptr | 0x80000000); 552 } 553 554 void vpu_windsor_init_rpc(struct vpu_shared_addr *shared, 555 struct vpu_buffer *rpc, dma_addr_t boot_addr) 556 { 557 unsigned long base_phy_addr; 558 unsigned long phy_addr; 559 unsigned long offset; 560 struct windsor_iface *iface; 561 struct windsor_ctrl_iface *ctrl; 562 struct vpu_enc_host_ctrls *hcs; 563 unsigned int i; 564 565 if (rpc->phys < boot_addr) 566 return; 567 568 base_phy_addr = rpc->phys - boot_addr; 569 iface = rpc->virt; 570 shared->iface = iface; 571 shared->boot_addr = boot_addr; 572 hcs = shared->priv; 573 574 iface->exec_base_addr = base_phy_addr; 575 iface->exec_area_size = rpc->length; 576 577 offset = sizeof(struct windsor_iface); 578 phy_addr = base_phy_addr + offset; 579 shared->cmd_desc = &iface->cmd_buffer_desc; 580 shared->cmd_mem_vir = rpc->virt + offset; 581 iface->cmd_buffer_desc.start = 582 iface->cmd_buffer_desc.rptr = 583 iface->cmd_buffer_desc.wptr = phy_addr; 584 iface->cmd_buffer_desc.end = iface->cmd_buffer_desc.start + CMD_SIZE; 585 586 offset += CMD_SIZE; 587 phy_addr = base_phy_addr + offset; 588 shared->msg_desc = &iface->msg_buffer_desc; 589 shared->msg_mem_vir = rpc->virt + offset; 590 iface->msg_buffer_desc.start = 591 iface->msg_buffer_desc.wptr = 592 iface->msg_buffer_desc.rptr = phy_addr; 593 iface->msg_buffer_desc.end = iface->msg_buffer_desc.start + MSG_SIZE; 594 595 offset += MSG_SIZE; 596 for (i = 0; i < ARRAY_SIZE(iface->ctrl_iface); i++) { 597 iface->ctrl_iface[i] = base_phy_addr + offset; 598 offset += sizeof(struct windsor_ctrl_iface); 599 } 600 for (i = 0; i < ARRAY_SIZE(iface->ctrl_iface); i++) { 601 ctrl = rpc->virt + (iface->ctrl_iface[i] - base_phy_addr); 602 603 ctrl->enc_yuv_buffer_desc = base_phy_addr + offset; 604 hcs->ctrls[i].yuv_desc = rpc->virt + offset; 605 offset += sizeof(struct vpu_enc_yuv_desc); 606 607 ctrl->enc_stream_buffer_desc = base_phy_addr + offset; 608 hcs->ctrls[i].stream_desc = rpc->virt + offset; 609 offset += sizeof(struct vpu_rpc_buffer_desc); 610 611 ctrl->enc_expert_mode_param = base_phy_addr + offset; 612 hcs->ctrls[i].expert = rpc->virt + offset; 613 offset += sizeof(struct vpu_enc_expert_mode_param); 614 615 ctrl->enc_param = base_phy_addr + offset; 616 hcs->ctrls[i].param = rpc->virt + offset; 617 offset += sizeof(struct vpu_enc_param); 618 619 ctrl->enc_mem_pool = base_phy_addr + offset; 620 hcs->ctrls[i].pool = rpc->virt + offset; 621 offset += sizeof(struct vpu_enc_mem_pool); 622 623 ctrl->enc_encoding_status = base_phy_addr + offset; 624 hcs->ctrls[i].status = rpc->virt + offset; 625 offset += sizeof(struct vpu_enc_encoding_status); 626 627 ctrl->enc_dsa_status = base_phy_addr + offset; 628 hcs->ctrls[i].dsa = rpc->virt + offset; 629 offset += sizeof(struct vpu_enc_dsa_status); 630 } 631 632 rpc->bytesused = offset; 633 } 634 635 void vpu_windsor_set_log_buf(struct vpu_shared_addr *shared, struct vpu_buffer *log) 636 { 637 struct windsor_iface *iface = shared->iface; 638 639 iface->log_buffer_desc.start = 640 iface->log_buffer_desc.wptr = 641 iface->log_buffer_desc.rptr = log->phys - shared->boot_addr; 642 iface->log_buffer_desc.end = iface->log_buffer_desc.start + log->length; 643 } 644 645 void vpu_windsor_set_system_cfg(struct vpu_shared_addr *shared, 646 u32 regs_base, void __iomem *regs, u32 core_id) 647 { 648 struct windsor_iface *iface = shared->iface; 649 struct vpu_rpc_system_config *config = &iface->system_config; 650 651 vpu_imx8q_set_system_cfg_common(config, regs_base, core_id); 652 } 653 654 int vpu_windsor_get_stream_buffer_size(struct vpu_shared_addr *shared) 655 { 656 return 0x300000; 657 } 658 659 static struct vpu_pair windsor_cmds[] = { 660 {VPU_CMD_ID_CONFIGURE_CODEC, GTB_ENC_CMD_CONFIGURE_CODEC}, 661 {VPU_CMD_ID_START, GTB_ENC_CMD_STREAM_START}, 662 {VPU_CMD_ID_STOP, GTB_ENC_CMD_STREAM_STOP}, 663 {VPU_CMD_ID_FRAME_ENCODE, GTB_ENC_CMD_FRAME_ENCODE}, 664 {VPU_CMD_ID_SNAPSHOT, GTB_ENC_CMD_SNAPSHOT}, 665 {VPU_CMD_ID_FIRM_RESET, GTB_ENC_CMD_FIRM_RESET}, 666 {VPU_CMD_ID_UPDATE_PARAMETER, GTB_ENC_CMD_PARAMETER_UPD}, 667 {VPU_CMD_ID_DEBUG, GTB_ENC_CMD_FW_STATUS} 668 }; 669 670 static struct vpu_pair windsor_msgs[] = { 671 {VPU_MSG_ID_RESET_DONE, VID_API_ENC_EVENT_RESET_DONE}, 672 {VPU_MSG_ID_START_DONE, VID_API_ENC_EVENT_START_DONE}, 673 {VPU_MSG_ID_STOP_DONE, VID_API_ENC_EVENT_STOP_DONE}, 674 {VPU_MSG_ID_FRAME_INPUT_DONE, VID_API_ENC_EVENT_FRAME_INPUT_DONE}, 675 {VPU_MSG_ID_ENC_DONE, VID_API_ENC_EVENT_FRAME_DONE}, 676 {VPU_MSG_ID_FRAME_RELEASE, VID_API_ENC_EVENT_FRAME_RELEASE}, 677 {VPU_MSG_ID_MEM_REQUEST, VID_API_ENC_EVENT_MEM_REQUEST}, 678 {VPU_MSG_ID_PARAM_UPD_DONE, VID_API_ENC_EVENT_PARA_UPD_DONE}, 679 {VPU_MSG_ID_FIRMWARE_XCPT, VID_API_ENC_EVENT_FIRMWARE_XCPT}, 680 }; 681 682 int vpu_windsor_pack_cmd(struct vpu_rpc_event *pkt, u32 index, u32 id, void *data) 683 { 684 int ret; 685 s64 timestamp; 686 687 ret = vpu_find_dst_by_src(windsor_cmds, ARRAY_SIZE(windsor_cmds), id); 688 if (ret < 0) 689 return ret; 690 pkt->hdr.id = ret; 691 pkt->hdr.num = 0; 692 pkt->hdr.index = index; 693 if (id == VPU_CMD_ID_FRAME_ENCODE) { 694 pkt->hdr.num = 2; 695 timestamp = *(s64 *)data; 696 if (timestamp < 0) { 697 pkt->data[0] = (u32)-1; 698 pkt->data[1] = 0; 699 } else { 700 pkt->data[0] = timestamp / NSEC_PER_SEC; 701 pkt->data[1] = timestamp % NSEC_PER_SEC; 702 } 703 } 704 705 return 0; 706 } 707 708 int vpu_windsor_convert_msg_id(u32 id) 709 { 710 return vpu_find_src_by_dst(windsor_msgs, ARRAY_SIZE(windsor_msgs), id); 711 } 712 713 static void vpu_windsor_unpack_pic_info(struct vpu_rpc_event *pkt, void *data) 714 { 715 struct vpu_enc_pic_info *info = data; 716 struct windsor_pic_info *windsor = (struct windsor_pic_info *)pkt->data; 717 718 info->frame_id = windsor->frame_id; 719 switch (windsor->pic_type) { 720 case MEDIAIP_ENC_PIC_TYPE_I_FRAME: 721 case MEDIAIP_ENC_PIC_TYPE_IDR_FRAME: 722 info->pic_type = V4L2_BUF_FLAG_KEYFRAME; 723 break; 724 case MEDIAIP_ENC_PIC_TYPE_P_FRAME: 725 info->pic_type = V4L2_BUF_FLAG_PFRAME; 726 break; 727 case MEDIAIP_ENC_PIC_TYPE_B_FRAME: 728 info->pic_type = V4L2_BUF_FLAG_BFRAME; 729 break; 730 default: 731 break; 732 } 733 info->skipped_frame = windsor->skipped_frame; 734 info->error_flag = windsor->error_flag; 735 info->psnr = windsor->psnr; 736 info->frame_size = windsor->frame_size; 737 info->wptr = get_ptr(windsor->str_buff_wptr); 738 info->crc = windsor->frame_crc; 739 info->timestamp = MAKE_TIMESTAMP(windsor->tv_s, windsor->tv_ns); 740 } 741 742 static void vpu_windsor_unpack_mem_req(struct vpu_rpc_event *pkt, void *data) 743 { 744 struct vpu_pkt_mem_req_data *req_data = data; 745 746 req_data->enc_frame_size = pkt->data[0]; 747 req_data->enc_frame_num = pkt->data[1]; 748 req_data->ref_frame_size = pkt->data[2]; 749 req_data->ref_frame_num = pkt->data[3]; 750 req_data->act_buf_size = pkt->data[4]; 751 req_data->act_buf_num = 1; 752 } 753 754 int vpu_windsor_unpack_msg_data(struct vpu_rpc_event *pkt, void *data) 755 { 756 if (!pkt || !data) 757 return -EINVAL; 758 759 switch (pkt->hdr.id) { 760 case VID_API_ENC_EVENT_FRAME_DONE: 761 vpu_windsor_unpack_pic_info(pkt, data); 762 break; 763 case VID_API_ENC_EVENT_MEM_REQUEST: 764 vpu_windsor_unpack_mem_req(pkt, data); 765 break; 766 case VID_API_ENC_EVENT_FRAME_RELEASE: 767 *(u32 *)data = pkt->data[0]; 768 break; 769 default: 770 break; 771 } 772 773 return 0; 774 } 775 776 static int vpu_windsor_fill_yuv_frame(struct vpu_shared_addr *shared, 777 u32 instance, 778 struct vb2_buffer *vb) 779 { 780 struct vpu_enc_yuv_desc *desc; 781 struct vb2_v4l2_buffer *vbuf; 782 783 if (instance >= VID_API_NUM_STREAMS) 784 return -EINVAL; 785 786 desc = get_yuv_desc(shared, instance); 787 788 vbuf = to_vb2_v4l2_buffer(vb); 789 desc->frame_id = vbuf->sequence; 790 if (vbuf->flags & V4L2_BUF_FLAG_KEYFRAME) 791 desc->key_frame = 1; 792 else 793 desc->key_frame = 0; 794 desc->luma_base = vpu_get_vb_phy_addr(vb, 0); 795 desc->chroma_base = vpu_get_vb_phy_addr(vb, 1); 796 797 return 0; 798 } 799 800 int vpu_windsor_input_frame(struct vpu_shared_addr *shared, 801 struct vpu_inst *inst, struct vb2_buffer *vb) 802 { 803 vpu_windsor_fill_yuv_frame(shared, inst->id, vb); 804 return vpu_session_encode_frame(inst, vb->timestamp); 805 } 806 807 int vpu_windsor_config_memory_resource(struct vpu_shared_addr *shared, 808 u32 instance, 809 u32 type, 810 u32 index, 811 struct vpu_buffer *buf) 812 { 813 struct vpu_enc_mem_pool *pool; 814 struct vpu_enc_memory_resource *res; 815 816 if (instance >= VID_API_NUM_STREAMS) 817 return -EINVAL; 818 819 pool = get_mem_pool(shared, instance); 820 821 switch (type) { 822 case MEM_RES_ENC: 823 res = &pool->enc_frames[index]; 824 break; 825 case MEM_RES_REF: 826 res = &pool->ref_frames[index]; 827 break; 828 case MEM_RES_ACT: 829 res = &pool->act_frame; 830 break; 831 default: 832 return -EINVAL; 833 } 834 835 res->phys = buf->phys; 836 res->virt = buf->phys - shared->boot_addr; 837 res->size = buf->length; 838 839 return 0; 840 } 841 842 int vpu_windsor_config_stream_buffer(struct vpu_shared_addr *shared, 843 u32 instance, 844 struct vpu_buffer *buf) 845 { 846 struct vpu_rpc_buffer_desc *desc; 847 struct vpu_enc_expert_mode_param *expert; 848 849 desc = get_stream_buf_desc(shared, instance); 850 expert = get_expert_param(shared, instance); 851 852 desc->start = buf->phys; 853 desc->wptr = buf->phys; 854 desc->rptr = buf->phys; 855 desc->end = buf->phys + buf->length; 856 857 expert->calib_param.mem_chunk_phys_addr = 0; 858 expert->calib_param.mem_chunk_virt_addr = 0; 859 expert->calib_param.mem_chunk_size = 0; 860 expert->calib_param.cb_base = buf->phys; 861 expert->calib_param.cb_size = buf->length; 862 863 return 0; 864 } 865 866 int vpu_windsor_update_stream_buffer(struct vpu_shared_addr *shared, 867 u32 instance, u32 ptr, bool write) 868 { 869 struct vpu_rpc_buffer_desc *desc; 870 871 desc = get_stream_buf_desc(shared, instance); 872 873 /*update wptr/rptr after data is written or read*/ 874 mb(); 875 if (write) 876 desc->wptr = ptr; 877 else 878 desc->rptr = ptr; 879 880 return 0; 881 } 882 883 int vpu_windsor_get_stream_buffer_desc(struct vpu_shared_addr *shared, 884 u32 instance, struct vpu_rpc_buffer_desc *desc) 885 { 886 struct vpu_rpc_buffer_desc *rpc_desc; 887 888 rpc_desc = get_stream_buf_desc(shared, instance); 889 if (desc) { 890 desc->wptr = get_ptr(rpc_desc->wptr); 891 desc->rptr = get_ptr(rpc_desc->rptr); 892 desc->start = get_ptr(rpc_desc->start); 893 desc->end = get_ptr(rpc_desc->end); 894 } 895 896 return 0; 897 } 898 899 u32 vpu_windsor_get_version(struct vpu_shared_addr *shared) 900 { 901 struct windsor_iface *iface = shared->iface; 902 903 return iface->fw_version; 904 } 905 906 static int vpu_windsor_set_frame_rate(struct vpu_enc_expert_mode_param *expert, 907 struct vpu_encode_params *params) 908 { 909 expert->config_param.frame_rate_num = params->frame_rate.numerator; 910 expert->config_param.frame_rate_den = params->frame_rate.denominator; 911 912 return 0; 913 } 914 915 static int vpu_windsor_set_format(struct vpu_enc_param *param, u32 pixelformat) 916 { 917 switch (pixelformat) { 918 case V4L2_PIX_FMT_H264: 919 param->codec_mode = MEDIAIP_ENC_FMT_H264; 920 break; 921 default: 922 return -EINVAL; 923 } 924 925 return 0; 926 } 927 928 static int vpu_windsor_set_profile(struct vpu_enc_param *param, u32 profile) 929 { 930 switch (profile) { 931 case V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE: 932 param->profile = MEDIAIP_ENC_PROF_H264_BP; 933 break; 934 case V4L2_MPEG_VIDEO_H264_PROFILE_MAIN: 935 param->profile = MEDIAIP_ENC_PROF_H264_MP; 936 break; 937 case V4L2_MPEG_VIDEO_H264_PROFILE_HIGH: 938 param->profile = MEDIAIP_ENC_PROF_H264_HP; 939 break; 940 default: 941 return -EINVAL; 942 } 943 944 return 0; 945 } 946 947 static const u32 h264_level[] = { 948 [V4L2_MPEG_VIDEO_H264_LEVEL_1_0] = 10, 949 [V4L2_MPEG_VIDEO_H264_LEVEL_1B] = 14, 950 [V4L2_MPEG_VIDEO_H264_LEVEL_1_1] = 11, 951 [V4L2_MPEG_VIDEO_H264_LEVEL_1_2] = 12, 952 [V4L2_MPEG_VIDEO_H264_LEVEL_1_3] = 13, 953 [V4L2_MPEG_VIDEO_H264_LEVEL_2_0] = 20, 954 [V4L2_MPEG_VIDEO_H264_LEVEL_2_1] = 21, 955 [V4L2_MPEG_VIDEO_H264_LEVEL_2_2] = 22, 956 [V4L2_MPEG_VIDEO_H264_LEVEL_3_0] = 30, 957 [V4L2_MPEG_VIDEO_H264_LEVEL_3_1] = 31, 958 [V4L2_MPEG_VIDEO_H264_LEVEL_3_2] = 32, 959 [V4L2_MPEG_VIDEO_H264_LEVEL_4_0] = 40, 960 [V4L2_MPEG_VIDEO_H264_LEVEL_4_1] = 41, 961 [V4L2_MPEG_VIDEO_H264_LEVEL_4_2] = 42, 962 [V4L2_MPEG_VIDEO_H264_LEVEL_5_0] = 50, 963 [V4L2_MPEG_VIDEO_H264_LEVEL_5_1] = 51 964 }; 965 966 static int vpu_windsor_set_level(struct vpu_enc_param *param, u32 level) 967 { 968 if (level >= ARRAY_SIZE(h264_level)) 969 return -EINVAL; 970 971 param->level = h264_level[level]; 972 973 return 0; 974 } 975 976 static int vpu_windsor_set_size(struct vpu_enc_param *windsor, 977 struct vpu_encode_params *params) 978 { 979 windsor->src_stride = params->src_stride; 980 windsor->src_width = params->src_width; 981 windsor->src_height = params->src_height; 982 windsor->src_offset_x = params->crop.left; 983 windsor->src_offset_y = params->crop.top; 984 windsor->src_crop_width = params->crop.width; 985 windsor->src_crop_height = params->crop.height; 986 windsor->out_width = params->out_width; 987 windsor->out_height = params->out_height; 988 989 return 0; 990 } 991 992 static int vpu_windsor_set_gop(struct vpu_enc_param *param, u32 gop) 993 { 994 param->iframe_interval = gop; 995 996 return 0; 997 } 998 999 static int vpu_windsor_set_bframes(struct vpu_enc_param *param, u32 bframes) 1000 { 1001 if (bframes) { 1002 param->low_latency_mode = 0; 1003 param->bframes = bframes; 1004 } else { 1005 param->low_latency_mode = 1; 1006 param->bframes = 0; 1007 } 1008 1009 return 0; 1010 } 1011 1012 static int vpu_windsor_set_bitrate_mode(struct vpu_enc_param *param, u32 rc_enable, u32 mode) 1013 { 1014 if (!rc_enable) 1015 param->bitrate_mode = MEDIAIP_ENC_BITRATE_MODE_CONSTANT_QP; 1016 else if (mode == V4L2_MPEG_VIDEO_BITRATE_MODE_VBR) 1017 param->bitrate_mode = MEDIAIP_ENC_BITRATE_MODE_VBR; 1018 else 1019 param->bitrate_mode = MEDIAIP_ENC_BITRATE_MODE_CBR; 1020 1021 return 0; 1022 } 1023 1024 static u32 vpu_windsor_bitrate(u32 bitrate) 1025 { 1026 return DIV_ROUND_CLOSEST(bitrate, WINDSOR_BITRATE_UNIT); 1027 } 1028 1029 static int vpu_windsor_set_bitrate(struct vpu_enc_param *windsor, 1030 struct vpu_encode_params *params) 1031 { 1032 windsor->target_bitrate = vpu_windsor_bitrate(params->bitrate); 1033 windsor->min_bitrate = vpu_windsor_bitrate(params->bitrate_min); 1034 windsor->max_bitrate = vpu_windsor_bitrate(params->bitrate_max); 1035 1036 return 0; 1037 } 1038 1039 static int vpu_windsor_set_qp(struct vpu_enc_expert_mode_param *expert, 1040 struct vpu_encode_params *params) 1041 { 1042 expert->static_param.rate_control_islice_qp = params->i_frame_qp; 1043 expert->static_param.rate_control_pslice_qp = params->p_frame_qp; 1044 expert->static_param.rate_control_bslice_qp = params->b_frame_qp; 1045 1046 return 0; 1047 } 1048 1049 static int vpu_windsor_set_sar(struct vpu_enc_expert_mode_param *expert, 1050 struct vpu_encode_params *params) 1051 { 1052 expert->config_param.h264_aspect_ratio_present = params->sar.enable; 1053 if (params->sar.idc == V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_EXTENDED) 1054 expert->config_param.aspect_ratio = WINDSOR_H264_EXTENDED_SAR; 1055 else 1056 expert->config_param.aspect_ratio = params->sar.idc; 1057 expert->config_param.h264_aspect_ratio_sar_width = params->sar.width; 1058 expert->config_param.h264_aspect_ratio_sar_height = params->sar.height; 1059 1060 return 0; 1061 } 1062 1063 static int vpu_windsor_set_color(struct vpu_enc_expert_mode_param *expert, 1064 struct vpu_encode_params *params) 1065 { 1066 expert->config_param.h264_video_type_present = 1; 1067 expert->config_param.h264_video_format = 5; 1068 expert->config_param.h264_video_colour_descriptor = 1; 1069 expert->config_param.h264_video_colour_primaries = 1070 vpu_color_cvrt_primaries_v2i(params->color.primaries); 1071 expert->config_param.h264_video_transfer_char = 1072 vpu_color_cvrt_transfers_v2i(params->color.transfer); 1073 expert->config_param.h264_video_matrix_coeff = 1074 vpu_color_cvrt_matrix_v2i(params->color.matrix); 1075 expert->config_param.h264_video_full_range = 1076 vpu_color_cvrt_full_range_v2i(params->color.full_range); 1077 return 0; 1078 } 1079 1080 static int vpu_windsor_update_bitrate(struct vpu_shared_addr *shared, 1081 u32 instance, struct vpu_encode_params *params) 1082 { 1083 struct vpu_enc_param *windsor; 1084 struct vpu_enc_expert_mode_param *expert; 1085 1086 windsor = get_enc_param(shared, instance); 1087 expert = get_expert_param(shared, instance); 1088 1089 if (windsor->bitrate_mode != MEDIAIP_ENC_BITRATE_MODE_CBR) 1090 return 0; 1091 if (!params->rc_enable) 1092 return 0; 1093 if (vpu_windsor_bitrate(params->bitrate) == windsor->target_bitrate) 1094 return 0; 1095 1096 vpu_windsor_set_bitrate(windsor, params); 1097 expert->static_param.rate_control_bitrate = windsor->target_bitrate; 1098 expert->static_param.rate_control_bitrate_min = windsor->min_bitrate; 1099 expert->static_param.rate_control_bitrate_max = windsor->max_bitrate; 1100 1101 return 0; 1102 } 1103 1104 static int vpu_windsor_set_params(struct vpu_shared_addr *shared, 1105 u32 instance, struct vpu_encode_params *params) 1106 { 1107 struct vpu_enc_param *windsor; 1108 int ret; 1109 1110 windsor = get_enc_param(shared, instance); 1111 1112 if (params->input_format != V4L2_PIX_FMT_NV12 && 1113 params->input_format != V4L2_PIX_FMT_NV12M) 1114 return -EINVAL; 1115 1116 ret = vpu_windsor_set_format(windsor, params->codec_format); 1117 if (ret) 1118 return ret; 1119 vpu_windsor_set_profile(windsor, params->profile); 1120 vpu_windsor_set_level(windsor, params->level); 1121 vpu_windsor_set_size(windsor, params); 1122 vpu_windsor_set_gop(windsor, params->gop_length); 1123 vpu_windsor_set_bframes(windsor, params->bframes); 1124 vpu_windsor_set_bitrate_mode(windsor, params->rc_enable, params->rc_mode); 1125 vpu_windsor_set_bitrate(windsor, params); 1126 windsor->init_slice_qp = params->i_frame_qp; 1127 1128 if (!params->frame_rate.numerator) 1129 return -EINVAL; 1130 windsor->frame_rate = params->frame_rate.denominator / params->frame_rate.numerator; 1131 1132 return 0; 1133 } 1134 1135 static int vpu_windsor_update_params(struct vpu_shared_addr *shared, 1136 u32 instance, struct vpu_encode_params *params) 1137 { 1138 struct vpu_enc_expert_mode_param *expert; 1139 1140 expert = get_expert_param(shared, instance); 1141 1142 vpu_windsor_set_frame_rate(expert, params); 1143 vpu_windsor_set_qp(expert, params); 1144 vpu_windsor_set_sar(expert, params); 1145 vpu_windsor_set_color(expert, params); 1146 vpu_windsor_update_bitrate(shared, instance, params); 1147 /*expert->config_param.iac_sc_threshold = 0;*/ 1148 1149 return 0; 1150 } 1151 1152 int vpu_windsor_set_encode_params(struct vpu_shared_addr *shared, 1153 u32 instance, struct vpu_encode_params *params, u32 update) 1154 { 1155 if (!params) 1156 return -EINVAL; 1157 1158 if (!update) 1159 return vpu_windsor_set_params(shared, instance, params); 1160 else 1161 return vpu_windsor_update_params(shared, instance, params); 1162 } 1163 1164 u32 vpu_windsor_get_max_instance_count(struct vpu_shared_addr *shared) 1165 { 1166 struct windsor_iface *iface = shared->iface; 1167 1168 return iface->max_streams; 1169 } 1170