1*61cbf1c1SMing Qian /* SPDX-License-Identifier: GPL-2.0 */ 2*61cbf1c1SMing Qian /* 3*61cbf1c1SMing Qian * Copyright 2020-2021 NXP 4*61cbf1c1SMing Qian */ 5*61cbf1c1SMing Qian 6*61cbf1c1SMing Qian #ifndef _AMPHION_VPU_MSGS_H 7*61cbf1c1SMing Qian #define _AMPHION_VPU_MSGS_H 8*61cbf1c1SMing Qian 9*61cbf1c1SMing Qian int vpu_isr(struct vpu_core *core, u32 irq); 10*61cbf1c1SMing Qian void vpu_inst_run_work(struct work_struct *work); 11*61cbf1c1SMing Qian void vpu_msg_run_work(struct work_struct *work); 12*61cbf1c1SMing Qian void vpu_msg_delayed_work(struct work_struct *work); 13*61cbf1c1SMing Qian 14*61cbf1c1SMing Qian #endif 15