1145e9363SMing Qian /* SPDX-License-Identifier: GPL-2.0 */ 2145e9363SMing Qian /* 3145e9363SMing Qian * Copyright 2020-2021 NXP 4145e9363SMing Qian */ 5145e9363SMing Qian 6145e9363SMing Qian #ifndef _AMPHION_VPU_MALONE_H 7145e9363SMing Qian #define _AMPHION_VPU_MALONE_H 8145e9363SMing Qian 9145e9363SMing Qian u32 vpu_malone_get_data_size(void); 10145e9363SMing Qian void vpu_malone_init_rpc(struct vpu_shared_addr *shared, 11145e9363SMing Qian struct vpu_buffer *rpc, dma_addr_t boot_addr); 12145e9363SMing Qian void vpu_malone_set_log_buf(struct vpu_shared_addr *shared, 13145e9363SMing Qian struct vpu_buffer *log); 14145e9363SMing Qian void vpu_malone_set_system_cfg(struct vpu_shared_addr *shared, 15145e9363SMing Qian u32 regs_base, void __iomem *regs, u32 core_id); 16145e9363SMing Qian u32 vpu_malone_get_version(struct vpu_shared_addr *shared); 17145e9363SMing Qian int vpu_malone_get_stream_buffer_size(struct vpu_shared_addr *shared); 18145e9363SMing Qian int vpu_malone_config_stream_buffer(struct vpu_shared_addr *shared, 19145e9363SMing Qian u32 instance, struct vpu_buffer *buf); 20145e9363SMing Qian int vpu_malone_get_stream_buffer_desc(struct vpu_shared_addr *shared, 21145e9363SMing Qian u32 instance, 22145e9363SMing Qian struct vpu_rpc_buffer_desc *desc); 23145e9363SMing Qian int vpu_malone_update_stream_buffer(struct vpu_shared_addr *shared, 24145e9363SMing Qian u32 instance, u32 ptr, bool write); 25145e9363SMing Qian int vpu_malone_set_decode_params(struct vpu_shared_addr *shared, 26145e9363SMing Qian u32 instance, 27145e9363SMing Qian struct vpu_decode_params *params, u32 update); 28145e9363SMing Qian int vpu_malone_pack_cmd(struct vpu_rpc_event *pkt, u32 index, u32 id, void *data); 29145e9363SMing Qian int vpu_malone_convert_msg_id(u32 msg_id); 30145e9363SMing Qian int vpu_malone_unpack_msg_data(struct vpu_rpc_event *pkt, void *data); 31145e9363SMing Qian int vpu_malone_add_scode(struct vpu_shared_addr *shared, 32145e9363SMing Qian u32 instance, 33145e9363SMing Qian struct vpu_buffer *stream_buffer, 34145e9363SMing Qian u32 pixelformat, 35145e9363SMing Qian u32 scode_type); 36145e9363SMing Qian int vpu_malone_input_frame(struct vpu_shared_addr *shared, 37145e9363SMing Qian struct vpu_inst *inst, struct vb2_buffer *vb); 38145e9363SMing Qian bool vpu_malone_is_ready(struct vpu_shared_addr *shared, u32 instance); 39145e9363SMing Qian int vpu_malone_pre_cmd(struct vpu_shared_addr *shared, u32 instance); 40145e9363SMing Qian int vpu_malone_post_cmd(struct vpu_shared_addr *shared, u32 instance); 41145e9363SMing Qian int vpu_malone_init_instance(struct vpu_shared_addr *shared, u32 instance); 42145e9363SMing Qian u32 vpu_malone_get_max_instance_count(struct vpu_shared_addr *shared); 43ded5c4faSMing Qian bool vpu_malone_check_fmt(enum vpu_core_type type, u32 pixelfmt); 44*3b514e79SMing Qian void vpu_malone_enable_format(u32 pixelformat, int enable); 45145e9363SMing Qian 46145e9363SMing Qian #endif 47