1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright 2020-2021 NXP 4 */ 5 6 #include <linux/init.h> 7 #include <linux/interconnect.h> 8 #include <linux/ioctl.h> 9 #include <linux/list.h> 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/of_device.h> 13 #include <linux/of_address.h> 14 #include <linux/platform_device.h> 15 #include <linux/delay.h> 16 #include <linux/rational.h> 17 #include <linux/time64.h> 18 #include <media/videobuf2-v4l2.h> 19 #include <media/videobuf2-dma-contig.h> 20 #include <linux/videodev2.h> 21 #include "vpu.h" 22 #include "vpu_rpc.h" 23 #include "vpu_defs.h" 24 #include "vpu_helpers.h" 25 #include "vpu_v4l2.h" 26 #include "vpu_cmds.h" 27 #include "vpu_imx8q.h" 28 #include "vpu_malone.h" 29 30 #define CMD_SIZE 25600 31 #define MSG_SIZE 25600 32 #define CODEC_SIZE 0x1000 33 #define JPEG_SIZE 0x1000 34 #define SEQ_SIZE 0x1000 35 #define GOP_SIZE 0x1000 36 #define PIC_SIZE 0x1000 37 #define QMETER_SIZE 0x1000 38 #define DBGLOG_SIZE 0x10000 39 #define DEBUG_SIZE 0x80000 40 #define ENG_SIZE 0x1000 41 #define MALONE_SKIPPED_FRAME_ID 0x555 42 43 #define MALONE_ALIGN_MBI 0x800 44 #define MALONE_DCP_CHUNK_BIT 16 45 #define MALONE_DCP_SIZE_MAX 0x3000000 46 #define MALONE_DCP_SIZE_MIN 0x100000 47 #define MALONE_DCP_FIXED_MB_ALLOC 250 48 49 #define CONFIG_SET(val, cfg, pos, mask) \ 50 (*(cfg) |= (((val) << (pos)) & (mask))) 51 //x means source data , y means destination data 52 #define STREAM_CONFIG_FORMAT_SET(x, y) CONFIG_SET(x, y, 0, 0x0000000F) 53 #define STREAM_CONFIG_STRBUFIDX_SET(x, y) CONFIG_SET(x, y, 8, 0x00000300) 54 #define STREAM_CONFIG_NOSEQ_SET(x, y) CONFIG_SET(x, y, 10, 0x00000400) 55 #define STREAM_CONFIG_DEBLOCK_SET(x, y) CONFIG_SET(x, y, 11, 0x00000800) 56 #define STREAM_CONFIG_DERING_SET(x, y) CONFIG_SET(x, y, 12, 0x00001000) 57 #define STREAM_CONFIG_IBWAIT_SET(x, y) CONFIG_SET(x, y, 13, 0x00002000) 58 #define STREAM_CONFIG_FBC_SET(x, y) CONFIG_SET(x, y, 14, 0x00004000) 59 #define STREAM_CONFIG_PLAY_MODE_SET(x, y) CONFIG_SET(x, y, 16, 0x00030000) 60 #define STREAM_CONFIG_ENABLE_DCP_SET(x, y) CONFIG_SET(x, y, 20, 0x00100000) 61 #define STREAM_CONFIG_NUM_STR_BUF_SET(x, y) CONFIG_SET(x, y, 21, 0x00600000) 62 #define STREAM_CONFIG_MALONE_USAGE_SET(x, y) CONFIG_SET(x, y, 23, 0x01800000) 63 #define STREAM_CONFIG_MULTI_VID_SET(x, y) CONFIG_SET(x, y, 25, 0x02000000) 64 #define STREAM_CONFIG_OBFUSC_EN_SET(x, y) CONFIG_SET(x, y, 26, 0x04000000) 65 #define STREAM_CONFIG_RC4_EN_SET(x, y) CONFIG_SET(x, y, 27, 0x08000000) 66 #define STREAM_CONFIG_MCX_SET(x, y) CONFIG_SET(x, y, 28, 0x10000000) 67 #define STREAM_CONFIG_PES_SET(x, y) CONFIG_SET(x, y, 29, 0x20000000) 68 #define STREAM_CONFIG_NUM_DBE_SET(x, y) CONFIG_SET(x, y, 30, 0x40000000) 69 #define STREAM_CONFIG_FS_CTRL_MODE_SET(x, y) CONFIG_SET(x, y, 31, 0x80000000) 70 71 #define MALONE_DEC_FMT_RV_MASK BIT(21) 72 73 enum vpu_malone_stream_input_mode { 74 INVALID_MODE = 0, 75 FRAME_LVL, 76 NON_FRAME_LVL 77 }; 78 79 enum vpu_malone_format { 80 MALONE_FMT_NULL = 0x0, 81 MALONE_FMT_AVC = 0x1, 82 MALONE_FMT_MP2 = 0x2, 83 MALONE_FMT_VC1 = 0x3, 84 MALONE_FMT_AVS = 0x4, 85 MALONE_FMT_ASP = 0x5, 86 MALONE_FMT_JPG = 0x6, 87 MALONE_FMT_RV = 0x7, 88 MALONE_FMT_VP6 = 0x8, 89 MALONE_FMT_SPK = 0x9, 90 MALONE_FMT_VP8 = 0xA, 91 MALONE_FMT_HEVC = 0xB, 92 MALONE_FMT_LAST = MALONE_FMT_HEVC 93 }; 94 95 enum { 96 VID_API_CMD_NULL = 0x00, 97 VID_API_CMD_PARSE_NEXT_SEQ = 0x01, 98 VID_API_CMD_PARSE_NEXT_I = 0x02, 99 VID_API_CMD_PARSE_NEXT_IP = 0x03, 100 VID_API_CMD_PARSE_NEXT_ANY = 0x04, 101 VID_API_CMD_DEC_PIC = 0x05, 102 VID_API_CMD_UPDATE_ES_WR_PTR = 0x06, 103 VID_API_CMD_UPDATE_ES_RD_PTR = 0x07, 104 VID_API_CMD_UPDATE_UDATA = 0x08, 105 VID_API_CMD_GET_FSINFO = 0x09, 106 VID_API_CMD_SKIP_PIC = 0x0a, 107 VID_API_CMD_DEC_CHUNK = 0x0b, 108 VID_API_CMD_START = 0x10, 109 VID_API_CMD_STOP = 0x11, 110 VID_API_CMD_ABORT = 0x12, 111 VID_API_CMD_RST_BUF = 0x13, 112 VID_API_CMD_FS_RELEASE = 0x15, 113 VID_API_CMD_MEM_REGION_ATTACH = 0x16, 114 VID_API_CMD_MEM_REGION_DETACH = 0x17, 115 VID_API_CMD_MVC_VIEW_SELECT = 0x18, 116 VID_API_CMD_FS_ALLOC = 0x19, 117 VID_API_CMD_DBG_GET_STATUS = 0x1C, 118 VID_API_CMD_DBG_START_LOG = 0x1D, 119 VID_API_CMD_DBG_STOP_LOG = 0x1E, 120 VID_API_CMD_DBG_DUMP_LOG = 0x1F, 121 VID_API_CMD_YUV_READY = 0x20, 122 VID_API_CMD_TS = 0x21, 123 124 VID_API_CMD_FIRM_RESET = 0x40, 125 126 VID_API_CMD_SNAPSHOT = 0xAA, 127 VID_API_CMD_ROLL_SNAPSHOT = 0xAB, 128 VID_API_CMD_LOCK_SCHEDULER = 0xAC, 129 VID_API_CMD_UNLOCK_SCHEDULER = 0xAD, 130 VID_API_CMD_CQ_FIFO_DUMP = 0xAE, 131 VID_API_CMD_DBG_FIFO_DUMP = 0xAF, 132 VID_API_CMD_SVC_ILP = 0xBB, 133 VID_API_CMD_FW_STATUS = 0xF0, 134 VID_API_CMD_INVALID = 0xFF 135 }; 136 137 enum { 138 VID_API_EVENT_NULL = 0x00, 139 VID_API_EVENT_RESET_DONE = 0x01, 140 VID_API_EVENT_SEQ_HDR_FOUND = 0x02, 141 VID_API_EVENT_PIC_HDR_FOUND = 0x03, 142 VID_API_EVENT_PIC_DECODED = 0x04, 143 VID_API_EVENT_FIFO_LOW = 0x05, 144 VID_API_EVENT_FIFO_HIGH = 0x06, 145 VID_API_EVENT_FIFO_EMPTY = 0x07, 146 VID_API_EVENT_FIFO_FULL = 0x08, 147 VID_API_EVENT_BS_ERROR = 0x09, 148 VID_API_EVENT_UDATA_FIFO_UPTD = 0x0A, 149 VID_API_EVENT_RES_CHANGE = 0x0B, 150 VID_API_EVENT_FIFO_OVF = 0x0C, 151 VID_API_EVENT_CHUNK_DECODED = 0x0D, 152 VID_API_EVENT_REQ_FRAME_BUFF = 0x10, 153 VID_API_EVENT_FRAME_BUFF_RDY = 0x11, 154 VID_API_EVENT_REL_FRAME_BUFF = 0x12, 155 VID_API_EVENT_STR_BUF_RST = 0x13, 156 VID_API_EVENT_RET_PING = 0x14, 157 VID_API_EVENT_QMETER = 0x15, 158 VID_API_EVENT_STR_FMT_CHANGE = 0x16, 159 VID_API_EVENT_FIRMWARE_XCPT = 0x17, 160 VID_API_EVENT_START_DONE = 0x18, 161 VID_API_EVENT_STOPPED = 0x19, 162 VID_API_EVENT_ABORT_DONE = 0x1A, 163 VID_API_EVENT_FINISHED = 0x1B, 164 VID_API_EVENT_DBG_STAT_UPDATE = 0x1C, 165 VID_API_EVENT_DBG_LOG_STARTED = 0x1D, 166 VID_API_EVENT_DBG_LOG_STOPPED = 0x1E, 167 VID_API_EVENT_DBG_LOG_UPDATED = 0x1F, 168 VID_API_EVENT_DBG_MSG_DEC = 0x20, 169 VID_API_EVENT_DEC_SC_ERR = 0x21, 170 VID_API_EVENT_CQ_FIFO_DUMP = 0x22, 171 VID_API_EVENT_DBG_FIFO_DUMP = 0x23, 172 VID_API_EVENT_DEC_CHECK_RES = 0x24, 173 VID_API_EVENT_DEC_CFG_INFO = 0x25, 174 VID_API_EVENT_UNSUPPORTED_STREAM = 0x26, 175 VID_API_EVENT_PIC_SKIPPED = 0x27, 176 VID_API_EVENT_STR_SUSPENDED = 0x30, 177 VID_API_EVENT_SNAPSHOT_DONE = 0x40, 178 VID_API_EVENT_FW_STATUS = 0xF0, 179 VID_API_EVENT_INVALID = 0xFF 180 }; 181 182 struct vpu_malone_buffer_desc { 183 struct vpu_rpc_buffer_desc buffer; 184 u32 low; 185 u32 high; 186 }; 187 188 struct vpu_malone_str_buffer { 189 u32 wptr; 190 u32 rptr; 191 u32 start; 192 u32 end; 193 u32 lwm; 194 }; 195 196 struct vpu_malone_picth_info { 197 u32 frame_pitch; 198 }; 199 200 struct vpu_malone_table_desc { 201 u32 array_base; 202 u32 size; 203 }; 204 205 struct vpu_malone_dbglog_desc { 206 u32 addr; 207 u32 size; 208 u32 level; 209 u32 reserved; 210 }; 211 212 struct vpu_malone_frame_buffer { 213 u32 addr; 214 u32 size; 215 }; 216 217 struct vpu_malone_udata { 218 u32 base; 219 u32 total_size; 220 u32 slot_size; 221 }; 222 223 struct vpu_malone_buffer_info { 224 u32 stream_input_mode; 225 u32 stream_pic_input_count; 226 u32 stream_pic_parsed_count; 227 u32 stream_buffer_threshold; 228 u32 stream_pic_end_flag; 229 }; 230 231 struct vpu_malone_encrypt_info { 232 u32 rec4key[8]; 233 u32 obfusc; 234 }; 235 236 struct malone_iface { 237 u32 exec_base_addr; 238 u32 exec_area_size; 239 struct vpu_malone_buffer_desc cmd_buffer_desc; 240 struct vpu_malone_buffer_desc msg_buffer_desc; 241 u32 cmd_int_enable[VID_API_NUM_STREAMS]; 242 struct vpu_malone_picth_info stream_pitch_info[VID_API_NUM_STREAMS]; 243 u32 stream_config[VID_API_NUM_STREAMS]; 244 struct vpu_malone_table_desc codec_param_tab_desc; 245 struct vpu_malone_table_desc jpeg_param_tab_desc; 246 u32 stream_buffer_desc[VID_API_NUM_STREAMS][VID_API_MAX_BUF_PER_STR]; 247 struct vpu_malone_table_desc seq_info_tab_desc; 248 struct vpu_malone_table_desc pic_info_tab_desc; 249 struct vpu_malone_table_desc gop_info_tab_desc; 250 struct vpu_malone_table_desc qmeter_info_tab_desc; 251 u32 stream_error[VID_API_NUM_STREAMS]; 252 u32 fw_version; 253 u32 fw_offset; 254 u32 max_streams; 255 struct vpu_malone_dbglog_desc dbglog_desc; 256 struct vpu_rpc_buffer_desc api_cmd_buffer_desc[VID_API_NUM_STREAMS]; 257 struct vpu_malone_udata udata_buffer[VID_API_NUM_STREAMS]; 258 struct vpu_malone_buffer_desc debug_buffer_desc; 259 struct vpu_malone_buffer_desc eng_access_buff_desc[VID_API_NUM_STREAMS]; 260 u32 encrypt_info[VID_API_NUM_STREAMS]; 261 struct vpu_rpc_system_config system_cfg; 262 u32 api_version; 263 struct vpu_malone_buffer_info stream_buff_info[VID_API_NUM_STREAMS]; 264 }; 265 266 struct malone_jpg_params { 267 u32 rotation_angle; 268 u32 horiz_scale_factor; 269 u32 vert_scale_factor; 270 u32 rotation_mode; 271 u32 rgb_mode; 272 u32 chunk_mode; /* 0 ~ 1 */ 273 u32 last_chunk; /* 0 ~ 1 */ 274 u32 chunk_rows; /* 0 ~ 255 */ 275 u32 num_bytes; 276 u32 jpg_crop_x; 277 u32 jpg_crop_y; 278 u32 jpg_crop_width; 279 u32 jpg_crop_height; 280 u32 jpg_mjpeg_mode; 281 u32 jpg_mjpeg_interlaced; 282 }; 283 284 struct malone_codec_params { 285 u32 disp_imm; 286 u32 fourcc; 287 u32 codec_version; 288 u32 frame_rate; 289 u32 dbglog_enable; 290 u32 bsdma_lwm; 291 u32 bbd_coring; 292 u32 bbd_s_thr_row; 293 u32 bbd_p_thr_row; 294 u32 bbd_s_thr_logo_row; 295 u32 bbd_p_thr_logo_row; 296 u32 bbd_s_thr_col; 297 u32 bbd_p_thr_col; 298 u32 bbd_chr_thr_row; 299 u32 bbd_chr_thr_col; 300 u32 bbd_uv_mid_level; 301 u32 bbd_excl_win_mb_left; 302 u32 bbd_excl_win_mb_right; 303 }; 304 305 struct malone_padding_scode { 306 u32 scode_type; 307 u32 pixelformat; 308 u32 data[2]; 309 }; 310 311 struct malone_fmt_mapping { 312 u32 pixelformat; 313 enum vpu_malone_format malone_format; 314 u32 is_disabled; 315 }; 316 317 struct malone_scode_t { 318 struct vpu_inst *inst; 319 struct vb2_buffer *vb; 320 u32 wptr; 321 u32 need_data; 322 }; 323 324 struct malone_scode_handler { 325 u32 pixelformat; 326 int (*insert_scode_seq)(struct malone_scode_t *scode); 327 int (*insert_scode_pic)(struct malone_scode_t *scode); 328 }; 329 330 struct vpu_dec_ctrl { 331 struct malone_codec_params *codec_param; 332 struct malone_jpg_params *jpg; 333 void *seq_mem; 334 void *pic_mem; 335 void *gop_mem; 336 void *qmeter_mem; 337 void *dbglog_mem; 338 struct vpu_malone_str_buffer __iomem *str_buf[VID_API_NUM_STREAMS]; 339 u32 buf_addr[VID_API_NUM_STREAMS]; 340 }; 341 342 u32 vpu_malone_get_data_size(void) 343 { 344 return sizeof(struct vpu_dec_ctrl); 345 } 346 347 void vpu_malone_init_rpc(struct vpu_shared_addr *shared, 348 struct vpu_buffer *rpc, dma_addr_t boot_addr) 349 { 350 struct malone_iface *iface; 351 struct vpu_dec_ctrl *hc; 352 unsigned long base_phy_addr; 353 unsigned long phy_addr; 354 unsigned long offset; 355 unsigned int i; 356 357 if (rpc->phys < boot_addr) 358 return; 359 360 iface = rpc->virt; 361 base_phy_addr = rpc->phys - boot_addr; 362 hc = shared->priv; 363 364 shared->iface = iface; 365 shared->boot_addr = boot_addr; 366 367 iface->exec_base_addr = base_phy_addr; 368 iface->exec_area_size = rpc->length; 369 370 offset = sizeof(struct malone_iface); 371 phy_addr = base_phy_addr + offset; 372 373 shared->cmd_desc = &iface->cmd_buffer_desc.buffer; 374 shared->cmd_mem_vir = rpc->virt + offset; 375 iface->cmd_buffer_desc.buffer.start = 376 iface->cmd_buffer_desc.buffer.rptr = 377 iface->cmd_buffer_desc.buffer.wptr = phy_addr; 378 iface->cmd_buffer_desc.buffer.end = iface->cmd_buffer_desc.buffer.start + CMD_SIZE; 379 offset += CMD_SIZE; 380 phy_addr = base_phy_addr + offset; 381 382 shared->msg_desc = &iface->msg_buffer_desc.buffer; 383 shared->msg_mem_vir = rpc->virt + offset; 384 iface->msg_buffer_desc.buffer.start = 385 iface->msg_buffer_desc.buffer.wptr = 386 iface->msg_buffer_desc.buffer.rptr = phy_addr; 387 iface->msg_buffer_desc.buffer.end = iface->msg_buffer_desc.buffer.start + MSG_SIZE; 388 offset += MSG_SIZE; 389 phy_addr = base_phy_addr + offset; 390 391 iface->codec_param_tab_desc.array_base = phy_addr; 392 hc->codec_param = rpc->virt + offset; 393 offset += CODEC_SIZE; 394 phy_addr = base_phy_addr + offset; 395 396 iface->jpeg_param_tab_desc.array_base = phy_addr; 397 hc->jpg = rpc->virt + offset; 398 offset += JPEG_SIZE; 399 phy_addr = base_phy_addr + offset; 400 401 iface->seq_info_tab_desc.array_base = phy_addr; 402 hc->seq_mem = rpc->virt + offset; 403 offset += SEQ_SIZE; 404 phy_addr = base_phy_addr + offset; 405 406 iface->pic_info_tab_desc.array_base = phy_addr; 407 hc->pic_mem = rpc->virt + offset; 408 offset += PIC_SIZE; 409 phy_addr = base_phy_addr + offset; 410 411 iface->gop_info_tab_desc.array_base = phy_addr; 412 hc->gop_mem = rpc->virt + offset; 413 offset += GOP_SIZE; 414 phy_addr = base_phy_addr + offset; 415 416 iface->qmeter_info_tab_desc.array_base = phy_addr; 417 hc->qmeter_mem = rpc->virt + offset; 418 offset += QMETER_SIZE; 419 phy_addr = base_phy_addr + offset; 420 421 iface->dbglog_desc.addr = phy_addr; 422 iface->dbglog_desc.size = DBGLOG_SIZE; 423 hc->dbglog_mem = rpc->virt + offset; 424 offset += DBGLOG_SIZE; 425 phy_addr = base_phy_addr + offset; 426 427 for (i = 0; i < VID_API_NUM_STREAMS; i++) { 428 iface->eng_access_buff_desc[i].buffer.start = 429 iface->eng_access_buff_desc[i].buffer.wptr = 430 iface->eng_access_buff_desc[i].buffer.rptr = phy_addr; 431 iface->eng_access_buff_desc[i].buffer.end = 432 iface->eng_access_buff_desc[i].buffer.start + ENG_SIZE; 433 offset += ENG_SIZE; 434 phy_addr = base_phy_addr + offset; 435 } 436 437 for (i = 0; i < VID_API_NUM_STREAMS; i++) { 438 iface->encrypt_info[i] = phy_addr; 439 offset += sizeof(struct vpu_malone_encrypt_info); 440 phy_addr = base_phy_addr + offset; 441 } 442 443 rpc->bytesused = offset; 444 } 445 446 void vpu_malone_set_log_buf(struct vpu_shared_addr *shared, 447 struct vpu_buffer *log) 448 { 449 struct malone_iface *iface = shared->iface; 450 451 iface->debug_buffer_desc.buffer.start = 452 iface->debug_buffer_desc.buffer.wptr = 453 iface->debug_buffer_desc.buffer.rptr = log->phys - shared->boot_addr; 454 iface->debug_buffer_desc.buffer.end = iface->debug_buffer_desc.buffer.start + log->length; 455 } 456 457 static u32 get_str_buffer_offset(u32 instance) 458 { 459 return DEC_MFD_XREG_SLV_BASE + MFD_MCX + MFD_MCX_OFF * instance; 460 } 461 462 void vpu_malone_set_system_cfg(struct vpu_shared_addr *shared, 463 u32 regs_base, void __iomem *regs, u32 core_id) 464 { 465 struct malone_iface *iface = shared->iface; 466 struct vpu_rpc_system_config *config = &iface->system_cfg; 467 struct vpu_dec_ctrl *hc = shared->priv; 468 int i; 469 470 vpu_imx8q_set_system_cfg_common(config, regs_base, core_id); 471 for (i = 0; i < VID_API_NUM_STREAMS; i++) { 472 u32 offset = get_str_buffer_offset(i); 473 474 hc->buf_addr[i] = regs_base + offset; 475 hc->str_buf[i] = regs + offset; 476 } 477 } 478 479 u32 vpu_malone_get_version(struct vpu_shared_addr *shared) 480 { 481 struct malone_iface *iface = shared->iface; 482 483 vpu_malone_enable_format(V4L2_PIX_FMT_RV30, iface->fw_version & MALONE_DEC_FMT_RV_MASK); 484 vpu_malone_enable_format(V4L2_PIX_FMT_RV40, iface->fw_version & MALONE_DEC_FMT_RV_MASK); 485 486 return iface->fw_version; 487 } 488 489 int vpu_malone_get_stream_buffer_size(struct vpu_shared_addr *shared) 490 { 491 return 0xc00000; 492 } 493 494 int vpu_malone_config_stream_buffer(struct vpu_shared_addr *shared, 495 u32 instance, 496 struct vpu_buffer *buf) 497 { 498 struct malone_iface *iface = shared->iface; 499 struct vpu_dec_ctrl *hc = shared->priv; 500 struct vpu_malone_str_buffer __iomem *str_buf = hc->str_buf[instance]; 501 502 writel(buf->phys, &str_buf->start); 503 writel(buf->phys, &str_buf->rptr); 504 writel(buf->phys, &str_buf->wptr); 505 writel(buf->phys + buf->length, &str_buf->end); 506 writel(0x1, &str_buf->lwm); 507 508 iface->stream_buffer_desc[instance][0] = hc->buf_addr[instance]; 509 510 return 0; 511 } 512 513 int vpu_malone_get_stream_buffer_desc(struct vpu_shared_addr *shared, 514 u32 instance, 515 struct vpu_rpc_buffer_desc *desc) 516 { 517 struct vpu_dec_ctrl *hc = shared->priv; 518 struct vpu_malone_str_buffer __iomem *str_buf = hc->str_buf[instance]; 519 520 if (desc) { 521 desc->wptr = readl(&str_buf->wptr); 522 desc->rptr = readl(&str_buf->rptr); 523 desc->start = readl(&str_buf->start); 524 desc->end = readl(&str_buf->end); 525 } 526 527 return 0; 528 } 529 530 static void vpu_malone_update_wptr(struct vpu_malone_str_buffer __iomem *str_buf, u32 wptr) 531 { 532 /*update wptr after data is written*/ 533 mb(); 534 writel(wptr, &str_buf->wptr); 535 } 536 537 static void vpu_malone_update_rptr(struct vpu_malone_str_buffer __iomem *str_buf, u32 rptr) 538 { 539 /*update rptr after data is read*/ 540 mb(); 541 writel(rptr, &str_buf->rptr); 542 } 543 544 int vpu_malone_update_stream_buffer(struct vpu_shared_addr *shared, 545 u32 instance, u32 ptr, bool write) 546 { 547 struct vpu_dec_ctrl *hc = shared->priv; 548 struct vpu_malone_str_buffer __iomem *str_buf = hc->str_buf[instance]; 549 550 if (write) 551 vpu_malone_update_wptr(str_buf, ptr); 552 else 553 vpu_malone_update_rptr(str_buf, ptr); 554 555 return 0; 556 } 557 558 static struct malone_fmt_mapping fmt_mappings[] = { 559 {V4L2_PIX_FMT_H264, MALONE_FMT_AVC}, 560 {V4L2_PIX_FMT_H264_MVC, MALONE_FMT_AVC}, 561 {V4L2_PIX_FMT_HEVC, MALONE_FMT_HEVC}, 562 {V4L2_PIX_FMT_VC1_ANNEX_G, MALONE_FMT_VC1}, 563 {V4L2_PIX_FMT_VC1_ANNEX_L, MALONE_FMT_VC1}, 564 {V4L2_PIX_FMT_MPEG2, MALONE_FMT_MP2}, 565 {V4L2_PIX_FMT_MPEG4, MALONE_FMT_ASP}, 566 {V4L2_PIX_FMT_XVID, MALONE_FMT_ASP}, 567 {V4L2_PIX_FMT_H263, MALONE_FMT_ASP}, 568 {V4L2_PIX_FMT_JPEG, MALONE_FMT_JPG}, 569 {V4L2_PIX_FMT_VP8, MALONE_FMT_VP8}, 570 {V4L2_PIX_FMT_SPK, MALONE_FMT_SPK}, 571 {V4L2_PIX_FMT_RV30, MALONE_FMT_RV}, 572 {V4L2_PIX_FMT_RV40, MALONE_FMT_RV}, 573 }; 574 575 void vpu_malone_enable_format(u32 pixelformat, int enable) 576 { 577 u32 i; 578 579 for (i = 0; i < ARRAY_SIZE(fmt_mappings); i++) { 580 if (pixelformat == fmt_mappings[i].pixelformat) { 581 fmt_mappings[i].is_disabled = enable ? 0 : 1; 582 return; 583 } 584 } 585 } 586 587 static enum vpu_malone_format vpu_malone_format_remap(u32 pixelformat) 588 { 589 u32 i; 590 591 for (i = 0; i < ARRAY_SIZE(fmt_mappings); i++) { 592 if (fmt_mappings[i].is_disabled) 593 continue; 594 if (pixelformat == fmt_mappings[i].pixelformat) 595 return fmt_mappings[i].malone_format; 596 } 597 598 return MALONE_FMT_NULL; 599 } 600 601 bool vpu_malone_check_fmt(enum vpu_core_type type, u32 pixelfmt) 602 { 603 if (!vpu_imx8q_check_fmt(type, pixelfmt)) 604 return false; 605 606 if (pixelfmt == V4L2_PIX_FMT_NV12_8L128 || pixelfmt == V4L2_PIX_FMT_NV12_10BE_8L128 || 607 pixelfmt == V4L2_PIX_FMT_NV12M_8L128 || pixelfmt == V4L2_PIX_FMT_NV12M_10BE_8L128) 608 return true; 609 if (vpu_malone_format_remap(pixelfmt) == MALONE_FMT_NULL) 610 return false; 611 612 return true; 613 } 614 615 static void vpu_malone_set_stream_cfg(struct vpu_shared_addr *shared, 616 u32 instance, 617 enum vpu_malone_format malone_format) 618 { 619 struct malone_iface *iface = shared->iface; 620 u32 *curr_str_cfg = &iface->stream_config[instance]; 621 622 *curr_str_cfg = 0; 623 STREAM_CONFIG_FORMAT_SET(malone_format, curr_str_cfg); 624 STREAM_CONFIG_STRBUFIDX_SET(0, curr_str_cfg); 625 STREAM_CONFIG_NOSEQ_SET(0, curr_str_cfg); 626 STREAM_CONFIG_DEBLOCK_SET(0, curr_str_cfg); 627 STREAM_CONFIG_DERING_SET(0, curr_str_cfg); 628 STREAM_CONFIG_PLAY_MODE_SET(0x3, curr_str_cfg); 629 STREAM_CONFIG_FS_CTRL_MODE_SET(0x1, curr_str_cfg); 630 STREAM_CONFIG_ENABLE_DCP_SET(1, curr_str_cfg); 631 STREAM_CONFIG_NUM_STR_BUF_SET(1, curr_str_cfg); 632 STREAM_CONFIG_MALONE_USAGE_SET(1, curr_str_cfg); 633 STREAM_CONFIG_MULTI_VID_SET(0, curr_str_cfg); 634 STREAM_CONFIG_OBFUSC_EN_SET(0, curr_str_cfg); 635 STREAM_CONFIG_RC4_EN_SET(0, curr_str_cfg); 636 STREAM_CONFIG_MCX_SET(1, curr_str_cfg); 637 STREAM_CONFIG_PES_SET(0, curr_str_cfg); 638 STREAM_CONFIG_NUM_DBE_SET(1, curr_str_cfg); 639 } 640 641 static int vpu_malone_set_params(struct vpu_shared_addr *shared, 642 u32 instance, 643 struct vpu_decode_params *params) 644 { 645 struct malone_iface *iface = shared->iface; 646 struct vpu_dec_ctrl *hc = shared->priv; 647 enum vpu_malone_format malone_format; 648 649 malone_format = vpu_malone_format_remap(params->codec_format); 650 if (WARN_ON(malone_format == MALONE_FMT_NULL)) 651 return -EINVAL; 652 iface->udata_buffer[instance].base = params->udata.base; 653 iface->udata_buffer[instance].slot_size = params->udata.size; 654 655 vpu_malone_set_stream_cfg(shared, instance, malone_format); 656 657 if (malone_format == MALONE_FMT_JPG) { 658 //1:JPGD_MJPEG_MODE_A; 2:JPGD_MJPEG_MODE_B 659 hc->jpg[instance].jpg_mjpeg_mode = 1; 660 //0: JPGD_MJPEG_PROGRESSIVE 661 hc->jpg[instance].jpg_mjpeg_interlaced = 0; 662 } 663 664 hc->codec_param[instance].disp_imm = params->display_delay_enable ? 1 : 0; 665 if (malone_format != MALONE_FMT_AVC) 666 hc->codec_param[instance].disp_imm = 0; 667 hc->codec_param[instance].dbglog_enable = 0; 668 iface->dbglog_desc.level = 0; 669 670 if (params->b_non_frame) 671 iface->stream_buff_info[instance].stream_input_mode = NON_FRAME_LVL; 672 else 673 iface->stream_buff_info[instance].stream_input_mode = FRAME_LVL; 674 iface->stream_buff_info[instance].stream_buffer_threshold = 0; 675 iface->stream_buff_info[instance].stream_pic_input_count = 0; 676 677 return 0; 678 } 679 680 static bool vpu_malone_is_non_frame_mode(struct vpu_shared_addr *shared, u32 instance) 681 { 682 struct malone_iface *iface = shared->iface; 683 684 if (iface->stream_buff_info[instance].stream_input_mode == NON_FRAME_LVL) 685 return true; 686 687 return false; 688 } 689 690 static int vpu_malone_update_params(struct vpu_shared_addr *shared, 691 u32 instance, 692 struct vpu_decode_params *params) 693 { 694 struct malone_iface *iface = shared->iface; 695 696 if (params->end_flag) 697 iface->stream_buff_info[instance].stream_pic_end_flag = params->end_flag; 698 params->end_flag = 0; 699 700 return 0; 701 } 702 703 int vpu_malone_set_decode_params(struct vpu_shared_addr *shared, 704 u32 instance, 705 struct vpu_decode_params *params, 706 u32 update) 707 { 708 if (!params) 709 return -EINVAL; 710 711 if (!update) 712 return vpu_malone_set_params(shared, instance, params); 713 else 714 return vpu_malone_update_params(shared, instance, params); 715 } 716 717 static struct vpu_pair malone_cmds[] = { 718 {VPU_CMD_ID_NOOP, VID_API_CMD_NULL}, 719 {VPU_CMD_ID_START, VID_API_CMD_START}, 720 {VPU_CMD_ID_STOP, VID_API_CMD_STOP}, 721 {VPU_CMD_ID_ABORT, VID_API_CMD_ABORT}, 722 {VPU_CMD_ID_RST_BUF, VID_API_CMD_RST_BUF}, 723 {VPU_CMD_ID_SNAPSHOT, VID_API_CMD_SNAPSHOT}, 724 {VPU_CMD_ID_FIRM_RESET, VID_API_CMD_FIRM_RESET}, 725 {VPU_CMD_ID_FS_ALLOC, VID_API_CMD_FS_ALLOC}, 726 {VPU_CMD_ID_FS_RELEASE, VID_API_CMD_FS_RELEASE}, 727 {VPU_CMD_ID_TIMESTAMP, VID_API_CMD_TS}, 728 {VPU_CMD_ID_DEBUG, VID_API_CMD_FW_STATUS}, 729 }; 730 731 static struct vpu_pair malone_msgs[] = { 732 {VPU_MSG_ID_RESET_DONE, VID_API_EVENT_RESET_DONE}, 733 {VPU_MSG_ID_START_DONE, VID_API_EVENT_START_DONE}, 734 {VPU_MSG_ID_STOP_DONE, VID_API_EVENT_STOPPED}, 735 {VPU_MSG_ID_ABORT_DONE, VID_API_EVENT_ABORT_DONE}, 736 {VPU_MSG_ID_BUF_RST, VID_API_EVENT_STR_BUF_RST}, 737 {VPU_MSG_ID_PIC_EOS, VID_API_EVENT_FINISHED}, 738 {VPU_MSG_ID_SEQ_HDR_FOUND, VID_API_EVENT_SEQ_HDR_FOUND}, 739 {VPU_MSG_ID_RES_CHANGE, VID_API_EVENT_RES_CHANGE}, 740 {VPU_MSG_ID_PIC_HDR_FOUND, VID_API_EVENT_PIC_HDR_FOUND}, 741 {VPU_MSG_ID_PIC_DECODED, VID_API_EVENT_PIC_DECODED}, 742 {VPU_MSG_ID_DEC_DONE, VID_API_EVENT_FRAME_BUFF_RDY}, 743 {VPU_MSG_ID_FRAME_REQ, VID_API_EVENT_REQ_FRAME_BUFF}, 744 {VPU_MSG_ID_FRAME_RELEASE, VID_API_EVENT_REL_FRAME_BUFF}, 745 {VPU_MSG_ID_FIFO_LOW, VID_API_EVENT_FIFO_LOW}, 746 {VPU_MSG_ID_BS_ERROR, VID_API_EVENT_BS_ERROR}, 747 {VPU_MSG_ID_UNSUPPORTED, VID_API_EVENT_UNSUPPORTED_STREAM}, 748 {VPU_MSG_ID_FIRMWARE_XCPT, VID_API_EVENT_FIRMWARE_XCPT}, 749 {VPU_MSG_ID_PIC_SKIPPED, VID_API_EVENT_PIC_SKIPPED}, 750 }; 751 752 static void vpu_malone_pack_fs_alloc(struct vpu_rpc_event *pkt, 753 struct vpu_fs_info *fs) 754 { 755 const u32 fs_type[] = { 756 [MEM_RES_FRAME] = 0, 757 [MEM_RES_MBI] = 1, 758 [MEM_RES_DCP] = 2, 759 }; 760 761 pkt->hdr.num = 7; 762 pkt->data[0] = fs->id | (fs->tag << 24); 763 pkt->data[1] = fs->luma_addr; 764 if (fs->type == MEM_RES_FRAME) { 765 /* 766 * if luma_addr equal to chroma_addr, 767 * means luma(plane[0]) and chromau(plane[1]) used the 768 * same fd -- usage of NXP codec2. Need to manually 769 * offset chroma addr. 770 */ 771 if (fs->luma_addr == fs->chroma_addr) 772 fs->chroma_addr = fs->luma_addr + fs->luma_size; 773 pkt->data[2] = fs->luma_addr + fs->luma_size / 2; 774 pkt->data[3] = fs->chroma_addr; 775 pkt->data[4] = fs->chroma_addr + fs->chromau_size / 2; 776 pkt->data[5] = fs->bytesperline; 777 } else { 778 pkt->data[2] = fs->luma_size; 779 pkt->data[3] = 0; 780 pkt->data[4] = 0; 781 pkt->data[5] = 0; 782 } 783 pkt->data[6] = fs_type[fs->type]; 784 } 785 786 static void vpu_malone_pack_fs_release(struct vpu_rpc_event *pkt, 787 struct vpu_fs_info *fs) 788 { 789 pkt->hdr.num = 1; 790 pkt->data[0] = fs->id | (fs->tag << 24); 791 } 792 793 static void vpu_malone_pack_timestamp(struct vpu_rpc_event *pkt, 794 struct vpu_ts_info *info) 795 { 796 struct timespec64 ts = ns_to_timespec64(info->timestamp); 797 798 pkt->hdr.num = 3; 799 800 pkt->data[0] = ts.tv_sec; 801 pkt->data[1] = ts.tv_nsec; 802 pkt->data[2] = info->size; 803 } 804 805 int vpu_malone_pack_cmd(struct vpu_rpc_event *pkt, u32 index, u32 id, void *data) 806 { 807 int ret; 808 809 ret = vpu_find_dst_by_src(malone_cmds, ARRAY_SIZE(malone_cmds), id); 810 if (ret < 0) 811 return ret; 812 813 pkt->hdr.id = ret; 814 pkt->hdr.num = 0; 815 pkt->hdr.index = index; 816 817 switch (id) { 818 case VPU_CMD_ID_FS_ALLOC: 819 vpu_malone_pack_fs_alloc(pkt, data); 820 break; 821 case VPU_CMD_ID_FS_RELEASE: 822 vpu_malone_pack_fs_release(pkt, data); 823 break; 824 case VPU_CMD_ID_TIMESTAMP: 825 vpu_malone_pack_timestamp(pkt, data); 826 break; 827 } 828 829 pkt->hdr.index = index; 830 return 0; 831 } 832 833 int vpu_malone_convert_msg_id(u32 id) 834 { 835 return vpu_find_src_by_dst(malone_msgs, ARRAY_SIZE(malone_msgs), id); 836 } 837 838 static void vpu_malone_fill_planes(struct vpu_dec_codec_info *info) 839 { 840 u32 interlaced = info->progressive ? 0 : 1; 841 842 info->bytesperline[0] = 0; 843 info->sizeimage[0] = vpu_helper_get_plane_size(info->pixfmt, 844 info->decoded_width, 845 info->decoded_height, 846 0, 847 info->stride, 848 interlaced, 849 &info->bytesperline[0]); 850 info->bytesperline[1] = 0; 851 info->sizeimage[1] = vpu_helper_get_plane_size(info->pixfmt, 852 info->decoded_width, 853 info->decoded_height, 854 1, 855 info->stride, 856 interlaced, 857 &info->bytesperline[1]); 858 } 859 860 static void vpu_malone_init_seq_hdr(struct vpu_dec_codec_info *info) 861 { 862 u32 chunks = info->num_dfe_area >> MALONE_DCP_CHUNK_BIT; 863 864 vpu_malone_fill_planes(info); 865 866 info->mbi_size = (info->sizeimage[0] + info->sizeimage[1]) >> 2; 867 info->mbi_size = ALIGN(info->mbi_size, MALONE_ALIGN_MBI); 868 869 info->dcp_size = MALONE_DCP_SIZE_MAX; 870 if (chunks) { 871 u32 mb_num; 872 u32 mb_w; 873 u32 mb_h; 874 875 mb_w = DIV_ROUND_UP(info->decoded_width, 16); 876 mb_h = DIV_ROUND_UP(info->decoded_height, 16); 877 mb_num = mb_w * mb_h; 878 info->dcp_size = mb_num * MALONE_DCP_FIXED_MB_ALLOC * chunks; 879 info->dcp_size = clamp_t(u32, info->dcp_size, 880 MALONE_DCP_SIZE_MIN, MALONE_DCP_SIZE_MAX); 881 } 882 } 883 884 static void vpu_malone_unpack_seq_hdr(struct vpu_rpc_event *pkt, 885 struct vpu_dec_codec_info *info) 886 { 887 info->num_ref_frms = pkt->data[0]; 888 info->num_dpb_frms = pkt->data[1]; 889 info->num_dfe_area = pkt->data[2]; 890 info->progressive = pkt->data[3]; 891 info->width = pkt->data[5]; 892 info->height = pkt->data[4]; 893 info->decoded_width = pkt->data[12]; 894 info->decoded_height = pkt->data[11]; 895 info->frame_rate.numerator = 1000; 896 info->frame_rate.denominator = pkt->data[8]; 897 info->dsp_asp_ratio = pkt->data[9]; 898 info->level_idc = pkt->data[10]; 899 info->bit_depth_luma = pkt->data[13]; 900 info->bit_depth_chroma = pkt->data[14]; 901 info->chroma_fmt = pkt->data[15]; 902 info->color_primaries = vpu_color_cvrt_primaries_i2v(pkt->data[16]); 903 info->transfer_chars = vpu_color_cvrt_transfers_i2v(pkt->data[17]); 904 info->matrix_coeffs = vpu_color_cvrt_matrix_i2v(pkt->data[18]); 905 info->full_range = vpu_color_cvrt_full_range_i2v(pkt->data[19]); 906 info->vui_present = pkt->data[20]; 907 info->mvc_num_views = pkt->data[21]; 908 info->offset_x = pkt->data[23]; 909 info->offset_y = pkt->data[25]; 910 info->tag = pkt->data[27]; 911 if (info->bit_depth_luma > 8) 912 info->pixfmt = V4L2_PIX_FMT_NV12M_10BE_8L128; 913 else 914 info->pixfmt = V4L2_PIX_FMT_NV12M_8L128; 915 if (info->frame_rate.numerator && info->frame_rate.denominator) { 916 unsigned long n, d; 917 918 rational_best_approximation(info->frame_rate.numerator, 919 info->frame_rate.denominator, 920 info->frame_rate.numerator, 921 info->frame_rate.denominator, 922 &n, &d); 923 info->frame_rate.numerator = n; 924 info->frame_rate.denominator = d; 925 } 926 vpu_malone_init_seq_hdr(info); 927 } 928 929 static void vpu_malone_unpack_pic_info(struct vpu_rpc_event *pkt, 930 struct vpu_dec_pic_info *info) 931 { 932 info->id = pkt->data[7]; 933 info->luma = pkt->data[0]; 934 info->start = pkt->data[10]; 935 info->end = pkt->data[12]; 936 info->pic_size = pkt->data[11]; 937 info->stride = pkt->data[5]; 938 info->consumed_count = pkt->data[13]; 939 if (info->id == MALONE_SKIPPED_FRAME_ID) 940 info->skipped = 1; 941 else 942 info->skipped = 0; 943 } 944 945 static void vpu_malone_unpack_req_frame(struct vpu_rpc_event *pkt, 946 struct vpu_fs_info *info) 947 { 948 info->type = pkt->data[1]; 949 } 950 951 static void vpu_malone_unpack_rel_frame(struct vpu_rpc_event *pkt, 952 struct vpu_fs_info *info) 953 { 954 info->id = pkt->data[0]; 955 info->type = pkt->data[1]; 956 info->not_displayed = pkt->data[2]; 957 } 958 959 static void vpu_malone_unpack_buff_rdy(struct vpu_rpc_event *pkt, 960 struct vpu_dec_pic_info *info) 961 { 962 struct timespec64 ts = { pkt->data[9], pkt->data[10] }; 963 964 info->id = pkt->data[0]; 965 info->luma = pkt->data[1]; 966 info->stride = pkt->data[3]; 967 if (info->id == MALONE_SKIPPED_FRAME_ID) 968 info->skipped = 1; 969 else 970 info->skipped = 0; 971 972 info->timestamp = timespec64_to_ns(&ts); 973 } 974 975 int vpu_malone_unpack_msg_data(struct vpu_rpc_event *pkt, void *data) 976 { 977 if (!pkt || !data) 978 return -EINVAL; 979 980 switch (pkt->hdr.id) { 981 case VID_API_EVENT_SEQ_HDR_FOUND: 982 vpu_malone_unpack_seq_hdr(pkt, data); 983 break; 984 case VID_API_EVENT_PIC_DECODED: 985 vpu_malone_unpack_pic_info(pkt, data); 986 break; 987 case VID_API_EVENT_REQ_FRAME_BUFF: 988 vpu_malone_unpack_req_frame(pkt, data); 989 break; 990 case VID_API_EVENT_REL_FRAME_BUFF: 991 vpu_malone_unpack_rel_frame(pkt, data); 992 break; 993 case VID_API_EVENT_FRAME_BUFF_RDY: 994 vpu_malone_unpack_buff_rdy(pkt, data); 995 break; 996 } 997 998 return 0; 999 } 1000 1001 static const struct malone_padding_scode padding_scodes[] = { 1002 {SCODE_PADDING_EOS, V4L2_PIX_FMT_H264, {0x0B010000, 0}}, 1003 {SCODE_PADDING_EOS, V4L2_PIX_FMT_H264_MVC, {0x0B010000, 0}}, 1004 {SCODE_PADDING_EOS, V4L2_PIX_FMT_HEVC, {0x4A010000, 0x20}}, 1005 {SCODE_PADDING_EOS, V4L2_PIX_FMT_VC1_ANNEX_G, {0x0a010000, 0x0}}, 1006 {SCODE_PADDING_EOS, V4L2_PIX_FMT_VC1_ANNEX_L, {0x0a010000, 0x0}}, 1007 {SCODE_PADDING_EOS, V4L2_PIX_FMT_MPEG2, {0xCC010000, 0x0}}, 1008 {SCODE_PADDING_EOS, V4L2_PIX_FMT_MPEG4, {0xb1010000, 0x0}}, 1009 {SCODE_PADDING_EOS, V4L2_PIX_FMT_XVID, {0xb1010000, 0x0}}, 1010 {SCODE_PADDING_EOS, V4L2_PIX_FMT_H263, {0xb1010000, 0x0}}, 1011 {SCODE_PADDING_EOS, V4L2_PIX_FMT_VP8, {0x34010000, 0x0}}, 1012 {SCODE_PADDING_EOS, V4L2_PIX_FMT_SPK, {0x34010000, 0x0}}, 1013 {SCODE_PADDING_EOS, V4L2_PIX_FMT_RV30, {0x34010000, 0x0}}, 1014 {SCODE_PADDING_EOS, V4L2_PIX_FMT_RV40, {0x34010000, 0x0}}, 1015 {SCODE_PADDING_EOS, V4L2_PIX_FMT_JPEG, {0xefff0000, 0x0}}, 1016 {SCODE_PADDING_ABORT, V4L2_PIX_FMT_H264, {0x0B010000, 0}}, 1017 {SCODE_PADDING_ABORT, V4L2_PIX_FMT_H264_MVC, {0x0B010000, 0}}, 1018 {SCODE_PADDING_ABORT, V4L2_PIX_FMT_HEVC, {0x4A010000, 0x20}}, 1019 {SCODE_PADDING_ABORT, V4L2_PIX_FMT_VC1_ANNEX_G, {0x0a010000, 0x0}}, 1020 {SCODE_PADDING_ABORT, V4L2_PIX_FMT_VC1_ANNEX_L, {0x0a010000, 0x0}}, 1021 {SCODE_PADDING_ABORT, V4L2_PIX_FMT_MPEG2, {0xb7010000, 0x0}}, 1022 {SCODE_PADDING_ABORT, V4L2_PIX_FMT_MPEG4, {0xb1010000, 0x0}}, 1023 {SCODE_PADDING_ABORT, V4L2_PIX_FMT_XVID, {0xb1010000, 0x0}}, 1024 {SCODE_PADDING_ABORT, V4L2_PIX_FMT_H263, {0xb1010000, 0x0}}, 1025 {SCODE_PADDING_ABORT, V4L2_PIX_FMT_VP8, {0x34010000, 0x0}}, 1026 {SCODE_PADDING_ABORT, V4L2_PIX_FMT_SPK, {0x34010000, 0x0}}, 1027 {SCODE_PADDING_ABORT, V4L2_PIX_FMT_RV30, {0x34010000, 0x0}}, 1028 {SCODE_PADDING_ABORT, V4L2_PIX_FMT_RV40, {0x34010000, 0x0}}, 1029 {SCODE_PADDING_EOS, V4L2_PIX_FMT_JPEG, {0x0, 0x0}}, 1030 {SCODE_PADDING_BUFFLUSH, V4L2_PIX_FMT_H264, {0x15010000, 0x0}}, 1031 {SCODE_PADDING_BUFFLUSH, V4L2_PIX_FMT_H264_MVC, {0x15010000, 0x0}}, 1032 }; 1033 1034 static const struct malone_padding_scode padding_scode_dft = {0x0, 0x0}; 1035 1036 static const struct malone_padding_scode *get_padding_scode(u32 type, u32 fmt) 1037 { 1038 const struct malone_padding_scode *s; 1039 int i; 1040 1041 for (i = 0; i < ARRAY_SIZE(padding_scodes); i++) { 1042 s = &padding_scodes[i]; 1043 1044 if (s->scode_type == type && s->pixelformat == fmt) 1045 return s; 1046 } 1047 1048 if (type != SCODE_PADDING_BUFFLUSH) 1049 return &padding_scode_dft; 1050 1051 return NULL; 1052 } 1053 1054 static int vpu_malone_add_padding_scode(struct vpu_buffer *stream_buffer, 1055 struct vpu_malone_str_buffer __iomem *str_buf, 1056 u32 pixelformat, u32 scode_type) 1057 { 1058 u32 wptr; 1059 int size; 1060 int total_size = 0; 1061 const struct malone_padding_scode *ps; 1062 const u32 padding_size = 4096; 1063 int ret; 1064 1065 ps = get_padding_scode(scode_type, pixelformat); 1066 if (!ps) 1067 return -EINVAL; 1068 1069 wptr = readl(&str_buf->wptr); 1070 if (wptr < stream_buffer->phys || wptr > stream_buffer->phys + stream_buffer->length) 1071 return -EINVAL; 1072 if (wptr == stream_buffer->phys + stream_buffer->length) 1073 wptr = stream_buffer->phys; 1074 size = ALIGN(wptr, 4) - wptr; 1075 if (size) 1076 vpu_helper_memset_stream_buffer(stream_buffer, &wptr, 0, size); 1077 total_size += size; 1078 1079 size = sizeof(ps->data); 1080 ret = vpu_helper_copy_to_stream_buffer(stream_buffer, &wptr, size, (void *)ps->data); 1081 if (ret < 0) 1082 return -EINVAL; 1083 total_size += size; 1084 1085 size = padding_size - sizeof(ps->data); 1086 vpu_helper_memset_stream_buffer(stream_buffer, &wptr, 0, size); 1087 total_size += size; 1088 1089 vpu_malone_update_wptr(str_buf, wptr); 1090 return total_size; 1091 } 1092 1093 int vpu_malone_add_scode(struct vpu_shared_addr *shared, 1094 u32 instance, 1095 struct vpu_buffer *stream_buffer, 1096 u32 pixelformat, 1097 u32 scode_type) 1098 { 1099 struct vpu_dec_ctrl *hc = shared->priv; 1100 struct vpu_malone_str_buffer __iomem *str_buf = hc->str_buf[instance]; 1101 int ret = -EINVAL; 1102 1103 switch (scode_type) { 1104 case SCODE_PADDING_EOS: 1105 case SCODE_PADDING_ABORT: 1106 case SCODE_PADDING_BUFFLUSH: 1107 ret = vpu_malone_add_padding_scode(stream_buffer, str_buf, pixelformat, scode_type); 1108 break; 1109 default: 1110 break; 1111 } 1112 1113 return ret; 1114 } 1115 1116 #define MALONE_PAYLOAD_HEADER_SIZE 16 1117 #define MALONE_CODEC_VERSION_ID 0x1 1118 #define MALONE_CODEC_ID_VC1_SIMPLE 0x10 1119 #define MALONE_CODEC_ID_VC1_MAIN 0x11 1120 #define MALONE_CODEC_ID_ARV8 0x28 1121 #define MALONE_CODEC_ID_ARV9 0x29 1122 #define MALONE_CODEC_ID_VP6 0x36 1123 #define MALONE_CODEC_ID_VP8 0x36 1124 #define MALONE_CODEC_ID_DIVX3 0x38 1125 #define MALONE_CODEC_ID_SPK 0x39 1126 1127 #define MALONE_VP8_IVF_SEQ_HEADER_LEN 32 1128 #define MALONE_VP8_IVF_FRAME_HEADER_LEN 8 1129 1130 #define MALONE_VC1_RCV_CODEC_V1_VERSION 0x85 1131 #define MALONE_VC1_RCV_CODEC_V2_VERSION 0xC5 1132 #define MALONE_VC1_RCV_NUM_FRAMES 0xFF 1133 #define MALONE_VC1_RCV_SEQ_EXT_DATA_SIZE 4 1134 #define MALONE_VC1_RCV_SEQ_HEADER_LEN 20 1135 #define MALONE_VC1_RCV_PIC_HEADER_LEN 4 1136 #define MALONE_VC1_NAL_HEADER_LEN 4 1137 #define MALONE_VC1_CONTAIN_NAL(data) (((data) & 0x00FFFFFF) == 0x00010000) 1138 1139 static void set_payload_hdr(u8 *dst, u32 scd_type, u32 codec_id, 1140 u32 buffer_size, u32 width, u32 height) 1141 { 1142 unsigned int payload_size; 1143 /* payload_size = buffer_size + itself_size(16) - start_code(4) */ 1144 payload_size = buffer_size + 12; 1145 1146 dst[0] = 0x00; 1147 dst[1] = 0x00; 1148 dst[2] = 0x01; 1149 dst[3] = scd_type; 1150 1151 /* length */ 1152 dst[4] = ((payload_size >> 16) & 0xff); 1153 dst[5] = ((payload_size >> 8) & 0xff); 1154 dst[6] = 0x4e; 1155 dst[7] = ((payload_size >> 0) & 0xff); 1156 1157 /* Codec ID and Version */ 1158 dst[8] = codec_id; 1159 dst[9] = MALONE_CODEC_VERSION_ID; 1160 1161 /* width */ 1162 dst[10] = ((width >> 8) & 0xff); 1163 dst[11] = ((width >> 0) & 0xff); 1164 dst[12] = 0x58; 1165 1166 /* height */ 1167 dst[13] = ((height >> 8) & 0xff); 1168 dst[14] = ((height >> 0) & 0xff); 1169 dst[15] = 0x50; 1170 } 1171 1172 static void set_vp8_ivf_seqhdr(u8 *dst, u32 width, u32 height) 1173 { 1174 /* 0-3byte signature "DKIF" */ 1175 dst[0] = 0x44; 1176 dst[1] = 0x4b; 1177 dst[2] = 0x49; 1178 dst[3] = 0x46; 1179 /* 4-5byte version: should be 0*/ 1180 dst[4] = 0x00; 1181 dst[5] = 0x00; 1182 /* 6-7 length of Header */ 1183 dst[6] = MALONE_VP8_IVF_SEQ_HEADER_LEN; 1184 dst[7] = MALONE_VP8_IVF_SEQ_HEADER_LEN >> 8; 1185 /* 8-11 VP8 fourcc */ 1186 dst[8] = 0x56; 1187 dst[9] = 0x50; 1188 dst[10] = 0x38; 1189 dst[11] = 0x30; 1190 /* 12-13 width in pixels */ 1191 dst[12] = width; 1192 dst[13] = width >> 8; 1193 /* 14-15 height in pixels */ 1194 dst[14] = height; 1195 dst[15] = height >> 8; 1196 /* 16-19 frame rate */ 1197 dst[16] = 0xe8; 1198 dst[17] = 0x03; 1199 dst[18] = 0x00; 1200 dst[19] = 0x00; 1201 /* 20-23 time scale */ 1202 dst[20] = 0x01; 1203 dst[21] = 0x00; 1204 dst[22] = 0x00; 1205 dst[23] = 0x00; 1206 /* 24-27 number frames */ 1207 dst[24] = 0xdf; 1208 dst[25] = 0xf9; 1209 dst[26] = 0x09; 1210 dst[27] = 0x00; 1211 /* 28-31 reserved */ 1212 } 1213 1214 static void set_vp8_ivf_pichdr(u8 *dst, u32 frame_size) 1215 { 1216 /* 1217 * firmware just parse 64-bit timestamp(8 bytes). 1218 * As not transfer timestamp to firmware, use default value(ZERO). 1219 * No need to do anything here 1220 */ 1221 } 1222 1223 static void set_vc1_rcv_seqhdr(u8 *dst, u8 *src, u32 width, u32 height) 1224 { 1225 u32 frames = MALONE_VC1_RCV_NUM_FRAMES; 1226 u32 ext_data_size = MALONE_VC1_RCV_SEQ_EXT_DATA_SIZE; 1227 1228 /* 0-2 Number of frames, used default value 0xFF */ 1229 dst[0] = frames; 1230 dst[1] = frames >> 8; 1231 dst[2] = frames >> 16; 1232 1233 /* 3 RCV version, used V1 */ 1234 dst[3] = MALONE_VC1_RCV_CODEC_V1_VERSION; 1235 1236 /* 4-7 extension data size */ 1237 dst[4] = ext_data_size; 1238 dst[5] = ext_data_size >> 8; 1239 dst[6] = ext_data_size >> 16; 1240 dst[7] = ext_data_size >> 24; 1241 /* 8-11 extension data */ 1242 dst[8] = src[0]; 1243 dst[9] = src[1]; 1244 dst[10] = src[2]; 1245 dst[11] = src[3]; 1246 1247 /* height */ 1248 dst[12] = height; 1249 dst[13] = (height >> 8) & 0xff; 1250 dst[14] = (height >> 16) & 0xff; 1251 dst[15] = (height >> 24) & 0xff; 1252 /* width */ 1253 dst[16] = width; 1254 dst[17] = (width >> 8) & 0xff; 1255 dst[18] = (width >> 16) & 0xff; 1256 dst[19] = (width >> 24) & 0xff; 1257 } 1258 1259 static void set_vc1_rcv_pichdr(u8 *dst, u32 buffer_size) 1260 { 1261 dst[0] = buffer_size; 1262 dst[1] = buffer_size >> 8; 1263 dst[2] = buffer_size >> 16; 1264 dst[3] = buffer_size >> 24; 1265 } 1266 1267 static void create_vc1_nal_pichdr(u8 *dst) 1268 { 1269 /* need insert nal header: special ID */ 1270 dst[0] = 0x0; 1271 dst[1] = 0x0; 1272 dst[2] = 0x01; 1273 dst[3] = 0x0D; 1274 } 1275 1276 static int vpu_malone_insert_scode_seq(struct malone_scode_t *scode, u32 codec_id, u32 ext_size) 1277 { 1278 u8 hdr[MALONE_PAYLOAD_HEADER_SIZE]; 1279 int ret; 1280 1281 set_payload_hdr(hdr, 1282 SCODE_SEQUENCE, 1283 codec_id, 1284 ext_size, 1285 scode->inst->out_format.width, 1286 scode->inst->out_format.height); 1287 ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer, 1288 &scode->wptr, 1289 sizeof(hdr), 1290 hdr); 1291 if (ret < 0) 1292 return ret; 1293 return sizeof(hdr); 1294 } 1295 1296 static int vpu_malone_insert_scode_pic(struct malone_scode_t *scode, u32 codec_id, u32 ext_size) 1297 { 1298 u8 hdr[MALONE_PAYLOAD_HEADER_SIZE]; 1299 int ret; 1300 1301 set_payload_hdr(hdr, 1302 SCODE_PICTURE, 1303 codec_id, 1304 ext_size + vb2_get_plane_payload(scode->vb, 0), 1305 scode->inst->out_format.width, 1306 scode->inst->out_format.height); 1307 ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer, 1308 &scode->wptr, 1309 sizeof(hdr), 1310 hdr); 1311 if (ret < 0) 1312 return ret; 1313 return sizeof(hdr); 1314 } 1315 1316 static int vpu_malone_insert_scode_vc1_g_pic(struct malone_scode_t *scode) 1317 { 1318 struct vb2_v4l2_buffer *vbuf; 1319 u8 nal_hdr[MALONE_VC1_NAL_HEADER_LEN]; 1320 u32 *data = NULL; 1321 int ret; 1322 1323 vbuf = to_vb2_v4l2_buffer(scode->vb); 1324 data = vb2_plane_vaddr(scode->vb, 0); 1325 1326 if (scode->inst->total_input_count == 0 || vpu_vb_is_codecconfig(vbuf)) 1327 return 0; 1328 if (MALONE_VC1_CONTAIN_NAL(*data)) 1329 return 0; 1330 1331 create_vc1_nal_pichdr(nal_hdr); 1332 ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer, 1333 &scode->wptr, 1334 sizeof(nal_hdr), 1335 nal_hdr); 1336 if (ret < 0) 1337 return ret; 1338 return sizeof(nal_hdr); 1339 } 1340 1341 static int vpu_malone_insert_scode_vc1_l_seq(struct malone_scode_t *scode) 1342 { 1343 int ret; 1344 int size = 0; 1345 u8 rcv_seqhdr[MALONE_VC1_RCV_SEQ_HEADER_LEN]; 1346 1347 if (scode->inst->total_input_count) 1348 return 0; 1349 scode->need_data = 0; 1350 1351 ret = vpu_malone_insert_scode_seq(scode, MALONE_CODEC_ID_VC1_SIMPLE, sizeof(rcv_seqhdr)); 1352 if (ret < 0) 1353 return ret; 1354 size = ret; 1355 1356 set_vc1_rcv_seqhdr(rcv_seqhdr, 1357 vb2_plane_vaddr(scode->vb, 0), 1358 scode->inst->out_format.width, 1359 scode->inst->out_format.height); 1360 ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer, 1361 &scode->wptr, 1362 sizeof(rcv_seqhdr), 1363 rcv_seqhdr); 1364 1365 if (ret < 0) 1366 return ret; 1367 size += sizeof(rcv_seqhdr); 1368 return size; 1369 } 1370 1371 static int vpu_malone_insert_scode_vc1_l_pic(struct malone_scode_t *scode) 1372 { 1373 int ret; 1374 int size = 0; 1375 u8 rcv_pichdr[MALONE_VC1_RCV_PIC_HEADER_LEN]; 1376 1377 ret = vpu_malone_insert_scode_pic(scode, MALONE_CODEC_ID_VC1_SIMPLE, 1378 sizeof(rcv_pichdr)); 1379 if (ret < 0) 1380 return ret; 1381 size = ret; 1382 1383 set_vc1_rcv_pichdr(rcv_pichdr, vb2_get_plane_payload(scode->vb, 0)); 1384 ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer, 1385 &scode->wptr, 1386 sizeof(rcv_pichdr), 1387 rcv_pichdr); 1388 if (ret < 0) 1389 return ret; 1390 size += sizeof(rcv_pichdr); 1391 return size; 1392 } 1393 1394 static int vpu_malone_insert_scode_vp8_seq(struct malone_scode_t *scode) 1395 { 1396 int ret; 1397 int size = 0; 1398 u8 ivf_hdr[MALONE_VP8_IVF_SEQ_HEADER_LEN]; 1399 1400 ret = vpu_malone_insert_scode_seq(scode, MALONE_CODEC_ID_VP8, sizeof(ivf_hdr)); 1401 if (ret < 0) 1402 return ret; 1403 size = ret; 1404 1405 set_vp8_ivf_seqhdr(ivf_hdr, 1406 scode->inst->out_format.width, 1407 scode->inst->out_format.height); 1408 ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer, 1409 &scode->wptr, 1410 sizeof(ivf_hdr), 1411 ivf_hdr); 1412 if (ret < 0) 1413 return ret; 1414 size += sizeof(ivf_hdr); 1415 1416 return size; 1417 } 1418 1419 static int vpu_malone_insert_scode_vp8_pic(struct malone_scode_t *scode) 1420 { 1421 int ret; 1422 int size = 0; 1423 u8 ivf_hdr[MALONE_VP8_IVF_FRAME_HEADER_LEN] = {0}; 1424 1425 ret = vpu_malone_insert_scode_pic(scode, MALONE_CODEC_ID_VP8, sizeof(ivf_hdr)); 1426 if (ret < 0) 1427 return ret; 1428 size = ret; 1429 1430 set_vp8_ivf_pichdr(ivf_hdr, vb2_get_plane_payload(scode->vb, 0)); 1431 ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer, 1432 &scode->wptr, 1433 sizeof(ivf_hdr), 1434 ivf_hdr); 1435 if (ret < 0) 1436 return ret; 1437 size += sizeof(ivf_hdr); 1438 1439 return size; 1440 } 1441 1442 static int vpu_malone_insert_scode_spk_seq(struct malone_scode_t *scode) 1443 { 1444 return vpu_malone_insert_scode_seq(scode, MALONE_CODEC_ID_SPK, 0); 1445 } 1446 1447 static int vpu_malone_insert_scode_spk_pic(struct malone_scode_t *scode) 1448 { 1449 return vpu_malone_insert_scode_pic(scode, MALONE_CODEC_ID_SPK, 0); 1450 } 1451 1452 static const struct malone_scode_handler scode_handlers[] = { 1453 { 1454 /* fix me, need to swap return operation after gstreamer swap */ 1455 .pixelformat = V4L2_PIX_FMT_VC1_ANNEX_L, 1456 .insert_scode_seq = vpu_malone_insert_scode_vc1_l_seq, 1457 .insert_scode_pic = vpu_malone_insert_scode_vc1_l_pic, 1458 }, 1459 { 1460 .pixelformat = V4L2_PIX_FMT_VC1_ANNEX_G, 1461 .insert_scode_pic = vpu_malone_insert_scode_vc1_g_pic, 1462 }, 1463 { 1464 .pixelformat = V4L2_PIX_FMT_VP8, 1465 .insert_scode_seq = vpu_malone_insert_scode_vp8_seq, 1466 .insert_scode_pic = vpu_malone_insert_scode_vp8_pic, 1467 }, 1468 { 1469 .pixelformat = V4L2_PIX_FMT_SPK, 1470 .insert_scode_seq = vpu_malone_insert_scode_spk_seq, 1471 .insert_scode_pic = vpu_malone_insert_scode_spk_pic, 1472 }, 1473 }; 1474 1475 static const struct malone_scode_handler *get_scode_handler(u32 pixelformat) 1476 { 1477 int i; 1478 1479 for (i = 0; i < ARRAY_SIZE(scode_handlers); i++) { 1480 if (scode_handlers[i].pixelformat == pixelformat) 1481 return &scode_handlers[i]; 1482 } 1483 1484 return NULL; 1485 } 1486 1487 static int vpu_malone_insert_scode(struct malone_scode_t *scode, u32 type) 1488 { 1489 const struct malone_scode_handler *handler; 1490 int ret = 0; 1491 1492 if (!scode || !scode->inst || !scode->vb) 1493 return 0; 1494 1495 scode->need_data = 1; 1496 handler = get_scode_handler(scode->inst->out_format.pixfmt); 1497 if (!handler) 1498 return 0; 1499 1500 switch (type) { 1501 case SCODE_SEQUENCE: 1502 if (handler->insert_scode_seq) 1503 ret = handler->insert_scode_seq(scode); 1504 break; 1505 case SCODE_PICTURE: 1506 if (handler->insert_scode_pic) 1507 ret = handler->insert_scode_pic(scode); 1508 break; 1509 default: 1510 break; 1511 } 1512 1513 return ret; 1514 } 1515 1516 static int vpu_malone_input_frame_data(struct vpu_malone_str_buffer __iomem *str_buf, 1517 struct vpu_inst *inst, struct vb2_buffer *vb, 1518 u32 disp_imm) 1519 { 1520 struct malone_scode_t scode; 1521 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); 1522 u32 wptr = readl(&str_buf->wptr); 1523 int size = 0; 1524 int ret = 0; 1525 1526 /*add scode: SCODE_SEQUENCE, SCODE_PICTURE, SCODE_SLICE*/ 1527 scode.inst = inst; 1528 scode.vb = vb; 1529 scode.wptr = wptr; 1530 scode.need_data = 1; 1531 if (vbuf->sequence == 0 || vpu_vb_is_codecconfig(vbuf)) 1532 ret = vpu_malone_insert_scode(&scode, SCODE_SEQUENCE); 1533 1534 if (ret < 0) 1535 return -ENOMEM; 1536 size += ret; 1537 wptr = scode.wptr; 1538 if (!scode.need_data) { 1539 vpu_malone_update_wptr(str_buf, wptr); 1540 return size; 1541 } 1542 1543 ret = vpu_malone_insert_scode(&scode, SCODE_PICTURE); 1544 if (ret < 0) 1545 return -ENOMEM; 1546 size += ret; 1547 wptr = scode.wptr; 1548 1549 ret = vpu_helper_copy_to_stream_buffer(&inst->stream_buffer, 1550 &wptr, 1551 vb2_get_plane_payload(vb, 0), 1552 vb2_plane_vaddr(vb, 0)); 1553 if (ret < 0) 1554 return -ENOMEM; 1555 size += vb2_get_plane_payload(vb, 0); 1556 1557 vpu_malone_update_wptr(str_buf, wptr); 1558 1559 if (disp_imm && !vpu_vb_is_codecconfig(vbuf)) { 1560 ret = vpu_malone_add_scode(inst->core->iface, 1561 inst->id, 1562 &inst->stream_buffer, 1563 inst->out_format.pixfmt, 1564 SCODE_PADDING_BUFFLUSH); 1565 if (ret < 0) 1566 return ret; 1567 size += ret; 1568 } 1569 1570 return size; 1571 } 1572 1573 static int vpu_malone_input_stream_data(struct vpu_malone_str_buffer __iomem *str_buf, 1574 struct vpu_inst *inst, struct vb2_buffer *vb) 1575 { 1576 u32 wptr = readl(&str_buf->wptr); 1577 int ret = 0; 1578 1579 ret = vpu_helper_copy_to_stream_buffer(&inst->stream_buffer, 1580 &wptr, 1581 vb2_get_plane_payload(vb, 0), 1582 vb2_plane_vaddr(vb, 0)); 1583 if (ret < 0) 1584 return -ENOMEM; 1585 1586 vpu_malone_update_wptr(str_buf, wptr); 1587 1588 return ret; 1589 } 1590 1591 static int vpu_malone_input_ts(struct vpu_inst *inst, s64 timestamp, u32 size) 1592 { 1593 struct vpu_ts_info info; 1594 1595 memset(&info, 0, sizeof(info)); 1596 info.timestamp = timestamp; 1597 info.size = size; 1598 1599 return vpu_session_fill_timestamp(inst, &info); 1600 } 1601 1602 int vpu_malone_input_frame(struct vpu_shared_addr *shared, 1603 struct vpu_inst *inst, struct vb2_buffer *vb) 1604 { 1605 struct vpu_dec_ctrl *hc = shared->priv; 1606 struct vb2_v4l2_buffer *vbuf; 1607 struct vpu_malone_str_buffer __iomem *str_buf = hc->str_buf[inst->id]; 1608 u32 disp_imm = hc->codec_param[inst->id].disp_imm; 1609 u32 size; 1610 int ret; 1611 1612 if (vpu_malone_is_non_frame_mode(shared, inst->id)) 1613 ret = vpu_malone_input_stream_data(str_buf, inst, vb); 1614 else 1615 ret = vpu_malone_input_frame_data(str_buf, inst, vb, disp_imm); 1616 if (ret < 0) 1617 return ret; 1618 size = ret; 1619 1620 /* 1621 * if buffer only contain codec data, and the timestamp is invalid, 1622 * don't put the invalid timestamp to resync 1623 * merge the data to next frame 1624 */ 1625 vbuf = to_vb2_v4l2_buffer(vb); 1626 if (vpu_vb_is_codecconfig(vbuf)) { 1627 inst->extra_size += size; 1628 return 0; 1629 } 1630 if (inst->extra_size) { 1631 size += inst->extra_size; 1632 inst->extra_size = 0; 1633 } 1634 1635 ret = vpu_malone_input_ts(inst, vb->timestamp, size); 1636 if (ret) 1637 return ret; 1638 1639 return 0; 1640 } 1641 1642 static bool vpu_malone_check_ready(struct vpu_shared_addr *shared, u32 instance) 1643 { 1644 struct malone_iface *iface = shared->iface; 1645 struct vpu_rpc_buffer_desc *desc = &iface->api_cmd_buffer_desc[instance]; 1646 u32 size = desc->end - desc->start; 1647 u32 rptr = desc->rptr; 1648 u32 wptr = desc->wptr; 1649 u32 used; 1650 1651 if (!size) 1652 return true; 1653 1654 used = (wptr + size - rptr) % size; 1655 if (used < (size / 2)) 1656 return true; 1657 1658 return false; 1659 } 1660 1661 bool vpu_malone_is_ready(struct vpu_shared_addr *shared, u32 instance) 1662 { 1663 u32 cnt = 0; 1664 1665 while (!vpu_malone_check_ready(shared, instance)) { 1666 if (cnt > 30) 1667 return false; 1668 mdelay(1); 1669 cnt++; 1670 } 1671 return true; 1672 } 1673 1674 int vpu_malone_pre_cmd(struct vpu_shared_addr *shared, u32 instance) 1675 { 1676 if (!vpu_malone_is_ready(shared, instance)) 1677 return -EINVAL; 1678 1679 return 0; 1680 } 1681 1682 int vpu_malone_post_cmd(struct vpu_shared_addr *shared, u32 instance) 1683 { 1684 struct malone_iface *iface = shared->iface; 1685 struct vpu_rpc_buffer_desc *desc = &iface->api_cmd_buffer_desc[instance]; 1686 1687 desc->wptr++; 1688 if (desc->wptr == desc->end) 1689 desc->wptr = desc->start; 1690 1691 return 0; 1692 } 1693 1694 int vpu_malone_init_instance(struct vpu_shared_addr *shared, u32 instance) 1695 { 1696 struct malone_iface *iface = shared->iface; 1697 struct vpu_rpc_buffer_desc *desc = &iface->api_cmd_buffer_desc[instance]; 1698 1699 desc->wptr = desc->rptr; 1700 if (desc->wptr == desc->end) 1701 desc->wptr = desc->start; 1702 1703 return 0; 1704 } 1705 1706 u32 vpu_malone_get_max_instance_count(struct vpu_shared_addr *shared) 1707 { 1708 struct malone_iface *iface = shared->iface; 1709 1710 return iface->max_streams; 1711 } 1712