1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright 2020-2021 NXP 4 */ 5 6 #include <linux/init.h> 7 #include <linux/interconnect.h> 8 #include <linux/ioctl.h> 9 #include <linux/list.h> 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/of_device.h> 13 #include <linux/of_address.h> 14 #include <linux/platform_device.h> 15 #include <linux/delay.h> 16 #include <linux/rational.h> 17 #include <linux/time64.h> 18 #include <media/videobuf2-v4l2.h> 19 #include <media/videobuf2-dma-contig.h> 20 #include <linux/videodev2.h> 21 #include "vpu.h" 22 #include "vpu_rpc.h" 23 #include "vpu_defs.h" 24 #include "vpu_helpers.h" 25 #include "vpu_v4l2.h" 26 #include "vpu_cmds.h" 27 #include "vpu_imx8q.h" 28 #include "vpu_malone.h" 29 30 #define CMD_SIZE 25600 31 #define MSG_SIZE 25600 32 #define CODEC_SIZE 0x1000 33 #define JPEG_SIZE 0x1000 34 #define SEQ_SIZE 0x1000 35 #define GOP_SIZE 0x1000 36 #define PIC_SIZE 0x1000 37 #define QMETER_SIZE 0x1000 38 #define DBGLOG_SIZE 0x10000 39 #define DEBUG_SIZE 0x80000 40 #define ENG_SIZE 0x1000 41 #define MALONE_SKIPPED_FRAME_ID 0x555 42 43 #define MALONE_ALIGN_MBI 0x800 44 #define MALONE_DCP_CHUNK_BIT 16 45 #define MALONE_DCP_SIZE_MAX 0x3000000 46 #define MALONE_DCP_SIZE_MIN 0x100000 47 #define MALONE_DCP_FIXED_MB_ALLOC 250 48 49 #define CONFIG_SET(val, cfg, pos, mask) \ 50 (*(cfg) |= (((val) << (pos)) & (mask))) 51 //x means source data , y means destination data 52 #define STREAM_CONFIG_FORMAT_SET(x, y) CONFIG_SET(x, y, 0, 0x0000000F) 53 #define STREAM_CONFIG_STRBUFIDX_SET(x, y) CONFIG_SET(x, y, 8, 0x00000300) 54 #define STREAM_CONFIG_NOSEQ_SET(x, y) CONFIG_SET(x, y, 10, 0x00000400) 55 #define STREAM_CONFIG_DEBLOCK_SET(x, y) CONFIG_SET(x, y, 11, 0x00000800) 56 #define STREAM_CONFIG_DERING_SET(x, y) CONFIG_SET(x, y, 12, 0x00001000) 57 #define STREAM_CONFIG_IBWAIT_SET(x, y) CONFIG_SET(x, y, 13, 0x00002000) 58 #define STREAM_CONFIG_FBC_SET(x, y) CONFIG_SET(x, y, 14, 0x00004000) 59 #define STREAM_CONFIG_PLAY_MODE_SET(x, y) CONFIG_SET(x, y, 16, 0x00030000) 60 #define STREAM_CONFIG_ENABLE_DCP_SET(x, y) CONFIG_SET(x, y, 20, 0x00100000) 61 #define STREAM_CONFIG_NUM_STR_BUF_SET(x, y) CONFIG_SET(x, y, 21, 0x00600000) 62 #define STREAM_CONFIG_MALONE_USAGE_SET(x, y) CONFIG_SET(x, y, 23, 0x01800000) 63 #define STREAM_CONFIG_MULTI_VID_SET(x, y) CONFIG_SET(x, y, 25, 0x02000000) 64 #define STREAM_CONFIG_OBFUSC_EN_SET(x, y) CONFIG_SET(x, y, 26, 0x04000000) 65 #define STREAM_CONFIG_RC4_EN_SET(x, y) CONFIG_SET(x, y, 27, 0x08000000) 66 #define STREAM_CONFIG_MCX_SET(x, y) CONFIG_SET(x, y, 28, 0x10000000) 67 #define STREAM_CONFIG_PES_SET(x, y) CONFIG_SET(x, y, 29, 0x20000000) 68 #define STREAM_CONFIG_NUM_DBE_SET(x, y) CONFIG_SET(x, y, 30, 0x40000000) 69 #define STREAM_CONFIG_FS_CTRL_MODE_SET(x, y) CONFIG_SET(x, y, 31, 0x80000000) 70 71 enum vpu_malone_stream_input_mode { 72 INVALID_MODE = 0, 73 FRAME_LVL, 74 NON_FRAME_LVL 75 }; 76 77 enum vpu_malone_format { 78 MALONE_FMT_NULL = 0x0, 79 MALONE_FMT_AVC = 0x1, 80 MALONE_FMT_MP2 = 0x2, 81 MALONE_FMT_VC1 = 0x3, 82 MALONE_FMT_AVS = 0x4, 83 MALONE_FMT_ASP = 0x5, 84 MALONE_FMT_JPG = 0x6, 85 MALONE_FMT_RV = 0x7, 86 MALONE_FMT_VP6 = 0x8, 87 MALONE_FMT_SPK = 0x9, 88 MALONE_FMT_VP8 = 0xA, 89 MALONE_FMT_HEVC = 0xB, 90 MALONE_FMT_LAST = MALONE_FMT_HEVC 91 }; 92 93 enum { 94 VID_API_CMD_NULL = 0x00, 95 VID_API_CMD_PARSE_NEXT_SEQ = 0x01, 96 VID_API_CMD_PARSE_NEXT_I = 0x02, 97 VID_API_CMD_PARSE_NEXT_IP = 0x03, 98 VID_API_CMD_PARSE_NEXT_ANY = 0x04, 99 VID_API_CMD_DEC_PIC = 0x05, 100 VID_API_CMD_UPDATE_ES_WR_PTR = 0x06, 101 VID_API_CMD_UPDATE_ES_RD_PTR = 0x07, 102 VID_API_CMD_UPDATE_UDATA = 0x08, 103 VID_API_CMD_GET_FSINFO = 0x09, 104 VID_API_CMD_SKIP_PIC = 0x0a, 105 VID_API_CMD_DEC_CHUNK = 0x0b, 106 VID_API_CMD_START = 0x10, 107 VID_API_CMD_STOP = 0x11, 108 VID_API_CMD_ABORT = 0x12, 109 VID_API_CMD_RST_BUF = 0x13, 110 VID_API_CMD_FS_RELEASE = 0x15, 111 VID_API_CMD_MEM_REGION_ATTACH = 0x16, 112 VID_API_CMD_MEM_REGION_DETACH = 0x17, 113 VID_API_CMD_MVC_VIEW_SELECT = 0x18, 114 VID_API_CMD_FS_ALLOC = 0x19, 115 VID_API_CMD_DBG_GET_STATUS = 0x1C, 116 VID_API_CMD_DBG_START_LOG = 0x1D, 117 VID_API_CMD_DBG_STOP_LOG = 0x1E, 118 VID_API_CMD_DBG_DUMP_LOG = 0x1F, 119 VID_API_CMD_YUV_READY = 0x20, 120 VID_API_CMD_TS = 0x21, 121 122 VID_API_CMD_FIRM_RESET = 0x40, 123 124 VID_API_CMD_SNAPSHOT = 0xAA, 125 VID_API_CMD_ROLL_SNAPSHOT = 0xAB, 126 VID_API_CMD_LOCK_SCHEDULER = 0xAC, 127 VID_API_CMD_UNLOCK_SCHEDULER = 0xAD, 128 VID_API_CMD_CQ_FIFO_DUMP = 0xAE, 129 VID_API_CMD_DBG_FIFO_DUMP = 0xAF, 130 VID_API_CMD_SVC_ILP = 0xBB, 131 VID_API_CMD_FW_STATUS = 0xF0, 132 VID_API_CMD_INVALID = 0xFF 133 }; 134 135 enum { 136 VID_API_EVENT_NULL = 0x00, 137 VID_API_EVENT_RESET_DONE = 0x01, 138 VID_API_EVENT_SEQ_HDR_FOUND = 0x02, 139 VID_API_EVENT_PIC_HDR_FOUND = 0x03, 140 VID_API_EVENT_PIC_DECODED = 0x04, 141 VID_API_EVENT_FIFO_LOW = 0x05, 142 VID_API_EVENT_FIFO_HIGH = 0x06, 143 VID_API_EVENT_FIFO_EMPTY = 0x07, 144 VID_API_EVENT_FIFO_FULL = 0x08, 145 VID_API_EVENT_BS_ERROR = 0x09, 146 VID_API_EVENT_UDATA_FIFO_UPTD = 0x0A, 147 VID_API_EVENT_RES_CHANGE = 0x0B, 148 VID_API_EVENT_FIFO_OVF = 0x0C, 149 VID_API_EVENT_CHUNK_DECODED = 0x0D, 150 VID_API_EVENT_REQ_FRAME_BUFF = 0x10, 151 VID_API_EVENT_FRAME_BUFF_RDY = 0x11, 152 VID_API_EVENT_REL_FRAME_BUFF = 0x12, 153 VID_API_EVENT_STR_BUF_RST = 0x13, 154 VID_API_EVENT_RET_PING = 0x14, 155 VID_API_EVENT_QMETER = 0x15, 156 VID_API_EVENT_STR_FMT_CHANGE = 0x16, 157 VID_API_EVENT_FIRMWARE_XCPT = 0x17, 158 VID_API_EVENT_START_DONE = 0x18, 159 VID_API_EVENT_STOPPED = 0x19, 160 VID_API_EVENT_ABORT_DONE = 0x1A, 161 VID_API_EVENT_FINISHED = 0x1B, 162 VID_API_EVENT_DBG_STAT_UPDATE = 0x1C, 163 VID_API_EVENT_DBG_LOG_STARTED = 0x1D, 164 VID_API_EVENT_DBG_LOG_STOPPED = 0x1E, 165 VID_API_EVENT_DBG_LOG_UPDATED = 0x1F, 166 VID_API_EVENT_DBG_MSG_DEC = 0x20, 167 VID_API_EVENT_DEC_SC_ERR = 0x21, 168 VID_API_EVENT_CQ_FIFO_DUMP = 0x22, 169 VID_API_EVENT_DBG_FIFO_DUMP = 0x23, 170 VID_API_EVENT_DEC_CHECK_RES = 0x24, 171 VID_API_EVENT_DEC_CFG_INFO = 0x25, 172 VID_API_EVENT_UNSUPPORTED_STREAM = 0x26, 173 VID_API_EVENT_PIC_SKIPPED = 0x27, 174 VID_API_EVENT_STR_SUSPENDED = 0x30, 175 VID_API_EVENT_SNAPSHOT_DONE = 0x40, 176 VID_API_EVENT_FW_STATUS = 0xF0, 177 VID_API_EVENT_INVALID = 0xFF 178 }; 179 180 struct vpu_malone_buffer_desc { 181 struct vpu_rpc_buffer_desc buffer; 182 u32 low; 183 u32 high; 184 }; 185 186 struct vpu_malone_str_buffer { 187 u32 wptr; 188 u32 rptr; 189 u32 start; 190 u32 end; 191 u32 lwm; 192 }; 193 194 struct vpu_malone_picth_info { 195 u32 frame_pitch; 196 }; 197 198 struct vpu_malone_table_desc { 199 u32 array_base; 200 u32 size; 201 }; 202 203 struct vpu_malone_dbglog_desc { 204 u32 addr; 205 u32 size; 206 u32 level; 207 u32 reserved; 208 }; 209 210 struct vpu_malone_frame_buffer { 211 u32 addr; 212 u32 size; 213 }; 214 215 struct vpu_malone_udata { 216 u32 base; 217 u32 total_size; 218 u32 slot_size; 219 }; 220 221 struct vpu_malone_buffer_info { 222 u32 stream_input_mode; 223 u32 stream_pic_input_count; 224 u32 stream_pic_parsed_count; 225 u32 stream_buffer_threshold; 226 u32 stream_pic_end_flag; 227 }; 228 229 struct vpu_malone_encrypt_info { 230 u32 rec4key[8]; 231 u32 obfusc; 232 }; 233 234 struct malone_iface { 235 u32 exec_base_addr; 236 u32 exec_area_size; 237 struct vpu_malone_buffer_desc cmd_buffer_desc; 238 struct vpu_malone_buffer_desc msg_buffer_desc; 239 u32 cmd_int_enable[VID_API_NUM_STREAMS]; 240 struct vpu_malone_picth_info stream_pitch_info[VID_API_NUM_STREAMS]; 241 u32 stream_config[VID_API_NUM_STREAMS]; 242 struct vpu_malone_table_desc codec_param_tab_desc; 243 struct vpu_malone_table_desc jpeg_param_tab_desc; 244 u32 stream_buffer_desc[VID_API_NUM_STREAMS][VID_API_MAX_BUF_PER_STR]; 245 struct vpu_malone_table_desc seq_info_tab_desc; 246 struct vpu_malone_table_desc pic_info_tab_desc; 247 struct vpu_malone_table_desc gop_info_tab_desc; 248 struct vpu_malone_table_desc qmeter_info_tab_desc; 249 u32 stream_error[VID_API_NUM_STREAMS]; 250 u32 fw_version; 251 u32 fw_offset; 252 u32 max_streams; 253 struct vpu_malone_dbglog_desc dbglog_desc; 254 struct vpu_rpc_buffer_desc api_cmd_buffer_desc[VID_API_NUM_STREAMS]; 255 struct vpu_malone_udata udata_buffer[VID_API_NUM_STREAMS]; 256 struct vpu_malone_buffer_desc debug_buffer_desc; 257 struct vpu_malone_buffer_desc eng_access_buff_desc[VID_API_NUM_STREAMS]; 258 u32 encrypt_info[VID_API_NUM_STREAMS]; 259 struct vpu_rpc_system_config system_cfg; 260 u32 api_version; 261 struct vpu_malone_buffer_info stream_buff_info[VID_API_NUM_STREAMS]; 262 }; 263 264 struct malone_jpg_params { 265 u32 rotation_angle; 266 u32 horiz_scale_factor; 267 u32 vert_scale_factor; 268 u32 rotation_mode; 269 u32 rgb_mode; 270 u32 chunk_mode; /* 0 ~ 1 */ 271 u32 last_chunk; /* 0 ~ 1 */ 272 u32 chunk_rows; /* 0 ~ 255 */ 273 u32 num_bytes; 274 u32 jpg_crop_x; 275 u32 jpg_crop_y; 276 u32 jpg_crop_width; 277 u32 jpg_crop_height; 278 u32 jpg_mjpeg_mode; 279 u32 jpg_mjpeg_interlaced; 280 }; 281 282 struct malone_codec_params { 283 u32 disp_imm; 284 u32 fourcc; 285 u32 codec_version; 286 u32 frame_rate; 287 u32 dbglog_enable; 288 u32 bsdma_lwm; 289 u32 bbd_coring; 290 u32 bbd_s_thr_row; 291 u32 bbd_p_thr_row; 292 u32 bbd_s_thr_logo_row; 293 u32 bbd_p_thr_logo_row; 294 u32 bbd_s_thr_col; 295 u32 bbd_p_thr_col; 296 u32 bbd_chr_thr_row; 297 u32 bbd_chr_thr_col; 298 u32 bbd_uv_mid_level; 299 u32 bbd_excl_win_mb_left; 300 u32 bbd_excl_win_mb_right; 301 }; 302 303 struct malone_padding_scode { 304 u32 scode_type; 305 u32 pixelformat; 306 u32 data[2]; 307 }; 308 309 struct malone_fmt_mapping { 310 u32 pixelformat; 311 enum vpu_malone_format malone_format; 312 u32 is_disabled; 313 }; 314 315 struct malone_scode_t { 316 struct vpu_inst *inst; 317 struct vb2_buffer *vb; 318 u32 wptr; 319 u32 need_data; 320 }; 321 322 struct malone_scode_handler { 323 u32 pixelformat; 324 int (*insert_scode_seq)(struct malone_scode_t *scode); 325 int (*insert_scode_pic)(struct malone_scode_t *scode); 326 }; 327 328 struct vpu_dec_ctrl { 329 struct malone_codec_params *codec_param; 330 struct malone_jpg_params *jpg; 331 void *seq_mem; 332 void *pic_mem; 333 void *gop_mem; 334 void *qmeter_mem; 335 void *dbglog_mem; 336 struct vpu_malone_str_buffer __iomem *str_buf[VID_API_NUM_STREAMS]; 337 u32 buf_addr[VID_API_NUM_STREAMS]; 338 }; 339 340 u32 vpu_malone_get_data_size(void) 341 { 342 return sizeof(struct vpu_dec_ctrl); 343 } 344 345 void vpu_malone_init_rpc(struct vpu_shared_addr *shared, 346 struct vpu_buffer *rpc, dma_addr_t boot_addr) 347 { 348 struct malone_iface *iface; 349 struct vpu_dec_ctrl *hc; 350 unsigned long base_phy_addr; 351 unsigned long phy_addr; 352 unsigned long offset; 353 unsigned int i; 354 355 if (rpc->phys < boot_addr) 356 return; 357 358 iface = rpc->virt; 359 base_phy_addr = rpc->phys - boot_addr; 360 hc = shared->priv; 361 362 shared->iface = iface; 363 shared->boot_addr = boot_addr; 364 365 iface->exec_base_addr = base_phy_addr; 366 iface->exec_area_size = rpc->length; 367 368 offset = sizeof(struct malone_iface); 369 phy_addr = base_phy_addr + offset; 370 371 shared->cmd_desc = &iface->cmd_buffer_desc.buffer; 372 shared->cmd_mem_vir = rpc->virt + offset; 373 iface->cmd_buffer_desc.buffer.start = 374 iface->cmd_buffer_desc.buffer.rptr = 375 iface->cmd_buffer_desc.buffer.wptr = phy_addr; 376 iface->cmd_buffer_desc.buffer.end = iface->cmd_buffer_desc.buffer.start + CMD_SIZE; 377 offset += CMD_SIZE; 378 phy_addr = base_phy_addr + offset; 379 380 shared->msg_desc = &iface->msg_buffer_desc.buffer; 381 shared->msg_mem_vir = rpc->virt + offset; 382 iface->msg_buffer_desc.buffer.start = 383 iface->msg_buffer_desc.buffer.wptr = 384 iface->msg_buffer_desc.buffer.rptr = phy_addr; 385 iface->msg_buffer_desc.buffer.end = iface->msg_buffer_desc.buffer.start + MSG_SIZE; 386 offset += MSG_SIZE; 387 phy_addr = base_phy_addr + offset; 388 389 iface->codec_param_tab_desc.array_base = phy_addr; 390 hc->codec_param = rpc->virt + offset; 391 offset += CODEC_SIZE; 392 phy_addr = base_phy_addr + offset; 393 394 iface->jpeg_param_tab_desc.array_base = phy_addr; 395 hc->jpg = rpc->virt + offset; 396 offset += JPEG_SIZE; 397 phy_addr = base_phy_addr + offset; 398 399 iface->seq_info_tab_desc.array_base = phy_addr; 400 hc->seq_mem = rpc->virt + offset; 401 offset += SEQ_SIZE; 402 phy_addr = base_phy_addr + offset; 403 404 iface->pic_info_tab_desc.array_base = phy_addr; 405 hc->pic_mem = rpc->virt + offset; 406 offset += PIC_SIZE; 407 phy_addr = base_phy_addr + offset; 408 409 iface->gop_info_tab_desc.array_base = phy_addr; 410 hc->gop_mem = rpc->virt + offset; 411 offset += GOP_SIZE; 412 phy_addr = base_phy_addr + offset; 413 414 iface->qmeter_info_tab_desc.array_base = phy_addr; 415 hc->qmeter_mem = rpc->virt + offset; 416 offset += QMETER_SIZE; 417 phy_addr = base_phy_addr + offset; 418 419 iface->dbglog_desc.addr = phy_addr; 420 iface->dbglog_desc.size = DBGLOG_SIZE; 421 hc->dbglog_mem = rpc->virt + offset; 422 offset += DBGLOG_SIZE; 423 phy_addr = base_phy_addr + offset; 424 425 for (i = 0; i < VID_API_NUM_STREAMS; i++) { 426 iface->eng_access_buff_desc[i].buffer.start = 427 iface->eng_access_buff_desc[i].buffer.wptr = 428 iface->eng_access_buff_desc[i].buffer.rptr = phy_addr; 429 iface->eng_access_buff_desc[i].buffer.end = 430 iface->eng_access_buff_desc[i].buffer.start + ENG_SIZE; 431 offset += ENG_SIZE; 432 phy_addr = base_phy_addr + offset; 433 } 434 435 for (i = 0; i < VID_API_NUM_STREAMS; i++) { 436 iface->encrypt_info[i] = phy_addr; 437 offset += sizeof(struct vpu_malone_encrypt_info); 438 phy_addr = base_phy_addr + offset; 439 } 440 441 rpc->bytesused = offset; 442 } 443 444 void vpu_malone_set_log_buf(struct vpu_shared_addr *shared, 445 struct vpu_buffer *log) 446 { 447 struct malone_iface *iface = shared->iface; 448 449 iface->debug_buffer_desc.buffer.start = 450 iface->debug_buffer_desc.buffer.wptr = 451 iface->debug_buffer_desc.buffer.rptr = log->phys - shared->boot_addr; 452 iface->debug_buffer_desc.buffer.end = iface->debug_buffer_desc.buffer.start + log->length; 453 } 454 455 static u32 get_str_buffer_offset(u32 instance) 456 { 457 return DEC_MFD_XREG_SLV_BASE + MFD_MCX + MFD_MCX_OFF * instance; 458 } 459 460 void vpu_malone_set_system_cfg(struct vpu_shared_addr *shared, 461 u32 regs_base, void __iomem *regs, u32 core_id) 462 { 463 struct malone_iface *iface = shared->iface; 464 struct vpu_rpc_system_config *config = &iface->system_cfg; 465 struct vpu_dec_ctrl *hc = shared->priv; 466 int i; 467 468 vpu_imx8q_set_system_cfg_common(config, regs_base, core_id); 469 for (i = 0; i < VID_API_NUM_STREAMS; i++) { 470 u32 offset = get_str_buffer_offset(i); 471 472 hc->buf_addr[i] = regs_base + offset; 473 hc->str_buf[i] = regs + offset; 474 } 475 } 476 477 u32 vpu_malone_get_version(struct vpu_shared_addr *shared) 478 { 479 struct malone_iface *iface = shared->iface; 480 481 return iface->fw_version; 482 } 483 484 int vpu_malone_get_stream_buffer_size(struct vpu_shared_addr *shared) 485 { 486 return 0xc00000; 487 } 488 489 int vpu_malone_config_stream_buffer(struct vpu_shared_addr *shared, 490 u32 instance, 491 struct vpu_buffer *buf) 492 { 493 struct malone_iface *iface = shared->iface; 494 struct vpu_dec_ctrl *hc = shared->priv; 495 struct vpu_malone_str_buffer __iomem *str_buf = hc->str_buf[instance]; 496 497 writel(buf->phys, &str_buf->start); 498 writel(buf->phys, &str_buf->rptr); 499 writel(buf->phys, &str_buf->wptr); 500 writel(buf->phys + buf->length, &str_buf->end); 501 writel(0x1, &str_buf->lwm); 502 503 iface->stream_buffer_desc[instance][0] = hc->buf_addr[instance]; 504 505 return 0; 506 } 507 508 int vpu_malone_get_stream_buffer_desc(struct vpu_shared_addr *shared, 509 u32 instance, 510 struct vpu_rpc_buffer_desc *desc) 511 { 512 struct vpu_dec_ctrl *hc = shared->priv; 513 struct vpu_malone_str_buffer __iomem *str_buf = hc->str_buf[instance]; 514 515 if (desc) { 516 desc->wptr = readl(&str_buf->wptr); 517 desc->rptr = readl(&str_buf->rptr); 518 desc->start = readl(&str_buf->start); 519 desc->end = readl(&str_buf->end); 520 } 521 522 return 0; 523 } 524 525 static void vpu_malone_update_wptr(struct vpu_malone_str_buffer __iomem *str_buf, u32 wptr) 526 { 527 /*update wptr after data is written*/ 528 mb(); 529 writel(wptr, &str_buf->wptr); 530 } 531 532 static void vpu_malone_update_rptr(struct vpu_malone_str_buffer __iomem *str_buf, u32 rptr) 533 { 534 /*update rptr after data is read*/ 535 mb(); 536 writel(rptr, &str_buf->rptr); 537 } 538 539 int vpu_malone_update_stream_buffer(struct vpu_shared_addr *shared, 540 u32 instance, u32 ptr, bool write) 541 { 542 struct vpu_dec_ctrl *hc = shared->priv; 543 struct vpu_malone_str_buffer __iomem *str_buf = hc->str_buf[instance]; 544 545 if (write) 546 vpu_malone_update_wptr(str_buf, ptr); 547 else 548 vpu_malone_update_rptr(str_buf, ptr); 549 550 return 0; 551 } 552 553 static struct malone_fmt_mapping fmt_mappings[] = { 554 {V4L2_PIX_FMT_H264, MALONE_FMT_AVC}, 555 {V4L2_PIX_FMT_H264_MVC, MALONE_FMT_AVC}, 556 {V4L2_PIX_FMT_HEVC, MALONE_FMT_HEVC}, 557 {V4L2_PIX_FMT_VC1_ANNEX_G, MALONE_FMT_VC1}, 558 {V4L2_PIX_FMT_VC1_ANNEX_L, MALONE_FMT_VC1}, 559 {V4L2_PIX_FMT_MPEG2, MALONE_FMT_MP2}, 560 {V4L2_PIX_FMT_MPEG4, MALONE_FMT_ASP}, 561 {V4L2_PIX_FMT_XVID, MALONE_FMT_ASP}, 562 {V4L2_PIX_FMT_H263, MALONE_FMT_ASP}, 563 {V4L2_PIX_FMT_JPEG, MALONE_FMT_JPG}, 564 {V4L2_PIX_FMT_VP8, MALONE_FMT_VP8}, 565 }; 566 567 static enum vpu_malone_format vpu_malone_format_remap(u32 pixelformat) 568 { 569 u32 i; 570 571 for (i = 0; i < ARRAY_SIZE(fmt_mappings); i++) { 572 if (fmt_mappings[i].is_disabled) 573 continue; 574 if (pixelformat == fmt_mappings[i].pixelformat) 575 return fmt_mappings[i].malone_format; 576 } 577 578 return MALONE_FMT_NULL; 579 } 580 581 bool vpu_malone_check_fmt(enum vpu_core_type type, u32 pixelfmt) 582 { 583 if (!vpu_imx8q_check_fmt(type, pixelfmt)) 584 return false; 585 586 if (pixelfmt == V4L2_PIX_FMT_NV12M_8L128 || pixelfmt == V4L2_PIX_FMT_NV12M_10BE_8L128) 587 return true; 588 if (vpu_malone_format_remap(pixelfmt) == MALONE_FMT_NULL) 589 return false; 590 591 return true; 592 } 593 594 static void vpu_malone_set_stream_cfg(struct vpu_shared_addr *shared, 595 u32 instance, 596 enum vpu_malone_format malone_format) 597 { 598 struct malone_iface *iface = shared->iface; 599 u32 *curr_str_cfg = &iface->stream_config[instance]; 600 601 *curr_str_cfg = 0; 602 STREAM_CONFIG_FORMAT_SET(malone_format, curr_str_cfg); 603 STREAM_CONFIG_STRBUFIDX_SET(0, curr_str_cfg); 604 STREAM_CONFIG_NOSEQ_SET(0, curr_str_cfg); 605 STREAM_CONFIG_DEBLOCK_SET(0, curr_str_cfg); 606 STREAM_CONFIG_DERING_SET(0, curr_str_cfg); 607 STREAM_CONFIG_PLAY_MODE_SET(0x3, curr_str_cfg); 608 STREAM_CONFIG_FS_CTRL_MODE_SET(0x1, curr_str_cfg); 609 STREAM_CONFIG_ENABLE_DCP_SET(1, curr_str_cfg); 610 STREAM_CONFIG_NUM_STR_BUF_SET(1, curr_str_cfg); 611 STREAM_CONFIG_MALONE_USAGE_SET(1, curr_str_cfg); 612 STREAM_CONFIG_MULTI_VID_SET(0, curr_str_cfg); 613 STREAM_CONFIG_OBFUSC_EN_SET(0, curr_str_cfg); 614 STREAM_CONFIG_RC4_EN_SET(0, curr_str_cfg); 615 STREAM_CONFIG_MCX_SET(1, curr_str_cfg); 616 STREAM_CONFIG_PES_SET(0, curr_str_cfg); 617 STREAM_CONFIG_NUM_DBE_SET(1, curr_str_cfg); 618 } 619 620 static int vpu_malone_set_params(struct vpu_shared_addr *shared, 621 u32 instance, 622 struct vpu_decode_params *params) 623 { 624 struct malone_iface *iface = shared->iface; 625 struct vpu_dec_ctrl *hc = shared->priv; 626 enum vpu_malone_format malone_format; 627 628 malone_format = vpu_malone_format_remap(params->codec_format); 629 iface->udata_buffer[instance].base = params->udata.base; 630 iface->udata_buffer[instance].slot_size = params->udata.size; 631 632 vpu_malone_set_stream_cfg(shared, instance, malone_format); 633 634 if (malone_format == MALONE_FMT_JPG) { 635 //1:JPGD_MJPEG_MODE_A; 2:JPGD_MJPEG_MODE_B 636 hc->jpg[instance].jpg_mjpeg_mode = 1; 637 //0: JPGD_MJPEG_PROGRESSIVE 638 hc->jpg[instance].jpg_mjpeg_interlaced = 0; 639 } 640 641 hc->codec_param[instance].disp_imm = params->b_dis_reorder ? 1 : 0; 642 hc->codec_param[instance].dbglog_enable = 0; 643 iface->dbglog_desc.level = 0; 644 645 if (params->b_non_frame) 646 iface->stream_buff_info[instance].stream_input_mode = NON_FRAME_LVL; 647 else 648 iface->stream_buff_info[instance].stream_input_mode = FRAME_LVL; 649 iface->stream_buff_info[instance].stream_buffer_threshold = 0; 650 iface->stream_buff_info[instance].stream_pic_input_count = 0; 651 652 return 0; 653 } 654 655 static bool vpu_malone_is_non_frame_mode(struct vpu_shared_addr *shared, u32 instance) 656 { 657 struct malone_iface *iface = shared->iface; 658 659 if (iface->stream_buff_info[instance].stream_input_mode == NON_FRAME_LVL) 660 return true; 661 662 return false; 663 } 664 665 static int vpu_malone_update_params(struct vpu_shared_addr *shared, 666 u32 instance, 667 struct vpu_decode_params *params) 668 { 669 struct malone_iface *iface = shared->iface; 670 671 if (params->end_flag) 672 iface->stream_buff_info[instance].stream_pic_end_flag = params->end_flag; 673 params->end_flag = 0; 674 675 return 0; 676 } 677 678 int vpu_malone_set_decode_params(struct vpu_shared_addr *shared, 679 u32 instance, 680 struct vpu_decode_params *params, 681 u32 update) 682 { 683 if (!params) 684 return -EINVAL; 685 686 if (!update) 687 return vpu_malone_set_params(shared, instance, params); 688 else 689 return vpu_malone_update_params(shared, instance, params); 690 } 691 692 static struct vpu_pair malone_cmds[] = { 693 {VPU_CMD_ID_START, VID_API_CMD_START}, 694 {VPU_CMD_ID_STOP, VID_API_CMD_STOP}, 695 {VPU_CMD_ID_ABORT, VID_API_CMD_ABORT}, 696 {VPU_CMD_ID_RST_BUF, VID_API_CMD_RST_BUF}, 697 {VPU_CMD_ID_SNAPSHOT, VID_API_CMD_SNAPSHOT}, 698 {VPU_CMD_ID_FIRM_RESET, VID_API_CMD_FIRM_RESET}, 699 {VPU_CMD_ID_FS_ALLOC, VID_API_CMD_FS_ALLOC}, 700 {VPU_CMD_ID_FS_RELEASE, VID_API_CMD_FS_RELEASE}, 701 {VPU_CMD_ID_TIMESTAMP, VID_API_CMD_TS}, 702 {VPU_CMD_ID_DEBUG, VID_API_CMD_FW_STATUS}, 703 }; 704 705 static struct vpu_pair malone_msgs[] = { 706 {VPU_MSG_ID_RESET_DONE, VID_API_EVENT_RESET_DONE}, 707 {VPU_MSG_ID_START_DONE, VID_API_EVENT_START_DONE}, 708 {VPU_MSG_ID_STOP_DONE, VID_API_EVENT_STOPPED}, 709 {VPU_MSG_ID_ABORT_DONE, VID_API_EVENT_ABORT_DONE}, 710 {VPU_MSG_ID_BUF_RST, VID_API_EVENT_STR_BUF_RST}, 711 {VPU_MSG_ID_PIC_EOS, VID_API_EVENT_FINISHED}, 712 {VPU_MSG_ID_SEQ_HDR_FOUND, VID_API_EVENT_SEQ_HDR_FOUND}, 713 {VPU_MSG_ID_RES_CHANGE, VID_API_EVENT_RES_CHANGE}, 714 {VPU_MSG_ID_PIC_HDR_FOUND, VID_API_EVENT_PIC_HDR_FOUND}, 715 {VPU_MSG_ID_PIC_DECODED, VID_API_EVENT_PIC_DECODED}, 716 {VPU_MSG_ID_DEC_DONE, VID_API_EVENT_FRAME_BUFF_RDY}, 717 {VPU_MSG_ID_FRAME_REQ, VID_API_EVENT_REQ_FRAME_BUFF}, 718 {VPU_MSG_ID_FRAME_RELEASE, VID_API_EVENT_REL_FRAME_BUFF}, 719 {VPU_MSG_ID_FIFO_LOW, VID_API_EVENT_FIFO_LOW}, 720 {VPU_MSG_ID_BS_ERROR, VID_API_EVENT_BS_ERROR}, 721 {VPU_MSG_ID_UNSUPPORTED, VID_API_EVENT_UNSUPPORTED_STREAM}, 722 {VPU_MSG_ID_FIRMWARE_XCPT, VID_API_EVENT_FIRMWARE_XCPT}, 723 {VPU_MSG_ID_PIC_SKIPPED, VID_API_EVENT_PIC_SKIPPED}, 724 }; 725 726 static void vpu_malone_pack_fs_alloc(struct vpu_rpc_event *pkt, 727 struct vpu_fs_info *fs) 728 { 729 const u32 fs_type[] = { 730 [MEM_RES_FRAME] = 0, 731 [MEM_RES_MBI] = 1, 732 [MEM_RES_DCP] = 2, 733 }; 734 735 pkt->hdr.num = 7; 736 pkt->data[0] = fs->id | (fs->tag << 24); 737 pkt->data[1] = fs->luma_addr; 738 if (fs->type == MEM_RES_FRAME) { 739 /* 740 * if luma_addr equal to chroma_addr, 741 * means luma(plane[0]) and chromau(plane[1]) used the 742 * same fd -- usage of NXP codec2. Need to manually 743 * offset chroma addr. 744 */ 745 if (fs->luma_addr == fs->chroma_addr) 746 fs->chroma_addr = fs->luma_addr + fs->luma_size; 747 pkt->data[2] = fs->luma_addr + fs->luma_size / 2; 748 pkt->data[3] = fs->chroma_addr; 749 pkt->data[4] = fs->chroma_addr + fs->chromau_size / 2; 750 pkt->data[5] = fs->bytesperline; 751 } else { 752 pkt->data[2] = fs->luma_size; 753 pkt->data[3] = 0; 754 pkt->data[4] = 0; 755 pkt->data[5] = 0; 756 } 757 pkt->data[6] = fs_type[fs->type]; 758 } 759 760 static void vpu_malone_pack_fs_release(struct vpu_rpc_event *pkt, 761 struct vpu_fs_info *fs) 762 { 763 pkt->hdr.num = 1; 764 pkt->data[0] = fs->id | (fs->tag << 24); 765 } 766 767 static void vpu_malone_pack_timestamp(struct vpu_rpc_event *pkt, 768 struct vpu_ts_info *info) 769 { 770 struct timespec64 ts = ns_to_timespec64(info->timestamp); 771 772 pkt->hdr.num = 3; 773 774 pkt->data[0] = ts.tv_sec; 775 pkt->data[1] = ts.tv_nsec; 776 pkt->data[2] = info->size; 777 } 778 779 int vpu_malone_pack_cmd(struct vpu_rpc_event *pkt, u32 index, u32 id, void *data) 780 { 781 int ret; 782 783 ret = vpu_find_dst_by_src(malone_cmds, ARRAY_SIZE(malone_cmds), id); 784 if (ret < 0) 785 return ret; 786 787 pkt->hdr.id = ret; 788 pkt->hdr.num = 0; 789 pkt->hdr.index = index; 790 791 switch (id) { 792 case VPU_CMD_ID_FS_ALLOC: 793 vpu_malone_pack_fs_alloc(pkt, data); 794 break; 795 case VPU_CMD_ID_FS_RELEASE: 796 vpu_malone_pack_fs_release(pkt, data); 797 break; 798 case VPU_CMD_ID_TIMESTAMP: 799 vpu_malone_pack_timestamp(pkt, data); 800 break; 801 } 802 803 pkt->hdr.index = index; 804 return 0; 805 } 806 807 int vpu_malone_convert_msg_id(u32 id) 808 { 809 return vpu_find_src_by_dst(malone_msgs, ARRAY_SIZE(malone_msgs), id); 810 } 811 812 static void vpu_malone_fill_planes(struct vpu_dec_codec_info *info) 813 { 814 u32 interlaced = info->progressive ? 0 : 1; 815 816 info->bytesperline[0] = 0; 817 info->sizeimage[0] = vpu_helper_get_plane_size(info->pixfmt, 818 info->decoded_width, 819 info->decoded_height, 820 0, 821 info->stride, 822 interlaced, 823 &info->bytesperline[0]); 824 info->bytesperline[1] = 0; 825 info->sizeimage[1] = vpu_helper_get_plane_size(info->pixfmt, 826 info->decoded_width, 827 info->decoded_height, 828 1, 829 info->stride, 830 interlaced, 831 &info->bytesperline[1]); 832 } 833 834 static void vpu_malone_init_seq_hdr(struct vpu_dec_codec_info *info) 835 { 836 u32 chunks = info->num_dfe_area >> MALONE_DCP_CHUNK_BIT; 837 838 vpu_malone_fill_planes(info); 839 840 info->mbi_size = (info->sizeimage[0] + info->sizeimage[1]) >> 2; 841 info->mbi_size = ALIGN(info->mbi_size, MALONE_ALIGN_MBI); 842 843 info->dcp_size = MALONE_DCP_SIZE_MAX; 844 if (chunks) { 845 u32 mb_num; 846 u32 mb_w; 847 u32 mb_h; 848 849 mb_w = DIV_ROUND_UP(info->decoded_width, 16); 850 mb_h = DIV_ROUND_UP(info->decoded_height, 16); 851 mb_num = mb_w * mb_h; 852 info->dcp_size = mb_num * MALONE_DCP_FIXED_MB_ALLOC * chunks; 853 info->dcp_size = clamp_t(u32, info->dcp_size, 854 MALONE_DCP_SIZE_MIN, MALONE_DCP_SIZE_MAX); 855 } 856 } 857 858 static void vpu_malone_unpack_seq_hdr(struct vpu_rpc_event *pkt, 859 struct vpu_dec_codec_info *info) 860 { 861 info->num_ref_frms = pkt->data[0]; 862 info->num_dpb_frms = pkt->data[1]; 863 info->num_dfe_area = pkt->data[2]; 864 info->progressive = pkt->data[3]; 865 info->width = pkt->data[5]; 866 info->height = pkt->data[4]; 867 info->decoded_width = pkt->data[12]; 868 info->decoded_height = pkt->data[11]; 869 info->frame_rate.numerator = 1000; 870 info->frame_rate.denominator = pkt->data[8]; 871 info->dsp_asp_ratio = pkt->data[9]; 872 info->level_idc = pkt->data[10]; 873 info->bit_depth_luma = pkt->data[13]; 874 info->bit_depth_chroma = pkt->data[14]; 875 info->chroma_fmt = pkt->data[15]; 876 info->color_primaries = vpu_color_cvrt_primaries_i2v(pkt->data[16]); 877 info->transfer_chars = vpu_color_cvrt_transfers_i2v(pkt->data[17]); 878 info->matrix_coeffs = vpu_color_cvrt_matrix_i2v(pkt->data[18]); 879 info->full_range = vpu_color_cvrt_full_range_i2v(pkt->data[19]); 880 info->vui_present = pkt->data[20]; 881 info->mvc_num_views = pkt->data[21]; 882 info->offset_x = pkt->data[23]; 883 info->offset_y = pkt->data[25]; 884 info->tag = pkt->data[27]; 885 if (info->bit_depth_luma > 8) 886 info->pixfmt = V4L2_PIX_FMT_NV12M_10BE_8L128; 887 else 888 info->pixfmt = V4L2_PIX_FMT_NV12M_8L128; 889 if (info->frame_rate.numerator && info->frame_rate.denominator) { 890 unsigned long n, d; 891 892 rational_best_approximation(info->frame_rate.numerator, 893 info->frame_rate.denominator, 894 info->frame_rate.numerator, 895 info->frame_rate.denominator, 896 &n, &d); 897 info->frame_rate.numerator = n; 898 info->frame_rate.denominator = d; 899 } 900 vpu_malone_init_seq_hdr(info); 901 } 902 903 static void vpu_malone_unpack_pic_info(struct vpu_rpc_event *pkt, 904 struct vpu_dec_pic_info *info) 905 { 906 info->id = pkt->data[7]; 907 info->luma = pkt->data[0]; 908 info->start = pkt->data[10]; 909 info->end = pkt->data[12]; 910 info->pic_size = pkt->data[11]; 911 info->stride = pkt->data[5]; 912 info->consumed_count = pkt->data[13]; 913 if (info->id == MALONE_SKIPPED_FRAME_ID) 914 info->skipped = 1; 915 else 916 info->skipped = 0; 917 } 918 919 static void vpu_malone_unpack_req_frame(struct vpu_rpc_event *pkt, 920 struct vpu_fs_info *info) 921 { 922 info->type = pkt->data[1]; 923 } 924 925 static void vpu_malone_unpack_rel_frame(struct vpu_rpc_event *pkt, 926 struct vpu_fs_info *info) 927 { 928 info->id = pkt->data[0]; 929 info->type = pkt->data[1]; 930 info->not_displayed = pkt->data[2]; 931 } 932 933 static void vpu_malone_unpack_buff_rdy(struct vpu_rpc_event *pkt, 934 struct vpu_dec_pic_info *info) 935 { 936 struct timespec64 ts = { pkt->data[9], pkt->data[10] }; 937 938 info->id = pkt->data[0]; 939 info->luma = pkt->data[1]; 940 info->stride = pkt->data[3]; 941 if (info->id == MALONE_SKIPPED_FRAME_ID) 942 info->skipped = 1; 943 else 944 info->skipped = 0; 945 946 info->timestamp = timespec64_to_ns(&ts); 947 } 948 949 int vpu_malone_unpack_msg_data(struct vpu_rpc_event *pkt, void *data) 950 { 951 if (!pkt || !data) 952 return -EINVAL; 953 954 switch (pkt->hdr.id) { 955 case VID_API_EVENT_SEQ_HDR_FOUND: 956 vpu_malone_unpack_seq_hdr(pkt, data); 957 break; 958 case VID_API_EVENT_PIC_DECODED: 959 vpu_malone_unpack_pic_info(pkt, data); 960 break; 961 case VID_API_EVENT_REQ_FRAME_BUFF: 962 vpu_malone_unpack_req_frame(pkt, data); 963 break; 964 case VID_API_EVENT_REL_FRAME_BUFF: 965 vpu_malone_unpack_rel_frame(pkt, data); 966 break; 967 case VID_API_EVENT_FRAME_BUFF_RDY: 968 vpu_malone_unpack_buff_rdy(pkt, data); 969 break; 970 } 971 972 return 0; 973 } 974 975 static const struct malone_padding_scode padding_scodes[] = { 976 {SCODE_PADDING_EOS, V4L2_PIX_FMT_H264, {0x0B010000, 0}}, 977 {SCODE_PADDING_EOS, V4L2_PIX_FMT_H264_MVC, {0x0B010000, 0}}, 978 {SCODE_PADDING_EOS, V4L2_PIX_FMT_HEVC, {0x4A010000, 0x20}}, 979 {SCODE_PADDING_EOS, V4L2_PIX_FMT_VC1_ANNEX_G, {0x0a010000, 0x0}}, 980 {SCODE_PADDING_EOS, V4L2_PIX_FMT_VC1_ANNEX_L, {0x0a010000, 0x0}}, 981 {SCODE_PADDING_EOS, V4L2_PIX_FMT_MPEG2, {0xCC010000, 0x0}}, 982 {SCODE_PADDING_EOS, V4L2_PIX_FMT_MPEG4, {0xb1010000, 0x0}}, 983 {SCODE_PADDING_EOS, V4L2_PIX_FMT_XVID, {0xb1010000, 0x0}}, 984 {SCODE_PADDING_EOS, V4L2_PIX_FMT_H263, {0xb1010000, 0x0}}, 985 {SCODE_PADDING_EOS, V4L2_PIX_FMT_VP8, {0x34010000, 0x0}}, 986 {SCODE_PADDING_EOS, V4L2_PIX_FMT_JPEG, {0xefff0000, 0x0}}, 987 {SCODE_PADDING_ABORT, V4L2_PIX_FMT_H264, {0x0B010000, 0}}, 988 {SCODE_PADDING_ABORT, V4L2_PIX_FMT_H264_MVC, {0x0B010000, 0}}, 989 {SCODE_PADDING_ABORT, V4L2_PIX_FMT_HEVC, {0x4A010000, 0x20}}, 990 {SCODE_PADDING_ABORT, V4L2_PIX_FMT_VC1_ANNEX_G, {0x0a010000, 0x0}}, 991 {SCODE_PADDING_ABORT, V4L2_PIX_FMT_VC1_ANNEX_L, {0x0a010000, 0x0}}, 992 {SCODE_PADDING_ABORT, V4L2_PIX_FMT_MPEG2, {0xb7010000, 0x0}}, 993 {SCODE_PADDING_ABORT, V4L2_PIX_FMT_MPEG4, {0xb1010000, 0x0}}, 994 {SCODE_PADDING_ABORT, V4L2_PIX_FMT_XVID, {0xb1010000, 0x0}}, 995 {SCODE_PADDING_ABORT, V4L2_PIX_FMT_H263, {0xb1010000, 0x0}}, 996 {SCODE_PADDING_ABORT, V4L2_PIX_FMT_VP8, {0x34010000, 0x0}}, 997 {SCODE_PADDING_EOS, V4L2_PIX_FMT_JPEG, {0x0, 0x0}}, 998 {SCODE_PADDING_BUFFLUSH, V4L2_PIX_FMT_H264, {0x15010000, 0x0}}, 999 {SCODE_PADDING_BUFFLUSH, V4L2_PIX_FMT_H264_MVC, {0x15010000, 0x0}}, 1000 }; 1001 1002 static const struct malone_padding_scode padding_scode_dft = {0x0, 0x0}; 1003 1004 static const struct malone_padding_scode *get_padding_scode(u32 type, u32 fmt) 1005 { 1006 const struct malone_padding_scode *s; 1007 int i; 1008 1009 for (i = 0; i < ARRAY_SIZE(padding_scodes); i++) { 1010 s = &padding_scodes[i]; 1011 1012 if (s->scode_type == type && s->pixelformat == fmt) 1013 return s; 1014 } 1015 1016 if (type != SCODE_PADDING_BUFFLUSH) 1017 return &padding_scode_dft; 1018 1019 return NULL; 1020 } 1021 1022 static int vpu_malone_add_padding_scode(struct vpu_buffer *stream_buffer, 1023 struct vpu_malone_str_buffer __iomem *str_buf, 1024 u32 pixelformat, u32 scode_type) 1025 { 1026 u32 wptr; 1027 int size; 1028 int total_size = 0; 1029 const struct malone_padding_scode *ps; 1030 const u32 padding_size = 4096; 1031 int ret; 1032 1033 ps = get_padding_scode(scode_type, pixelformat); 1034 if (!ps) 1035 return -EINVAL; 1036 1037 wptr = readl(&str_buf->wptr); 1038 if (wptr < stream_buffer->phys || wptr > stream_buffer->phys + stream_buffer->length) 1039 return -EINVAL; 1040 if (wptr == stream_buffer->phys + stream_buffer->length) 1041 wptr = stream_buffer->phys; 1042 size = ALIGN(wptr, 4) - wptr; 1043 if (size) 1044 vpu_helper_memset_stream_buffer(stream_buffer, &wptr, 0, size); 1045 total_size += size; 1046 1047 size = sizeof(ps->data); 1048 ret = vpu_helper_copy_to_stream_buffer(stream_buffer, &wptr, size, (void *)ps->data); 1049 if (ret < 0) 1050 return -EINVAL; 1051 total_size += size; 1052 1053 size = padding_size - sizeof(ps->data); 1054 vpu_helper_memset_stream_buffer(stream_buffer, &wptr, 0, size); 1055 total_size += size; 1056 1057 vpu_malone_update_wptr(str_buf, wptr); 1058 return total_size; 1059 } 1060 1061 int vpu_malone_add_scode(struct vpu_shared_addr *shared, 1062 u32 instance, 1063 struct vpu_buffer *stream_buffer, 1064 u32 pixelformat, 1065 u32 scode_type) 1066 { 1067 struct vpu_dec_ctrl *hc = shared->priv; 1068 struct vpu_malone_str_buffer __iomem *str_buf = hc->str_buf[instance]; 1069 int ret = -EINVAL; 1070 1071 switch (scode_type) { 1072 case SCODE_PADDING_EOS: 1073 case SCODE_PADDING_ABORT: 1074 case SCODE_PADDING_BUFFLUSH: 1075 ret = vpu_malone_add_padding_scode(stream_buffer, str_buf, pixelformat, scode_type); 1076 break; 1077 default: 1078 break; 1079 } 1080 1081 return ret; 1082 } 1083 1084 #define MALONE_PAYLOAD_HEADER_SIZE 16 1085 #define MALONE_CODEC_VERSION_ID 0x1 1086 #define MALONE_CODEC_ID_VC1_SIMPLE 0x10 1087 #define MALONE_CODEC_ID_VC1_MAIN 0x11 1088 #define MALONE_CODEC_ID_ARV8 0x28 1089 #define MALONE_CODEC_ID_ARV9 0x29 1090 #define MALONE_CODEC_ID_VP6 0x36 1091 #define MALONE_CODEC_ID_VP8 0x36 1092 #define MALONE_CODEC_ID_DIVX3 0x38 1093 #define MALONE_CODEC_ID_SPK 0x39 1094 1095 #define MALONE_VP8_IVF_SEQ_HEADER_LEN 32 1096 #define MALONE_VP8_IVF_FRAME_HEADER_LEN 8 1097 1098 #define MALONE_VC1_RCV_CODEC_V1_VERSION 0x85 1099 #define MALONE_VC1_RCV_CODEC_V2_VERSION 0xC5 1100 #define MALONE_VC1_RCV_NUM_FRAMES 0xFF 1101 #define MALONE_VC1_RCV_SEQ_EXT_DATA_SIZE 4 1102 #define MALONE_VC1_RCV_SEQ_HEADER_LEN 20 1103 #define MALONE_VC1_RCV_PIC_HEADER_LEN 4 1104 #define MALONE_VC1_NAL_HEADER_LEN 4 1105 #define MALONE_VC1_CONTAIN_NAL(data) (((data) & 0x00FFFFFF) == 0x00010000) 1106 1107 static void set_payload_hdr(u8 *dst, u32 scd_type, u32 codec_id, 1108 u32 buffer_size, u32 width, u32 height) 1109 { 1110 unsigned int payload_size; 1111 /* payload_size = buffer_size + itself_size(16) - start_code(4) */ 1112 payload_size = buffer_size + 12; 1113 1114 dst[0] = 0x00; 1115 dst[1] = 0x00; 1116 dst[2] = 0x01; 1117 dst[3] = scd_type; 1118 1119 /* length */ 1120 dst[4] = ((payload_size >> 16) & 0xff); 1121 dst[5] = ((payload_size >> 8) & 0xff); 1122 dst[6] = 0x4e; 1123 dst[7] = ((payload_size >> 0) & 0xff); 1124 1125 /* Codec ID and Version */ 1126 dst[8] = codec_id; 1127 dst[9] = MALONE_CODEC_VERSION_ID; 1128 1129 /* width */ 1130 dst[10] = ((width >> 8) & 0xff); 1131 dst[11] = ((width >> 0) & 0xff); 1132 dst[12] = 0x58; 1133 1134 /* height */ 1135 dst[13] = ((height >> 8) & 0xff); 1136 dst[14] = ((height >> 0) & 0xff); 1137 dst[15] = 0x50; 1138 } 1139 1140 static void set_vp8_ivf_seqhdr(u8 *dst, u32 width, u32 height) 1141 { 1142 /* 0-3byte signature "DKIF" */ 1143 dst[0] = 0x44; 1144 dst[1] = 0x4b; 1145 dst[2] = 0x49; 1146 dst[3] = 0x46; 1147 /* 4-5byte version: should be 0*/ 1148 dst[4] = 0x00; 1149 dst[5] = 0x00; 1150 /* 6-7 length of Header */ 1151 dst[6] = MALONE_VP8_IVF_SEQ_HEADER_LEN; 1152 dst[7] = MALONE_VP8_IVF_SEQ_HEADER_LEN >> 8; 1153 /* 8-11 VP8 fourcc */ 1154 dst[8] = 0x56; 1155 dst[9] = 0x50; 1156 dst[10] = 0x38; 1157 dst[11] = 0x30; 1158 /* 12-13 width in pixels */ 1159 dst[12] = width; 1160 dst[13] = width >> 8; 1161 /* 14-15 height in pixels */ 1162 dst[14] = height; 1163 dst[15] = height >> 8; 1164 /* 16-19 frame rate */ 1165 dst[16] = 0xe8; 1166 dst[17] = 0x03; 1167 dst[18] = 0x00; 1168 dst[19] = 0x00; 1169 /* 20-23 time scale */ 1170 dst[20] = 0x01; 1171 dst[21] = 0x00; 1172 dst[22] = 0x00; 1173 dst[23] = 0x00; 1174 /* 24-27 number frames */ 1175 dst[24] = 0xdf; 1176 dst[25] = 0xf9; 1177 dst[26] = 0x09; 1178 dst[27] = 0x00; 1179 /* 28-31 reserved */ 1180 } 1181 1182 static void set_vp8_ivf_pichdr(u8 *dst, u32 frame_size) 1183 { 1184 /* 1185 * firmware just parse 64-bit timestamp(8 bytes). 1186 * As not transfer timestamp to firmware, use default value(ZERO). 1187 * No need to do anything here 1188 */ 1189 } 1190 1191 static void set_vc1_rcv_seqhdr(u8 *dst, u8 *src, u32 width, u32 height) 1192 { 1193 u32 frames = MALONE_VC1_RCV_NUM_FRAMES; 1194 u32 ext_data_size = MALONE_VC1_RCV_SEQ_EXT_DATA_SIZE; 1195 1196 /* 0-2 Number of frames, used default value 0xFF */ 1197 dst[0] = frames; 1198 dst[1] = frames >> 8; 1199 dst[2] = frames >> 16; 1200 1201 /* 3 RCV version, used V1 */ 1202 dst[3] = MALONE_VC1_RCV_CODEC_V1_VERSION; 1203 1204 /* 4-7 extension data size */ 1205 dst[4] = ext_data_size; 1206 dst[5] = ext_data_size >> 8; 1207 dst[6] = ext_data_size >> 16; 1208 dst[7] = ext_data_size >> 24; 1209 /* 8-11 extension data */ 1210 dst[8] = src[0]; 1211 dst[9] = src[1]; 1212 dst[10] = src[2]; 1213 dst[11] = src[3]; 1214 1215 /* height */ 1216 dst[12] = height; 1217 dst[13] = (height >> 8) & 0xff; 1218 dst[14] = (height >> 16) & 0xff; 1219 dst[15] = (height >> 24) & 0xff; 1220 /* width */ 1221 dst[16] = width; 1222 dst[17] = (width >> 8) & 0xff; 1223 dst[18] = (width >> 16) & 0xff; 1224 dst[19] = (width >> 24) & 0xff; 1225 } 1226 1227 static void set_vc1_rcv_pichdr(u8 *dst, u32 buffer_size) 1228 { 1229 dst[0] = buffer_size; 1230 dst[1] = buffer_size >> 8; 1231 dst[2] = buffer_size >> 16; 1232 dst[3] = buffer_size >> 24; 1233 } 1234 1235 static void create_vc1_nal_pichdr(u8 *dst) 1236 { 1237 /* need insert nal header: special ID */ 1238 dst[0] = 0x0; 1239 dst[1] = 0x0; 1240 dst[2] = 0x01; 1241 dst[3] = 0x0D; 1242 } 1243 1244 static int vpu_malone_insert_scode_seq(struct malone_scode_t *scode, u32 codec_id, u32 ext_size) 1245 { 1246 u8 hdr[MALONE_PAYLOAD_HEADER_SIZE]; 1247 int ret; 1248 1249 set_payload_hdr(hdr, 1250 SCODE_SEQUENCE, 1251 codec_id, 1252 ext_size, 1253 scode->inst->out_format.width, 1254 scode->inst->out_format.height); 1255 ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer, 1256 &scode->wptr, 1257 sizeof(hdr), 1258 hdr); 1259 if (ret < 0) 1260 return ret; 1261 return sizeof(hdr); 1262 } 1263 1264 static int vpu_malone_insert_scode_pic(struct malone_scode_t *scode, u32 codec_id, u32 ext_size) 1265 { 1266 u8 hdr[MALONE_PAYLOAD_HEADER_SIZE]; 1267 int ret; 1268 1269 set_payload_hdr(hdr, 1270 SCODE_PICTURE, 1271 codec_id, 1272 ext_size + vb2_get_plane_payload(scode->vb, 0), 1273 scode->inst->out_format.width, 1274 scode->inst->out_format.height); 1275 ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer, 1276 &scode->wptr, 1277 sizeof(hdr), 1278 hdr); 1279 if (ret < 0) 1280 return ret; 1281 return sizeof(hdr); 1282 } 1283 1284 static int vpu_malone_insert_scode_vc1_g_pic(struct malone_scode_t *scode) 1285 { 1286 struct vb2_v4l2_buffer *vbuf; 1287 u8 nal_hdr[MALONE_VC1_NAL_HEADER_LEN]; 1288 u32 *data = NULL; 1289 int ret; 1290 1291 vbuf = to_vb2_v4l2_buffer(scode->vb); 1292 data = vb2_plane_vaddr(scode->vb, 0); 1293 1294 if (vbuf->sequence == 0 || vpu_vb_is_codecconfig(vbuf)) 1295 return 0; 1296 if (MALONE_VC1_CONTAIN_NAL(*data)) 1297 return 0; 1298 1299 create_vc1_nal_pichdr(nal_hdr); 1300 ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer, 1301 &scode->wptr, 1302 sizeof(nal_hdr), 1303 nal_hdr); 1304 if (ret < 0) 1305 return ret; 1306 return sizeof(nal_hdr); 1307 } 1308 1309 static int vpu_malone_insert_scode_vc1_l_seq(struct malone_scode_t *scode) 1310 { 1311 int ret; 1312 int size = 0; 1313 u8 rcv_seqhdr[MALONE_VC1_RCV_SEQ_HEADER_LEN]; 1314 1315 scode->need_data = 0; 1316 1317 ret = vpu_malone_insert_scode_seq(scode, MALONE_CODEC_ID_VC1_SIMPLE, sizeof(rcv_seqhdr)); 1318 if (ret < 0) 1319 return ret; 1320 size = ret; 1321 1322 set_vc1_rcv_seqhdr(rcv_seqhdr, 1323 vb2_plane_vaddr(scode->vb, 0), 1324 scode->inst->out_format.width, 1325 scode->inst->out_format.height); 1326 ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer, 1327 &scode->wptr, 1328 sizeof(rcv_seqhdr), 1329 rcv_seqhdr); 1330 1331 if (ret < 0) 1332 return ret; 1333 size += sizeof(rcv_seqhdr); 1334 return size; 1335 } 1336 1337 static int vpu_malone_insert_scode_vc1_l_pic(struct malone_scode_t *scode) 1338 { 1339 int ret; 1340 int size = 0; 1341 u8 rcv_pichdr[MALONE_VC1_RCV_PIC_HEADER_LEN]; 1342 1343 ret = vpu_malone_insert_scode_pic(scode, MALONE_CODEC_ID_VC1_SIMPLE, 1344 sizeof(rcv_pichdr)); 1345 if (ret < 0) 1346 return ret; 1347 size = ret; 1348 1349 set_vc1_rcv_pichdr(rcv_pichdr, vb2_get_plane_payload(scode->vb, 0)); 1350 ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer, 1351 &scode->wptr, 1352 sizeof(rcv_pichdr), 1353 rcv_pichdr); 1354 if (ret < 0) 1355 return ret; 1356 size += sizeof(rcv_pichdr); 1357 return size; 1358 } 1359 1360 static int vpu_malone_insert_scode_vp8_seq(struct malone_scode_t *scode) 1361 { 1362 int ret; 1363 int size = 0; 1364 u8 ivf_hdr[MALONE_VP8_IVF_SEQ_HEADER_LEN]; 1365 1366 ret = vpu_malone_insert_scode_seq(scode, MALONE_CODEC_ID_VP8, sizeof(ivf_hdr)); 1367 if (ret < 0) 1368 return ret; 1369 size = ret; 1370 1371 set_vp8_ivf_seqhdr(ivf_hdr, 1372 scode->inst->out_format.width, 1373 scode->inst->out_format.height); 1374 ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer, 1375 &scode->wptr, 1376 sizeof(ivf_hdr), 1377 ivf_hdr); 1378 if (ret < 0) 1379 return ret; 1380 size += sizeof(ivf_hdr); 1381 1382 return size; 1383 } 1384 1385 static int vpu_malone_insert_scode_vp8_pic(struct malone_scode_t *scode) 1386 { 1387 int ret; 1388 int size = 0; 1389 u8 ivf_hdr[MALONE_VP8_IVF_FRAME_HEADER_LEN] = {0}; 1390 1391 ret = vpu_malone_insert_scode_pic(scode, MALONE_CODEC_ID_VP8, sizeof(ivf_hdr)); 1392 if (ret < 0) 1393 return ret; 1394 size = ret; 1395 1396 set_vp8_ivf_pichdr(ivf_hdr, vb2_get_plane_payload(scode->vb, 0)); 1397 ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer, 1398 &scode->wptr, 1399 sizeof(ivf_hdr), 1400 ivf_hdr); 1401 if (ret < 0) 1402 return ret; 1403 size += sizeof(ivf_hdr); 1404 1405 return size; 1406 } 1407 1408 static const struct malone_scode_handler scode_handlers[] = { 1409 { 1410 /* fix me, need to swap return operation after gstreamer swap */ 1411 .pixelformat = V4L2_PIX_FMT_VC1_ANNEX_L, 1412 .insert_scode_seq = vpu_malone_insert_scode_vc1_l_seq, 1413 .insert_scode_pic = vpu_malone_insert_scode_vc1_l_pic, 1414 }, 1415 { 1416 .pixelformat = V4L2_PIX_FMT_VC1_ANNEX_G, 1417 .insert_scode_pic = vpu_malone_insert_scode_vc1_g_pic, 1418 }, 1419 { 1420 .pixelformat = V4L2_PIX_FMT_VP8, 1421 .insert_scode_seq = vpu_malone_insert_scode_vp8_seq, 1422 .insert_scode_pic = vpu_malone_insert_scode_vp8_pic, 1423 }, 1424 }; 1425 1426 static const struct malone_scode_handler *get_scode_handler(u32 pixelformat) 1427 { 1428 int i; 1429 1430 for (i = 0; i < ARRAY_SIZE(scode_handlers); i++) { 1431 if (scode_handlers[i].pixelformat == pixelformat) 1432 return &scode_handlers[i]; 1433 } 1434 1435 return NULL; 1436 } 1437 1438 static int vpu_malone_insert_scode(struct malone_scode_t *scode, u32 type) 1439 { 1440 const struct malone_scode_handler *handler; 1441 int ret = 0; 1442 1443 if (!scode || !scode->inst || !scode->vb) 1444 return 0; 1445 1446 scode->need_data = 1; 1447 handler = get_scode_handler(scode->inst->out_format.pixfmt); 1448 if (!handler) 1449 return 0; 1450 1451 switch (type) { 1452 case SCODE_SEQUENCE: 1453 if (handler->insert_scode_seq) 1454 ret = handler->insert_scode_seq(scode); 1455 break; 1456 case SCODE_PICTURE: 1457 if (handler->insert_scode_pic) 1458 ret = handler->insert_scode_pic(scode); 1459 break; 1460 default: 1461 break; 1462 } 1463 1464 return ret; 1465 } 1466 1467 static int vpu_malone_input_frame_data(struct vpu_malone_str_buffer __iomem *str_buf, 1468 struct vpu_inst *inst, struct vb2_buffer *vb, 1469 u32 disp_imm) 1470 { 1471 struct malone_scode_t scode; 1472 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); 1473 u32 wptr = readl(&str_buf->wptr); 1474 int size = 0; 1475 int ret = 0; 1476 1477 /*add scode: SCODE_SEQUENCE, SCODE_PICTURE, SCODE_SLICE*/ 1478 scode.inst = inst; 1479 scode.vb = vb; 1480 scode.wptr = wptr; 1481 scode.need_data = 1; 1482 if (vbuf->sequence == 0 || vpu_vb_is_codecconfig(vbuf)) 1483 ret = vpu_malone_insert_scode(&scode, SCODE_SEQUENCE); 1484 1485 if (ret < 0) 1486 return -ENOMEM; 1487 size += ret; 1488 wptr = scode.wptr; 1489 if (!scode.need_data) { 1490 vpu_malone_update_wptr(str_buf, wptr); 1491 return size; 1492 } 1493 1494 ret = vpu_malone_insert_scode(&scode, SCODE_PICTURE); 1495 if (ret < 0) 1496 return -ENOMEM; 1497 size += ret; 1498 wptr = scode.wptr; 1499 1500 ret = vpu_helper_copy_to_stream_buffer(&inst->stream_buffer, 1501 &wptr, 1502 vb2_get_plane_payload(vb, 0), 1503 vb2_plane_vaddr(vb, 0)); 1504 if (ret < 0) 1505 return -ENOMEM; 1506 size += vb2_get_plane_payload(vb, 0); 1507 1508 vpu_malone_update_wptr(str_buf, wptr); 1509 1510 if (disp_imm && !vpu_vb_is_codecconfig(vbuf)) { 1511 ret = vpu_malone_add_scode(inst->core->iface, 1512 inst->id, 1513 &inst->stream_buffer, 1514 inst->out_format.pixfmt, 1515 SCODE_PADDING_BUFFLUSH); 1516 if (ret < 0) 1517 return ret; 1518 size += ret; 1519 } 1520 1521 return size; 1522 } 1523 1524 static int vpu_malone_input_stream_data(struct vpu_malone_str_buffer __iomem *str_buf, 1525 struct vpu_inst *inst, struct vb2_buffer *vb) 1526 { 1527 u32 wptr = readl(&str_buf->wptr); 1528 int ret = 0; 1529 1530 ret = vpu_helper_copy_to_stream_buffer(&inst->stream_buffer, 1531 &wptr, 1532 vb2_get_plane_payload(vb, 0), 1533 vb2_plane_vaddr(vb, 0)); 1534 if (ret < 0) 1535 return -ENOMEM; 1536 1537 vpu_malone_update_wptr(str_buf, wptr); 1538 1539 return ret; 1540 } 1541 1542 static int vpu_malone_input_ts(struct vpu_inst *inst, s64 timestamp, u32 size) 1543 { 1544 struct vpu_ts_info info; 1545 1546 memset(&info, 0, sizeof(info)); 1547 info.timestamp = timestamp; 1548 info.size = size; 1549 1550 return vpu_session_fill_timestamp(inst, &info); 1551 } 1552 1553 int vpu_malone_input_frame(struct vpu_shared_addr *shared, 1554 struct vpu_inst *inst, struct vb2_buffer *vb) 1555 { 1556 struct vpu_dec_ctrl *hc = shared->priv; 1557 struct vb2_v4l2_buffer *vbuf; 1558 struct vpu_malone_str_buffer __iomem *str_buf = hc->str_buf[inst->id]; 1559 u32 disp_imm = hc->codec_param[inst->id].disp_imm; 1560 u32 size; 1561 int ret; 1562 1563 if (vpu_malone_is_non_frame_mode(shared, inst->id)) 1564 ret = vpu_malone_input_stream_data(str_buf, inst, vb); 1565 else 1566 ret = vpu_malone_input_frame_data(str_buf, inst, vb, disp_imm); 1567 if (ret < 0) 1568 return ret; 1569 size = ret; 1570 1571 /* 1572 * if buffer only contain codec data, and the timestamp is invalid, 1573 * don't put the invalid timestamp to resync 1574 * merge the data to next frame 1575 */ 1576 vbuf = to_vb2_v4l2_buffer(vb); 1577 if (vpu_vb_is_codecconfig(vbuf)) { 1578 inst->extra_size += size; 1579 return 0; 1580 } 1581 if (inst->extra_size) { 1582 size += inst->extra_size; 1583 inst->extra_size = 0; 1584 } 1585 1586 ret = vpu_malone_input_ts(inst, vb->timestamp, size); 1587 if (ret) 1588 return ret; 1589 1590 return 0; 1591 } 1592 1593 static bool vpu_malone_check_ready(struct vpu_shared_addr *shared, u32 instance) 1594 { 1595 struct malone_iface *iface = shared->iface; 1596 struct vpu_rpc_buffer_desc *desc = &iface->api_cmd_buffer_desc[instance]; 1597 u32 size = desc->end - desc->start; 1598 u32 rptr = desc->rptr; 1599 u32 wptr = desc->wptr; 1600 u32 used; 1601 1602 if (!size) 1603 return true; 1604 1605 used = (wptr + size - rptr) % size; 1606 if (used < (size / 2)) 1607 return true; 1608 1609 return false; 1610 } 1611 1612 bool vpu_malone_is_ready(struct vpu_shared_addr *shared, u32 instance) 1613 { 1614 u32 cnt = 0; 1615 1616 while (!vpu_malone_check_ready(shared, instance)) { 1617 if (cnt > 30) 1618 return false; 1619 mdelay(1); 1620 cnt++; 1621 } 1622 return true; 1623 } 1624 1625 int vpu_malone_pre_cmd(struct vpu_shared_addr *shared, u32 instance) 1626 { 1627 if (!vpu_malone_is_ready(shared, instance)) 1628 return -EINVAL; 1629 1630 return 0; 1631 } 1632 1633 int vpu_malone_post_cmd(struct vpu_shared_addr *shared, u32 instance) 1634 { 1635 struct malone_iface *iface = shared->iface; 1636 struct vpu_rpc_buffer_desc *desc = &iface->api_cmd_buffer_desc[instance]; 1637 1638 desc->wptr++; 1639 if (desc->wptr == desc->end) 1640 desc->wptr = desc->start; 1641 1642 return 0; 1643 } 1644 1645 int vpu_malone_init_instance(struct vpu_shared_addr *shared, u32 instance) 1646 { 1647 struct malone_iface *iface = shared->iface; 1648 struct vpu_rpc_buffer_desc *desc = &iface->api_cmd_buffer_desc[instance]; 1649 1650 desc->wptr = desc->rptr; 1651 if (desc->wptr == desc->end) 1652 desc->wptr = desc->start; 1653 1654 return 0; 1655 } 1656 1657 u32 vpu_malone_get_max_instance_count(struct vpu_shared_addr *shared) 1658 { 1659 struct malone_iface *iface = shared->iface; 1660 1661 return iface->max_streams; 1662 } 1663