19f599f35SMing Qian /* SPDX-License-Identifier: GPL-2.0 */ 29f599f35SMing Qian /* 39f599f35SMing Qian * Copyright 2020-2021 NXP 49f599f35SMing Qian */ 59f599f35SMing Qian 69f599f35SMing Qian #ifndef _AMPHION_VPU_CORE_H 79f599f35SMing Qian #define _AMPHION_VPU_CORE_H 89f599f35SMing Qian 99f599f35SMing Qian void csr_writel(struct vpu_core *core, u32 reg, u32 val); 109f599f35SMing Qian u32 csr_readl(struct vpu_core *core, u32 reg); 119f599f35SMing Qian int vpu_alloc_dma(struct vpu_core *core, struct vpu_buffer *buf); 129f599f35SMing Qian void vpu_free_dma(struct vpu_buffer *buf); 139f599f35SMing Qian struct vpu_inst *vpu_core_find_instance(struct vpu_core *core, u32 index); 14*0202a665SMing Qian void vpu_core_set_state(struct vpu_core *core, enum vpu_core_state state); 159f599f35SMing Qian 169f599f35SMing Qian #endif 17