1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) 2019 Pengutronix, Michael Tretter <kernel@pengutronix.de>
4  *
5  * Allegro DVT video encoder driver
6  */
7 
8 #include <linux/bits.h>
9 #include <linux/clk.h>
10 #include <linux/firmware.h>
11 #include <linux/gcd.h>
12 #include <linux/interrupt.h>
13 #include <linux/io.h>
14 #include <linux/kernel.h>
15 #include <linux/log2.h>
16 #include <linux/mfd/syscon.h>
17 #include <linux/mfd/syscon/xlnx-vcu.h>
18 #include <linux/module.h>
19 #include <linux/of.h>
20 #include <linux/of_device.h>
21 #include <linux/platform_device.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/regmap.h>
24 #include <linux/sizes.h>
25 #include <linux/slab.h>
26 #include <linux/videodev2.h>
27 #include <media/v4l2-ctrls.h>
28 #include <media/v4l2-device.h>
29 #include <media/v4l2-event.h>
30 #include <media/v4l2-ioctl.h>
31 #include <media/v4l2-mem2mem.h>
32 #include <media/videobuf2-dma-contig.h>
33 #include <media/videobuf2-v4l2.h>
34 
35 #include "allegro-mail.h"
36 #include "nal-h264.h"
37 #include "nal-hevc.h"
38 
39 /*
40  * Support up to 4k video streams. The hardware actually supports higher
41  * resolutions, which are specified in PG252 June 6, 2018 (H.264/H.265 Video
42  * Codec Unit v1.1) Chapter 3.
43  */
44 #define ALLEGRO_WIDTH_MIN 128
45 #define ALLEGRO_WIDTH_DEFAULT 1920
46 #define ALLEGRO_WIDTH_MAX 3840
47 #define ALLEGRO_HEIGHT_MIN 64
48 #define ALLEGRO_HEIGHT_DEFAULT 1080
49 #define ALLEGRO_HEIGHT_MAX 2160
50 
51 #define ALLEGRO_FRAMERATE_DEFAULT ((struct v4l2_fract) { 30, 1 })
52 
53 #define ALLEGRO_GOP_SIZE_DEFAULT 25
54 #define ALLEGRO_GOP_SIZE_MAX 1000
55 
56 /*
57  * MCU Control Registers
58  *
59  * The Zynq UltraScale+ Devices Register Reference documents the registers
60  * with an offset of 0x9000, which equals the size of the SRAM and one page
61  * gap. The driver handles SRAM and registers separately and, therefore, is
62  * oblivious of the offset.
63  */
64 #define AL5_MCU_RESET                   0x0000
65 #define AL5_MCU_RESET_SOFT              BIT(0)
66 #define AL5_MCU_RESET_REGS              BIT(1)
67 #define AL5_MCU_RESET_MODE              0x0004
68 #define AL5_MCU_RESET_MODE_SLEEP        BIT(0)
69 #define AL5_MCU_RESET_MODE_HALT         BIT(1)
70 #define AL5_MCU_STA                     0x0008
71 #define AL5_MCU_STA_SLEEP               BIT(0)
72 #define AL5_MCU_WAKEUP                  0x000c
73 
74 #define AL5_ICACHE_ADDR_OFFSET_MSB      0x0010
75 #define AL5_ICACHE_ADDR_OFFSET_LSB      0x0014
76 #define AL5_DCACHE_ADDR_OFFSET_MSB      0x0018
77 #define AL5_DCACHE_ADDR_OFFSET_LSB      0x001c
78 
79 #define AL5_MCU_INTERRUPT               0x0100
80 #define AL5_ITC_CPU_IRQ_MSK             0x0104
81 #define AL5_ITC_CPU_IRQ_CLR             0x0108
82 #define AL5_ITC_CPU_IRQ_STA             0x010C
83 #define AL5_ITC_CPU_IRQ_STA_TRIGGERED   BIT(0)
84 
85 #define AXI_ADDR_OFFSET_IP              0x0208
86 
87 /*
88  * The MCU accesses the system memory with a 2G offset compared to CPU
89  * physical addresses.
90  */
91 #define MCU_CACHE_OFFSET SZ_2G
92 
93 /*
94  * The driver needs to reserve some space at the beginning of capture buffers,
95  * because it needs to write SPS/PPS NAL units. The encoder writes the actual
96  * frame data after the offset.
97  */
98 #define ENCODER_STREAM_OFFSET SZ_128
99 
100 #define SIZE_MACROBLOCK 16
101 
102 /* Encoding options */
103 #define LOG2_MAX_FRAME_NUM		4
104 #define LOG2_MAX_PIC_ORDER_CNT		10
105 #define BETA_OFFSET_DIV_2		-1
106 #define TC_OFFSET_DIV_2			-1
107 
108 /*
109  * This control allows applications to explicitly disable the encoder buffer.
110  * This value is Allegro specific.
111  */
112 #define V4L2_CID_USER_ALLEGRO_ENCODER_BUFFER (V4L2_CID_USER_ALLEGRO_BASE + 0)
113 
114 static int debug;
115 module_param(debug, int, 0644);
116 MODULE_PARM_DESC(debug, "Debug level (0-2)");
117 
118 struct allegro_buffer {
119 	void *vaddr;
120 	dma_addr_t paddr;
121 	size_t size;
122 	struct list_head head;
123 };
124 
125 struct allegro_dev;
126 struct allegro_channel;
127 
128 struct allegro_mbox {
129 	struct allegro_dev *dev;
130 	unsigned int head;
131 	unsigned int tail;
132 	unsigned int data;
133 	size_t size;
134 	/* protect mailbox from simultaneous accesses */
135 	struct mutex lock;
136 };
137 
138 struct allegro_encoder_buffer {
139 	unsigned int size;
140 	unsigned int color_depth;
141 	unsigned int num_cores;
142 	unsigned int clk_rate;
143 };
144 
145 struct allegro_dev {
146 	struct v4l2_device v4l2_dev;
147 	struct video_device video_dev;
148 	struct v4l2_m2m_dev *m2m_dev;
149 	struct platform_device *plat_dev;
150 
151 	/* mutex protecting vb2_queue structure */
152 	struct mutex lock;
153 
154 	struct regmap *regmap;
155 	struct regmap *sram;
156 	struct regmap *settings;
157 
158 	struct clk *clk_core;
159 	struct clk *clk_mcu;
160 
161 	const struct fw_info *fw_info;
162 	struct allegro_buffer firmware;
163 	struct allegro_buffer suballocator;
164 	bool has_encoder_buffer;
165 	struct allegro_encoder_buffer encoder_buffer;
166 
167 	struct completion init_complete;
168 	bool initialized;
169 
170 	/* The mailbox interface */
171 	struct allegro_mbox *mbox_command;
172 	struct allegro_mbox *mbox_status;
173 
174 	/*
175 	 * The downstream driver limits the users to 64 users, thus I can use
176 	 * a bitfield for the user_ids that are in use. See also user_id in
177 	 * struct allegro_channel.
178 	 */
179 	unsigned long channel_user_ids;
180 	struct list_head channels;
181 };
182 
183 static struct regmap_config allegro_regmap_config = {
184 	.name = "regmap",
185 	.reg_bits = 32,
186 	.val_bits = 32,
187 	.reg_stride = 4,
188 	.max_register = 0xfff,
189 	.cache_type = REGCACHE_NONE,
190 };
191 
192 static struct regmap_config allegro_sram_config = {
193 	.name = "sram",
194 	.reg_bits = 32,
195 	.val_bits = 32,
196 	.reg_stride = 4,
197 	.max_register = 0x7fff,
198 	.cache_type = REGCACHE_NONE,
199 };
200 
201 #define fh_to_channel(__fh) container_of(__fh, struct allegro_channel, fh)
202 
203 struct allegro_channel {
204 	struct allegro_dev *dev;
205 	struct v4l2_fh fh;
206 	struct v4l2_ctrl_handler ctrl_handler;
207 
208 	unsigned int width;
209 	unsigned int height;
210 	unsigned int stride;
211 	struct v4l2_fract framerate;
212 
213 	enum v4l2_colorspace colorspace;
214 	enum v4l2_ycbcr_encoding ycbcr_enc;
215 	enum v4l2_quantization quantization;
216 	enum v4l2_xfer_func xfer_func;
217 
218 	u32 pixelformat;
219 	unsigned int sizeimage_raw;
220 	unsigned int osequence;
221 
222 	u32 codec;
223 	unsigned int sizeimage_encoded;
224 	unsigned int csequence;
225 
226 	bool frame_rc_enable;
227 	unsigned int bitrate;
228 	unsigned int bitrate_peak;
229 
230 	struct allegro_buffer config_blob;
231 
232 	unsigned int log2_max_frame_num;
233 	bool temporal_mvp_enable;
234 
235 	bool enable_loop_filter_across_tiles;
236 	bool enable_loop_filter_across_slices;
237 	bool enable_deblocking_filter_override;
238 	bool enable_reordering;
239 	bool dbf_ovr_en;
240 
241 	unsigned int num_ref_idx_l0;
242 	unsigned int num_ref_idx_l1;
243 
244 	/* Maximum range for motion estimation */
245 	int b_hrz_me_range;
246 	int b_vrt_me_range;
247 	int p_hrz_me_range;
248 	int p_vrt_me_range;
249 	/* Size limits of coding unit */
250 	int min_cu_size;
251 	int max_cu_size;
252 	/* Size limits of transform unit */
253 	int min_tu_size;
254 	int max_tu_size;
255 	int max_transfo_depth_intra;
256 	int max_transfo_depth_inter;
257 
258 	struct v4l2_ctrl *mpeg_video_h264_profile;
259 	struct v4l2_ctrl *mpeg_video_h264_level;
260 	struct v4l2_ctrl *mpeg_video_h264_i_frame_qp;
261 	struct v4l2_ctrl *mpeg_video_h264_max_qp;
262 	struct v4l2_ctrl *mpeg_video_h264_min_qp;
263 	struct v4l2_ctrl *mpeg_video_h264_p_frame_qp;
264 	struct v4l2_ctrl *mpeg_video_h264_b_frame_qp;
265 
266 	struct v4l2_ctrl *mpeg_video_hevc_profile;
267 	struct v4l2_ctrl *mpeg_video_hevc_level;
268 	struct v4l2_ctrl *mpeg_video_hevc_tier;
269 	struct v4l2_ctrl *mpeg_video_hevc_i_frame_qp;
270 	struct v4l2_ctrl *mpeg_video_hevc_max_qp;
271 	struct v4l2_ctrl *mpeg_video_hevc_min_qp;
272 	struct v4l2_ctrl *mpeg_video_hevc_p_frame_qp;
273 	struct v4l2_ctrl *mpeg_video_hevc_b_frame_qp;
274 
275 	struct v4l2_ctrl *mpeg_video_frame_rc_enable;
276 	struct { /* video bitrate mode control cluster */
277 		struct v4l2_ctrl *mpeg_video_bitrate_mode;
278 		struct v4l2_ctrl *mpeg_video_bitrate;
279 		struct v4l2_ctrl *mpeg_video_bitrate_peak;
280 	};
281 	struct v4l2_ctrl *mpeg_video_cpb_size;
282 	struct v4l2_ctrl *mpeg_video_gop_size;
283 
284 	struct v4l2_ctrl *encoder_buffer;
285 
286 	/* user_id is used to identify the channel during CREATE_CHANNEL */
287 	/* not sure, what to set here and if this is actually required */
288 	int user_id;
289 	/* channel_id is set by the mcu and used by all later commands */
290 	int mcu_channel_id;
291 
292 	struct list_head buffers_reference;
293 	struct list_head buffers_intermediate;
294 
295 	struct list_head source_shadow_list;
296 	struct list_head stream_shadow_list;
297 	/* protect shadow lists of buffers passed to firmware */
298 	struct mutex shadow_list_lock;
299 
300 	struct list_head list;
301 	struct completion completion;
302 
303 	unsigned int error;
304 };
305 
306 static inline int
307 allegro_channel_get_i_frame_qp(struct allegro_channel *channel)
308 {
309 	if (channel->codec == V4L2_PIX_FMT_HEVC)
310 		return v4l2_ctrl_g_ctrl(channel->mpeg_video_hevc_i_frame_qp);
311 	else
312 		return v4l2_ctrl_g_ctrl(channel->mpeg_video_h264_i_frame_qp);
313 }
314 
315 static inline int
316 allegro_channel_get_p_frame_qp(struct allegro_channel *channel)
317 {
318 	if (channel->codec == V4L2_PIX_FMT_HEVC)
319 		return v4l2_ctrl_g_ctrl(channel->mpeg_video_hevc_p_frame_qp);
320 	else
321 		return v4l2_ctrl_g_ctrl(channel->mpeg_video_h264_p_frame_qp);
322 }
323 
324 static inline int
325 allegro_channel_get_b_frame_qp(struct allegro_channel *channel)
326 {
327 	if (channel->codec == V4L2_PIX_FMT_HEVC)
328 		return v4l2_ctrl_g_ctrl(channel->mpeg_video_hevc_b_frame_qp);
329 	else
330 		return v4l2_ctrl_g_ctrl(channel->mpeg_video_h264_b_frame_qp);
331 }
332 
333 static inline int
334 allegro_channel_get_min_qp(struct allegro_channel *channel)
335 {
336 	if (channel->codec == V4L2_PIX_FMT_HEVC)
337 		return v4l2_ctrl_g_ctrl(channel->mpeg_video_hevc_min_qp);
338 	else
339 		return v4l2_ctrl_g_ctrl(channel->mpeg_video_h264_min_qp);
340 }
341 
342 static inline int
343 allegro_channel_get_max_qp(struct allegro_channel *channel)
344 {
345 	if (channel->codec == V4L2_PIX_FMT_HEVC)
346 		return v4l2_ctrl_g_ctrl(channel->mpeg_video_hevc_max_qp);
347 	else
348 		return v4l2_ctrl_g_ctrl(channel->mpeg_video_h264_max_qp);
349 }
350 
351 struct allegro_m2m_buffer {
352 	struct v4l2_m2m_buffer buf;
353 	struct list_head head;
354 };
355 
356 #define to_allegro_m2m_buffer(__buf) \
357 	container_of(__buf, struct allegro_m2m_buffer, buf)
358 
359 struct fw_info {
360 	unsigned int id;
361 	unsigned int id_codec;
362 	char *version;
363 	unsigned int mailbox_cmd;
364 	unsigned int mailbox_status;
365 	size_t mailbox_size;
366 	enum mcu_msg_version mailbox_version;
367 	size_t suballocator_size;
368 };
369 
370 static const struct fw_info supported_firmware[] = {
371 	{
372 		.id = 18296,
373 		.id_codec = 96272,
374 		.version = "v2018.2",
375 		.mailbox_cmd = 0x7800,
376 		.mailbox_status = 0x7c00,
377 		.mailbox_size = 0x400 - 0x8,
378 		.mailbox_version = MCU_MSG_VERSION_2018_2,
379 		.suballocator_size = SZ_16M,
380 	}, {
381 		.id = 14680,
382 		.id_codec = 126572,
383 		.version = "v2019.2",
384 		.mailbox_cmd = 0x7000,
385 		.mailbox_status = 0x7800,
386 		.mailbox_size = 0x800 - 0x8,
387 		.mailbox_version = MCU_MSG_VERSION_2019_2,
388 		.suballocator_size = SZ_32M,
389 	},
390 };
391 
392 static inline u32 to_mcu_addr(struct allegro_dev *dev, dma_addr_t phys)
393 {
394 	if (upper_32_bits(phys) || (lower_32_bits(phys) & MCU_CACHE_OFFSET))
395 		v4l2_warn(&dev->v4l2_dev,
396 			  "address %pad is outside mcu window\n", &phys);
397 
398 	return lower_32_bits(phys) | MCU_CACHE_OFFSET;
399 }
400 
401 static inline u32 to_mcu_size(struct allegro_dev *dev, size_t size)
402 {
403 	return lower_32_bits(size);
404 }
405 
406 static inline u32 to_codec_addr(struct allegro_dev *dev, dma_addr_t phys)
407 {
408 	if (upper_32_bits(phys))
409 		v4l2_warn(&dev->v4l2_dev,
410 			  "address %pad cannot be used by codec\n", &phys);
411 
412 	return lower_32_bits(phys);
413 }
414 
415 static inline u64 ptr_to_u64(const void *ptr)
416 {
417 	return (uintptr_t)ptr;
418 }
419 
420 /* Helper functions for channel and user operations */
421 
422 static unsigned long allegro_next_user_id(struct allegro_dev *dev)
423 {
424 	if (dev->channel_user_ids == ~0UL)
425 		return -EBUSY;
426 
427 	return ffz(dev->channel_user_ids);
428 }
429 
430 static struct allegro_channel *
431 allegro_find_channel_by_user_id(struct allegro_dev *dev,
432 				unsigned int user_id)
433 {
434 	struct allegro_channel *channel;
435 
436 	list_for_each_entry(channel, &dev->channels, list) {
437 		if (channel->user_id == user_id)
438 			return channel;
439 	}
440 
441 	return ERR_PTR(-EINVAL);
442 }
443 
444 static struct allegro_channel *
445 allegro_find_channel_by_channel_id(struct allegro_dev *dev,
446 				   unsigned int channel_id)
447 {
448 	struct allegro_channel *channel;
449 
450 	list_for_each_entry(channel, &dev->channels, list) {
451 		if (channel->mcu_channel_id == channel_id)
452 			return channel;
453 	}
454 
455 	return ERR_PTR(-EINVAL);
456 }
457 
458 static inline bool channel_exists(struct allegro_channel *channel)
459 {
460 	return channel->mcu_channel_id != -1;
461 }
462 
463 #define AL_ERROR			0x80
464 #define AL_ERR_INIT_FAILED		0x81
465 #define AL_ERR_NO_FRAME_DECODED		0x82
466 #define AL_ERR_RESOLUTION_CHANGE	0x85
467 #define AL_ERR_NO_MEMORY		0x87
468 #define AL_ERR_STREAM_OVERFLOW		0x88
469 #define AL_ERR_TOO_MANY_SLICES		0x89
470 #define AL_ERR_BUF_NOT_READY		0x8c
471 #define AL_ERR_NO_CHANNEL_AVAILABLE	0x8d
472 #define AL_ERR_RESOURCE_UNAVAILABLE	0x8e
473 #define AL_ERR_NOT_ENOUGH_CORES		0x8f
474 #define AL_ERR_REQUEST_MALFORMED	0x90
475 #define AL_ERR_CMD_NOT_ALLOWED		0x91
476 #define AL_ERR_INVALID_CMD_VALUE	0x92
477 
478 static inline const char *allegro_err_to_string(unsigned int err)
479 {
480 	switch (err) {
481 	case AL_ERR_INIT_FAILED:
482 		return "initialization failed";
483 	case AL_ERR_NO_FRAME_DECODED:
484 		return "no frame decoded";
485 	case AL_ERR_RESOLUTION_CHANGE:
486 		return "resolution change";
487 	case AL_ERR_NO_MEMORY:
488 		return "out of memory";
489 	case AL_ERR_STREAM_OVERFLOW:
490 		return "stream buffer overflow";
491 	case AL_ERR_TOO_MANY_SLICES:
492 		return "too many slices";
493 	case AL_ERR_BUF_NOT_READY:
494 		return "buffer not ready";
495 	case AL_ERR_NO_CHANNEL_AVAILABLE:
496 		return "no channel available";
497 	case AL_ERR_RESOURCE_UNAVAILABLE:
498 		return "resource unavailable";
499 	case AL_ERR_NOT_ENOUGH_CORES:
500 		return "not enough cores";
501 	case AL_ERR_REQUEST_MALFORMED:
502 		return "request malformed";
503 	case AL_ERR_CMD_NOT_ALLOWED:
504 		return "command not allowed";
505 	case AL_ERR_INVALID_CMD_VALUE:
506 		return "invalid command value";
507 	case AL_ERROR:
508 	default:
509 		return "unknown error";
510 	}
511 }
512 
513 static unsigned int estimate_stream_size(unsigned int width,
514 					 unsigned int height)
515 {
516 	unsigned int offset = ENCODER_STREAM_OFFSET;
517 	unsigned int num_blocks = DIV_ROUND_UP(width, SIZE_MACROBLOCK) *
518 					DIV_ROUND_UP(height, SIZE_MACROBLOCK);
519 	unsigned int pcm_size = SZ_256;
520 	unsigned int partition_table = SZ_256;
521 
522 	return round_up(offset + num_blocks * pcm_size + partition_table, 32);
523 }
524 
525 static enum v4l2_mpeg_video_h264_level
526 select_minimum_h264_level(unsigned int width, unsigned int height)
527 {
528 	unsigned int pic_width_in_mb = DIV_ROUND_UP(width, SIZE_MACROBLOCK);
529 	unsigned int frame_height_in_mb = DIV_ROUND_UP(height, SIZE_MACROBLOCK);
530 	unsigned int frame_size_in_mb = pic_width_in_mb * frame_height_in_mb;
531 	enum v4l2_mpeg_video_h264_level level = V4L2_MPEG_VIDEO_H264_LEVEL_4_0;
532 
533 	/*
534 	 * The level limits are specified in Rec. ITU-T H.264 Annex A.3.1 and
535 	 * also specify limits regarding bit rate and CBP size. Only approximate
536 	 * the levels using the frame size.
537 	 *
538 	 * Level 5.1 allows up to 4k video resolution.
539 	 */
540 	if (frame_size_in_mb <= 99)
541 		level = V4L2_MPEG_VIDEO_H264_LEVEL_1_0;
542 	else if (frame_size_in_mb <= 396)
543 		level = V4L2_MPEG_VIDEO_H264_LEVEL_1_1;
544 	else if (frame_size_in_mb <= 792)
545 		level = V4L2_MPEG_VIDEO_H264_LEVEL_2_1;
546 	else if (frame_size_in_mb <= 1620)
547 		level = V4L2_MPEG_VIDEO_H264_LEVEL_2_2;
548 	else if (frame_size_in_mb <= 3600)
549 		level = V4L2_MPEG_VIDEO_H264_LEVEL_3_1;
550 	else if (frame_size_in_mb <= 5120)
551 		level = V4L2_MPEG_VIDEO_H264_LEVEL_3_2;
552 	else if (frame_size_in_mb <= 8192)
553 		level = V4L2_MPEG_VIDEO_H264_LEVEL_4_0;
554 	else if (frame_size_in_mb <= 8704)
555 		level = V4L2_MPEG_VIDEO_H264_LEVEL_4_2;
556 	else if (frame_size_in_mb <= 22080)
557 		level = V4L2_MPEG_VIDEO_H264_LEVEL_5_0;
558 	else
559 		level = V4L2_MPEG_VIDEO_H264_LEVEL_5_1;
560 
561 	return level;
562 }
563 
564 static unsigned int h264_maximum_bitrate(enum v4l2_mpeg_video_h264_level level)
565 {
566 	switch (level) {
567 	case V4L2_MPEG_VIDEO_H264_LEVEL_1_0:
568 		return 64000;
569 	case V4L2_MPEG_VIDEO_H264_LEVEL_1B:
570 		return 128000;
571 	case V4L2_MPEG_VIDEO_H264_LEVEL_1_1:
572 		return 192000;
573 	case V4L2_MPEG_VIDEO_H264_LEVEL_1_2:
574 		return 384000;
575 	case V4L2_MPEG_VIDEO_H264_LEVEL_1_3:
576 		return 768000;
577 	case V4L2_MPEG_VIDEO_H264_LEVEL_2_0:
578 		return 2000000;
579 	case V4L2_MPEG_VIDEO_H264_LEVEL_2_1:
580 		return 4000000;
581 	case V4L2_MPEG_VIDEO_H264_LEVEL_2_2:
582 		return 4000000;
583 	case V4L2_MPEG_VIDEO_H264_LEVEL_3_0:
584 		return 10000000;
585 	case V4L2_MPEG_VIDEO_H264_LEVEL_3_1:
586 		return 14000000;
587 	case V4L2_MPEG_VIDEO_H264_LEVEL_3_2:
588 		return 20000000;
589 	case V4L2_MPEG_VIDEO_H264_LEVEL_4_0:
590 		return 20000000;
591 	case V4L2_MPEG_VIDEO_H264_LEVEL_4_1:
592 		return 50000000;
593 	case V4L2_MPEG_VIDEO_H264_LEVEL_4_2:
594 		return 50000000;
595 	case V4L2_MPEG_VIDEO_H264_LEVEL_5_0:
596 		return 135000000;
597 	case V4L2_MPEG_VIDEO_H264_LEVEL_5_1:
598 	default:
599 		return 240000000;
600 	}
601 }
602 
603 static unsigned int h264_maximum_cpb_size(enum v4l2_mpeg_video_h264_level level)
604 {
605 	switch (level) {
606 	case V4L2_MPEG_VIDEO_H264_LEVEL_1_0:
607 		return 175;
608 	case V4L2_MPEG_VIDEO_H264_LEVEL_1B:
609 		return 350;
610 	case V4L2_MPEG_VIDEO_H264_LEVEL_1_1:
611 		return 500;
612 	case V4L2_MPEG_VIDEO_H264_LEVEL_1_2:
613 		return 1000;
614 	case V4L2_MPEG_VIDEO_H264_LEVEL_1_3:
615 		return 2000;
616 	case V4L2_MPEG_VIDEO_H264_LEVEL_2_0:
617 		return 2000;
618 	case V4L2_MPEG_VIDEO_H264_LEVEL_2_1:
619 		return 4000;
620 	case V4L2_MPEG_VIDEO_H264_LEVEL_2_2:
621 		return 4000;
622 	case V4L2_MPEG_VIDEO_H264_LEVEL_3_0:
623 		return 10000;
624 	case V4L2_MPEG_VIDEO_H264_LEVEL_3_1:
625 		return 14000;
626 	case V4L2_MPEG_VIDEO_H264_LEVEL_3_2:
627 		return 20000;
628 	case V4L2_MPEG_VIDEO_H264_LEVEL_4_0:
629 		return 25000;
630 	case V4L2_MPEG_VIDEO_H264_LEVEL_4_1:
631 		return 62500;
632 	case V4L2_MPEG_VIDEO_H264_LEVEL_4_2:
633 		return 62500;
634 	case V4L2_MPEG_VIDEO_H264_LEVEL_5_0:
635 		return 135000;
636 	case V4L2_MPEG_VIDEO_H264_LEVEL_5_1:
637 	default:
638 		return 240000;
639 	}
640 }
641 
642 static enum v4l2_mpeg_video_hevc_level
643 select_minimum_hevc_level(unsigned int width, unsigned int height)
644 {
645 	unsigned int luma_picture_size = width * height;
646 	enum v4l2_mpeg_video_hevc_level level;
647 
648 	if (luma_picture_size <= 36864)
649 		level = V4L2_MPEG_VIDEO_HEVC_LEVEL_1;
650 	else if (luma_picture_size <= 122880)
651 		level = V4L2_MPEG_VIDEO_HEVC_LEVEL_2;
652 	else if (luma_picture_size <= 245760)
653 		level = V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1;
654 	else if (luma_picture_size <= 552960)
655 		level = V4L2_MPEG_VIDEO_HEVC_LEVEL_3;
656 	else if (luma_picture_size <= 983040)
657 		level = V4L2_MPEG_VIDEO_HEVC_LEVEL_3_1;
658 	else if (luma_picture_size <= 2228224)
659 		level = V4L2_MPEG_VIDEO_HEVC_LEVEL_4;
660 	else if (luma_picture_size <= 8912896)
661 		level = V4L2_MPEG_VIDEO_HEVC_LEVEL_5;
662 	else
663 		level = V4L2_MPEG_VIDEO_HEVC_LEVEL_6;
664 
665 	return level;
666 }
667 
668 static unsigned int hevc_maximum_bitrate(enum v4l2_mpeg_video_hevc_level level)
669 {
670 	/*
671 	 * See Rec. ITU-T H.265 v5 (02/2018), A.4.2 Profile-specific level
672 	 * limits for the video profiles.
673 	 */
674 	switch (level) {
675 	case V4L2_MPEG_VIDEO_HEVC_LEVEL_1:
676 		return 128;
677 	case V4L2_MPEG_VIDEO_HEVC_LEVEL_2:
678 		return 1500;
679 	case V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1:
680 		return 3000;
681 	case V4L2_MPEG_VIDEO_HEVC_LEVEL_3:
682 		return 6000;
683 	case V4L2_MPEG_VIDEO_HEVC_LEVEL_3_1:
684 		return 10000;
685 	case V4L2_MPEG_VIDEO_HEVC_LEVEL_4:
686 		return 12000;
687 	case V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1:
688 		return 20000;
689 	case V4L2_MPEG_VIDEO_HEVC_LEVEL_5:
690 		return 25000;
691 	default:
692 	case V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1:
693 		return 40000;
694 	}
695 }
696 
697 static unsigned int hevc_maximum_cpb_size(enum v4l2_mpeg_video_hevc_level level)
698 {
699 	switch (level) {
700 	case V4L2_MPEG_VIDEO_HEVC_LEVEL_1:
701 		return 350;
702 	case V4L2_MPEG_VIDEO_HEVC_LEVEL_2:
703 		return 1500;
704 	case V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1:
705 		return 3000;
706 	case V4L2_MPEG_VIDEO_HEVC_LEVEL_3:
707 		return 6000;
708 	case V4L2_MPEG_VIDEO_HEVC_LEVEL_3_1:
709 		return 10000;
710 	case V4L2_MPEG_VIDEO_HEVC_LEVEL_4:
711 		return 12000;
712 	case V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1:
713 		return 20000;
714 	case V4L2_MPEG_VIDEO_HEVC_LEVEL_5:
715 		return 25000;
716 	default:
717 	case V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1:
718 		return 40000;
719 	}
720 }
721 
722 static const struct fw_info *
723 allegro_get_firmware_info(struct allegro_dev *dev,
724 			  const struct firmware *fw,
725 			  const struct firmware *fw_codec)
726 {
727 	int i;
728 	unsigned int id = fw->size;
729 	unsigned int id_codec = fw_codec->size;
730 
731 	for (i = 0; i < ARRAY_SIZE(supported_firmware); i++)
732 		if (supported_firmware[i].id == id &&
733 		    supported_firmware[i].id_codec == id_codec)
734 			return &supported_firmware[i];
735 
736 	return NULL;
737 }
738 
739 /*
740  * Buffers that are used internally by the MCU.
741  */
742 
743 static int allegro_alloc_buffer(struct allegro_dev *dev,
744 				struct allegro_buffer *buffer, size_t size)
745 {
746 	buffer->vaddr = dma_alloc_coherent(&dev->plat_dev->dev, size,
747 					   &buffer->paddr, GFP_KERNEL);
748 	if (!buffer->vaddr)
749 		return -ENOMEM;
750 	buffer->size = size;
751 
752 	return 0;
753 }
754 
755 static void allegro_free_buffer(struct allegro_dev *dev,
756 				struct allegro_buffer *buffer)
757 {
758 	if (buffer->vaddr) {
759 		dma_free_coherent(&dev->plat_dev->dev, buffer->size,
760 				  buffer->vaddr, buffer->paddr);
761 		buffer->vaddr = NULL;
762 		buffer->size = 0;
763 	}
764 }
765 
766 /*
767  * Mailbox interface to send messages to the MCU.
768  */
769 
770 static void allegro_mcu_interrupt(struct allegro_dev *dev);
771 static void allegro_handle_message(struct allegro_dev *dev,
772 				   union mcu_msg_response *msg);
773 
774 static struct allegro_mbox *allegro_mbox_init(struct allegro_dev *dev,
775 					      unsigned int base, size_t size)
776 {
777 	struct allegro_mbox *mbox;
778 
779 	mbox = devm_kmalloc(&dev->plat_dev->dev, sizeof(*mbox), GFP_KERNEL);
780 	if (!mbox)
781 		return ERR_PTR(-ENOMEM);
782 
783 	mbox->dev = dev;
784 
785 	mbox->head = base;
786 	mbox->tail = base + 0x4;
787 	mbox->data = base + 0x8;
788 	mbox->size = size;
789 	mutex_init(&mbox->lock);
790 
791 	regmap_write(dev->sram, mbox->head, 0);
792 	regmap_write(dev->sram, mbox->tail, 0);
793 
794 	return mbox;
795 }
796 
797 static int allegro_mbox_write(struct allegro_mbox *mbox,
798 			      const u32 *src, size_t size)
799 {
800 	struct regmap *sram = mbox->dev->sram;
801 	unsigned int tail;
802 	size_t size_no_wrap;
803 	int err = 0;
804 	int stride = regmap_get_reg_stride(sram);
805 
806 	if (!src)
807 		return -EINVAL;
808 
809 	if (size > mbox->size)
810 		return -EINVAL;
811 
812 	mutex_lock(&mbox->lock);
813 	regmap_read(sram, mbox->tail, &tail);
814 	if (tail > mbox->size) {
815 		err = -EIO;
816 		goto out;
817 	}
818 	size_no_wrap = min(size, mbox->size - (size_t)tail);
819 	regmap_bulk_write(sram, mbox->data + tail,
820 			  src, size_no_wrap / stride);
821 	regmap_bulk_write(sram, mbox->data,
822 			  src + (size_no_wrap / sizeof(*src)),
823 			  (size - size_no_wrap) / stride);
824 	regmap_write(sram, mbox->tail, (tail + size) % mbox->size);
825 
826 out:
827 	mutex_unlock(&mbox->lock);
828 
829 	return err;
830 }
831 
832 static ssize_t allegro_mbox_read(struct allegro_mbox *mbox,
833 				 u32 *dst, size_t nbyte)
834 {
835 	struct {
836 		u16 length;
837 		u16 type;
838 	} __attribute__ ((__packed__)) *header;
839 	struct regmap *sram = mbox->dev->sram;
840 	unsigned int head;
841 	ssize_t size;
842 	size_t body_no_wrap;
843 	int stride = regmap_get_reg_stride(sram);
844 
845 	regmap_read(sram, mbox->head, &head);
846 	if (head > mbox->size)
847 		return -EIO;
848 
849 	/* Assume that the header does not wrap. */
850 	regmap_bulk_read(sram, mbox->data + head,
851 			 dst, sizeof(*header) / stride);
852 	header = (void *)dst;
853 	size = header->length + sizeof(*header);
854 	if (size > mbox->size || size & 0x3)
855 		return -EIO;
856 	if (size > nbyte)
857 		return -EINVAL;
858 
859 	/*
860 	 * The message might wrap within the mailbox. If the message does not
861 	 * wrap, the first read will read the entire message, otherwise the
862 	 * first read will read message until the end of the mailbox and the
863 	 * second read will read the remaining bytes from the beginning of the
864 	 * mailbox.
865 	 *
866 	 * Skip the header, as was already read to get the size of the body.
867 	 */
868 	body_no_wrap = min((size_t)header->length,
869 			   (size_t)(mbox->size - (head + sizeof(*header))));
870 	regmap_bulk_read(sram, mbox->data + head + sizeof(*header),
871 			 dst + (sizeof(*header) / sizeof(*dst)),
872 			 body_no_wrap / stride);
873 	regmap_bulk_read(sram, mbox->data,
874 			 dst + (sizeof(*header) + body_no_wrap) / sizeof(*dst),
875 			 (header->length - body_no_wrap) / stride);
876 
877 	regmap_write(sram, mbox->head, (head + size) % mbox->size);
878 
879 	return size;
880 }
881 
882 /**
883  * allegro_mbox_send() - Send a message via the mailbox
884  * @mbox: the mailbox which is used to send the message
885  * @msg: the message to send
886  */
887 static int allegro_mbox_send(struct allegro_mbox *mbox, void *msg)
888 {
889 	struct allegro_dev *dev = mbox->dev;
890 	ssize_t size;
891 	int err;
892 	u32 *tmp;
893 
894 	tmp = kzalloc(mbox->size, GFP_KERNEL);
895 	if (!tmp) {
896 		err = -ENOMEM;
897 		goto out;
898 	}
899 
900 	size = allegro_encode_mail(tmp, msg);
901 
902 	err = allegro_mbox_write(mbox, tmp, size);
903 	kfree(tmp);
904 	if (err)
905 		goto out;
906 
907 	allegro_mcu_interrupt(dev);
908 
909 out:
910 	return err;
911 }
912 
913 /**
914  * allegro_mbox_notify() - Notify the mailbox about a new message
915  * @mbox: The allegro_mbox to notify
916  */
917 static void allegro_mbox_notify(struct allegro_mbox *mbox)
918 {
919 	struct allegro_dev *dev = mbox->dev;
920 	union mcu_msg_response *msg;
921 	ssize_t size;
922 	u32 *tmp;
923 	int err;
924 
925 	msg = kmalloc(sizeof(*msg), GFP_KERNEL);
926 	if (!msg)
927 		return;
928 
929 	msg->header.version = dev->fw_info->mailbox_version;
930 
931 	tmp = kmalloc(mbox->size, GFP_KERNEL);
932 	if (!tmp)
933 		goto out;
934 
935 	size = allegro_mbox_read(mbox, tmp, mbox->size);
936 	if (size < 0)
937 		goto out;
938 
939 	err = allegro_decode_mail(msg, tmp);
940 	if (err)
941 		goto out;
942 
943 	allegro_handle_message(dev, msg);
944 
945 out:
946 	kfree(tmp);
947 	kfree(msg);
948 }
949 
950 static int allegro_encoder_buffer_init(struct allegro_dev *dev,
951 				       struct allegro_encoder_buffer *buffer)
952 {
953 	int err;
954 	struct regmap *settings = dev->settings;
955 	unsigned int supports_10_bit;
956 	unsigned int memory_depth;
957 	unsigned int num_cores;
958 	unsigned int color_depth;
959 	unsigned long clk_rate;
960 
961 	/* We don't support the encoder buffer pre Firmware version 2019.2 */
962 	if (dev->fw_info->mailbox_version < MCU_MSG_VERSION_2019_2)
963 		return -ENODEV;
964 
965 	if (!settings)
966 		return -EINVAL;
967 
968 	err = regmap_read(settings, VCU_ENC_COLOR_DEPTH, &supports_10_bit);
969 	if (err < 0)
970 		return err;
971 	err = regmap_read(settings, VCU_MEMORY_DEPTH, &memory_depth);
972 	if (err < 0)
973 		return err;
974 	err = regmap_read(settings, VCU_NUM_CORE, &num_cores);
975 	if (err < 0)
976 		return err;
977 
978 	clk_rate = clk_get_rate(dev->clk_core);
979 	if (clk_rate == 0)
980 		return -EINVAL;
981 
982 	color_depth = supports_10_bit ? 10 : 8;
983 	/* The firmware expects the encoder buffer size in bits. */
984 	buffer->size = color_depth * 32 * memory_depth;
985 	buffer->color_depth = color_depth;
986 	buffer->num_cores = num_cores;
987 	buffer->clk_rate = clk_rate;
988 
989 	v4l2_dbg(1, debug, &dev->v4l2_dev,
990 		 "using %d bits encoder buffer with %d-bit color depth\n",
991 		 buffer->size, color_depth);
992 
993 	return 0;
994 }
995 
996 static void allegro_mcu_send_init(struct allegro_dev *dev,
997 				  dma_addr_t suballoc_dma, size_t suballoc_size)
998 {
999 	struct mcu_msg_init_request msg;
1000 
1001 	memset(&msg, 0, sizeof(msg));
1002 
1003 	msg.header.type = MCU_MSG_TYPE_INIT;
1004 	msg.header.version = dev->fw_info->mailbox_version;
1005 
1006 	msg.suballoc_dma = to_mcu_addr(dev, suballoc_dma);
1007 	msg.suballoc_size = to_mcu_size(dev, suballoc_size);
1008 
1009 	if (dev->has_encoder_buffer) {
1010 		msg.encoder_buffer_size = dev->encoder_buffer.size;
1011 		msg.encoder_buffer_color_depth = dev->encoder_buffer.color_depth;
1012 		msg.num_cores = dev->encoder_buffer.num_cores;
1013 		msg.clk_rate = dev->encoder_buffer.clk_rate;
1014 	} else {
1015 		msg.encoder_buffer_size = -1;
1016 		msg.encoder_buffer_color_depth = -1;
1017 		msg.num_cores = -1;
1018 		msg.clk_rate = -1;
1019 	}
1020 
1021 	allegro_mbox_send(dev->mbox_command, &msg);
1022 }
1023 
1024 static u32 v4l2_pixelformat_to_mcu_format(u32 pixelformat)
1025 {
1026 	switch (pixelformat) {
1027 	case V4L2_PIX_FMT_NV12:
1028 		/* AL_420_8BITS: 0x100 -> NV12, 0x88 -> 8 bit */
1029 		return 0x100 | 0x88;
1030 	default:
1031 		return -EINVAL;
1032 	}
1033 }
1034 
1035 static u32 v4l2_colorspace_to_mcu_colorspace(enum v4l2_colorspace colorspace)
1036 {
1037 	switch (colorspace) {
1038 	case V4L2_COLORSPACE_REC709:
1039 		return 2;
1040 	case V4L2_COLORSPACE_SMPTE170M:
1041 		return 3;
1042 	case V4L2_COLORSPACE_SMPTE240M:
1043 		return 4;
1044 	case V4L2_COLORSPACE_SRGB:
1045 		return 7;
1046 	default:
1047 		/* UNKNOWN */
1048 		return 0;
1049 	}
1050 }
1051 
1052 static u8 v4l2_profile_to_mcu_profile(enum v4l2_mpeg_video_h264_profile profile)
1053 {
1054 	switch (profile) {
1055 	case V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE:
1056 	default:
1057 		return 66;
1058 	}
1059 }
1060 
1061 static u16 v4l2_level_to_mcu_level(enum v4l2_mpeg_video_h264_level level)
1062 {
1063 	switch (level) {
1064 	case V4L2_MPEG_VIDEO_H264_LEVEL_1_0:
1065 		return 10;
1066 	case V4L2_MPEG_VIDEO_H264_LEVEL_1_1:
1067 		return 11;
1068 	case V4L2_MPEG_VIDEO_H264_LEVEL_1_2:
1069 		return 12;
1070 	case V4L2_MPEG_VIDEO_H264_LEVEL_1_3:
1071 		return 13;
1072 	case V4L2_MPEG_VIDEO_H264_LEVEL_2_0:
1073 		return 20;
1074 	case V4L2_MPEG_VIDEO_H264_LEVEL_2_1:
1075 		return 21;
1076 	case V4L2_MPEG_VIDEO_H264_LEVEL_2_2:
1077 		return 22;
1078 	case V4L2_MPEG_VIDEO_H264_LEVEL_3_0:
1079 		return 30;
1080 	case V4L2_MPEG_VIDEO_H264_LEVEL_3_1:
1081 		return 31;
1082 	case V4L2_MPEG_VIDEO_H264_LEVEL_3_2:
1083 		return 32;
1084 	case V4L2_MPEG_VIDEO_H264_LEVEL_4_0:
1085 		return 40;
1086 	case V4L2_MPEG_VIDEO_H264_LEVEL_4_1:
1087 		return 41;
1088 	case V4L2_MPEG_VIDEO_H264_LEVEL_4_2:
1089 		return 42;
1090 	case V4L2_MPEG_VIDEO_H264_LEVEL_5_0:
1091 		return 50;
1092 	case V4L2_MPEG_VIDEO_H264_LEVEL_5_1:
1093 	default:
1094 		return 51;
1095 	}
1096 }
1097 
1098 static u8 hevc_profile_to_mcu_profile(enum v4l2_mpeg_video_hevc_profile profile)
1099 {
1100 	switch (profile) {
1101 	default:
1102 	case V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN:
1103 		return 1;
1104 	case V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10:
1105 		return 2;
1106 	case V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE:
1107 		return 3;
1108 	}
1109 }
1110 
1111 static u16 hevc_level_to_mcu_level(enum v4l2_mpeg_video_hevc_level level)
1112 {
1113 	switch (level) {
1114 	case V4L2_MPEG_VIDEO_HEVC_LEVEL_1:
1115 		return 10;
1116 	case V4L2_MPEG_VIDEO_HEVC_LEVEL_2:
1117 		return 20;
1118 	case V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1:
1119 		return 21;
1120 	case V4L2_MPEG_VIDEO_HEVC_LEVEL_3:
1121 		return 30;
1122 	case V4L2_MPEG_VIDEO_HEVC_LEVEL_3_1:
1123 		return 31;
1124 	case V4L2_MPEG_VIDEO_HEVC_LEVEL_4:
1125 		return 40;
1126 	case V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1:
1127 		return 41;
1128 	case V4L2_MPEG_VIDEO_HEVC_LEVEL_5:
1129 		return 50;
1130 	default:
1131 	case V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1:
1132 		return 51;
1133 	}
1134 }
1135 
1136 static u8 hevc_tier_to_mcu_tier(enum v4l2_mpeg_video_hevc_tier tier)
1137 {
1138 	switch (tier) {
1139 	default:
1140 	case V4L2_MPEG_VIDEO_HEVC_TIER_MAIN:
1141 		return 0;
1142 	case V4L2_MPEG_VIDEO_HEVC_TIER_HIGH:
1143 		return 1;
1144 	}
1145 }
1146 
1147 static u32
1148 v4l2_bitrate_mode_to_mcu_mode(enum v4l2_mpeg_video_bitrate_mode mode)
1149 {
1150 	switch (mode) {
1151 	case V4L2_MPEG_VIDEO_BITRATE_MODE_VBR:
1152 		return 2;
1153 	case V4L2_MPEG_VIDEO_BITRATE_MODE_CBR:
1154 	default:
1155 		return 1;
1156 	}
1157 }
1158 
1159 static u32 v4l2_cpb_size_to_mcu(unsigned int cpb_size, unsigned int bitrate)
1160 {
1161 	unsigned int cpb_size_kbit;
1162 	unsigned int bitrate_kbps;
1163 
1164 	/*
1165 	 * The mcu expects the CPB size in units of a 90 kHz clock, but the
1166 	 * channel follows the V4L2_CID_MPEG_VIDEO_H264_CPB_SIZE and stores
1167 	 * the CPB size in kilobytes.
1168 	 */
1169 	cpb_size_kbit = cpb_size * BITS_PER_BYTE;
1170 	bitrate_kbps = bitrate / 1000;
1171 
1172 	return (cpb_size_kbit * 90000) / bitrate_kbps;
1173 }
1174 
1175 static s16 get_qp_delta(int minuend, int subtrahend)
1176 {
1177 	if (minuend == subtrahend)
1178 		return -1;
1179 	else
1180 		return minuend - subtrahend;
1181 }
1182 
1183 static u32 allegro_channel_get_entropy_mode(struct allegro_channel *channel)
1184 {
1185 #define ALLEGRO_ENTROPY_MODE_CAVLC 0
1186 #define ALLEGRO_ENTROPY_MODE_CABAC 1
1187 
1188 	/* HEVC always uses CABAC, but this has to be explicitly set */
1189 	if (channel->codec == V4L2_PIX_FMT_HEVC)
1190 		return ALLEGRO_ENTROPY_MODE_CABAC;
1191 
1192 	return ALLEGRO_ENTROPY_MODE_CAVLC;
1193 }
1194 
1195 static int fill_create_channel_param(struct allegro_channel *channel,
1196 				     struct create_channel_param *param)
1197 {
1198 	int i_frame_qp = allegro_channel_get_i_frame_qp(channel);
1199 	int p_frame_qp = allegro_channel_get_p_frame_qp(channel);
1200 	int b_frame_qp = allegro_channel_get_b_frame_qp(channel);
1201 	int bitrate_mode = v4l2_ctrl_g_ctrl(channel->mpeg_video_bitrate_mode);
1202 	unsigned int cpb_size = v4l2_ctrl_g_ctrl(channel->mpeg_video_cpb_size);
1203 
1204 	param->width = channel->width;
1205 	param->height = channel->height;
1206 	param->format = v4l2_pixelformat_to_mcu_format(channel->pixelformat);
1207 	param->colorspace =
1208 		v4l2_colorspace_to_mcu_colorspace(channel->colorspace);
1209 	param->src_mode = 0x0;
1210 
1211 	param->codec = channel->codec;
1212 	if (channel->codec == V4L2_PIX_FMT_H264) {
1213 		enum v4l2_mpeg_video_h264_profile profile;
1214 		enum v4l2_mpeg_video_h264_level level;
1215 
1216 		profile = v4l2_ctrl_g_ctrl(channel->mpeg_video_h264_profile);
1217 		level = v4l2_ctrl_g_ctrl(channel->mpeg_video_h264_level);
1218 
1219 		param->profile = v4l2_profile_to_mcu_profile(profile);
1220 		param->constraint_set_flags = BIT(1);
1221 		param->level = v4l2_level_to_mcu_level(level);
1222 	} else {
1223 		enum v4l2_mpeg_video_hevc_profile profile;
1224 		enum v4l2_mpeg_video_hevc_level level;
1225 		enum v4l2_mpeg_video_hevc_tier tier;
1226 
1227 		profile = v4l2_ctrl_g_ctrl(channel->mpeg_video_hevc_profile);
1228 		level = v4l2_ctrl_g_ctrl(channel->mpeg_video_hevc_level);
1229 		tier = v4l2_ctrl_g_ctrl(channel->mpeg_video_hevc_tier);
1230 
1231 		param->profile = hevc_profile_to_mcu_profile(profile);
1232 		param->level = hevc_level_to_mcu_level(level);
1233 		param->tier = hevc_tier_to_mcu_tier(tier);
1234 	}
1235 
1236 	param->log2_max_poc = LOG2_MAX_PIC_ORDER_CNT;
1237 	param->log2_max_frame_num = channel->log2_max_frame_num;
1238 	param->temporal_mvp_enable = channel->temporal_mvp_enable;
1239 
1240 	param->dbf_ovr_en = channel->dbf_ovr_en;
1241 	param->override_lf = channel->enable_deblocking_filter_override;
1242 	param->enable_reordering = channel->enable_reordering;
1243 	param->entropy_mode = allegro_channel_get_entropy_mode(channel);
1244 	param->rdo_cost_mode = 1;
1245 	param->custom_lda = 1;
1246 	param->lf = 1;
1247 	param->lf_x_tile = channel->enable_loop_filter_across_tiles;
1248 	param->lf_x_slice = channel->enable_loop_filter_across_slices;
1249 
1250 	param->src_bit_depth = 8;
1251 
1252 	param->beta_offset = BETA_OFFSET_DIV_2;
1253 	param->tc_offset = TC_OFFSET_DIV_2;
1254 	param->num_slices = 1;
1255 	param->me_range[0] = channel->b_hrz_me_range;
1256 	param->me_range[1] = channel->b_vrt_me_range;
1257 	param->me_range[2] = channel->p_hrz_me_range;
1258 	param->me_range[3] = channel->p_vrt_me_range;
1259 	param->max_cu_size = channel->max_cu_size;
1260 	param->min_cu_size = channel->min_cu_size;
1261 	param->max_tu_size = channel->max_tu_size;
1262 	param->min_tu_size = channel->min_tu_size;
1263 	param->max_transfo_depth_intra = channel->max_transfo_depth_intra;
1264 	param->max_transfo_depth_inter = channel->max_transfo_depth_inter;
1265 
1266 	param->encoder_buffer_enabled = v4l2_ctrl_g_ctrl(channel->encoder_buffer);
1267 	param->encoder_buffer_offset = 0;
1268 
1269 	param->rate_control_mode = channel->frame_rc_enable ?
1270 		v4l2_bitrate_mode_to_mcu_mode(bitrate_mode) : 0;
1271 
1272 	param->cpb_size = v4l2_cpb_size_to_mcu(cpb_size, channel->bitrate_peak);
1273 	/* Shall be ]0;cpb_size in 90 kHz units]. Use maximum value. */
1274 	param->initial_rem_delay = param->cpb_size;
1275 	param->framerate = DIV_ROUND_UP(channel->framerate.numerator,
1276 					channel->framerate.denominator);
1277 	param->clk_ratio = channel->framerate.denominator == 1001 ? 1001 : 1000;
1278 	param->target_bitrate = channel->bitrate;
1279 	param->max_bitrate = channel->bitrate_peak;
1280 	param->initial_qp = i_frame_qp;
1281 	param->min_qp = allegro_channel_get_min_qp(channel);
1282 	param->max_qp = allegro_channel_get_max_qp(channel);
1283 	param->ip_delta = get_qp_delta(i_frame_qp, p_frame_qp);
1284 	param->pb_delta = get_qp_delta(p_frame_qp, b_frame_qp);
1285 	param->golden_ref = 0;
1286 	param->golden_delta = 2;
1287 	param->golden_ref_frequency = 10;
1288 	param->rate_control_option = 0x00000000;
1289 
1290 	param->num_pixel = channel->width + channel->height;
1291 	param->max_psnr = 4200;
1292 	param->max_pixel_value = 255;
1293 
1294 	param->gop_ctrl_mode = 0x00000002;
1295 	param->freq_idr = v4l2_ctrl_g_ctrl(channel->mpeg_video_gop_size);
1296 	param->freq_lt = 0;
1297 	param->gdr_mode = 0x00000000;
1298 	param->gop_length = v4l2_ctrl_g_ctrl(channel->mpeg_video_gop_size);
1299 	param->subframe_latency = 0x00000000;
1300 
1301 	param->lda_factors[0] = 51;
1302 	param->lda_factors[1] = 90;
1303 	param->lda_factors[2] = 151;
1304 	param->lda_factors[3] = 151;
1305 	param->lda_factors[4] = 151;
1306 	param->lda_factors[5] = 151;
1307 
1308 	param->max_num_merge_cand = 5;
1309 
1310 	return 0;
1311 }
1312 
1313 static int allegro_mcu_send_create_channel(struct allegro_dev *dev,
1314 					   struct allegro_channel *channel)
1315 {
1316 	struct mcu_msg_create_channel msg;
1317 	struct allegro_buffer *blob = &channel->config_blob;
1318 	struct create_channel_param param;
1319 	size_t size;
1320 
1321 	memset(&param, 0, sizeof(param));
1322 	fill_create_channel_param(channel, &param);
1323 	allegro_alloc_buffer(dev, blob, sizeof(struct create_channel_param));
1324 	param.version = dev->fw_info->mailbox_version;
1325 	size = allegro_encode_config_blob(blob->vaddr, &param);
1326 
1327 	memset(&msg, 0, sizeof(msg));
1328 
1329 	msg.header.type = MCU_MSG_TYPE_CREATE_CHANNEL;
1330 	msg.header.version = dev->fw_info->mailbox_version;
1331 
1332 	msg.user_id = channel->user_id;
1333 
1334 	msg.blob = blob->vaddr;
1335 	msg.blob_size = size;
1336 	msg.blob_mcu_addr = to_mcu_addr(dev, blob->paddr);
1337 
1338 	allegro_mbox_send(dev->mbox_command, &msg);
1339 
1340 	return 0;
1341 }
1342 
1343 static int allegro_mcu_send_destroy_channel(struct allegro_dev *dev,
1344 					    struct allegro_channel *channel)
1345 {
1346 	struct mcu_msg_destroy_channel msg;
1347 
1348 	memset(&msg, 0, sizeof(msg));
1349 
1350 	msg.header.type = MCU_MSG_TYPE_DESTROY_CHANNEL;
1351 	msg.header.version = dev->fw_info->mailbox_version;
1352 
1353 	msg.channel_id = channel->mcu_channel_id;
1354 
1355 	allegro_mbox_send(dev->mbox_command, &msg);
1356 
1357 	return 0;
1358 }
1359 
1360 static int allegro_mcu_send_put_stream_buffer(struct allegro_dev *dev,
1361 					      struct allegro_channel *channel,
1362 					      dma_addr_t paddr,
1363 					      unsigned long size,
1364 					      u64 dst_handle)
1365 {
1366 	struct mcu_msg_put_stream_buffer msg;
1367 
1368 	memset(&msg, 0, sizeof(msg));
1369 
1370 	msg.header.type = MCU_MSG_TYPE_PUT_STREAM_BUFFER;
1371 	msg.header.version = dev->fw_info->mailbox_version;
1372 
1373 	msg.channel_id = channel->mcu_channel_id;
1374 	msg.dma_addr = to_codec_addr(dev, paddr);
1375 	msg.mcu_addr = to_mcu_addr(dev, paddr);
1376 	msg.size = size;
1377 	msg.offset = ENCODER_STREAM_OFFSET;
1378 	/* copied to mcu_msg_encode_frame_response */
1379 	msg.dst_handle = dst_handle;
1380 
1381 	allegro_mbox_send(dev->mbox_command, &msg);
1382 
1383 	return 0;
1384 }
1385 
1386 static int allegro_mcu_send_encode_frame(struct allegro_dev *dev,
1387 					 struct allegro_channel *channel,
1388 					 dma_addr_t src_y, dma_addr_t src_uv,
1389 					 u64 src_handle)
1390 {
1391 	struct mcu_msg_encode_frame msg;
1392 	bool use_encoder_buffer = v4l2_ctrl_g_ctrl(channel->encoder_buffer);
1393 
1394 	memset(&msg, 0, sizeof(msg));
1395 
1396 	msg.header.type = MCU_MSG_TYPE_ENCODE_FRAME;
1397 	msg.header.version = dev->fw_info->mailbox_version;
1398 
1399 	msg.channel_id = channel->mcu_channel_id;
1400 	msg.encoding_options = AL_OPT_FORCE_LOAD;
1401 	if (use_encoder_buffer)
1402 		msg.encoding_options |= AL_OPT_USE_L2;
1403 	msg.pps_qp = 26; /* qp are relative to 26 */
1404 	msg.user_param = 0; /* copied to mcu_msg_encode_frame_response */
1405 	/* src_handle is copied to mcu_msg_encode_frame_response */
1406 	msg.src_handle = src_handle;
1407 	msg.src_y = to_codec_addr(dev, src_y);
1408 	msg.src_uv = to_codec_addr(dev, src_uv);
1409 	msg.stride = channel->stride;
1410 
1411 	allegro_mbox_send(dev->mbox_command, &msg);
1412 
1413 	return 0;
1414 }
1415 
1416 static int allegro_mcu_wait_for_init_timeout(struct allegro_dev *dev,
1417 					     unsigned long timeout_ms)
1418 {
1419 	unsigned long tmo;
1420 
1421 	tmo = wait_for_completion_timeout(&dev->init_complete,
1422 					  msecs_to_jiffies(timeout_ms));
1423 	if (tmo == 0)
1424 		return -ETIMEDOUT;
1425 
1426 	reinit_completion(&dev->init_complete);
1427 	return 0;
1428 }
1429 
1430 static int allegro_mcu_push_buffer_internal(struct allegro_channel *channel,
1431 					    enum mcu_msg_type type)
1432 {
1433 	struct allegro_dev *dev = channel->dev;
1434 	struct mcu_msg_push_buffers_internal *msg;
1435 	struct mcu_msg_push_buffers_internal_buffer *buffer;
1436 	unsigned int num_buffers = 0;
1437 	size_t size;
1438 	struct allegro_buffer *al_buffer;
1439 	struct list_head *list;
1440 	int err;
1441 
1442 	switch (type) {
1443 	case MCU_MSG_TYPE_PUSH_BUFFER_REFERENCE:
1444 		list = &channel->buffers_reference;
1445 		break;
1446 	case MCU_MSG_TYPE_PUSH_BUFFER_INTERMEDIATE:
1447 		list = &channel->buffers_intermediate;
1448 		break;
1449 	default:
1450 		return -EINVAL;
1451 	}
1452 
1453 	list_for_each_entry(al_buffer, list, head)
1454 		num_buffers++;
1455 	size = struct_size(msg, buffer, num_buffers);
1456 
1457 	msg = kmalloc(size, GFP_KERNEL);
1458 	if (!msg)
1459 		return -ENOMEM;
1460 
1461 	msg->header.type = type;
1462 	msg->header.version = dev->fw_info->mailbox_version;
1463 
1464 	msg->channel_id = channel->mcu_channel_id;
1465 	msg->num_buffers = num_buffers;
1466 
1467 	buffer = msg->buffer;
1468 	list_for_each_entry(al_buffer, list, head) {
1469 		buffer->dma_addr = to_codec_addr(dev, al_buffer->paddr);
1470 		buffer->mcu_addr = to_mcu_addr(dev, al_buffer->paddr);
1471 		buffer->size = to_mcu_size(dev, al_buffer->size);
1472 		buffer++;
1473 	}
1474 
1475 	err = allegro_mbox_send(dev->mbox_command, msg);
1476 
1477 	kfree(msg);
1478 	return err;
1479 }
1480 
1481 static int allegro_mcu_push_buffer_intermediate(struct allegro_channel *channel)
1482 {
1483 	enum mcu_msg_type type = MCU_MSG_TYPE_PUSH_BUFFER_INTERMEDIATE;
1484 
1485 	return allegro_mcu_push_buffer_internal(channel, type);
1486 }
1487 
1488 static int allegro_mcu_push_buffer_reference(struct allegro_channel *channel)
1489 {
1490 	enum mcu_msg_type type = MCU_MSG_TYPE_PUSH_BUFFER_REFERENCE;
1491 
1492 	return allegro_mcu_push_buffer_internal(channel, type);
1493 }
1494 
1495 static int allocate_buffers_internal(struct allegro_channel *channel,
1496 				     struct list_head *list,
1497 				     size_t n, size_t size)
1498 {
1499 	struct allegro_dev *dev = channel->dev;
1500 	unsigned int i;
1501 	int err;
1502 	struct allegro_buffer *buffer, *tmp;
1503 
1504 	for (i = 0; i < n; i++) {
1505 		buffer = kmalloc(sizeof(*buffer), GFP_KERNEL);
1506 		if (!buffer) {
1507 			err = -ENOMEM;
1508 			goto err;
1509 		}
1510 		INIT_LIST_HEAD(&buffer->head);
1511 
1512 		err = allegro_alloc_buffer(dev, buffer, size);
1513 		if (err)
1514 			goto err;
1515 		list_add(&buffer->head, list);
1516 	}
1517 
1518 	return 0;
1519 
1520 err:
1521 	list_for_each_entry_safe(buffer, tmp, list, head) {
1522 		list_del(&buffer->head);
1523 		allegro_free_buffer(dev, buffer);
1524 		kfree(buffer);
1525 	}
1526 	return err;
1527 }
1528 
1529 static void destroy_buffers_internal(struct allegro_channel *channel,
1530 				     struct list_head *list)
1531 {
1532 	struct allegro_dev *dev = channel->dev;
1533 	struct allegro_buffer *buffer, *tmp;
1534 
1535 	list_for_each_entry_safe(buffer, tmp, list, head) {
1536 		list_del(&buffer->head);
1537 		allegro_free_buffer(dev, buffer);
1538 		kfree(buffer);
1539 	}
1540 }
1541 
1542 static void destroy_reference_buffers(struct allegro_channel *channel)
1543 {
1544 	return destroy_buffers_internal(channel, &channel->buffers_reference);
1545 }
1546 
1547 static void destroy_intermediate_buffers(struct allegro_channel *channel)
1548 {
1549 	return destroy_buffers_internal(channel,
1550 					&channel->buffers_intermediate);
1551 }
1552 
1553 static int allocate_intermediate_buffers(struct allegro_channel *channel,
1554 					 size_t n, size_t size)
1555 {
1556 	return allocate_buffers_internal(channel,
1557 					 &channel->buffers_intermediate,
1558 					 n, size);
1559 }
1560 
1561 static int allocate_reference_buffers(struct allegro_channel *channel,
1562 				      size_t n, size_t size)
1563 {
1564 	return allocate_buffers_internal(channel,
1565 					 &channel->buffers_reference,
1566 					 n, PAGE_ALIGN(size));
1567 }
1568 
1569 static ssize_t allegro_h264_write_sps(struct allegro_channel *channel,
1570 				      void *dest, size_t n)
1571 {
1572 	struct allegro_dev *dev = channel->dev;
1573 	struct nal_h264_sps *sps;
1574 	ssize_t size;
1575 	unsigned int size_mb = SIZE_MACROBLOCK;
1576 	/* Calculation of crop units in Rec. ITU-T H.264 (04/2017) p. 76 */
1577 	unsigned int crop_unit_x = 2;
1578 	unsigned int crop_unit_y = 2;
1579 	enum v4l2_mpeg_video_h264_profile profile;
1580 	enum v4l2_mpeg_video_h264_level level;
1581 	unsigned int cpb_size;
1582 	unsigned int cpb_size_scale;
1583 
1584 	sps = kzalloc(sizeof(*sps), GFP_KERNEL);
1585 	if (!sps)
1586 		return -ENOMEM;
1587 
1588 	profile = v4l2_ctrl_g_ctrl(channel->mpeg_video_h264_profile);
1589 	level = v4l2_ctrl_g_ctrl(channel->mpeg_video_h264_level);
1590 
1591 	sps->profile_idc = nal_h264_profile(profile);
1592 	sps->constraint_set0_flag = 0;
1593 	sps->constraint_set1_flag = 1;
1594 	sps->constraint_set2_flag = 0;
1595 	sps->constraint_set3_flag = 0;
1596 	sps->constraint_set4_flag = 0;
1597 	sps->constraint_set5_flag = 0;
1598 	sps->level_idc = nal_h264_level(level);
1599 	sps->seq_parameter_set_id = 0;
1600 	sps->log2_max_frame_num_minus4 = LOG2_MAX_FRAME_NUM - 4;
1601 	sps->pic_order_cnt_type = 0;
1602 	sps->log2_max_pic_order_cnt_lsb_minus4 = LOG2_MAX_PIC_ORDER_CNT - 4;
1603 	sps->max_num_ref_frames = 3;
1604 	sps->gaps_in_frame_num_value_allowed_flag = 0;
1605 	sps->pic_width_in_mbs_minus1 =
1606 		DIV_ROUND_UP(channel->width, size_mb) - 1;
1607 	sps->pic_height_in_map_units_minus1 =
1608 		DIV_ROUND_UP(channel->height, size_mb) - 1;
1609 	sps->frame_mbs_only_flag = 1;
1610 	sps->mb_adaptive_frame_field_flag = 0;
1611 	sps->direct_8x8_inference_flag = 1;
1612 	sps->frame_cropping_flag =
1613 		(channel->width % size_mb) || (channel->height % size_mb);
1614 	if (sps->frame_cropping_flag) {
1615 		sps->crop_left = 0;
1616 		sps->crop_right = (round_up(channel->width, size_mb) - channel->width) / crop_unit_x;
1617 		sps->crop_top = 0;
1618 		sps->crop_bottom = (round_up(channel->height, size_mb) - channel->height) / crop_unit_y;
1619 	}
1620 	sps->vui_parameters_present_flag = 1;
1621 	sps->vui.aspect_ratio_info_present_flag = 0;
1622 	sps->vui.overscan_info_present_flag = 0;
1623 
1624 	sps->vui.video_signal_type_present_flag = 1;
1625 	sps->vui.video_format = 5; /* unspecified */
1626 	sps->vui.video_full_range_flag = nal_h264_full_range(channel->quantization);
1627 	sps->vui.colour_description_present_flag = 1;
1628 	sps->vui.colour_primaries = nal_h264_color_primaries(channel->colorspace);
1629 	sps->vui.transfer_characteristics =
1630 		nal_h264_transfer_characteristics(channel->colorspace, channel->xfer_func);
1631 	sps->vui.matrix_coefficients =
1632 		nal_h264_matrix_coeffs(channel->colorspace, channel->ycbcr_enc);
1633 
1634 	sps->vui.chroma_loc_info_present_flag = 1;
1635 	sps->vui.chroma_sample_loc_type_top_field = 0;
1636 	sps->vui.chroma_sample_loc_type_bottom_field = 0;
1637 
1638 	sps->vui.timing_info_present_flag = 1;
1639 	sps->vui.num_units_in_tick = channel->framerate.denominator;
1640 	sps->vui.time_scale = 2 * channel->framerate.numerator;
1641 
1642 	sps->vui.fixed_frame_rate_flag = 1;
1643 	sps->vui.nal_hrd_parameters_present_flag = 0;
1644 	sps->vui.vcl_hrd_parameters_present_flag = 1;
1645 	sps->vui.vcl_hrd_parameters.cpb_cnt_minus1 = 0;
1646 	/* See Rec. ITU-T H.264 (04/2017) p. 410 E-53 */
1647 	sps->vui.vcl_hrd_parameters.bit_rate_scale =
1648 		ffs(channel->bitrate_peak) - 6;
1649 	sps->vui.vcl_hrd_parameters.bit_rate_value_minus1[0] =
1650 		channel->bitrate_peak / (1 << (6 + sps->vui.vcl_hrd_parameters.bit_rate_scale)) - 1;
1651 	/* See Rec. ITU-T H.264 (04/2017) p. 410 E-54 */
1652 	cpb_size = v4l2_ctrl_g_ctrl(channel->mpeg_video_cpb_size);
1653 	cpb_size_scale = ffs(cpb_size) - 4;
1654 	sps->vui.vcl_hrd_parameters.cpb_size_scale = cpb_size_scale;
1655 	sps->vui.vcl_hrd_parameters.cpb_size_value_minus1[0] =
1656 		(cpb_size * 1000) / (1 << (4 + cpb_size_scale)) - 1;
1657 	sps->vui.vcl_hrd_parameters.cbr_flag[0] =
1658 		!v4l2_ctrl_g_ctrl(channel->mpeg_video_frame_rc_enable);
1659 	sps->vui.vcl_hrd_parameters.initial_cpb_removal_delay_length_minus1 = 31;
1660 	sps->vui.vcl_hrd_parameters.cpb_removal_delay_length_minus1 = 31;
1661 	sps->vui.vcl_hrd_parameters.dpb_output_delay_length_minus1 = 31;
1662 	sps->vui.vcl_hrd_parameters.time_offset_length = 0;
1663 	sps->vui.low_delay_hrd_flag = 0;
1664 	sps->vui.pic_struct_present_flag = 1;
1665 	sps->vui.bitstream_restriction_flag = 0;
1666 
1667 	size = nal_h264_write_sps(&dev->plat_dev->dev, dest, n, sps);
1668 
1669 	kfree(sps);
1670 
1671 	return size;
1672 }
1673 
1674 static ssize_t allegro_h264_write_pps(struct allegro_channel *channel,
1675 				      void *dest, size_t n)
1676 {
1677 	struct allegro_dev *dev = channel->dev;
1678 	struct nal_h264_pps *pps;
1679 	ssize_t size;
1680 
1681 	pps = kzalloc(sizeof(*pps), GFP_KERNEL);
1682 	if (!pps)
1683 		return -ENOMEM;
1684 
1685 	pps->pic_parameter_set_id = 0;
1686 	pps->seq_parameter_set_id = 0;
1687 	pps->entropy_coding_mode_flag = 0;
1688 	pps->bottom_field_pic_order_in_frame_present_flag = 0;
1689 	pps->num_slice_groups_minus1 = 0;
1690 	pps->num_ref_idx_l0_default_active_minus1 = channel->num_ref_idx_l0 - 1;
1691 	pps->num_ref_idx_l1_default_active_minus1 = channel->num_ref_idx_l1 - 1;
1692 	pps->weighted_pred_flag = 0;
1693 	pps->weighted_bipred_idc = 0;
1694 	pps->pic_init_qp_minus26 = 0;
1695 	pps->pic_init_qs_minus26 = 0;
1696 	pps->chroma_qp_index_offset = 0;
1697 	pps->deblocking_filter_control_present_flag = 1;
1698 	pps->constrained_intra_pred_flag = 0;
1699 	pps->redundant_pic_cnt_present_flag = 0;
1700 	pps->transform_8x8_mode_flag = 0;
1701 	pps->pic_scaling_matrix_present_flag = 0;
1702 	pps->second_chroma_qp_index_offset = 0;
1703 
1704 	size = nal_h264_write_pps(&dev->plat_dev->dev, dest, n, pps);
1705 
1706 	kfree(pps);
1707 
1708 	return size;
1709 }
1710 
1711 static void allegro_channel_eos_event(struct allegro_channel *channel)
1712 {
1713 	const struct v4l2_event eos_event = {
1714 		.type = V4L2_EVENT_EOS
1715 	};
1716 
1717 	v4l2_event_queue_fh(&channel->fh, &eos_event);
1718 }
1719 
1720 static ssize_t allegro_hevc_write_vps(struct allegro_channel *channel,
1721 				      void *dest, size_t n)
1722 {
1723 	struct allegro_dev *dev = channel->dev;
1724 	struct nal_hevc_vps *vps;
1725 	struct nal_hevc_profile_tier_level *ptl;
1726 	ssize_t size;
1727 	unsigned int num_ref_frames = channel->num_ref_idx_l0;
1728 	s32 profile = v4l2_ctrl_g_ctrl(channel->mpeg_video_hevc_profile);
1729 	s32 level = v4l2_ctrl_g_ctrl(channel->mpeg_video_hevc_level);
1730 	s32 tier = v4l2_ctrl_g_ctrl(channel->mpeg_video_hevc_tier);
1731 
1732 	vps = kzalloc(sizeof(*vps), GFP_KERNEL);
1733 	if (!vps)
1734 		return -ENOMEM;
1735 
1736 	vps->base_layer_internal_flag = 1;
1737 	vps->base_layer_available_flag = 1;
1738 	vps->temporal_id_nesting_flag = 1;
1739 
1740 	ptl = &vps->profile_tier_level;
1741 	ptl->general_profile_idc = nal_hevc_profile(profile);
1742 	ptl->general_profile_compatibility_flag[ptl->general_profile_idc] = 1;
1743 	ptl->general_tier_flag = nal_hevc_tier(tier);
1744 	ptl->general_progressive_source_flag = 1;
1745 	ptl->general_frame_only_constraint_flag = 1;
1746 	ptl->general_level_idc = nal_hevc_level(level);
1747 
1748 	vps->sub_layer_ordering_info_present_flag = 0;
1749 	vps->max_dec_pic_buffering_minus1[0] = num_ref_frames;
1750 	vps->max_num_reorder_pics[0] = num_ref_frames;
1751 
1752 	size = nal_hevc_write_vps(&dev->plat_dev->dev, dest, n, vps);
1753 
1754 	kfree(vps);
1755 
1756 	return size;
1757 }
1758 
1759 static ssize_t allegro_hevc_write_sps(struct allegro_channel *channel,
1760 				      void *dest, size_t n)
1761 {
1762 	struct allegro_dev *dev = channel->dev;
1763 	struct nal_hevc_sps *sps;
1764 	struct nal_hevc_profile_tier_level *ptl;
1765 	struct nal_hevc_vui_parameters *vui;
1766 	struct nal_hevc_hrd_parameters *hrd;
1767 	ssize_t size;
1768 	unsigned int cpb_size;
1769 	unsigned int num_ref_frames = channel->num_ref_idx_l0;
1770 	s32 profile = v4l2_ctrl_g_ctrl(channel->mpeg_video_hevc_profile);
1771 	s32 level = v4l2_ctrl_g_ctrl(channel->mpeg_video_hevc_level);
1772 	s32 tier = v4l2_ctrl_g_ctrl(channel->mpeg_video_hevc_tier);
1773 
1774 	sps = kzalloc(sizeof(*sps), GFP_KERNEL);
1775 	if (!sps)
1776 		return -ENOMEM;
1777 
1778 	sps->temporal_id_nesting_flag = 1;
1779 
1780 	ptl = &sps->profile_tier_level;
1781 	ptl->general_profile_idc = nal_hevc_profile(profile);
1782 	ptl->general_profile_compatibility_flag[ptl->general_profile_idc] = 1;
1783 	ptl->general_tier_flag = nal_hevc_tier(tier);
1784 	ptl->general_progressive_source_flag = 1;
1785 	ptl->general_frame_only_constraint_flag = 1;
1786 	ptl->general_level_idc = nal_hevc_level(level);
1787 
1788 	sps->seq_parameter_set_id = 0;
1789 	sps->chroma_format_idc = 1; /* Only 4:2:0 sampling supported */
1790 	sps->pic_width_in_luma_samples = round_up(channel->width, 8);
1791 	sps->pic_height_in_luma_samples = round_up(channel->height, 8);
1792 	sps->conf_win_right_offset =
1793 		sps->pic_width_in_luma_samples - channel->width;
1794 	sps->conf_win_bottom_offset =
1795 		sps->pic_height_in_luma_samples - channel->height;
1796 	sps->conformance_window_flag =
1797 		sps->conf_win_right_offset || sps->conf_win_bottom_offset;
1798 
1799 	sps->log2_max_pic_order_cnt_lsb_minus4 = LOG2_MAX_PIC_ORDER_CNT - 4;
1800 
1801 	sps->sub_layer_ordering_info_present_flag = 1;
1802 	sps->max_dec_pic_buffering_minus1[0] = num_ref_frames;
1803 	sps->max_num_reorder_pics[0] = num_ref_frames;
1804 
1805 	sps->log2_min_luma_coding_block_size_minus3 =
1806 		channel->min_cu_size - 3;
1807 	sps->log2_diff_max_min_luma_coding_block_size =
1808 		channel->max_cu_size - channel->min_cu_size;
1809 	sps->log2_min_luma_transform_block_size_minus2 =
1810 		channel->min_tu_size - 2;
1811 	sps->log2_diff_max_min_luma_transform_block_size =
1812 		channel->max_tu_size - channel->min_tu_size;
1813 	sps->max_transform_hierarchy_depth_intra =
1814 		channel->max_transfo_depth_intra;
1815 	sps->max_transform_hierarchy_depth_inter =
1816 		channel->max_transfo_depth_inter;
1817 
1818 	sps->sps_temporal_mvp_enabled_flag = channel->temporal_mvp_enable;
1819 	sps->strong_intra_smoothing_enabled_flag = channel->max_cu_size > 4;
1820 
1821 	sps->vui_parameters_present_flag = 1;
1822 	vui = &sps->vui;
1823 
1824 	vui->video_signal_type_present_flag = 1;
1825 	vui->video_format = 5; /* unspecified */
1826 	vui->video_full_range_flag = nal_hevc_full_range(channel->quantization);
1827 	vui->colour_description_present_flag = 1;
1828 	vui->colour_primaries = nal_hevc_color_primaries(channel->colorspace);
1829 	vui->transfer_characteristics = nal_hevc_transfer_characteristics(channel->colorspace,
1830 									  channel->xfer_func);
1831 	vui->matrix_coeffs = nal_hevc_matrix_coeffs(channel->colorspace, channel->ycbcr_enc);
1832 
1833 	vui->chroma_loc_info_present_flag = 1;
1834 	vui->chroma_sample_loc_type_top_field = 0;
1835 	vui->chroma_sample_loc_type_bottom_field = 0;
1836 
1837 	vui->vui_timing_info_present_flag = 1;
1838 	vui->vui_num_units_in_tick = channel->framerate.denominator;
1839 	vui->vui_time_scale = channel->framerate.numerator;
1840 
1841 	vui->bitstream_restriction_flag = 1;
1842 	vui->motion_vectors_over_pic_boundaries_flag = 1;
1843 	vui->restricted_ref_pic_lists_flag = 1;
1844 	vui->log2_max_mv_length_horizontal = 15;
1845 	vui->log2_max_mv_length_vertical = 15;
1846 
1847 	vui->vui_hrd_parameters_present_flag = 1;
1848 	hrd = &vui->nal_hrd_parameters;
1849 	hrd->vcl_hrd_parameters_present_flag = 1;
1850 
1851 	hrd->initial_cpb_removal_delay_length_minus1 = 31;
1852 	hrd->au_cpb_removal_delay_length_minus1 = 30;
1853 	hrd->dpb_output_delay_length_minus1 = 30;
1854 
1855 	hrd->bit_rate_scale = ffs(channel->bitrate_peak) - 6;
1856 	hrd->vcl_hrd[0].bit_rate_value_minus1[0] =
1857 		(channel->bitrate_peak >> (6 + hrd->bit_rate_scale)) - 1;
1858 
1859 	cpb_size = v4l2_ctrl_g_ctrl(channel->mpeg_video_cpb_size) * 1000;
1860 	hrd->cpb_size_scale = ffs(cpb_size) - 4;
1861 	hrd->vcl_hrd[0].cpb_size_value_minus1[0] = (cpb_size >> (4 + hrd->cpb_size_scale)) - 1;
1862 
1863 	hrd->vcl_hrd[0].cbr_flag[0] = !v4l2_ctrl_g_ctrl(channel->mpeg_video_frame_rc_enable);
1864 
1865 	size = nal_hevc_write_sps(&dev->plat_dev->dev, dest, n, sps);
1866 
1867 	kfree(sps);
1868 
1869 	return size;
1870 }
1871 
1872 static ssize_t allegro_hevc_write_pps(struct allegro_channel *channel,
1873 				      struct mcu_msg_encode_frame_response *msg,
1874 				      void *dest, size_t n)
1875 {
1876 	struct allegro_dev *dev = channel->dev;
1877 	struct nal_hevc_pps *pps;
1878 	ssize_t size;
1879 	int i;
1880 
1881 	pps = kzalloc(sizeof(*pps), GFP_KERNEL);
1882 	if (!pps)
1883 		return -ENOMEM;
1884 
1885 	pps->pps_pic_parameter_set_id = 0;
1886 	pps->pps_seq_parameter_set_id = 0;
1887 
1888 	if (msg->num_column > 1 || msg->num_row > 1) {
1889 		pps->tiles_enabled_flag = 1;
1890 		pps->num_tile_columns_minus1 = msg->num_column - 1;
1891 		pps->num_tile_rows_minus1 = msg->num_row - 1;
1892 
1893 		for (i = 0; i < msg->num_column; i++)
1894 			pps->column_width_minus1[i] = msg->tile_width[i] - 1;
1895 
1896 		for (i = 0; i < msg->num_row; i++)
1897 			pps->row_height_minus1[i] = msg->tile_height[i] - 1;
1898 	}
1899 
1900 	pps->loop_filter_across_tiles_enabled_flag =
1901 		channel->enable_loop_filter_across_tiles;
1902 	pps->pps_loop_filter_across_slices_enabled_flag =
1903 		channel->enable_loop_filter_across_slices;
1904 	pps->deblocking_filter_control_present_flag = 1;
1905 	pps->deblocking_filter_override_enabled_flag =
1906 		channel->enable_deblocking_filter_override;
1907 	pps->pps_beta_offset_div2 = BETA_OFFSET_DIV_2;
1908 	pps->pps_tc_offset_div2 = TC_OFFSET_DIV_2;
1909 
1910 	pps->lists_modification_present_flag = channel->enable_reordering;
1911 
1912 	size = nal_hevc_write_pps(&dev->plat_dev->dev, dest, n, pps);
1913 
1914 	kfree(pps);
1915 
1916 	return size;
1917 }
1918 
1919 static u64 allegro_put_buffer(struct allegro_channel *channel,
1920 			      struct list_head *list,
1921 			      struct vb2_v4l2_buffer *buffer)
1922 {
1923 	struct v4l2_m2m_buffer *b = container_of(buffer,
1924 						 struct v4l2_m2m_buffer, vb);
1925 	struct allegro_m2m_buffer *shadow = to_allegro_m2m_buffer(b);
1926 
1927 	mutex_lock(&channel->shadow_list_lock);
1928 	list_add_tail(&shadow->head, list);
1929 	mutex_unlock(&channel->shadow_list_lock);
1930 
1931 	return ptr_to_u64(buffer);
1932 }
1933 
1934 static struct vb2_v4l2_buffer *
1935 allegro_get_buffer(struct allegro_channel *channel,
1936 		   struct list_head *list, u64 handle)
1937 {
1938 	struct allegro_m2m_buffer *shadow, *tmp;
1939 	struct vb2_v4l2_buffer *buffer = NULL;
1940 
1941 	mutex_lock(&channel->shadow_list_lock);
1942 	list_for_each_entry_safe(shadow, tmp, list, head) {
1943 		if (handle == ptr_to_u64(&shadow->buf.vb)) {
1944 			buffer = &shadow->buf.vb;
1945 			list_del_init(&shadow->head);
1946 			break;
1947 		}
1948 	}
1949 	mutex_unlock(&channel->shadow_list_lock);
1950 
1951 	return buffer;
1952 }
1953 
1954 static void allegro_channel_finish_frame(struct allegro_channel *channel,
1955 		struct mcu_msg_encode_frame_response *msg)
1956 {
1957 	struct allegro_dev *dev = channel->dev;
1958 	struct vb2_v4l2_buffer *src_buf;
1959 	struct vb2_v4l2_buffer *dst_buf;
1960 	struct {
1961 		u32 offset;
1962 		u32 size;
1963 	} *partition;
1964 	enum vb2_buffer_state state = VB2_BUF_STATE_ERROR;
1965 	char *curr;
1966 	ssize_t len;
1967 	ssize_t free;
1968 
1969 	src_buf = allegro_get_buffer(channel, &channel->source_shadow_list,
1970 				     msg->src_handle);
1971 	if (!src_buf)
1972 		v4l2_warn(&dev->v4l2_dev,
1973 			  "channel %d: invalid source buffer\n",
1974 			  channel->mcu_channel_id);
1975 
1976 	dst_buf = allegro_get_buffer(channel, &channel->stream_shadow_list,
1977 				     msg->dst_handle);
1978 	if (!dst_buf)
1979 		v4l2_warn(&dev->v4l2_dev,
1980 			  "channel %d: invalid stream buffer\n",
1981 			  channel->mcu_channel_id);
1982 
1983 	if (!src_buf || !dst_buf)
1984 		goto err;
1985 
1986 	if (v4l2_m2m_is_last_draining_src_buf(channel->fh.m2m_ctx, src_buf)) {
1987 		dst_buf->flags |= V4L2_BUF_FLAG_LAST;
1988 		allegro_channel_eos_event(channel);
1989 		v4l2_m2m_mark_stopped(channel->fh.m2m_ctx);
1990 	}
1991 
1992 	dst_buf->sequence = channel->csequence++;
1993 
1994 	if (msg->error_code & AL_ERROR) {
1995 		v4l2_err(&dev->v4l2_dev,
1996 			 "channel %d: failed to encode frame: %s (%x)\n",
1997 			 channel->mcu_channel_id,
1998 			 allegro_err_to_string(msg->error_code),
1999 			 msg->error_code);
2000 		goto err;
2001 	}
2002 
2003 	if (msg->partition_table_size != 1) {
2004 		v4l2_warn(&dev->v4l2_dev,
2005 			  "channel %d: only handling first partition table entry (%d entries)\n",
2006 			  channel->mcu_channel_id, msg->partition_table_size);
2007 	}
2008 
2009 	if (msg->partition_table_offset +
2010 	    msg->partition_table_size * sizeof(*partition) >
2011 	    vb2_plane_size(&dst_buf->vb2_buf, 0)) {
2012 		v4l2_err(&dev->v4l2_dev,
2013 			 "channel %d: partition table outside of dst_buf\n",
2014 			 channel->mcu_channel_id);
2015 		goto err;
2016 	}
2017 
2018 	partition =
2019 	    vb2_plane_vaddr(&dst_buf->vb2_buf, 0) + msg->partition_table_offset;
2020 	if (partition->offset + partition->size >
2021 	    vb2_plane_size(&dst_buf->vb2_buf, 0)) {
2022 		v4l2_err(&dev->v4l2_dev,
2023 			 "channel %d: encoded frame is outside of dst_buf (offset 0x%x, size 0x%x)\n",
2024 			 channel->mcu_channel_id, partition->offset,
2025 			 partition->size);
2026 		goto err;
2027 	}
2028 
2029 	v4l2_dbg(2, debug, &dev->v4l2_dev,
2030 		 "channel %d: encoded frame of size %d is at offset 0x%x\n",
2031 		 channel->mcu_channel_id, partition->size, partition->offset);
2032 
2033 	/*
2034 	 * The payload must include the data before the partition offset,
2035 	 * because we will put the sps and pps data there.
2036 	 */
2037 	vb2_set_plane_payload(&dst_buf->vb2_buf, 0,
2038 			      partition->offset + partition->size);
2039 
2040 	curr = vb2_plane_vaddr(&dst_buf->vb2_buf, 0);
2041 	free = partition->offset;
2042 
2043 	if (channel->codec == V4L2_PIX_FMT_HEVC && msg->is_idr) {
2044 		len = allegro_hevc_write_vps(channel, curr, free);
2045 		if (len < 0) {
2046 			v4l2_err(&dev->v4l2_dev,
2047 				 "not enough space for video parameter set: %zd left\n",
2048 				 free);
2049 			goto err;
2050 		}
2051 		curr += len;
2052 		free -= len;
2053 		v4l2_dbg(1, debug, &dev->v4l2_dev,
2054 			 "channel %d: wrote %zd byte VPS nal unit\n",
2055 			 channel->mcu_channel_id, len);
2056 	}
2057 
2058 	if (msg->is_idr) {
2059 		if (channel->codec == V4L2_PIX_FMT_H264)
2060 			len = allegro_h264_write_sps(channel, curr, free);
2061 		else
2062 			len = allegro_hevc_write_sps(channel, curr, free);
2063 		if (len < 0) {
2064 			v4l2_err(&dev->v4l2_dev,
2065 				 "not enough space for sequence parameter set: %zd left\n",
2066 				 free);
2067 			goto err;
2068 		}
2069 		curr += len;
2070 		free -= len;
2071 		v4l2_dbg(1, debug, &dev->v4l2_dev,
2072 			 "channel %d: wrote %zd byte SPS nal unit\n",
2073 			 channel->mcu_channel_id, len);
2074 	}
2075 
2076 	if (msg->slice_type == AL_ENC_SLICE_TYPE_I) {
2077 		if (channel->codec == V4L2_PIX_FMT_H264)
2078 			len = allegro_h264_write_pps(channel, curr, free);
2079 		else
2080 			len = allegro_hevc_write_pps(channel, msg, curr, free);
2081 		if (len < 0) {
2082 			v4l2_err(&dev->v4l2_dev,
2083 				 "not enough space for picture parameter set: %zd left\n",
2084 				 free);
2085 			goto err;
2086 		}
2087 		curr += len;
2088 		free -= len;
2089 		v4l2_dbg(1, debug, &dev->v4l2_dev,
2090 			 "channel %d: wrote %zd byte PPS nal unit\n",
2091 			 channel->mcu_channel_id, len);
2092 	}
2093 
2094 	if (msg->slice_type != AL_ENC_SLICE_TYPE_I && !msg->is_idr) {
2095 		dst_buf->vb2_buf.planes[0].data_offset = free;
2096 		free = 0;
2097 	} else {
2098 		if (channel->codec == V4L2_PIX_FMT_H264)
2099 			len = nal_h264_write_filler(&dev->plat_dev->dev, curr, free);
2100 		else
2101 			len = nal_hevc_write_filler(&dev->plat_dev->dev, curr, free);
2102 		if (len < 0) {
2103 			v4l2_err(&dev->v4l2_dev,
2104 				 "failed to write %zd filler data\n", free);
2105 			goto err;
2106 		}
2107 		curr += len;
2108 		free -= len;
2109 		v4l2_dbg(2, debug, &dev->v4l2_dev,
2110 			 "channel %d: wrote %zd bytes filler nal unit\n",
2111 			 channel->mcu_channel_id, len);
2112 	}
2113 
2114 	if (free != 0) {
2115 		v4l2_err(&dev->v4l2_dev,
2116 			 "non-VCL NAL units do not fill space until VCL NAL unit: %zd bytes left\n",
2117 			 free);
2118 		goto err;
2119 	}
2120 
2121 	state = VB2_BUF_STATE_DONE;
2122 
2123 	v4l2_m2m_buf_copy_metadata(src_buf, dst_buf, false);
2124 	if (msg->is_idr)
2125 		dst_buf->flags |= V4L2_BUF_FLAG_KEYFRAME;
2126 	else
2127 		dst_buf->flags |= V4L2_BUF_FLAG_PFRAME;
2128 
2129 	v4l2_dbg(1, debug, &dev->v4l2_dev,
2130 		 "channel %d: encoded frame #%03d (%s%s, QP %d, %d bytes)\n",
2131 		 channel->mcu_channel_id,
2132 		 dst_buf->sequence,
2133 		 msg->is_idr ? "IDR, " : "",
2134 		 msg->slice_type == AL_ENC_SLICE_TYPE_I ? "I slice" :
2135 		 msg->slice_type == AL_ENC_SLICE_TYPE_P ? "P slice" : "unknown",
2136 		 msg->qp, partition->size);
2137 
2138 err:
2139 	if (src_buf)
2140 		v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
2141 
2142 	if (dst_buf)
2143 		v4l2_m2m_buf_done(dst_buf, state);
2144 }
2145 
2146 static int allegro_handle_init(struct allegro_dev *dev,
2147 			       struct mcu_msg_init_response *msg)
2148 {
2149 	complete(&dev->init_complete);
2150 
2151 	return 0;
2152 }
2153 
2154 static int
2155 allegro_handle_create_channel(struct allegro_dev *dev,
2156 			      struct mcu_msg_create_channel_response *msg)
2157 {
2158 	struct allegro_channel *channel;
2159 	int err = 0;
2160 	struct create_channel_param param;
2161 
2162 	channel = allegro_find_channel_by_user_id(dev, msg->user_id);
2163 	if (IS_ERR(channel)) {
2164 		v4l2_warn(&dev->v4l2_dev,
2165 			  "received %s for unknown user %d\n",
2166 			  msg_type_name(msg->header.type),
2167 			  msg->user_id);
2168 		return -EINVAL;
2169 	}
2170 
2171 	if (msg->error_code) {
2172 		v4l2_err(&dev->v4l2_dev,
2173 			 "user %d: mcu failed to create channel: %s (%x)\n",
2174 			 channel->user_id,
2175 			 allegro_err_to_string(msg->error_code),
2176 			 msg->error_code);
2177 		err = -EIO;
2178 		goto out;
2179 	}
2180 
2181 	channel->mcu_channel_id = msg->channel_id;
2182 	v4l2_dbg(1, debug, &dev->v4l2_dev,
2183 		 "user %d: channel has channel id %d\n",
2184 		 channel->user_id, channel->mcu_channel_id);
2185 
2186 	err = allegro_decode_config_blob(&param, msg, channel->config_blob.vaddr);
2187 	allegro_free_buffer(channel->dev, &channel->config_blob);
2188 	if (err)
2189 		goto out;
2190 
2191 	channel->num_ref_idx_l0 = param.num_ref_idx_l0;
2192 	channel->num_ref_idx_l1 = param.num_ref_idx_l1;
2193 
2194 	v4l2_dbg(1, debug, &dev->v4l2_dev,
2195 		 "channel %d: intermediate buffers: %d x %d bytes\n",
2196 		 channel->mcu_channel_id,
2197 		 msg->int_buffers_count, msg->int_buffers_size);
2198 	err = allocate_intermediate_buffers(channel, msg->int_buffers_count,
2199 					    msg->int_buffers_size);
2200 	if (err) {
2201 		v4l2_err(&dev->v4l2_dev,
2202 			 "channel %d: failed to allocate intermediate buffers\n",
2203 			 channel->mcu_channel_id);
2204 		goto out;
2205 	}
2206 	err = allegro_mcu_push_buffer_intermediate(channel);
2207 	if (err)
2208 		goto out;
2209 
2210 	v4l2_dbg(1, debug, &dev->v4l2_dev,
2211 		 "channel %d: reference buffers: %d x %d bytes\n",
2212 		 channel->mcu_channel_id,
2213 		 msg->rec_buffers_count, msg->rec_buffers_size);
2214 	err = allocate_reference_buffers(channel, msg->rec_buffers_count,
2215 					 msg->rec_buffers_size);
2216 	if (err) {
2217 		v4l2_err(&dev->v4l2_dev,
2218 			 "channel %d: failed to allocate reference buffers\n",
2219 			 channel->mcu_channel_id);
2220 		goto out;
2221 	}
2222 	err = allegro_mcu_push_buffer_reference(channel);
2223 	if (err)
2224 		goto out;
2225 
2226 out:
2227 	channel->error = err;
2228 	complete(&channel->completion);
2229 
2230 	/* Handled successfully, error is passed via channel->error */
2231 	return 0;
2232 }
2233 
2234 static int
2235 allegro_handle_destroy_channel(struct allegro_dev *dev,
2236 			       struct mcu_msg_destroy_channel_response *msg)
2237 {
2238 	struct allegro_channel *channel;
2239 
2240 	channel = allegro_find_channel_by_channel_id(dev, msg->channel_id);
2241 	if (IS_ERR(channel)) {
2242 		v4l2_err(&dev->v4l2_dev,
2243 			 "received %s for unknown channel %d\n",
2244 			 msg_type_name(msg->header.type),
2245 			 msg->channel_id);
2246 		return -EINVAL;
2247 	}
2248 
2249 	v4l2_dbg(2, debug, &dev->v4l2_dev,
2250 		 "user %d: vcu destroyed channel %d\n",
2251 		 channel->user_id, channel->mcu_channel_id);
2252 	complete(&channel->completion);
2253 
2254 	return 0;
2255 }
2256 
2257 static int
2258 allegro_handle_encode_frame(struct allegro_dev *dev,
2259 			    struct mcu_msg_encode_frame_response *msg)
2260 {
2261 	struct allegro_channel *channel;
2262 
2263 	channel = allegro_find_channel_by_channel_id(dev, msg->channel_id);
2264 	if (IS_ERR(channel)) {
2265 		v4l2_err(&dev->v4l2_dev,
2266 			 "received %s for unknown channel %d\n",
2267 			 msg_type_name(msg->header.type),
2268 			 msg->channel_id);
2269 		return -EINVAL;
2270 	}
2271 
2272 	allegro_channel_finish_frame(channel, msg);
2273 
2274 	return 0;
2275 }
2276 
2277 static void allegro_handle_message(struct allegro_dev *dev,
2278 				   union mcu_msg_response *msg)
2279 {
2280 	switch (msg->header.type) {
2281 	case MCU_MSG_TYPE_INIT:
2282 		allegro_handle_init(dev, &msg->init);
2283 		break;
2284 	case MCU_MSG_TYPE_CREATE_CHANNEL:
2285 		allegro_handle_create_channel(dev, &msg->create_channel);
2286 		break;
2287 	case MCU_MSG_TYPE_DESTROY_CHANNEL:
2288 		allegro_handle_destroy_channel(dev, &msg->destroy_channel);
2289 		break;
2290 	case MCU_MSG_TYPE_ENCODE_FRAME:
2291 		allegro_handle_encode_frame(dev, &msg->encode_frame);
2292 		break;
2293 	default:
2294 		v4l2_warn(&dev->v4l2_dev,
2295 			  "%s: unknown message %s\n",
2296 			  __func__, msg_type_name(msg->header.type));
2297 		break;
2298 	}
2299 }
2300 
2301 static irqreturn_t allegro_hardirq(int irq, void *data)
2302 {
2303 	struct allegro_dev *dev = data;
2304 	unsigned int status;
2305 
2306 	regmap_read(dev->regmap, AL5_ITC_CPU_IRQ_STA, &status);
2307 	if (!(status & AL5_ITC_CPU_IRQ_STA_TRIGGERED))
2308 		return IRQ_NONE;
2309 
2310 	regmap_write(dev->regmap, AL5_ITC_CPU_IRQ_CLR, status);
2311 
2312 	return IRQ_WAKE_THREAD;
2313 }
2314 
2315 static irqreturn_t allegro_irq_thread(int irq, void *data)
2316 {
2317 	struct allegro_dev *dev = data;
2318 
2319 	/*
2320 	 * The firmware is initialized after the mailbox is setup. We further
2321 	 * check the AL5_ITC_CPU_IRQ_STA register, if the firmware actually
2322 	 * triggered the interrupt. Although this should not happen, make sure
2323 	 * that we ignore interrupts, if the mailbox is not initialized.
2324 	 */
2325 	if (!dev->mbox_status)
2326 		return IRQ_NONE;
2327 
2328 	allegro_mbox_notify(dev->mbox_status);
2329 
2330 	return IRQ_HANDLED;
2331 }
2332 
2333 static void allegro_copy_firmware(struct allegro_dev *dev,
2334 				  const u8 * const buf, size_t size)
2335 {
2336 	int err = 0;
2337 
2338 	v4l2_dbg(1, debug, &dev->v4l2_dev,
2339 		 "copy mcu firmware (%zu B) to SRAM\n", size);
2340 	err = regmap_bulk_write(dev->sram, 0x0, buf, size / 4);
2341 	if (err)
2342 		v4l2_err(&dev->v4l2_dev,
2343 			 "failed to copy firmware: %d\n", err);
2344 }
2345 
2346 static void allegro_copy_fw_codec(struct allegro_dev *dev,
2347 				  const u8 * const buf, size_t size)
2348 {
2349 	int err;
2350 	dma_addr_t icache_offset, dcache_offset;
2351 
2352 	/*
2353 	 * The downstream allocates 600 KB for the codec firmware to have some
2354 	 * extra space for "possible extensions." My tests were fine with
2355 	 * allocating just enough memory for the actual firmware, but I am not
2356 	 * sure that the firmware really does not use the remaining space.
2357 	 */
2358 	err = allegro_alloc_buffer(dev, &dev->firmware, size);
2359 	if (err) {
2360 		v4l2_err(&dev->v4l2_dev,
2361 			 "failed to allocate %zu bytes for firmware\n", size);
2362 		return;
2363 	}
2364 
2365 	v4l2_dbg(1, debug, &dev->v4l2_dev,
2366 		 "copy codec firmware (%zd B) to phys %pad\n",
2367 		 size, &dev->firmware.paddr);
2368 	memcpy(dev->firmware.vaddr, buf, size);
2369 
2370 	regmap_write(dev->regmap, AXI_ADDR_OFFSET_IP,
2371 		     upper_32_bits(dev->firmware.paddr));
2372 
2373 	icache_offset = dev->firmware.paddr - MCU_CACHE_OFFSET;
2374 	v4l2_dbg(2, debug, &dev->v4l2_dev,
2375 		 "icache_offset: msb = 0x%x, lsb = 0x%x\n",
2376 		 upper_32_bits(icache_offset), lower_32_bits(icache_offset));
2377 	regmap_write(dev->regmap, AL5_ICACHE_ADDR_OFFSET_MSB,
2378 		     upper_32_bits(icache_offset));
2379 	regmap_write(dev->regmap, AL5_ICACHE_ADDR_OFFSET_LSB,
2380 		     lower_32_bits(icache_offset));
2381 
2382 	dcache_offset =
2383 	    (dev->firmware.paddr & 0xffffffff00000000ULL) - MCU_CACHE_OFFSET;
2384 	v4l2_dbg(2, debug, &dev->v4l2_dev,
2385 		 "dcache_offset: msb = 0x%x, lsb = 0x%x\n",
2386 		 upper_32_bits(dcache_offset), lower_32_bits(dcache_offset));
2387 	regmap_write(dev->regmap, AL5_DCACHE_ADDR_OFFSET_MSB,
2388 		     upper_32_bits(dcache_offset));
2389 	regmap_write(dev->regmap, AL5_DCACHE_ADDR_OFFSET_LSB,
2390 		     lower_32_bits(dcache_offset));
2391 }
2392 
2393 static void allegro_free_fw_codec(struct allegro_dev *dev)
2394 {
2395 	allegro_free_buffer(dev, &dev->firmware);
2396 }
2397 
2398 /*
2399  * Control functions for the MCU
2400  */
2401 
2402 static int allegro_mcu_enable_interrupts(struct allegro_dev *dev)
2403 {
2404 	return regmap_write(dev->regmap, AL5_ITC_CPU_IRQ_MSK, BIT(0));
2405 }
2406 
2407 static int allegro_mcu_disable_interrupts(struct allegro_dev *dev)
2408 {
2409 	return regmap_write(dev->regmap, AL5_ITC_CPU_IRQ_MSK, 0);
2410 }
2411 
2412 static int allegro_mcu_wait_for_sleep(struct allegro_dev *dev)
2413 {
2414 	unsigned long timeout;
2415 	unsigned int status;
2416 
2417 	timeout = jiffies + msecs_to_jiffies(100);
2418 	while (regmap_read(dev->regmap, AL5_MCU_STA, &status) == 0 &&
2419 	       status != AL5_MCU_STA_SLEEP) {
2420 		if (time_after(jiffies, timeout))
2421 			return -ETIMEDOUT;
2422 		cpu_relax();
2423 	}
2424 
2425 	return 0;
2426 }
2427 
2428 static int allegro_mcu_start(struct allegro_dev *dev)
2429 {
2430 	unsigned long timeout;
2431 	unsigned int status;
2432 	int err;
2433 
2434 	err = regmap_write(dev->regmap, AL5_MCU_WAKEUP, BIT(0));
2435 	if (err)
2436 		return err;
2437 
2438 	timeout = jiffies + msecs_to_jiffies(100);
2439 	while (regmap_read(dev->regmap, AL5_MCU_STA, &status) == 0 &&
2440 	       status == AL5_MCU_STA_SLEEP) {
2441 		if (time_after(jiffies, timeout))
2442 			return -ETIMEDOUT;
2443 		cpu_relax();
2444 	}
2445 
2446 	err = regmap_write(dev->regmap, AL5_MCU_WAKEUP, 0);
2447 	if (err)
2448 		return err;
2449 
2450 	return 0;
2451 }
2452 
2453 static int allegro_mcu_reset(struct allegro_dev *dev)
2454 {
2455 	int err;
2456 
2457 	/*
2458 	 * Ensure that the AL5_MCU_WAKEUP bit is set to 0 otherwise the mcu
2459 	 * does not go to sleep after the reset.
2460 	 */
2461 	err = regmap_write(dev->regmap, AL5_MCU_WAKEUP, 0);
2462 	if (err)
2463 		return err;
2464 
2465 	err = regmap_write(dev->regmap,
2466 			   AL5_MCU_RESET_MODE, AL5_MCU_RESET_MODE_SLEEP);
2467 	if (err < 0)
2468 		return err;
2469 
2470 	err = regmap_write(dev->regmap, AL5_MCU_RESET, AL5_MCU_RESET_SOFT);
2471 	if (err < 0)
2472 		return err;
2473 
2474 	return allegro_mcu_wait_for_sleep(dev);
2475 }
2476 
2477 static void allegro_mcu_interrupt(struct allegro_dev *dev)
2478 {
2479 	regmap_write(dev->regmap, AL5_MCU_INTERRUPT, BIT(0));
2480 }
2481 
2482 static void allegro_destroy_channel(struct allegro_channel *channel)
2483 {
2484 	struct allegro_dev *dev = channel->dev;
2485 	unsigned long timeout;
2486 
2487 	if (channel_exists(channel)) {
2488 		reinit_completion(&channel->completion);
2489 		allegro_mcu_send_destroy_channel(dev, channel);
2490 		timeout = wait_for_completion_timeout(&channel->completion,
2491 						      msecs_to_jiffies(5000));
2492 		if (timeout == 0)
2493 			v4l2_warn(&dev->v4l2_dev,
2494 				  "channel %d: timeout while destroying\n",
2495 				  channel->mcu_channel_id);
2496 
2497 		channel->mcu_channel_id = -1;
2498 	}
2499 
2500 	destroy_intermediate_buffers(channel);
2501 	destroy_reference_buffers(channel);
2502 
2503 	v4l2_ctrl_grab(channel->mpeg_video_h264_profile, false);
2504 	v4l2_ctrl_grab(channel->mpeg_video_h264_level, false);
2505 	v4l2_ctrl_grab(channel->mpeg_video_h264_i_frame_qp, false);
2506 	v4l2_ctrl_grab(channel->mpeg_video_h264_max_qp, false);
2507 	v4l2_ctrl_grab(channel->mpeg_video_h264_min_qp, false);
2508 	v4l2_ctrl_grab(channel->mpeg_video_h264_p_frame_qp, false);
2509 	v4l2_ctrl_grab(channel->mpeg_video_h264_b_frame_qp, false);
2510 
2511 	v4l2_ctrl_grab(channel->mpeg_video_hevc_profile, false);
2512 	v4l2_ctrl_grab(channel->mpeg_video_hevc_level, false);
2513 	v4l2_ctrl_grab(channel->mpeg_video_hevc_tier, false);
2514 	v4l2_ctrl_grab(channel->mpeg_video_hevc_i_frame_qp, false);
2515 	v4l2_ctrl_grab(channel->mpeg_video_hevc_max_qp, false);
2516 	v4l2_ctrl_grab(channel->mpeg_video_hevc_min_qp, false);
2517 	v4l2_ctrl_grab(channel->mpeg_video_hevc_p_frame_qp, false);
2518 	v4l2_ctrl_grab(channel->mpeg_video_hevc_b_frame_qp, false);
2519 
2520 	v4l2_ctrl_grab(channel->mpeg_video_frame_rc_enable, false);
2521 	v4l2_ctrl_grab(channel->mpeg_video_bitrate_mode, false);
2522 	v4l2_ctrl_grab(channel->mpeg_video_bitrate, false);
2523 	v4l2_ctrl_grab(channel->mpeg_video_bitrate_peak, false);
2524 	v4l2_ctrl_grab(channel->mpeg_video_cpb_size, false);
2525 	v4l2_ctrl_grab(channel->mpeg_video_gop_size, false);
2526 
2527 	v4l2_ctrl_grab(channel->encoder_buffer, false);
2528 
2529 	if (channel->user_id != -1) {
2530 		clear_bit(channel->user_id, &dev->channel_user_ids);
2531 		channel->user_id = -1;
2532 	}
2533 }
2534 
2535 /*
2536  * Create the MCU channel
2537  *
2538  * After the channel has been created, the picture size, format, colorspace
2539  * and framerate are fixed. Also the codec, profile, bitrate, etc. cannot be
2540  * changed anymore.
2541  *
2542  * The channel can be created only once. The MCU will accept source buffers
2543  * and stream buffers only after a channel has been created.
2544  */
2545 static int allegro_create_channel(struct allegro_channel *channel)
2546 {
2547 	struct allegro_dev *dev = channel->dev;
2548 	unsigned long timeout;
2549 
2550 	if (channel_exists(channel)) {
2551 		v4l2_warn(&dev->v4l2_dev,
2552 			  "channel already exists\n");
2553 		return 0;
2554 	}
2555 
2556 	channel->user_id = allegro_next_user_id(dev);
2557 	if (channel->user_id < 0) {
2558 		v4l2_err(&dev->v4l2_dev,
2559 			 "no free channels available\n");
2560 		return -EBUSY;
2561 	}
2562 	set_bit(channel->user_id, &dev->channel_user_ids);
2563 
2564 	v4l2_dbg(1, debug, &dev->v4l2_dev,
2565 		 "user %d: creating channel (%4.4s, %dx%d@%d)\n",
2566 		 channel->user_id,
2567 		 (char *)&channel->codec, channel->width, channel->height,
2568 		 DIV_ROUND_UP(channel->framerate.numerator,
2569 			      channel->framerate.denominator));
2570 
2571 	v4l2_ctrl_grab(channel->mpeg_video_h264_profile, true);
2572 	v4l2_ctrl_grab(channel->mpeg_video_h264_level, true);
2573 	v4l2_ctrl_grab(channel->mpeg_video_h264_i_frame_qp, true);
2574 	v4l2_ctrl_grab(channel->mpeg_video_h264_max_qp, true);
2575 	v4l2_ctrl_grab(channel->mpeg_video_h264_min_qp, true);
2576 	v4l2_ctrl_grab(channel->mpeg_video_h264_p_frame_qp, true);
2577 	v4l2_ctrl_grab(channel->mpeg_video_h264_b_frame_qp, true);
2578 
2579 	v4l2_ctrl_grab(channel->mpeg_video_hevc_profile, true);
2580 	v4l2_ctrl_grab(channel->mpeg_video_hevc_level, true);
2581 	v4l2_ctrl_grab(channel->mpeg_video_hevc_tier, true);
2582 	v4l2_ctrl_grab(channel->mpeg_video_hevc_i_frame_qp, true);
2583 	v4l2_ctrl_grab(channel->mpeg_video_hevc_max_qp, true);
2584 	v4l2_ctrl_grab(channel->mpeg_video_hevc_min_qp, true);
2585 	v4l2_ctrl_grab(channel->mpeg_video_hevc_p_frame_qp, true);
2586 	v4l2_ctrl_grab(channel->mpeg_video_hevc_b_frame_qp, true);
2587 
2588 	v4l2_ctrl_grab(channel->mpeg_video_frame_rc_enable, true);
2589 	v4l2_ctrl_grab(channel->mpeg_video_bitrate_mode, true);
2590 	v4l2_ctrl_grab(channel->mpeg_video_bitrate, true);
2591 	v4l2_ctrl_grab(channel->mpeg_video_bitrate_peak, true);
2592 	v4l2_ctrl_grab(channel->mpeg_video_cpb_size, true);
2593 	v4l2_ctrl_grab(channel->mpeg_video_gop_size, true);
2594 
2595 	v4l2_ctrl_grab(channel->encoder_buffer, true);
2596 
2597 	reinit_completion(&channel->completion);
2598 	allegro_mcu_send_create_channel(dev, channel);
2599 	timeout = wait_for_completion_timeout(&channel->completion,
2600 					      msecs_to_jiffies(5000));
2601 	if (timeout == 0)
2602 		channel->error = -ETIMEDOUT;
2603 	if (channel->error)
2604 		goto err;
2605 
2606 	v4l2_dbg(1, debug, &dev->v4l2_dev,
2607 		 "channel %d: accepting buffers\n",
2608 		 channel->mcu_channel_id);
2609 
2610 	return 0;
2611 
2612 err:
2613 	allegro_destroy_channel(channel);
2614 
2615 	return channel->error;
2616 }
2617 
2618 /**
2619  * allegro_channel_adjust() - Adjust channel parameters to current format
2620  * @channel: the channel to adjust
2621  *
2622  * Various parameters of a channel and their limits depend on the currently
2623  * set format. Adjust the parameters after a format change in one go.
2624  */
2625 static void allegro_channel_adjust(struct allegro_channel *channel)
2626 {
2627 	struct allegro_dev *dev = channel->dev;
2628 	u32 codec = channel->codec;
2629 	struct v4l2_ctrl *ctrl;
2630 	s64 min;
2631 	s64 max;
2632 
2633 	channel->sizeimage_encoded =
2634 		estimate_stream_size(channel->width, channel->height);
2635 
2636 	if (codec == V4L2_PIX_FMT_H264) {
2637 		ctrl = channel->mpeg_video_h264_level;
2638 		min = select_minimum_h264_level(channel->width, channel->height);
2639 	} else {
2640 		ctrl = channel->mpeg_video_hevc_level;
2641 		min = select_minimum_hevc_level(channel->width, channel->height);
2642 	}
2643 	if (ctrl->minimum > min)
2644 		v4l2_dbg(1, debug, &dev->v4l2_dev,
2645 			 "%s.minimum: %lld -> %lld\n",
2646 			 v4l2_ctrl_get_name(ctrl->id), ctrl->minimum, min);
2647 	v4l2_ctrl_lock(ctrl);
2648 	__v4l2_ctrl_modify_range(ctrl, min, ctrl->maximum,
2649 				 ctrl->step, ctrl->default_value);
2650 	v4l2_ctrl_unlock(ctrl);
2651 
2652 	ctrl = channel->mpeg_video_bitrate;
2653 	if (codec == V4L2_PIX_FMT_H264)
2654 		max = h264_maximum_bitrate(v4l2_ctrl_g_ctrl(channel->mpeg_video_h264_level));
2655 	else
2656 		max = hevc_maximum_bitrate(v4l2_ctrl_g_ctrl(channel->mpeg_video_hevc_level));
2657 	if (ctrl->maximum < max)
2658 		v4l2_dbg(1, debug, &dev->v4l2_dev,
2659 			 "%s: maximum: %lld -> %lld\n",
2660 			 v4l2_ctrl_get_name(ctrl->id), ctrl->maximum, max);
2661 	v4l2_ctrl_lock(ctrl);
2662 	__v4l2_ctrl_modify_range(ctrl, ctrl->minimum, max,
2663 				 ctrl->step, ctrl->default_value);
2664 	v4l2_ctrl_unlock(ctrl);
2665 
2666 	ctrl = channel->mpeg_video_bitrate_peak;
2667 	v4l2_ctrl_lock(ctrl);
2668 	__v4l2_ctrl_modify_range(ctrl, ctrl->minimum, max,
2669 				 ctrl->step, ctrl->default_value);
2670 	v4l2_ctrl_unlock(ctrl);
2671 
2672 	v4l2_ctrl_activate(channel->mpeg_video_h264_profile,
2673 			   codec == V4L2_PIX_FMT_H264);
2674 	v4l2_ctrl_activate(channel->mpeg_video_h264_level,
2675 			   codec == V4L2_PIX_FMT_H264);
2676 	v4l2_ctrl_activate(channel->mpeg_video_h264_i_frame_qp,
2677 			   codec == V4L2_PIX_FMT_H264);
2678 	v4l2_ctrl_activate(channel->mpeg_video_h264_max_qp,
2679 			   codec == V4L2_PIX_FMT_H264);
2680 	v4l2_ctrl_activate(channel->mpeg_video_h264_min_qp,
2681 			   codec == V4L2_PIX_FMT_H264);
2682 	v4l2_ctrl_activate(channel->mpeg_video_h264_p_frame_qp,
2683 			   codec == V4L2_PIX_FMT_H264);
2684 	v4l2_ctrl_activate(channel->mpeg_video_h264_b_frame_qp,
2685 			   codec == V4L2_PIX_FMT_H264);
2686 
2687 	v4l2_ctrl_activate(channel->mpeg_video_hevc_profile,
2688 			   codec == V4L2_PIX_FMT_HEVC);
2689 	v4l2_ctrl_activate(channel->mpeg_video_hevc_level,
2690 			   codec == V4L2_PIX_FMT_HEVC);
2691 	v4l2_ctrl_activate(channel->mpeg_video_hevc_tier,
2692 			   codec == V4L2_PIX_FMT_HEVC);
2693 	v4l2_ctrl_activate(channel->mpeg_video_hevc_i_frame_qp,
2694 			   codec == V4L2_PIX_FMT_HEVC);
2695 	v4l2_ctrl_activate(channel->mpeg_video_hevc_max_qp,
2696 			   codec == V4L2_PIX_FMT_HEVC);
2697 	v4l2_ctrl_activate(channel->mpeg_video_hevc_min_qp,
2698 			   codec == V4L2_PIX_FMT_HEVC);
2699 	v4l2_ctrl_activate(channel->mpeg_video_hevc_p_frame_qp,
2700 			   codec == V4L2_PIX_FMT_HEVC);
2701 	v4l2_ctrl_activate(channel->mpeg_video_hevc_b_frame_qp,
2702 			   codec == V4L2_PIX_FMT_HEVC);
2703 
2704 	if (codec == V4L2_PIX_FMT_H264)
2705 		channel->log2_max_frame_num = LOG2_MAX_FRAME_NUM;
2706 	channel->temporal_mvp_enable = true;
2707 	channel->dbf_ovr_en = (codec == V4L2_PIX_FMT_H264);
2708 	channel->enable_deblocking_filter_override = (codec == V4L2_PIX_FMT_HEVC);
2709 	channel->enable_reordering = (codec == V4L2_PIX_FMT_HEVC);
2710 	channel->enable_loop_filter_across_tiles = true;
2711 	channel->enable_loop_filter_across_slices = true;
2712 
2713 	if (codec == V4L2_PIX_FMT_H264) {
2714 		channel->b_hrz_me_range = 8;
2715 		channel->b_vrt_me_range = 8;
2716 		channel->p_hrz_me_range = 16;
2717 		channel->p_vrt_me_range = 16;
2718 		channel->max_cu_size = ilog2(16);
2719 		channel->min_cu_size = ilog2(8);
2720 		channel->max_tu_size = ilog2(4);
2721 		channel->min_tu_size = ilog2(4);
2722 	} else {
2723 		channel->b_hrz_me_range = 16;
2724 		channel->b_vrt_me_range = 16;
2725 		channel->p_hrz_me_range = 32;
2726 		channel->p_vrt_me_range = 32;
2727 		channel->max_cu_size = ilog2(32);
2728 		channel->min_cu_size = ilog2(8);
2729 		channel->max_tu_size = ilog2(32);
2730 		channel->min_tu_size = ilog2(4);
2731 	}
2732 	channel->max_transfo_depth_intra = 1;
2733 	channel->max_transfo_depth_inter = 1;
2734 }
2735 
2736 static void allegro_set_default_params(struct allegro_channel *channel)
2737 {
2738 	channel->width = ALLEGRO_WIDTH_DEFAULT;
2739 	channel->height = ALLEGRO_HEIGHT_DEFAULT;
2740 	channel->stride = round_up(channel->width, 32);
2741 	channel->framerate = ALLEGRO_FRAMERATE_DEFAULT;
2742 
2743 	channel->colorspace = V4L2_COLORSPACE_REC709;
2744 	channel->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
2745 	channel->quantization = V4L2_QUANTIZATION_DEFAULT;
2746 	channel->xfer_func = V4L2_XFER_FUNC_DEFAULT;
2747 
2748 	channel->pixelformat = V4L2_PIX_FMT_NV12;
2749 	channel->sizeimage_raw = channel->stride * channel->height * 3 / 2;
2750 
2751 	channel->codec = V4L2_PIX_FMT_H264;
2752 }
2753 
2754 static int allegro_queue_setup(struct vb2_queue *vq,
2755 			       unsigned int *nbuffers, unsigned int *nplanes,
2756 			       unsigned int sizes[],
2757 			       struct device *alloc_devs[])
2758 {
2759 	struct allegro_channel *channel = vb2_get_drv_priv(vq);
2760 	struct allegro_dev *dev = channel->dev;
2761 
2762 	v4l2_dbg(2, debug, &dev->v4l2_dev,
2763 		 "%s: queue setup[%s]: nplanes = %d\n",
2764 		 V4L2_TYPE_IS_OUTPUT(vq->type) ? "output" : "capture",
2765 		 *nplanes == 0 ? "REQBUFS" : "CREATE_BUFS", *nplanes);
2766 
2767 	if (*nplanes != 0) {
2768 		if (V4L2_TYPE_IS_OUTPUT(vq->type)) {
2769 			if (sizes[0] < channel->sizeimage_raw)
2770 				return -EINVAL;
2771 		} else {
2772 			if (sizes[0] < channel->sizeimage_encoded)
2773 				return -EINVAL;
2774 		}
2775 	} else {
2776 		*nplanes = 1;
2777 		if (V4L2_TYPE_IS_OUTPUT(vq->type))
2778 			sizes[0] = channel->sizeimage_raw;
2779 		else
2780 			sizes[0] = channel->sizeimage_encoded;
2781 	}
2782 
2783 	return 0;
2784 }
2785 
2786 static int allegro_buf_prepare(struct vb2_buffer *vb)
2787 {
2788 	struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
2789 	struct allegro_channel *channel = vb2_get_drv_priv(vb->vb2_queue);
2790 	struct allegro_dev *dev = channel->dev;
2791 
2792 	if (V4L2_TYPE_IS_OUTPUT(vb->vb2_queue->type)) {
2793 		if (vbuf->field == V4L2_FIELD_ANY)
2794 			vbuf->field = V4L2_FIELD_NONE;
2795 		if (vbuf->field != V4L2_FIELD_NONE) {
2796 			v4l2_err(&dev->v4l2_dev,
2797 				 "channel %d: unsupported field\n",
2798 				 channel->mcu_channel_id);
2799 			return -EINVAL;
2800 		}
2801 	}
2802 
2803 	return 0;
2804 }
2805 
2806 static void allegro_buf_queue(struct vb2_buffer *vb)
2807 {
2808 	struct allegro_channel *channel = vb2_get_drv_priv(vb->vb2_queue);
2809 	struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
2810 	struct vb2_queue *q = vb->vb2_queue;
2811 
2812 	if (V4L2_TYPE_IS_CAPTURE(q->type) &&
2813 	    vb2_is_streaming(q) &&
2814 	    v4l2_m2m_dst_buf_is_last(channel->fh.m2m_ctx)) {
2815 		unsigned int i;
2816 
2817 		for (i = 0; i < vb->num_planes; i++)
2818 			vb2_set_plane_payload(vb, i, 0);
2819 
2820 		vbuf->field = V4L2_FIELD_NONE;
2821 		vbuf->sequence = channel->csequence++;
2822 
2823 		v4l2_m2m_last_buffer_done(channel->fh.m2m_ctx, vbuf);
2824 		allegro_channel_eos_event(channel);
2825 		return;
2826 	}
2827 
2828 	v4l2_m2m_buf_queue(channel->fh.m2m_ctx, vbuf);
2829 }
2830 
2831 static int allegro_start_streaming(struct vb2_queue *q, unsigned int count)
2832 {
2833 	struct allegro_channel *channel = vb2_get_drv_priv(q);
2834 	struct allegro_dev *dev = channel->dev;
2835 
2836 	v4l2_dbg(2, debug, &dev->v4l2_dev,
2837 		 "%s: start streaming\n",
2838 		 V4L2_TYPE_IS_OUTPUT(q->type) ? "output" : "capture");
2839 
2840 	v4l2_m2m_update_start_streaming_state(channel->fh.m2m_ctx, q);
2841 
2842 	if (V4L2_TYPE_IS_OUTPUT(q->type))
2843 		channel->osequence = 0;
2844 	else
2845 		channel->csequence = 0;
2846 
2847 	return 0;
2848 }
2849 
2850 static void allegro_stop_streaming(struct vb2_queue *q)
2851 {
2852 	struct allegro_channel *channel = vb2_get_drv_priv(q);
2853 	struct allegro_dev *dev = channel->dev;
2854 	struct vb2_v4l2_buffer *buffer;
2855 	struct allegro_m2m_buffer *shadow, *tmp;
2856 
2857 	v4l2_dbg(2, debug, &dev->v4l2_dev,
2858 		 "%s: stop streaming\n",
2859 		 V4L2_TYPE_IS_OUTPUT(q->type) ? "output" : "capture");
2860 
2861 	if (V4L2_TYPE_IS_OUTPUT(q->type)) {
2862 		mutex_lock(&channel->shadow_list_lock);
2863 		list_for_each_entry_safe(shadow, tmp,
2864 					 &channel->source_shadow_list, head) {
2865 			list_del(&shadow->head);
2866 			v4l2_m2m_buf_done(&shadow->buf.vb, VB2_BUF_STATE_ERROR);
2867 		}
2868 		mutex_unlock(&channel->shadow_list_lock);
2869 
2870 		while ((buffer = v4l2_m2m_src_buf_remove(channel->fh.m2m_ctx)))
2871 			v4l2_m2m_buf_done(buffer, VB2_BUF_STATE_ERROR);
2872 	} else {
2873 		mutex_lock(&channel->shadow_list_lock);
2874 		list_for_each_entry_safe(shadow, tmp,
2875 					 &channel->stream_shadow_list, head) {
2876 			list_del(&shadow->head);
2877 			v4l2_m2m_buf_done(&shadow->buf.vb, VB2_BUF_STATE_ERROR);
2878 		}
2879 		mutex_unlock(&channel->shadow_list_lock);
2880 
2881 		allegro_destroy_channel(channel);
2882 		while ((buffer = v4l2_m2m_dst_buf_remove(channel->fh.m2m_ctx)))
2883 			v4l2_m2m_buf_done(buffer, VB2_BUF_STATE_ERROR);
2884 	}
2885 
2886 	v4l2_m2m_update_stop_streaming_state(channel->fh.m2m_ctx, q);
2887 
2888 	if (V4L2_TYPE_IS_OUTPUT(q->type) &&
2889 	    v4l2_m2m_has_stopped(channel->fh.m2m_ctx))
2890 		allegro_channel_eos_event(channel);
2891 }
2892 
2893 static const struct vb2_ops allegro_queue_ops = {
2894 	.queue_setup = allegro_queue_setup,
2895 	.buf_prepare = allegro_buf_prepare,
2896 	.buf_queue = allegro_buf_queue,
2897 	.start_streaming = allegro_start_streaming,
2898 	.stop_streaming = allegro_stop_streaming,
2899 	.wait_prepare = vb2_ops_wait_prepare,
2900 	.wait_finish = vb2_ops_wait_finish,
2901 };
2902 
2903 static int allegro_queue_init(void *priv,
2904 			      struct vb2_queue *src_vq,
2905 			      struct vb2_queue *dst_vq)
2906 {
2907 	int err;
2908 	struct allegro_channel *channel = priv;
2909 
2910 	src_vq->dev = &channel->dev->plat_dev->dev;
2911 	src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
2912 	src_vq->io_modes = VB2_DMABUF | VB2_MMAP;
2913 	src_vq->mem_ops = &vb2_dma_contig_memops;
2914 	src_vq->drv_priv = channel;
2915 	src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
2916 	src_vq->ops = &allegro_queue_ops;
2917 	src_vq->buf_struct_size = sizeof(struct allegro_m2m_buffer);
2918 	src_vq->lock = &channel->dev->lock;
2919 	err = vb2_queue_init(src_vq);
2920 	if (err)
2921 		return err;
2922 
2923 	dst_vq->dev = &channel->dev->plat_dev->dev;
2924 	dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
2925 	dst_vq->io_modes = VB2_DMABUF | VB2_MMAP;
2926 	dst_vq->mem_ops = &vb2_dma_contig_memops;
2927 	dst_vq->drv_priv = channel;
2928 	dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
2929 	dst_vq->ops = &allegro_queue_ops;
2930 	dst_vq->buf_struct_size = sizeof(struct allegro_m2m_buffer);
2931 	dst_vq->lock = &channel->dev->lock;
2932 	err = vb2_queue_init(dst_vq);
2933 	if (err)
2934 		return err;
2935 
2936 	return 0;
2937 }
2938 
2939 static int allegro_clamp_qp(struct allegro_channel *channel,
2940 			    struct v4l2_ctrl *ctrl)
2941 {
2942 	struct v4l2_ctrl *next_ctrl;
2943 
2944 	if (ctrl->id == V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP)
2945 		next_ctrl = channel->mpeg_video_h264_p_frame_qp;
2946 	else if (ctrl->id == V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP)
2947 		next_ctrl = channel->mpeg_video_h264_b_frame_qp;
2948 	else
2949 		return 0;
2950 
2951 	/* Modify range automatically updates the value */
2952 	__v4l2_ctrl_modify_range(next_ctrl, ctrl->val, 51, 1, ctrl->val);
2953 
2954 	return allegro_clamp_qp(channel, next_ctrl);
2955 }
2956 
2957 static int allegro_clamp_bitrate(struct allegro_channel *channel,
2958 				 struct v4l2_ctrl *ctrl)
2959 {
2960 	struct v4l2_ctrl *ctrl_bitrate = channel->mpeg_video_bitrate;
2961 	struct v4l2_ctrl *ctrl_bitrate_peak = channel->mpeg_video_bitrate_peak;
2962 
2963 	if (ctrl->val == V4L2_MPEG_VIDEO_BITRATE_MODE_VBR &&
2964 	    ctrl_bitrate_peak->val < ctrl_bitrate->val)
2965 		ctrl_bitrate_peak->val = ctrl_bitrate->val;
2966 
2967 	return 0;
2968 }
2969 
2970 static int allegro_try_ctrl(struct v4l2_ctrl *ctrl)
2971 {
2972 	struct allegro_channel *channel = container_of(ctrl->handler,
2973 						       struct allegro_channel,
2974 						       ctrl_handler);
2975 
2976 	switch (ctrl->id) {
2977 	case V4L2_CID_MPEG_VIDEO_BITRATE_MODE:
2978 		allegro_clamp_bitrate(channel, ctrl);
2979 		break;
2980 	case V4L2_CID_USER_ALLEGRO_ENCODER_BUFFER:
2981 		if (!channel->dev->has_encoder_buffer)
2982 			ctrl->val = 0;
2983 		break;
2984 	}
2985 
2986 	return 0;
2987 }
2988 
2989 static int allegro_s_ctrl(struct v4l2_ctrl *ctrl)
2990 {
2991 	struct allegro_channel *channel = container_of(ctrl->handler,
2992 						       struct allegro_channel,
2993 						       ctrl_handler);
2994 	struct allegro_dev *dev = channel->dev;
2995 
2996 	v4l2_dbg(1, debug, &dev->v4l2_dev,
2997 		 "s_ctrl: %s = %d\n", v4l2_ctrl_get_name(ctrl->id), ctrl->val);
2998 
2999 	switch (ctrl->id) {
3000 	case V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE:
3001 		channel->frame_rc_enable = ctrl->val;
3002 		break;
3003 	case V4L2_CID_MPEG_VIDEO_BITRATE_MODE:
3004 		channel->bitrate = channel->mpeg_video_bitrate->val;
3005 		channel->bitrate_peak = channel->mpeg_video_bitrate_peak->val;
3006 		v4l2_ctrl_activate(channel->mpeg_video_bitrate_peak,
3007 				   ctrl->val == V4L2_MPEG_VIDEO_BITRATE_MODE_VBR);
3008 		break;
3009 	case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP:
3010 	case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP:
3011 	case V4L2_CID_MPEG_VIDEO_H264_B_FRAME_QP:
3012 		allegro_clamp_qp(channel, ctrl);
3013 		break;
3014 	}
3015 
3016 	return 0;
3017 }
3018 
3019 static const struct v4l2_ctrl_ops allegro_ctrl_ops = {
3020 	.try_ctrl = allegro_try_ctrl,
3021 	.s_ctrl = allegro_s_ctrl,
3022 };
3023 
3024 static const struct v4l2_ctrl_config allegro_encoder_buffer_ctrl_config = {
3025 	.id = V4L2_CID_USER_ALLEGRO_ENCODER_BUFFER,
3026 	.name = "Encoder Buffer Enable",
3027 	.type = V4L2_CTRL_TYPE_BOOLEAN,
3028 	.min = 0,
3029 	.max = 1,
3030 	.step = 1,
3031 	.def = 1,
3032 };
3033 
3034 static int allegro_open(struct file *file)
3035 {
3036 	struct video_device *vdev = video_devdata(file);
3037 	struct allegro_dev *dev = video_get_drvdata(vdev);
3038 	struct allegro_channel *channel = NULL;
3039 	struct v4l2_ctrl_handler *handler;
3040 	u64 mask;
3041 	int ret;
3042 	unsigned int bitrate_max;
3043 	unsigned int bitrate_def;
3044 	unsigned int cpb_size_max;
3045 	unsigned int cpb_size_def;
3046 
3047 	channel = kzalloc(sizeof(*channel), GFP_KERNEL);
3048 	if (!channel)
3049 		return -ENOMEM;
3050 
3051 	v4l2_fh_init(&channel->fh, vdev);
3052 
3053 	init_completion(&channel->completion);
3054 	INIT_LIST_HEAD(&channel->source_shadow_list);
3055 	INIT_LIST_HEAD(&channel->stream_shadow_list);
3056 	mutex_init(&channel->shadow_list_lock);
3057 
3058 	channel->dev = dev;
3059 
3060 	allegro_set_default_params(channel);
3061 
3062 	handler = &channel->ctrl_handler;
3063 	v4l2_ctrl_handler_init(handler, 0);
3064 	channel->mpeg_video_h264_profile = v4l2_ctrl_new_std_menu(handler,
3065 			&allegro_ctrl_ops,
3066 			V4L2_CID_MPEG_VIDEO_H264_PROFILE,
3067 			V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE, 0x0,
3068 			V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE);
3069 	mask = 1 << V4L2_MPEG_VIDEO_H264_LEVEL_1B;
3070 	channel->mpeg_video_h264_level = v4l2_ctrl_new_std_menu(handler,
3071 			&allegro_ctrl_ops,
3072 			V4L2_CID_MPEG_VIDEO_H264_LEVEL,
3073 			V4L2_MPEG_VIDEO_H264_LEVEL_5_1, mask,
3074 			V4L2_MPEG_VIDEO_H264_LEVEL_5_1);
3075 	channel->mpeg_video_h264_i_frame_qp =
3076 		v4l2_ctrl_new_std(handler,
3077 				  &allegro_ctrl_ops,
3078 				  V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP,
3079 				  0, 51, 1, 30);
3080 	channel->mpeg_video_h264_max_qp =
3081 		v4l2_ctrl_new_std(handler,
3082 				  &allegro_ctrl_ops,
3083 				  V4L2_CID_MPEG_VIDEO_H264_MAX_QP,
3084 				  0, 51, 1, 51);
3085 	channel->mpeg_video_h264_min_qp =
3086 		v4l2_ctrl_new_std(handler,
3087 				  &allegro_ctrl_ops,
3088 				  V4L2_CID_MPEG_VIDEO_H264_MIN_QP,
3089 				  0, 51, 1, 0);
3090 	channel->mpeg_video_h264_p_frame_qp =
3091 		v4l2_ctrl_new_std(handler,
3092 				  &allegro_ctrl_ops,
3093 				  V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP,
3094 				  0, 51, 1, 30);
3095 	channel->mpeg_video_h264_b_frame_qp =
3096 		v4l2_ctrl_new_std(handler,
3097 				  &allegro_ctrl_ops,
3098 				  V4L2_CID_MPEG_VIDEO_H264_B_FRAME_QP,
3099 				  0, 51, 1, 30);
3100 
3101 	channel->mpeg_video_hevc_profile =
3102 		v4l2_ctrl_new_std_menu(handler,
3103 				       &allegro_ctrl_ops,
3104 				       V4L2_CID_MPEG_VIDEO_HEVC_PROFILE,
3105 				       V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, 0x0,
3106 				       V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN);
3107 	channel->mpeg_video_hevc_level =
3108 		v4l2_ctrl_new_std_menu(handler,
3109 				       &allegro_ctrl_ops,
3110 				       V4L2_CID_MPEG_VIDEO_HEVC_LEVEL,
3111 				       V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1, 0x0,
3112 				       V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1);
3113 	channel->mpeg_video_hevc_tier =
3114 		v4l2_ctrl_new_std_menu(handler,
3115 				       &allegro_ctrl_ops,
3116 				       V4L2_CID_MPEG_VIDEO_HEVC_TIER,
3117 				       V4L2_MPEG_VIDEO_HEVC_TIER_HIGH, 0x0,
3118 				       V4L2_MPEG_VIDEO_HEVC_TIER_MAIN);
3119 	channel->mpeg_video_hevc_i_frame_qp =
3120 		v4l2_ctrl_new_std(handler,
3121 				  &allegro_ctrl_ops,
3122 				  V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP,
3123 				  0, 51, 1, 30);
3124 	channel->mpeg_video_hevc_max_qp =
3125 		v4l2_ctrl_new_std(handler,
3126 				  &allegro_ctrl_ops,
3127 				  V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP,
3128 				  0, 51, 1, 51);
3129 	channel->mpeg_video_hevc_min_qp =
3130 		v4l2_ctrl_new_std(handler,
3131 				  &allegro_ctrl_ops,
3132 				  V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP,
3133 				  0, 51, 1, 0);
3134 	channel->mpeg_video_hevc_p_frame_qp =
3135 		v4l2_ctrl_new_std(handler,
3136 				  &allegro_ctrl_ops,
3137 				  V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_QP,
3138 				  0, 51, 1, 30);
3139 	channel->mpeg_video_hevc_b_frame_qp =
3140 		v4l2_ctrl_new_std(handler,
3141 				  &allegro_ctrl_ops,
3142 				  V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_QP,
3143 				  0, 51, 1, 30);
3144 
3145 	channel->mpeg_video_frame_rc_enable =
3146 		v4l2_ctrl_new_std(handler,
3147 				  &allegro_ctrl_ops,
3148 				  V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE,
3149 				  false, 0x1,
3150 				  true, false);
3151 	channel->mpeg_video_bitrate_mode = v4l2_ctrl_new_std_menu(handler,
3152 			&allegro_ctrl_ops,
3153 			V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
3154 			V4L2_MPEG_VIDEO_BITRATE_MODE_CBR, 0,
3155 			V4L2_MPEG_VIDEO_BITRATE_MODE_CBR);
3156 
3157 	if (channel->codec == V4L2_PIX_FMT_H264) {
3158 		bitrate_max = h264_maximum_bitrate(V4L2_MPEG_VIDEO_H264_LEVEL_5_1);
3159 		bitrate_def = h264_maximum_bitrate(V4L2_MPEG_VIDEO_H264_LEVEL_5_1);
3160 		cpb_size_max = h264_maximum_cpb_size(V4L2_MPEG_VIDEO_H264_LEVEL_5_1);
3161 		cpb_size_def = h264_maximum_cpb_size(V4L2_MPEG_VIDEO_H264_LEVEL_5_1);
3162 	} else {
3163 		bitrate_max = hevc_maximum_bitrate(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1);
3164 		bitrate_def = hevc_maximum_bitrate(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1);
3165 		cpb_size_max = hevc_maximum_cpb_size(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1);
3166 		cpb_size_def = hevc_maximum_cpb_size(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1);
3167 	}
3168 	channel->mpeg_video_bitrate = v4l2_ctrl_new_std(handler,
3169 			&allegro_ctrl_ops,
3170 			V4L2_CID_MPEG_VIDEO_BITRATE,
3171 			0, bitrate_max, 1, bitrate_def);
3172 	channel->mpeg_video_bitrate_peak = v4l2_ctrl_new_std(handler,
3173 			&allegro_ctrl_ops,
3174 			V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
3175 			0, bitrate_max, 1, bitrate_def);
3176 	channel->mpeg_video_cpb_size = v4l2_ctrl_new_std(handler,
3177 			&allegro_ctrl_ops,
3178 			V4L2_CID_MPEG_VIDEO_H264_CPB_SIZE,
3179 			0, cpb_size_max, 1, cpb_size_def);
3180 	channel->mpeg_video_gop_size = v4l2_ctrl_new_std(handler,
3181 			&allegro_ctrl_ops,
3182 			V4L2_CID_MPEG_VIDEO_GOP_SIZE,
3183 			0, ALLEGRO_GOP_SIZE_MAX,
3184 			1, ALLEGRO_GOP_SIZE_DEFAULT);
3185 	channel->encoder_buffer = v4l2_ctrl_new_custom(handler,
3186 			&allegro_encoder_buffer_ctrl_config, NULL);
3187 	v4l2_ctrl_new_std(handler,
3188 			  &allegro_ctrl_ops,
3189 			  V4L2_CID_MIN_BUFFERS_FOR_OUTPUT,
3190 			  1, 32,
3191 			  1, 1);
3192 	if (handler->error != 0) {
3193 		ret = handler->error;
3194 		goto error;
3195 	}
3196 
3197 	channel->fh.ctrl_handler = handler;
3198 
3199 	v4l2_ctrl_cluster(3, &channel->mpeg_video_bitrate_mode);
3200 
3201 	v4l2_ctrl_handler_setup(handler);
3202 
3203 	channel->mcu_channel_id = -1;
3204 	channel->user_id = -1;
3205 
3206 	INIT_LIST_HEAD(&channel->buffers_reference);
3207 	INIT_LIST_HEAD(&channel->buffers_intermediate);
3208 
3209 	channel->fh.m2m_ctx = v4l2_m2m_ctx_init(dev->m2m_dev, channel,
3210 						allegro_queue_init);
3211 
3212 	if (IS_ERR(channel->fh.m2m_ctx)) {
3213 		ret = PTR_ERR(channel->fh.m2m_ctx);
3214 		goto error;
3215 	}
3216 
3217 	list_add(&channel->list, &dev->channels);
3218 	file->private_data = &channel->fh;
3219 	v4l2_fh_add(&channel->fh);
3220 
3221 	allegro_channel_adjust(channel);
3222 
3223 	return 0;
3224 
3225 error:
3226 	v4l2_ctrl_handler_free(handler);
3227 	kfree(channel);
3228 	return ret;
3229 }
3230 
3231 static int allegro_release(struct file *file)
3232 {
3233 	struct allegro_channel *channel = fh_to_channel(file->private_data);
3234 
3235 	v4l2_m2m_ctx_release(channel->fh.m2m_ctx);
3236 
3237 	list_del(&channel->list);
3238 
3239 	v4l2_ctrl_handler_free(&channel->ctrl_handler);
3240 
3241 	v4l2_fh_del(&channel->fh);
3242 	v4l2_fh_exit(&channel->fh);
3243 
3244 	kfree(channel);
3245 
3246 	return 0;
3247 }
3248 
3249 static int allegro_querycap(struct file *file, void *fh,
3250 			    struct v4l2_capability *cap)
3251 {
3252 	strscpy(cap->driver, KBUILD_MODNAME, sizeof(cap->driver));
3253 	strscpy(cap->card, "Allegro DVT Video Encoder", sizeof(cap->card));
3254 
3255 	return 0;
3256 }
3257 
3258 static int allegro_enum_fmt_vid(struct file *file, void *fh,
3259 				struct v4l2_fmtdesc *f)
3260 {
3261 	switch (f->type) {
3262 	case V4L2_BUF_TYPE_VIDEO_OUTPUT:
3263 		if (f->index >= 1)
3264 			return -EINVAL;
3265 		f->pixelformat = V4L2_PIX_FMT_NV12;
3266 		break;
3267 	case V4L2_BUF_TYPE_VIDEO_CAPTURE:
3268 		if (f->index >= 2)
3269 			return -EINVAL;
3270 		if (f->index == 0)
3271 			f->pixelformat = V4L2_PIX_FMT_H264;
3272 		if (f->index == 1)
3273 			f->pixelformat = V4L2_PIX_FMT_HEVC;
3274 		break;
3275 	default:
3276 		return -EINVAL;
3277 	}
3278 	return 0;
3279 }
3280 
3281 static int allegro_g_fmt_vid_cap(struct file *file, void *fh,
3282 				 struct v4l2_format *f)
3283 {
3284 	struct allegro_channel *channel = fh_to_channel(fh);
3285 
3286 	f->fmt.pix.field = V4L2_FIELD_NONE;
3287 	f->fmt.pix.width = channel->width;
3288 	f->fmt.pix.height = channel->height;
3289 
3290 	f->fmt.pix.colorspace = channel->colorspace;
3291 	f->fmt.pix.ycbcr_enc = channel->ycbcr_enc;
3292 	f->fmt.pix.quantization = channel->quantization;
3293 	f->fmt.pix.xfer_func = channel->xfer_func;
3294 
3295 	f->fmt.pix.pixelformat = channel->codec;
3296 	f->fmt.pix.bytesperline = 0;
3297 	f->fmt.pix.sizeimage = channel->sizeimage_encoded;
3298 
3299 	return 0;
3300 }
3301 
3302 static int allegro_try_fmt_vid_cap(struct file *file, void *fh,
3303 				   struct v4l2_format *f)
3304 {
3305 	f->fmt.pix.field = V4L2_FIELD_NONE;
3306 
3307 	f->fmt.pix.width = clamp_t(__u32, f->fmt.pix.width,
3308 				   ALLEGRO_WIDTH_MIN, ALLEGRO_WIDTH_MAX);
3309 	f->fmt.pix.height = clamp_t(__u32, f->fmt.pix.height,
3310 				    ALLEGRO_HEIGHT_MIN, ALLEGRO_HEIGHT_MAX);
3311 
3312 	if (f->fmt.pix.pixelformat != V4L2_PIX_FMT_HEVC &&
3313 	    f->fmt.pix.pixelformat != V4L2_PIX_FMT_H264)
3314 		f->fmt.pix.pixelformat = V4L2_PIX_FMT_H264;
3315 
3316 	f->fmt.pix.bytesperline = 0;
3317 	f->fmt.pix.sizeimage =
3318 		estimate_stream_size(f->fmt.pix.width, f->fmt.pix.height);
3319 
3320 	return 0;
3321 }
3322 
3323 static int allegro_s_fmt_vid_cap(struct file *file, void *fh,
3324 				 struct v4l2_format *f)
3325 {
3326 	struct allegro_channel *channel = fh_to_channel(fh);
3327 	struct vb2_queue *vq;
3328 	int err;
3329 
3330 	err = allegro_try_fmt_vid_cap(file, fh, f);
3331 	if (err)
3332 		return err;
3333 
3334 	vq = v4l2_m2m_get_vq(channel->fh.m2m_ctx, f->type);
3335 	if (!vq)
3336 		return -EINVAL;
3337 	if (vb2_is_busy(vq))
3338 		return -EBUSY;
3339 
3340 	channel->codec = f->fmt.pix.pixelformat;
3341 
3342 	allegro_channel_adjust(channel);
3343 
3344 	return 0;
3345 }
3346 
3347 static int allegro_g_fmt_vid_out(struct file *file, void *fh,
3348 				 struct v4l2_format *f)
3349 {
3350 	struct allegro_channel *channel = fh_to_channel(fh);
3351 
3352 	f->fmt.pix.field = V4L2_FIELD_NONE;
3353 
3354 	f->fmt.pix.width = channel->width;
3355 	f->fmt.pix.height = channel->height;
3356 
3357 	f->fmt.pix.colorspace = channel->colorspace;
3358 	f->fmt.pix.ycbcr_enc = channel->ycbcr_enc;
3359 	f->fmt.pix.quantization = channel->quantization;
3360 	f->fmt.pix.xfer_func = channel->xfer_func;
3361 
3362 	f->fmt.pix.pixelformat = channel->pixelformat;
3363 	f->fmt.pix.bytesperline = channel->stride;
3364 	f->fmt.pix.sizeimage = channel->sizeimage_raw;
3365 
3366 	return 0;
3367 }
3368 
3369 static int allegro_try_fmt_vid_out(struct file *file, void *fh,
3370 				   struct v4l2_format *f)
3371 {
3372 	f->fmt.pix.field = V4L2_FIELD_NONE;
3373 
3374 	/*
3375 	 * The firmware of the Allegro codec handles the padding internally
3376 	 * and expects the visual frame size when configuring a channel.
3377 	 * Therefore, unlike other encoder drivers, this driver does not round
3378 	 * up the width and height to macroblock alignment and does not
3379 	 * implement the selection api.
3380 	 */
3381 	f->fmt.pix.width = clamp_t(__u32, f->fmt.pix.width,
3382 				   ALLEGRO_WIDTH_MIN, ALLEGRO_WIDTH_MAX);
3383 	f->fmt.pix.height = clamp_t(__u32, f->fmt.pix.height,
3384 				    ALLEGRO_HEIGHT_MIN, ALLEGRO_HEIGHT_MAX);
3385 
3386 	f->fmt.pix.pixelformat = V4L2_PIX_FMT_NV12;
3387 	f->fmt.pix.bytesperline = round_up(f->fmt.pix.width, 32);
3388 	f->fmt.pix.sizeimage =
3389 		f->fmt.pix.bytesperline * f->fmt.pix.height * 3 / 2;
3390 
3391 	return 0;
3392 }
3393 
3394 static int allegro_s_fmt_vid_out(struct file *file, void *fh,
3395 				 struct v4l2_format *f)
3396 {
3397 	struct allegro_channel *channel = fh_to_channel(fh);
3398 	int err;
3399 
3400 	err = allegro_try_fmt_vid_out(file, fh, f);
3401 	if (err)
3402 		return err;
3403 
3404 	channel->width = f->fmt.pix.width;
3405 	channel->height = f->fmt.pix.height;
3406 	channel->stride = f->fmt.pix.bytesperline;
3407 	channel->sizeimage_raw = f->fmt.pix.sizeimage;
3408 
3409 	channel->colorspace = f->fmt.pix.colorspace;
3410 	channel->ycbcr_enc = f->fmt.pix.ycbcr_enc;
3411 	channel->quantization = f->fmt.pix.quantization;
3412 	channel->xfer_func = f->fmt.pix.xfer_func;
3413 
3414 	allegro_channel_adjust(channel);
3415 
3416 	return 0;
3417 }
3418 
3419 static int allegro_channel_cmd_stop(struct allegro_channel *channel)
3420 {
3421 	if (v4l2_m2m_has_stopped(channel->fh.m2m_ctx))
3422 		allegro_channel_eos_event(channel);
3423 
3424 	return 0;
3425 }
3426 
3427 static int allegro_channel_cmd_start(struct allegro_channel *channel)
3428 {
3429 	if (v4l2_m2m_has_stopped(channel->fh.m2m_ctx))
3430 		vb2_clear_last_buffer_dequeued(&channel->fh.m2m_ctx->cap_q_ctx.q);
3431 
3432 	return 0;
3433 }
3434 
3435 static int allegro_encoder_cmd(struct file *file, void *fh,
3436 			       struct v4l2_encoder_cmd *cmd)
3437 {
3438 	struct allegro_channel *channel = fh_to_channel(fh);
3439 	int err;
3440 
3441 	err = v4l2_m2m_ioctl_try_encoder_cmd(file, fh, cmd);
3442 	if (err)
3443 		return err;
3444 
3445 	err = v4l2_m2m_ioctl_encoder_cmd(file, fh, cmd);
3446 	if (err)
3447 		return err;
3448 
3449 	if (cmd->cmd == V4L2_ENC_CMD_STOP)
3450 		err = allegro_channel_cmd_stop(channel);
3451 
3452 	if (cmd->cmd == V4L2_ENC_CMD_START)
3453 		err = allegro_channel_cmd_start(channel);
3454 
3455 	return err;
3456 }
3457 
3458 static int allegro_enum_framesizes(struct file *file, void *fh,
3459 				   struct v4l2_frmsizeenum *fsize)
3460 {
3461 	switch (fsize->pixel_format) {
3462 	case V4L2_PIX_FMT_HEVC:
3463 	case V4L2_PIX_FMT_H264:
3464 	case V4L2_PIX_FMT_NV12:
3465 		break;
3466 	default:
3467 		return -EINVAL;
3468 	}
3469 
3470 	if (fsize->index)
3471 		return -EINVAL;
3472 
3473 	fsize->type = V4L2_FRMSIZE_TYPE_CONTINUOUS;
3474 	fsize->stepwise.min_width = ALLEGRO_WIDTH_MIN;
3475 	fsize->stepwise.max_width = ALLEGRO_WIDTH_MAX;
3476 	fsize->stepwise.step_width = 1;
3477 	fsize->stepwise.min_height = ALLEGRO_HEIGHT_MIN;
3478 	fsize->stepwise.max_height = ALLEGRO_HEIGHT_MAX;
3479 	fsize->stepwise.step_height = 1;
3480 
3481 	return 0;
3482 }
3483 
3484 static int allegro_ioctl_streamon(struct file *file, void *priv,
3485 				  enum v4l2_buf_type type)
3486 {
3487 	struct v4l2_fh *fh = file->private_data;
3488 	struct allegro_channel *channel = fh_to_channel(fh);
3489 	int err;
3490 
3491 	if (type == V4L2_BUF_TYPE_VIDEO_CAPTURE) {
3492 		err = allegro_create_channel(channel);
3493 		if (err)
3494 			return err;
3495 	}
3496 
3497 	return v4l2_m2m_streamon(file, fh->m2m_ctx, type);
3498 }
3499 
3500 static int allegro_g_parm(struct file *file, void *fh,
3501 			  struct v4l2_streamparm *a)
3502 {
3503 	struct allegro_channel *channel = fh_to_channel(fh);
3504 	struct v4l2_fract *timeperframe;
3505 
3506 	if (a->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
3507 		return -EINVAL;
3508 
3509 	a->parm.output.capability = V4L2_CAP_TIMEPERFRAME;
3510 	timeperframe = &a->parm.output.timeperframe;
3511 	timeperframe->numerator = channel->framerate.denominator;
3512 	timeperframe->denominator = channel->framerate.numerator;
3513 
3514 	return 0;
3515 }
3516 
3517 static int allegro_s_parm(struct file *file, void *fh,
3518 			  struct v4l2_streamparm *a)
3519 {
3520 	struct allegro_channel *channel = fh_to_channel(fh);
3521 	struct v4l2_fract *timeperframe;
3522 	int div;
3523 
3524 	if (a->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
3525 		return -EINVAL;
3526 
3527 	a->parm.output.capability = V4L2_CAP_TIMEPERFRAME;
3528 	timeperframe = &a->parm.output.timeperframe;
3529 
3530 	if (timeperframe->numerator == 0 || timeperframe->denominator == 0)
3531 		return allegro_g_parm(file, fh, a);
3532 
3533 	div = gcd(timeperframe->denominator, timeperframe->numerator);
3534 	channel->framerate.numerator = timeperframe->denominator / div;
3535 	channel->framerate.denominator = timeperframe->numerator / div;
3536 
3537 	return 0;
3538 }
3539 
3540 static int allegro_subscribe_event(struct v4l2_fh *fh,
3541 				   const struct v4l2_event_subscription *sub)
3542 {
3543 	switch (sub->type) {
3544 	case V4L2_EVENT_EOS:
3545 		return v4l2_event_subscribe(fh, sub, 0, NULL);
3546 	default:
3547 		return v4l2_ctrl_subscribe_event(fh, sub);
3548 	}
3549 }
3550 
3551 static const struct v4l2_ioctl_ops allegro_ioctl_ops = {
3552 	.vidioc_querycap = allegro_querycap,
3553 	.vidioc_enum_fmt_vid_cap = allegro_enum_fmt_vid,
3554 	.vidioc_enum_fmt_vid_out = allegro_enum_fmt_vid,
3555 	.vidioc_g_fmt_vid_cap = allegro_g_fmt_vid_cap,
3556 	.vidioc_try_fmt_vid_cap = allegro_try_fmt_vid_cap,
3557 	.vidioc_s_fmt_vid_cap = allegro_s_fmt_vid_cap,
3558 	.vidioc_g_fmt_vid_out = allegro_g_fmt_vid_out,
3559 	.vidioc_try_fmt_vid_out = allegro_try_fmt_vid_out,
3560 	.vidioc_s_fmt_vid_out = allegro_s_fmt_vid_out,
3561 
3562 	.vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs,
3563 	.vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs,
3564 
3565 	.vidioc_expbuf = v4l2_m2m_ioctl_expbuf,
3566 	.vidioc_querybuf = v4l2_m2m_ioctl_querybuf,
3567 	.vidioc_qbuf = v4l2_m2m_ioctl_qbuf,
3568 	.vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf,
3569 	.vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf,
3570 
3571 	.vidioc_streamon = allegro_ioctl_streamon,
3572 	.vidioc_streamoff = v4l2_m2m_ioctl_streamoff,
3573 
3574 	.vidioc_try_encoder_cmd = v4l2_m2m_ioctl_try_encoder_cmd,
3575 	.vidioc_encoder_cmd = allegro_encoder_cmd,
3576 	.vidioc_enum_framesizes = allegro_enum_framesizes,
3577 
3578 	.vidioc_g_parm		= allegro_g_parm,
3579 	.vidioc_s_parm		= allegro_s_parm,
3580 
3581 	.vidioc_subscribe_event = allegro_subscribe_event,
3582 	.vidioc_unsubscribe_event = v4l2_event_unsubscribe,
3583 };
3584 
3585 static const struct v4l2_file_operations allegro_fops = {
3586 	.owner = THIS_MODULE,
3587 	.open = allegro_open,
3588 	.release = allegro_release,
3589 	.poll = v4l2_m2m_fop_poll,
3590 	.unlocked_ioctl = video_ioctl2,
3591 	.mmap = v4l2_m2m_fop_mmap,
3592 };
3593 
3594 static int allegro_register_device(struct allegro_dev *dev)
3595 {
3596 	struct video_device *video_dev = &dev->video_dev;
3597 
3598 	strscpy(video_dev->name, "allegro", sizeof(video_dev->name));
3599 	video_dev->fops = &allegro_fops;
3600 	video_dev->ioctl_ops = &allegro_ioctl_ops;
3601 	video_dev->release = video_device_release_empty;
3602 	video_dev->lock = &dev->lock;
3603 	video_dev->v4l2_dev = &dev->v4l2_dev;
3604 	video_dev->vfl_dir = VFL_DIR_M2M;
3605 	video_dev->device_caps = V4L2_CAP_VIDEO_M2M | V4L2_CAP_STREAMING;
3606 	video_set_drvdata(video_dev, dev);
3607 
3608 	return video_register_device(video_dev, VFL_TYPE_VIDEO, 0);
3609 }
3610 
3611 static void allegro_device_run(void *priv)
3612 {
3613 	struct allegro_channel *channel = priv;
3614 	struct allegro_dev *dev = channel->dev;
3615 	struct vb2_v4l2_buffer *src_buf;
3616 	struct vb2_v4l2_buffer *dst_buf;
3617 	dma_addr_t src_y;
3618 	dma_addr_t src_uv;
3619 	dma_addr_t dst_addr;
3620 	unsigned long dst_size;
3621 	u64 src_handle;
3622 	u64 dst_handle;
3623 
3624 	dst_buf = v4l2_m2m_dst_buf_remove(channel->fh.m2m_ctx);
3625 	dst_addr = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0);
3626 	dst_size = vb2_plane_size(&dst_buf->vb2_buf, 0);
3627 	dst_handle = allegro_put_buffer(channel, &channel->stream_shadow_list,
3628 					dst_buf);
3629 	allegro_mcu_send_put_stream_buffer(dev, channel, dst_addr, dst_size,
3630 					   dst_handle);
3631 
3632 	src_buf = v4l2_m2m_src_buf_remove(channel->fh.m2m_ctx);
3633 	src_buf->sequence = channel->osequence++;
3634 	src_y = vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0);
3635 	src_uv = src_y + (channel->stride * channel->height);
3636 	src_handle = allegro_put_buffer(channel, &channel->source_shadow_list,
3637 					src_buf);
3638 	allegro_mcu_send_encode_frame(dev, channel, src_y, src_uv, src_handle);
3639 
3640 	v4l2_m2m_job_finish(dev->m2m_dev, channel->fh.m2m_ctx);
3641 }
3642 
3643 static const struct v4l2_m2m_ops allegro_m2m_ops = {
3644 	.device_run = allegro_device_run,
3645 };
3646 
3647 static int allegro_mcu_hw_init(struct allegro_dev *dev,
3648 			       const struct fw_info *info)
3649 {
3650 	int err;
3651 
3652 	dev->mbox_command = allegro_mbox_init(dev, info->mailbox_cmd,
3653 					      info->mailbox_size);
3654 	dev->mbox_status = allegro_mbox_init(dev, info->mailbox_status,
3655 					     info->mailbox_size);
3656 	if (IS_ERR(dev->mbox_command) || IS_ERR(dev->mbox_status)) {
3657 		v4l2_err(&dev->v4l2_dev,
3658 			 "failed to initialize mailboxes\n");
3659 		return -EIO;
3660 	}
3661 
3662 	err = allegro_encoder_buffer_init(dev, &dev->encoder_buffer);
3663 	dev->has_encoder_buffer = (err == 0);
3664 	if (!dev->has_encoder_buffer)
3665 		v4l2_info(&dev->v4l2_dev, "encoder buffer not available\n");
3666 
3667 	allegro_mcu_enable_interrupts(dev);
3668 
3669 	/* The mcu sends INIT after reset. */
3670 	allegro_mcu_start(dev);
3671 	err = allegro_mcu_wait_for_init_timeout(dev, 5000);
3672 	if (err < 0) {
3673 		v4l2_err(&dev->v4l2_dev,
3674 			 "mcu did not send INIT after reset\n");
3675 		err = -EIO;
3676 		goto err_disable_interrupts;
3677 	}
3678 
3679 	err = allegro_alloc_buffer(dev, &dev->suballocator,
3680 				   info->suballocator_size);
3681 	if (err) {
3682 		v4l2_err(&dev->v4l2_dev,
3683 			 "failed to allocate %zu bytes for suballocator\n",
3684 			 info->suballocator_size);
3685 		goto err_reset_mcu;
3686 	}
3687 
3688 	allegro_mcu_send_init(dev, dev->suballocator.paddr,
3689 			      dev->suballocator.size);
3690 	err = allegro_mcu_wait_for_init_timeout(dev, 5000);
3691 	if (err < 0) {
3692 		v4l2_err(&dev->v4l2_dev,
3693 			 "mcu failed to configure sub-allocator\n");
3694 		err = -EIO;
3695 		goto err_free_suballocator;
3696 	}
3697 
3698 	return 0;
3699 
3700 err_free_suballocator:
3701 	allegro_free_buffer(dev, &dev->suballocator);
3702 err_reset_mcu:
3703 	allegro_mcu_reset(dev);
3704 err_disable_interrupts:
3705 	allegro_mcu_disable_interrupts(dev);
3706 
3707 	return err;
3708 }
3709 
3710 static int allegro_mcu_hw_deinit(struct allegro_dev *dev)
3711 {
3712 	int err;
3713 
3714 	err = allegro_mcu_reset(dev);
3715 	if (err)
3716 		v4l2_warn(&dev->v4l2_dev,
3717 			  "mcu failed to enter sleep state\n");
3718 
3719 	err = allegro_mcu_disable_interrupts(dev);
3720 	if (err)
3721 		v4l2_warn(&dev->v4l2_dev,
3722 			  "failed to disable interrupts\n");
3723 
3724 	allegro_free_buffer(dev, &dev->suballocator);
3725 
3726 	return 0;
3727 }
3728 
3729 static void allegro_fw_callback(const struct firmware *fw, void *context)
3730 {
3731 	struct allegro_dev *dev = context;
3732 	const char *fw_codec_name = "al5e.fw";
3733 	const struct firmware *fw_codec;
3734 	int err;
3735 
3736 	if (!fw)
3737 		return;
3738 
3739 	v4l2_dbg(1, debug, &dev->v4l2_dev,
3740 		 "requesting codec firmware '%s'\n", fw_codec_name);
3741 	err = request_firmware(&fw_codec, fw_codec_name, &dev->plat_dev->dev);
3742 	if (err)
3743 		goto err_release_firmware;
3744 
3745 	dev->fw_info = allegro_get_firmware_info(dev, fw, fw_codec);
3746 	if (!dev->fw_info) {
3747 		v4l2_err(&dev->v4l2_dev, "firmware is not supported\n");
3748 		goto err_release_firmware_codec;
3749 	}
3750 
3751 	v4l2_info(&dev->v4l2_dev,
3752 		  "using mcu firmware version '%s'\n", dev->fw_info->version);
3753 
3754 	pm_runtime_enable(&dev->plat_dev->dev);
3755 	err = pm_runtime_resume_and_get(&dev->plat_dev->dev);
3756 	if (err)
3757 		goto err_release_firmware_codec;
3758 
3759 	/* Ensure that the mcu is sleeping at the reset vector */
3760 	err = allegro_mcu_reset(dev);
3761 	if (err) {
3762 		v4l2_err(&dev->v4l2_dev, "failed to reset mcu\n");
3763 		goto err_suspend;
3764 	}
3765 
3766 	allegro_copy_firmware(dev, fw->data, fw->size);
3767 	allegro_copy_fw_codec(dev, fw_codec->data, fw_codec->size);
3768 
3769 	err = allegro_mcu_hw_init(dev, dev->fw_info);
3770 	if (err) {
3771 		v4l2_err(&dev->v4l2_dev, "failed to initialize mcu\n");
3772 		goto err_free_fw_codec;
3773 	}
3774 
3775 	dev->m2m_dev = v4l2_m2m_init(&allegro_m2m_ops);
3776 	if (IS_ERR(dev->m2m_dev)) {
3777 		v4l2_err(&dev->v4l2_dev, "failed to init mem2mem device\n");
3778 		goto err_mcu_hw_deinit;
3779 	}
3780 
3781 	err = allegro_register_device(dev);
3782 	if (err) {
3783 		v4l2_err(&dev->v4l2_dev, "failed to register video device\n");
3784 		goto err_m2m_release;
3785 	}
3786 
3787 	v4l2_dbg(1, debug, &dev->v4l2_dev,
3788 		 "allegro codec registered as /dev/video%d\n",
3789 		 dev->video_dev.num);
3790 
3791 	dev->initialized = true;
3792 
3793 	release_firmware(fw_codec);
3794 	release_firmware(fw);
3795 
3796 	return;
3797 
3798 err_m2m_release:
3799 	v4l2_m2m_release(dev->m2m_dev);
3800 	dev->m2m_dev = NULL;
3801 err_mcu_hw_deinit:
3802 	allegro_mcu_hw_deinit(dev);
3803 err_free_fw_codec:
3804 	allegro_free_fw_codec(dev);
3805 err_suspend:
3806 	pm_runtime_put(&dev->plat_dev->dev);
3807 	pm_runtime_disable(&dev->plat_dev->dev);
3808 err_release_firmware_codec:
3809 	release_firmware(fw_codec);
3810 err_release_firmware:
3811 	release_firmware(fw);
3812 }
3813 
3814 static int allegro_firmware_request_nowait(struct allegro_dev *dev)
3815 {
3816 	const char *fw = "al5e_b.fw";
3817 
3818 	v4l2_dbg(1, debug, &dev->v4l2_dev,
3819 		 "requesting firmware '%s'\n", fw);
3820 	return request_firmware_nowait(THIS_MODULE, true, fw,
3821 				       &dev->plat_dev->dev, GFP_KERNEL, dev,
3822 				       allegro_fw_callback);
3823 }
3824 
3825 static int allegro_probe(struct platform_device *pdev)
3826 {
3827 	struct allegro_dev *dev;
3828 	struct resource *res, *sram_res;
3829 	int ret;
3830 	int irq;
3831 	void __iomem *regs, *sram_regs;
3832 
3833 	dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
3834 	if (!dev)
3835 		return -ENOMEM;
3836 	dev->plat_dev = pdev;
3837 	init_completion(&dev->init_complete);
3838 	INIT_LIST_HEAD(&dev->channels);
3839 
3840 	mutex_init(&dev->lock);
3841 
3842 	dev->initialized = false;
3843 
3844 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
3845 	if (!res) {
3846 		dev_err(&pdev->dev,
3847 			"regs resource missing from device tree\n");
3848 		return -EINVAL;
3849 	}
3850 	regs = devm_ioremap(&pdev->dev, res->start, resource_size(res));
3851 	if (!regs) {
3852 		dev_err(&pdev->dev, "failed to map registers\n");
3853 		return -ENOMEM;
3854 	}
3855 	dev->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
3856 					    &allegro_regmap_config);
3857 	if (IS_ERR(dev->regmap)) {
3858 		dev_err(&pdev->dev, "failed to init regmap\n");
3859 		return PTR_ERR(dev->regmap);
3860 	}
3861 
3862 	sram_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sram");
3863 	if (!sram_res) {
3864 		dev_err(&pdev->dev,
3865 			"sram resource missing from device tree\n");
3866 		return -EINVAL;
3867 	}
3868 	sram_regs = devm_ioremap(&pdev->dev,
3869 				 sram_res->start,
3870 				 resource_size(sram_res));
3871 	if (!sram_regs) {
3872 		dev_err(&pdev->dev, "failed to map sram\n");
3873 		return -ENOMEM;
3874 	}
3875 	dev->sram = devm_regmap_init_mmio(&pdev->dev, sram_regs,
3876 					  &allegro_sram_config);
3877 	if (IS_ERR(dev->sram)) {
3878 		dev_err(&pdev->dev, "failed to init sram\n");
3879 		return PTR_ERR(dev->sram);
3880 	}
3881 
3882 	dev->settings = syscon_regmap_lookup_by_compatible("xlnx,vcu-settings");
3883 	if (IS_ERR(dev->settings))
3884 		dev_warn(&pdev->dev, "failed to open settings\n");
3885 
3886 	dev->clk_core = devm_clk_get(&pdev->dev, "core_clk");
3887 	if (IS_ERR(dev->clk_core))
3888 		return PTR_ERR(dev->clk_core);
3889 
3890 	dev->clk_mcu = devm_clk_get(&pdev->dev, "mcu_clk");
3891 	if (IS_ERR(dev->clk_mcu))
3892 		return PTR_ERR(dev->clk_mcu);
3893 
3894 	irq = platform_get_irq(pdev, 0);
3895 	if (irq < 0)
3896 		return irq;
3897 	ret = devm_request_threaded_irq(&pdev->dev, irq,
3898 					allegro_hardirq,
3899 					allegro_irq_thread,
3900 					IRQF_SHARED, dev_name(&pdev->dev), dev);
3901 	if (ret < 0) {
3902 		dev_err(&pdev->dev, "failed to request irq: %d\n", ret);
3903 		return ret;
3904 	}
3905 
3906 	ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
3907 	if (ret)
3908 		return ret;
3909 
3910 	platform_set_drvdata(pdev, dev);
3911 
3912 	ret = allegro_firmware_request_nowait(dev);
3913 	if (ret < 0) {
3914 		v4l2_err(&dev->v4l2_dev,
3915 			 "failed to request firmware: %d\n", ret);
3916 		return ret;
3917 	}
3918 
3919 	return 0;
3920 }
3921 
3922 static int allegro_remove(struct platform_device *pdev)
3923 {
3924 	struct allegro_dev *dev = platform_get_drvdata(pdev);
3925 
3926 	if (dev->initialized) {
3927 		video_unregister_device(&dev->video_dev);
3928 		if (dev->m2m_dev)
3929 			v4l2_m2m_release(dev->m2m_dev);
3930 		allegro_mcu_hw_deinit(dev);
3931 		allegro_free_fw_codec(dev);
3932 	}
3933 
3934 	pm_runtime_put(&dev->plat_dev->dev);
3935 	pm_runtime_disable(&dev->plat_dev->dev);
3936 
3937 	v4l2_device_unregister(&dev->v4l2_dev);
3938 
3939 	return 0;
3940 }
3941 
3942 static int allegro_runtime_resume(struct device *device)
3943 {
3944 	struct allegro_dev *dev = dev_get_drvdata(device);
3945 	struct regmap *settings = dev->settings;
3946 	unsigned int clk_mcu;
3947 	unsigned int clk_core;
3948 	int err;
3949 
3950 	if (!settings)
3951 		return -EINVAL;
3952 
3953 #define MHZ_TO_HZ(freq) ((freq) * 1000 * 1000)
3954 
3955 	err = regmap_read(settings, VCU_CORE_CLK, &clk_core);
3956 	if (err < 0)
3957 		return err;
3958 	err = clk_set_rate(dev->clk_core, MHZ_TO_HZ(clk_core));
3959 	if (err < 0)
3960 		return err;
3961 	err = clk_prepare_enable(dev->clk_core);
3962 	if (err)
3963 		return err;
3964 
3965 	err = regmap_read(settings, VCU_MCU_CLK, &clk_mcu);
3966 	if (err < 0)
3967 		goto disable_clk_core;
3968 	err = clk_set_rate(dev->clk_mcu, MHZ_TO_HZ(clk_mcu));
3969 	if (err < 0)
3970 		goto disable_clk_core;
3971 	err = clk_prepare_enable(dev->clk_mcu);
3972 	if (err)
3973 		goto disable_clk_core;
3974 
3975 #undef MHZ_TO_HZ
3976 
3977 	return 0;
3978 
3979 disable_clk_core:
3980 	clk_disable_unprepare(dev->clk_core);
3981 
3982 	return err;
3983 }
3984 
3985 static int allegro_runtime_suspend(struct device *device)
3986 {
3987 	struct allegro_dev *dev = dev_get_drvdata(device);
3988 
3989 	clk_disable_unprepare(dev->clk_mcu);
3990 	clk_disable_unprepare(dev->clk_core);
3991 
3992 	return 0;
3993 }
3994 
3995 static const struct of_device_id allegro_dt_ids[] = {
3996 	{ .compatible = "allegro,al5e-1.1" },
3997 	{ /* sentinel */ }
3998 };
3999 
4000 MODULE_DEVICE_TABLE(of, allegro_dt_ids);
4001 
4002 static const struct dev_pm_ops allegro_pm_ops = {
4003 	.runtime_resume = allegro_runtime_resume,
4004 	.runtime_suspend = allegro_runtime_suspend,
4005 };
4006 
4007 static struct platform_driver allegro_driver = {
4008 	.probe = allegro_probe,
4009 	.remove = allegro_remove,
4010 	.driver = {
4011 		.name = "allegro",
4012 		.of_match_table = of_match_ptr(allegro_dt_ids),
4013 		.pm = &allegro_pm_ops,
4014 	},
4015 };
4016 
4017 module_platform_driver(allegro_driver);
4018 
4019 MODULE_LICENSE("GPL");
4020 MODULE_AUTHOR("Michael Tretter <kernel@pengutronix.de>");
4021 MODULE_DESCRIPTION("Allegro DVT encoder driver");
4022