15a20fabfSMauro Carvalho Chehab# SPDX-License-Identifier: GPL-2.0-only 2*63fe3d27SMauro Carvalho Chehab 3*63fe3d27SMauro Carvalho Chehabcomment "Allegro DVT media platform drivers" 4*63fe3d27SMauro Carvalho Chehab 55a20fabfSMauro Carvalho Chehabconfig VIDEO_ALLEGRO_DVT 65a20fabfSMauro Carvalho Chehab tristate "Allegro DVT Video IP Core" 75a20fabfSMauro Carvalho Chehab depends on V4L_MEM2MEM_DRIVERS 85a20fabfSMauro Carvalho Chehab depends on VIDEO_DEV && VIDEO_V4L2 95a20fabfSMauro Carvalho Chehab depends on ARCH_ZYNQMP || COMPILE_TEST 105a20fabfSMauro Carvalho Chehab select V4L2_MEM2MEM_DEV 115a20fabfSMauro Carvalho Chehab select VIDEOBUF2_DMA_CONTIG 125a20fabfSMauro Carvalho Chehab select REGMAP_MMIO 135a20fabfSMauro Carvalho Chehab help 145a20fabfSMauro Carvalho Chehab Support for the encoder video IP core by Allegro DVT. This core is 155a20fabfSMauro Carvalho Chehab found for example on the Xilinx ZynqMP SoC in the EV family and is 165a20fabfSMauro Carvalho Chehab called VCU in the reference manual. 175a20fabfSMauro Carvalho Chehab 185a20fabfSMauro Carvalho Chehab To compile this driver as a module, choose M here: the module 195a20fabfSMauro Carvalho Chehab will be called allegro. 20