1*5a20fabfSMauro Carvalho Chehab# SPDX-License-Identifier: GPL-2.0-only
2*5a20fabfSMauro Carvalho Chehabconfig VIDEO_ALLEGRO_DVT
3*5a20fabfSMauro Carvalho Chehab	tristate "Allegro DVT Video IP Core"
4*5a20fabfSMauro Carvalho Chehab	depends on V4L_MEM2MEM_DRIVERS
5*5a20fabfSMauro Carvalho Chehab	depends on VIDEO_DEV && VIDEO_V4L2
6*5a20fabfSMauro Carvalho Chehab	depends on ARCH_ZYNQMP || COMPILE_TEST
7*5a20fabfSMauro Carvalho Chehab	select V4L2_MEM2MEM_DEV
8*5a20fabfSMauro Carvalho Chehab	select VIDEOBUF2_DMA_CONTIG
9*5a20fabfSMauro Carvalho Chehab	select REGMAP_MMIO
10*5a20fabfSMauro Carvalho Chehab	help
11*5a20fabfSMauro Carvalho Chehab	  Support for the encoder video IP core by Allegro DVT. This core is
12*5a20fabfSMauro Carvalho Chehab	  found for example on the Xilinx ZynqMP SoC in the EV family and is
13*5a20fabfSMauro Carvalho Chehab	  called VCU in the reference manual.
14*5a20fabfSMauro Carvalho Chehab
15*5a20fabfSMauro Carvalho Chehab	  To compile this driver as a module, choose M here: the module
16*5a20fabfSMauro Carvalho Chehab	  will be called allegro.
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