1 /* 2 * tw68 functions to handle video data 3 * 4 * Much of this code is derived from the cx88 and sa7134 drivers, which 5 * were in turn derived from the bt87x driver. The original work was by 6 * Gerd Knorr; more recently the code was enhanced by Mauro Carvalho Chehab, 7 * Hans Verkuil, Andy Walls and many others. Their work is gratefully 8 * acknowledged. Full credit goes to them - any problems within this code 9 * are mine. 10 * 11 * Copyright (C) 2009 William M. Brack 12 * 13 * Refactored and updated to the latest v4l core frameworks: 14 * 15 * Copyright (C) 2014 Hans Verkuil <hverkuil@xs4all.nl> 16 * 17 * This program is free software; you can redistribute it and/or modify 18 * it under the terms of the GNU General Public License as published by 19 * the Free Software Foundation; either version 2 of the License, or 20 * (at your option) any later version. 21 * 22 * This program is distributed in the hope that it will be useful, 23 * but WITHOUT ANY WARRANTY; without even the implied warranty of 24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 25 * GNU General Public License for more details. 26 */ 27 28 #include <linux/module.h> 29 #include <media/v4l2-common.h> 30 #include <media/v4l2-event.h> 31 #include <media/videobuf2-dma-sg.h> 32 33 #include "tw68.h" 34 #include "tw68-reg.h" 35 36 /* ------------------------------------------------------------------ */ 37 /* data structs for video */ 38 /* 39 * FIXME - 40 * Note that the saa7134 has formats, e.g. YUV420, which are classified 41 * as "planar". These affect overlay mode, and are flagged with a field 42 * ".planar" in the format. Do we need to implement this in this driver? 43 */ 44 static const struct tw68_format formats[] = { 45 { 46 .name = "15 bpp RGB, le", 47 .fourcc = V4L2_PIX_FMT_RGB555, 48 .depth = 16, 49 .twformat = ColorFormatRGB15, 50 }, { 51 .name = "15 bpp RGB, be", 52 .fourcc = V4L2_PIX_FMT_RGB555X, 53 .depth = 16, 54 .twformat = ColorFormatRGB15 | ColorFormatBSWAP, 55 }, { 56 .name = "16 bpp RGB, le", 57 .fourcc = V4L2_PIX_FMT_RGB565, 58 .depth = 16, 59 .twformat = ColorFormatRGB16, 60 }, { 61 .name = "16 bpp RGB, be", 62 .fourcc = V4L2_PIX_FMT_RGB565X, 63 .depth = 16, 64 .twformat = ColorFormatRGB16 | ColorFormatBSWAP, 65 }, { 66 .name = "24 bpp RGB, le", 67 .fourcc = V4L2_PIX_FMT_BGR24, 68 .depth = 24, 69 .twformat = ColorFormatRGB24, 70 }, { 71 .name = "24 bpp RGB, be", 72 .fourcc = V4L2_PIX_FMT_RGB24, 73 .depth = 24, 74 .twformat = ColorFormatRGB24 | ColorFormatBSWAP, 75 }, { 76 .name = "32 bpp RGB, le", 77 .fourcc = V4L2_PIX_FMT_BGR32, 78 .depth = 32, 79 .twformat = ColorFormatRGB32, 80 }, { 81 .name = "32 bpp RGB, be", 82 .fourcc = V4L2_PIX_FMT_RGB32, 83 .depth = 32, 84 .twformat = ColorFormatRGB32 | ColorFormatBSWAP | 85 ColorFormatWSWAP, 86 }, { 87 .name = "4:2:2 packed, YUYV", 88 .fourcc = V4L2_PIX_FMT_YUYV, 89 .depth = 16, 90 .twformat = ColorFormatYUY2, 91 }, { 92 .name = "4:2:2 packed, UYVY", 93 .fourcc = V4L2_PIX_FMT_UYVY, 94 .depth = 16, 95 .twformat = ColorFormatYUY2 | ColorFormatBSWAP, 96 } 97 }; 98 #define FORMATS ARRAY_SIZE(formats) 99 100 #define NORM_625_50 \ 101 .h_delay = 3, \ 102 .h_delay0 = 133, \ 103 .h_start = 0, \ 104 .h_stop = 719, \ 105 .v_delay = 24, \ 106 .vbi_v_start_0 = 7, \ 107 .vbi_v_stop_0 = 22, \ 108 .video_v_start = 24, \ 109 .video_v_stop = 311, \ 110 .vbi_v_start_1 = 319 111 112 #define NORM_525_60 \ 113 .h_delay = 8, \ 114 .h_delay0 = 138, \ 115 .h_start = 0, \ 116 .h_stop = 719, \ 117 .v_delay = 22, \ 118 .vbi_v_start_0 = 10, \ 119 .vbi_v_stop_0 = 21, \ 120 .video_v_start = 22, \ 121 .video_v_stop = 262, \ 122 .vbi_v_start_1 = 273 123 124 /* 125 * The following table is searched by tw68_s_std, first for a specific 126 * match, then for an entry which contains the desired id. The table 127 * entries should therefore be ordered in ascending order of specificity. 128 */ 129 static const struct tw68_tvnorm tvnorms[] = { 130 { 131 .name = "PAL", /* autodetect */ 132 .id = V4L2_STD_PAL, 133 NORM_625_50, 134 135 .sync_control = 0x18, 136 .luma_control = 0x40, 137 .chroma_ctrl1 = 0x81, 138 .chroma_gain = 0x2a, 139 .chroma_ctrl2 = 0x06, 140 .vgate_misc = 0x1c, 141 .format = VideoFormatPALBDGHI, 142 }, { 143 .name = "NTSC", 144 .id = V4L2_STD_NTSC, 145 NORM_525_60, 146 147 .sync_control = 0x59, 148 .luma_control = 0x40, 149 .chroma_ctrl1 = 0x89, 150 .chroma_gain = 0x2a, 151 .chroma_ctrl2 = 0x0e, 152 .vgate_misc = 0x18, 153 .format = VideoFormatNTSC, 154 }, { 155 .name = "SECAM", 156 .id = V4L2_STD_SECAM, 157 NORM_625_50, 158 159 .sync_control = 0x18, 160 .luma_control = 0x1b, 161 .chroma_ctrl1 = 0xd1, 162 .chroma_gain = 0x80, 163 .chroma_ctrl2 = 0x00, 164 .vgate_misc = 0x1c, 165 .format = VideoFormatSECAM, 166 }, { 167 .name = "PAL-M", 168 .id = V4L2_STD_PAL_M, 169 NORM_525_60, 170 171 .sync_control = 0x59, 172 .luma_control = 0x40, 173 .chroma_ctrl1 = 0xb9, 174 .chroma_gain = 0x2a, 175 .chroma_ctrl2 = 0x0e, 176 .vgate_misc = 0x18, 177 .format = VideoFormatPALM, 178 }, { 179 .name = "PAL-Nc", 180 .id = V4L2_STD_PAL_Nc, 181 NORM_625_50, 182 183 .sync_control = 0x18, 184 .luma_control = 0x40, 185 .chroma_ctrl1 = 0xa1, 186 .chroma_gain = 0x2a, 187 .chroma_ctrl2 = 0x06, 188 .vgate_misc = 0x1c, 189 .format = VideoFormatPALNC, 190 }, { 191 .name = "PAL-60", 192 .id = V4L2_STD_PAL_60, 193 .h_delay = 186, 194 .h_start = 0, 195 .h_stop = 719, 196 .v_delay = 26, 197 .video_v_start = 23, 198 .video_v_stop = 262, 199 .vbi_v_start_0 = 10, 200 .vbi_v_stop_0 = 21, 201 .vbi_v_start_1 = 273, 202 203 .sync_control = 0x18, 204 .luma_control = 0x40, 205 .chroma_ctrl1 = 0x81, 206 .chroma_gain = 0x2a, 207 .chroma_ctrl2 = 0x06, 208 .vgate_misc = 0x1c, 209 .format = VideoFormatPAL60, 210 } 211 }; 212 #define TVNORMS ARRAY_SIZE(tvnorms) 213 214 static const struct tw68_format *format_by_fourcc(unsigned int fourcc) 215 { 216 unsigned int i; 217 218 for (i = 0; i < FORMATS; i++) 219 if (formats[i].fourcc == fourcc) 220 return formats+i; 221 return NULL; 222 } 223 224 225 /* ------------------------------------------------------------------ */ 226 /* 227 * Note that the cropping rectangles are described in terms of a single 228 * frame, i.e. line positions are only 1/2 the interlaced equivalent 229 */ 230 static void set_tvnorm(struct tw68_dev *dev, const struct tw68_tvnorm *norm) 231 { 232 if (norm != dev->tvnorm) { 233 dev->width = 720; 234 dev->height = (norm->id & V4L2_STD_525_60) ? 480 : 576; 235 dev->tvnorm = norm; 236 tw68_set_tvnorm_hw(dev); 237 } 238 } 239 240 /* 241 * tw68_set_scale 242 * 243 * Scaling and Cropping for video decoding 244 * 245 * We are working with 3 values for horizontal and vertical - scale, 246 * delay and active. 247 * 248 * HACTIVE represent the actual number of pixels in the "usable" image, 249 * before scaling. HDELAY represents the number of pixels skipped 250 * between the start of the horizontal sync and the start of the image. 251 * HSCALE is calculated using the formula 252 * HSCALE = (HACTIVE / (#pixels desired)) * 256 253 * 254 * The vertical registers are similar, except based upon the total number 255 * of lines in the image, and the first line of the image (i.e. ignoring 256 * vertical sync and VBI). 257 * 258 * Note that the number of bytes reaching the FIFO (and hence needing 259 * to be processed by the DMAP program) is completely dependent upon 260 * these values, especially HSCALE. 261 * 262 * Parameters: 263 * @dev pointer to the device structure, needed for 264 * getting current norm (as well as debug print) 265 * @width actual image width (from user buffer) 266 * @height actual image height 267 * @field indicates Top, Bottom or Interlaced 268 */ 269 static int tw68_set_scale(struct tw68_dev *dev, unsigned int width, 270 unsigned int height, enum v4l2_field field) 271 { 272 const struct tw68_tvnorm *norm = dev->tvnorm; 273 /* set individually for debugging clarity */ 274 int hactive, hdelay, hscale; 275 int vactive, vdelay, vscale; 276 int comb; 277 278 if (V4L2_FIELD_HAS_BOTH(field)) /* if field is interlaced */ 279 height /= 2; /* we must set for 1-frame */ 280 281 pr_debug("%s: width=%d, height=%d, both=%d\n" 282 " tvnorm h_delay=%d, h_start=%d, h_stop=%d, " 283 "v_delay=%d, v_start=%d, v_stop=%d\n" , __func__, 284 width, height, V4L2_FIELD_HAS_BOTH(field), 285 norm->h_delay, norm->h_start, norm->h_stop, 286 norm->v_delay, norm->video_v_start, 287 norm->video_v_stop); 288 289 switch (dev->vdecoder) { 290 case TW6800: 291 hdelay = norm->h_delay0; 292 break; 293 default: 294 hdelay = norm->h_delay; 295 break; 296 } 297 298 hdelay += norm->h_start; 299 hactive = norm->h_stop - norm->h_start + 1; 300 301 hscale = (hactive * 256) / (width); 302 303 vdelay = norm->v_delay; 304 vactive = ((norm->id & V4L2_STD_525_60) ? 524 : 624) / 2 - norm->video_v_start; 305 vscale = (vactive * 256) / height; 306 307 pr_debug("%s: %dx%d [%s%s,%s]\n", __func__, 308 width, height, 309 V4L2_FIELD_HAS_TOP(field) ? "T" : "", 310 V4L2_FIELD_HAS_BOTTOM(field) ? "B" : "", 311 v4l2_norm_to_name(dev->tvnorm->id)); 312 pr_debug("%s: hactive=%d, hdelay=%d, hscale=%d; " 313 "vactive=%d, vdelay=%d, vscale=%d\n", __func__, 314 hactive, hdelay, hscale, vactive, vdelay, vscale); 315 316 comb = ((vdelay & 0x300) >> 2) | 317 ((vactive & 0x300) >> 4) | 318 ((hdelay & 0x300) >> 6) | 319 ((hactive & 0x300) >> 8); 320 pr_debug("%s: setting CROP_HI=%02x, VDELAY_LO=%02x, " 321 "VACTIVE_LO=%02x, HDELAY_LO=%02x, HACTIVE_LO=%02x\n", 322 __func__, comb, vdelay, vactive, hdelay, hactive); 323 tw_writeb(TW68_CROP_HI, comb); 324 tw_writeb(TW68_VDELAY_LO, vdelay & 0xff); 325 tw_writeb(TW68_VACTIVE_LO, vactive & 0xff); 326 tw_writeb(TW68_HDELAY_LO, hdelay & 0xff); 327 tw_writeb(TW68_HACTIVE_LO, hactive & 0xff); 328 329 comb = ((vscale & 0xf00) >> 4) | ((hscale & 0xf00) >> 8); 330 pr_debug("%s: setting SCALE_HI=%02x, VSCALE_LO=%02x, " 331 "HSCALE_LO=%02x\n", __func__, comb, vscale, hscale); 332 tw_writeb(TW68_SCALE_HI, comb); 333 tw_writeb(TW68_VSCALE_LO, vscale); 334 tw_writeb(TW68_HSCALE_LO, hscale); 335 336 return 0; 337 } 338 339 /* ------------------------------------------------------------------ */ 340 341 int tw68_video_start_dma(struct tw68_dev *dev, struct tw68_buf *buf) 342 { 343 /* Set cropping and scaling */ 344 tw68_set_scale(dev, dev->width, dev->height, dev->field); 345 /* 346 * Set start address for RISC program. Note that if the DMAP 347 * processor is currently running, it must be stopped before 348 * a new address can be set. 349 */ 350 tw_clearl(TW68_DMAC, TW68_DMAP_EN); 351 tw_writel(TW68_DMAP_SA, buf->dma); 352 /* Clear any pending interrupts */ 353 tw_writel(TW68_INTSTAT, dev->board_virqmask); 354 /* Enable the risc engine and the fifo */ 355 tw_andorl(TW68_DMAC, 0xff, dev->fmt->twformat | 356 ColorFormatGamma | TW68_DMAP_EN | TW68_FIFO_EN); 357 dev->pci_irqmask |= dev->board_virqmask; 358 tw_setl(TW68_INTMASK, dev->pci_irqmask); 359 return 0; 360 } 361 362 /* ------------------------------------------------------------------ */ 363 364 /* calc max # of buffers from size (must not exceed the 4MB virtual 365 * address space per DMA channel) */ 366 static int tw68_buffer_count(unsigned int size, unsigned int count) 367 { 368 unsigned int maxcount; 369 370 maxcount = (4 * 1024 * 1024) / roundup(size, PAGE_SIZE); 371 if (count > maxcount) 372 count = maxcount; 373 return count; 374 } 375 376 /* ------------------------------------------------------------- */ 377 /* vb2 queue operations */ 378 379 static int tw68_queue_setup(struct vb2_queue *q, const struct v4l2_format *fmt, 380 unsigned int *num_buffers, unsigned int *num_planes, 381 unsigned int sizes[], void *alloc_ctxs[]) 382 { 383 struct tw68_dev *dev = vb2_get_drv_priv(q); 384 unsigned tot_bufs = q->num_buffers + *num_buffers; 385 386 sizes[0] = (dev->fmt->depth * dev->width * dev->height) >> 3; 387 alloc_ctxs[0] = dev->alloc_ctx; 388 /* 389 * We allow create_bufs, but only if the sizeimage is the same as the 390 * current sizeimage. The tw68_buffer_count calculation becomes quite 391 * difficult otherwise. 392 */ 393 if (fmt && fmt->fmt.pix.sizeimage < sizes[0]) 394 return -EINVAL; 395 *num_planes = 1; 396 if (tot_bufs < 2) 397 tot_bufs = 2; 398 tot_bufs = tw68_buffer_count(sizes[0], tot_bufs); 399 *num_buffers = tot_bufs - q->num_buffers; 400 401 return 0; 402 } 403 404 /* 405 * The risc program for each buffers works as follows: it starts with a simple 406 * 'JUMP to addr + 8', which is effectively a NOP. Then the program to DMA the 407 * buffer follows and at the end we have a JUMP back to the start + 8 (skipping 408 * the initial JUMP). 409 * 410 * This is the program of the first buffer to be queued if the active list is 411 * empty and it just keeps DMAing this buffer without generating any interrupts. 412 * 413 * If a new buffer is added then the initial JUMP in the program generates an 414 * interrupt as well which signals that the previous buffer has been DMAed 415 * successfully and that it can be returned to userspace. 416 * 417 * It also sets the final jump of the previous buffer to the start of the new 418 * buffer, thus chaining the new buffer into the DMA chain. This is a single 419 * atomic u32 write, so there is no race condition. 420 * 421 * The end-result of all this that you only get an interrupt when a buffer 422 * is ready, so the control flow is very easy. 423 */ 424 static void tw68_buf_queue(struct vb2_buffer *vb) 425 { 426 struct vb2_queue *vq = vb->vb2_queue; 427 struct tw68_dev *dev = vb2_get_drv_priv(vq); 428 struct tw68_buf *buf = container_of(vb, struct tw68_buf, vb); 429 struct tw68_buf *prev; 430 unsigned long flags; 431 432 spin_lock_irqsave(&dev->slock, flags); 433 434 /* append a 'JUMP to start of buffer' to the buffer risc program */ 435 buf->jmp[0] = cpu_to_le32(RISC_JUMP); 436 buf->jmp[1] = cpu_to_le32(buf->dma + 8); 437 438 if (!list_empty(&dev->active)) { 439 prev = list_entry(dev->active.prev, struct tw68_buf, list); 440 buf->cpu[0] |= cpu_to_le32(RISC_INT_BIT); 441 prev->jmp[1] = cpu_to_le32(buf->dma); 442 } 443 list_add_tail(&buf->list, &dev->active); 444 spin_unlock_irqrestore(&dev->slock, flags); 445 } 446 447 /* 448 * buffer_prepare 449 * 450 * Set the ancilliary information into the buffer structure. This 451 * includes generating the necessary risc program if it hasn't already 452 * been done for the current buffer format. 453 * The structure fh contains the details of the format requested by the 454 * user - type, width, height and #fields. This is compared with the 455 * last format set for the current buffer. If they differ, the risc 456 * code (which controls the filling of the buffer) is (re-)generated. 457 */ 458 static int tw68_buf_prepare(struct vb2_buffer *vb) 459 { 460 struct vb2_queue *vq = vb->vb2_queue; 461 struct tw68_dev *dev = vb2_get_drv_priv(vq); 462 struct tw68_buf *buf = container_of(vb, struct tw68_buf, vb); 463 struct sg_table *dma = vb2_dma_sg_plane_desc(vb, 0); 464 unsigned size, bpl; 465 int rc; 466 467 size = (dev->width * dev->height * dev->fmt->depth) >> 3; 468 if (vb2_plane_size(vb, 0) < size) 469 return -EINVAL; 470 vb2_set_plane_payload(vb, 0, size); 471 472 rc = dma_map_sg(&dev->pci->dev, dma->sgl, dma->nents, DMA_FROM_DEVICE); 473 if (!rc) 474 return -EIO; 475 476 bpl = (dev->width * dev->fmt->depth) >> 3; 477 switch (dev->field) { 478 case V4L2_FIELD_TOP: 479 tw68_risc_buffer(dev->pci, buf, dma->sgl, 480 0, UNSET, bpl, 0, dev->height); 481 break; 482 case V4L2_FIELD_BOTTOM: 483 tw68_risc_buffer(dev->pci, buf, dma->sgl, 484 UNSET, 0, bpl, 0, dev->height); 485 break; 486 case V4L2_FIELD_SEQ_TB: 487 tw68_risc_buffer(dev->pci, buf, dma->sgl, 488 0, bpl * (dev->height >> 1), 489 bpl, 0, dev->height >> 1); 490 break; 491 case V4L2_FIELD_SEQ_BT: 492 tw68_risc_buffer(dev->pci, buf, dma->sgl, 493 bpl * (dev->height >> 1), 0, 494 bpl, 0, dev->height >> 1); 495 break; 496 case V4L2_FIELD_INTERLACED: 497 default: 498 tw68_risc_buffer(dev->pci, buf, dma->sgl, 499 0, bpl, bpl, bpl, dev->height >> 1); 500 break; 501 } 502 return 0; 503 } 504 505 static void tw68_buf_finish(struct vb2_buffer *vb) 506 { 507 struct vb2_queue *vq = vb->vb2_queue; 508 struct tw68_dev *dev = vb2_get_drv_priv(vq); 509 struct sg_table *dma = vb2_dma_sg_plane_desc(vb, 0); 510 struct tw68_buf *buf = container_of(vb, struct tw68_buf, vb); 511 512 dma_unmap_sg(&dev->pci->dev, dma->sgl, dma->nents, DMA_FROM_DEVICE); 513 514 pci_free_consistent(dev->pci, buf->size, buf->cpu, buf->dma); 515 } 516 517 static int tw68_start_streaming(struct vb2_queue *q, unsigned int count) 518 { 519 struct tw68_dev *dev = vb2_get_drv_priv(q); 520 struct tw68_buf *buf = 521 container_of(dev->active.next, struct tw68_buf, list); 522 523 dev->seqnr = 0; 524 tw68_video_start_dma(dev, buf); 525 return 0; 526 } 527 528 static void tw68_stop_streaming(struct vb2_queue *q) 529 { 530 struct tw68_dev *dev = vb2_get_drv_priv(q); 531 532 /* Stop risc & fifo */ 533 tw_clearl(TW68_DMAC, TW68_DMAP_EN | TW68_FIFO_EN); 534 while (!list_empty(&dev->active)) { 535 struct tw68_buf *buf = 536 container_of(dev->active.next, struct tw68_buf, list); 537 538 list_del(&buf->list); 539 vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR); 540 } 541 } 542 543 static struct vb2_ops tw68_video_qops = { 544 .queue_setup = tw68_queue_setup, 545 .buf_queue = tw68_buf_queue, 546 .buf_prepare = tw68_buf_prepare, 547 .buf_finish = tw68_buf_finish, 548 .start_streaming = tw68_start_streaming, 549 .stop_streaming = tw68_stop_streaming, 550 .wait_prepare = vb2_ops_wait_prepare, 551 .wait_finish = vb2_ops_wait_finish, 552 }; 553 554 /* ------------------------------------------------------------------ */ 555 556 static int tw68_s_ctrl(struct v4l2_ctrl *ctrl) 557 { 558 struct tw68_dev *dev = 559 container_of(ctrl->handler, struct tw68_dev, hdl); 560 561 switch (ctrl->id) { 562 case V4L2_CID_BRIGHTNESS: 563 tw_writeb(TW68_BRIGHT, ctrl->val); 564 break; 565 case V4L2_CID_HUE: 566 tw_writeb(TW68_HUE, ctrl->val); 567 break; 568 case V4L2_CID_CONTRAST: 569 tw_writeb(TW68_CONTRAST, ctrl->val); 570 break; 571 case V4L2_CID_SATURATION: 572 tw_writeb(TW68_SAT_U, ctrl->val); 573 tw_writeb(TW68_SAT_V, ctrl->val); 574 break; 575 case V4L2_CID_COLOR_KILLER: 576 if (ctrl->val) 577 tw_andorb(TW68_MISC2, 0xe0, 0xe0); 578 else 579 tw_andorb(TW68_MISC2, 0xe0, 0x00); 580 break; 581 case V4L2_CID_CHROMA_AGC: 582 if (ctrl->val) 583 tw_andorb(TW68_LOOP, 0x30, 0x20); 584 else 585 tw_andorb(TW68_LOOP, 0x30, 0x00); 586 break; 587 } 588 return 0; 589 } 590 591 /* ------------------------------------------------------------------ */ 592 593 /* 594 * Note that this routine returns what is stored in the fh structure, and 595 * does not interrogate any of the device registers. 596 */ 597 static int tw68_g_fmt_vid_cap(struct file *file, void *priv, 598 struct v4l2_format *f) 599 { 600 struct tw68_dev *dev = video_drvdata(file); 601 602 f->fmt.pix.width = dev->width; 603 f->fmt.pix.height = dev->height; 604 f->fmt.pix.field = dev->field; 605 f->fmt.pix.pixelformat = dev->fmt->fourcc; 606 f->fmt.pix.bytesperline = 607 (f->fmt.pix.width * (dev->fmt->depth)) >> 3; 608 f->fmt.pix.sizeimage = 609 f->fmt.pix.height * f->fmt.pix.bytesperline; 610 f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M; 611 f->fmt.pix.priv = 0; 612 return 0; 613 } 614 615 static int tw68_try_fmt_vid_cap(struct file *file, void *priv, 616 struct v4l2_format *f) 617 { 618 struct tw68_dev *dev = video_drvdata(file); 619 const struct tw68_format *fmt; 620 enum v4l2_field field; 621 unsigned int maxh; 622 623 fmt = format_by_fourcc(f->fmt.pix.pixelformat); 624 if (NULL == fmt) 625 return -EINVAL; 626 627 field = f->fmt.pix.field; 628 maxh = (dev->tvnorm->id & V4L2_STD_525_60) ? 480 : 576; 629 630 switch (field) { 631 case V4L2_FIELD_TOP: 632 case V4L2_FIELD_BOTTOM: 633 break; 634 case V4L2_FIELD_INTERLACED: 635 case V4L2_FIELD_SEQ_BT: 636 case V4L2_FIELD_SEQ_TB: 637 maxh = maxh * 2; 638 break; 639 default: 640 field = (f->fmt.pix.height > maxh / 2) 641 ? V4L2_FIELD_INTERLACED 642 : V4L2_FIELD_BOTTOM; 643 break; 644 } 645 646 f->fmt.pix.field = field; 647 if (f->fmt.pix.width < 48) 648 f->fmt.pix.width = 48; 649 if (f->fmt.pix.height < 32) 650 f->fmt.pix.height = 32; 651 if (f->fmt.pix.width > 720) 652 f->fmt.pix.width = 720; 653 if (f->fmt.pix.height > maxh) 654 f->fmt.pix.height = maxh; 655 f->fmt.pix.width &= ~0x03; 656 f->fmt.pix.bytesperline = 657 (f->fmt.pix.width * (fmt->depth)) >> 3; 658 f->fmt.pix.sizeimage = 659 f->fmt.pix.height * f->fmt.pix.bytesperline; 660 f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M; 661 return 0; 662 } 663 664 /* 665 * Note that tw68_s_fmt_vid_cap sets the information into the fh structure, 666 * and it will be used for all future new buffers. However, there could be 667 * some number of buffers on the "active" chain which will be filled before 668 * the change takes place. 669 */ 670 static int tw68_s_fmt_vid_cap(struct file *file, void *priv, 671 struct v4l2_format *f) 672 { 673 struct tw68_dev *dev = video_drvdata(file); 674 int err; 675 676 err = tw68_try_fmt_vid_cap(file, priv, f); 677 if (0 != err) 678 return err; 679 680 dev->fmt = format_by_fourcc(f->fmt.pix.pixelformat); 681 dev->width = f->fmt.pix.width; 682 dev->height = f->fmt.pix.height; 683 dev->field = f->fmt.pix.field; 684 return 0; 685 } 686 687 static int tw68_enum_input(struct file *file, void *priv, 688 struct v4l2_input *i) 689 { 690 struct tw68_dev *dev = video_drvdata(file); 691 unsigned int n; 692 693 n = i->index; 694 if (n >= TW68_INPUT_MAX) 695 return -EINVAL; 696 i->index = n; 697 i->type = V4L2_INPUT_TYPE_CAMERA; 698 snprintf(i->name, sizeof(i->name), "Composite %d", n); 699 700 /* If the query is for the current input, get live data */ 701 if (n == dev->input) { 702 int v1 = tw_readb(TW68_STATUS1); 703 int v2 = tw_readb(TW68_MVSN); 704 705 if (0 != (v1 & (1 << 7))) 706 i->status |= V4L2_IN_ST_NO_SYNC; 707 if (0 != (v1 & (1 << 6))) 708 i->status |= V4L2_IN_ST_NO_H_LOCK; 709 if (0 != (v1 & (1 << 2))) 710 i->status |= V4L2_IN_ST_NO_SIGNAL; 711 if (0 != (v1 & 1 << 1)) 712 i->status |= V4L2_IN_ST_NO_COLOR; 713 if (0 != (v2 & (1 << 2))) 714 i->status |= V4L2_IN_ST_MACROVISION; 715 } 716 i->std = video_devdata(file)->tvnorms; 717 return 0; 718 } 719 720 static int tw68_g_input(struct file *file, void *priv, unsigned int *i) 721 { 722 struct tw68_dev *dev = video_drvdata(file); 723 724 *i = dev->input; 725 return 0; 726 } 727 728 static int tw68_s_input(struct file *file, void *priv, unsigned int i) 729 { 730 struct tw68_dev *dev = video_drvdata(file); 731 732 if (i >= TW68_INPUT_MAX) 733 return -EINVAL; 734 dev->input = i; 735 tw_andorb(TW68_INFORM, 0x03 << 2, dev->input << 2); 736 return 0; 737 } 738 739 static int tw68_querycap(struct file *file, void *priv, 740 struct v4l2_capability *cap) 741 { 742 struct tw68_dev *dev = video_drvdata(file); 743 744 strcpy(cap->driver, "tw68"); 745 strlcpy(cap->card, "Techwell Capture Card", 746 sizeof(cap->card)); 747 sprintf(cap->bus_info, "PCI:%s", pci_name(dev->pci)); 748 cap->device_caps = 749 V4L2_CAP_VIDEO_CAPTURE | 750 V4L2_CAP_READWRITE | 751 V4L2_CAP_STREAMING; 752 753 cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS; 754 return 0; 755 } 756 757 static int tw68_s_std(struct file *file, void *priv, v4l2_std_id id) 758 { 759 struct tw68_dev *dev = video_drvdata(file); 760 unsigned int i; 761 762 if (vb2_is_busy(&dev->vidq)) 763 return -EBUSY; 764 765 /* Look for match on complete norm id (may have mult bits) */ 766 for (i = 0; i < TVNORMS; i++) { 767 if (id == tvnorms[i].id) 768 break; 769 } 770 771 /* If no exact match, look for norm which contains this one */ 772 if (i == TVNORMS) { 773 for (i = 0; i < TVNORMS; i++) 774 if (id & tvnorms[i].id) 775 break; 776 } 777 /* If still not matched, give up */ 778 if (i == TVNORMS) 779 return -EINVAL; 780 781 set_tvnorm(dev, &tvnorms[i]); /* do the actual setting */ 782 return 0; 783 } 784 785 static int tw68_g_std(struct file *file, void *priv, v4l2_std_id *id) 786 { 787 struct tw68_dev *dev = video_drvdata(file); 788 789 *id = dev->tvnorm->id; 790 return 0; 791 } 792 793 static int tw68_enum_fmt_vid_cap(struct file *file, void *priv, 794 struct v4l2_fmtdesc *f) 795 { 796 if (f->index >= FORMATS) 797 return -EINVAL; 798 799 strlcpy(f->description, formats[f->index].name, 800 sizeof(f->description)); 801 802 f->pixelformat = formats[f->index].fourcc; 803 804 return 0; 805 } 806 807 /* 808 * Used strictly for internal development and debugging, this routine 809 * prints out the current register contents for the tw68xx device. 810 */ 811 static void tw68_dump_regs(struct tw68_dev *dev) 812 { 813 unsigned char line[80]; 814 int i, j, k; 815 unsigned char *cptr; 816 817 pr_info("Full dump of TW68 registers:\n"); 818 /* First we do the PCI regs, 8 4-byte regs per line */ 819 for (i = 0; i < 0x100; i += 32) { 820 cptr = line; 821 cptr += sprintf(cptr, "%03x ", i); 822 /* j steps through the next 4 words */ 823 for (j = i; j < i + 16; j += 4) 824 cptr += sprintf(cptr, "%08x ", tw_readl(j)); 825 *cptr++ = ' '; 826 for (; j < i + 32; j += 4) 827 cptr += sprintf(cptr, "%08x ", tw_readl(j)); 828 *cptr++ = '\n'; 829 *cptr = 0; 830 pr_info("%s", line); 831 } 832 /* Next the control regs, which are single-byte, address mod 4 */ 833 while (i < 0x400) { 834 cptr = line; 835 cptr += sprintf(cptr, "%03x ", i); 836 /* Print out 4 groups of 4 bytes */ 837 for (j = 0; j < 4; j++) { 838 for (k = 0; k < 4; k++) { 839 cptr += sprintf(cptr, "%02x ", 840 tw_readb(i)); 841 i += 4; 842 } 843 *cptr++ = ' '; 844 } 845 *cptr++ = '\n'; 846 *cptr = 0; 847 pr_info("%s", line); 848 } 849 } 850 851 static int vidioc_log_status(struct file *file, void *priv) 852 { 853 struct tw68_dev *dev = video_drvdata(file); 854 855 tw68_dump_regs(dev); 856 return v4l2_ctrl_log_status(file, priv); 857 } 858 859 #ifdef CONFIG_VIDEO_ADV_DEBUG 860 static int vidioc_g_register(struct file *file, void *priv, 861 struct v4l2_dbg_register *reg) 862 { 863 struct tw68_dev *dev = video_drvdata(file); 864 865 if (reg->size == 1) 866 reg->val = tw_readb(reg->reg); 867 else 868 reg->val = tw_readl(reg->reg); 869 return 0; 870 } 871 872 static int vidioc_s_register(struct file *file, void *priv, 873 const struct v4l2_dbg_register *reg) 874 { 875 struct tw68_dev *dev = video_drvdata(file); 876 877 if (reg->size == 1) 878 tw_writeb(reg->reg, reg->val); 879 else 880 tw_writel(reg->reg & 0xffff, reg->val); 881 return 0; 882 } 883 #endif 884 885 static const struct v4l2_ctrl_ops tw68_ctrl_ops = { 886 .s_ctrl = tw68_s_ctrl, 887 }; 888 889 static const struct v4l2_file_operations video_fops = { 890 .owner = THIS_MODULE, 891 .open = v4l2_fh_open, 892 .release = vb2_fop_release, 893 .read = vb2_fop_read, 894 .poll = vb2_fop_poll, 895 .mmap = vb2_fop_mmap, 896 .unlocked_ioctl = video_ioctl2, 897 }; 898 899 static const struct v4l2_ioctl_ops video_ioctl_ops = { 900 .vidioc_querycap = tw68_querycap, 901 .vidioc_enum_fmt_vid_cap = tw68_enum_fmt_vid_cap, 902 .vidioc_reqbufs = vb2_ioctl_reqbufs, 903 .vidioc_create_bufs = vb2_ioctl_create_bufs, 904 .vidioc_querybuf = vb2_ioctl_querybuf, 905 .vidioc_qbuf = vb2_ioctl_qbuf, 906 .vidioc_dqbuf = vb2_ioctl_dqbuf, 907 .vidioc_s_std = tw68_s_std, 908 .vidioc_g_std = tw68_g_std, 909 .vidioc_enum_input = tw68_enum_input, 910 .vidioc_g_input = tw68_g_input, 911 .vidioc_s_input = tw68_s_input, 912 .vidioc_streamon = vb2_ioctl_streamon, 913 .vidioc_streamoff = vb2_ioctl_streamoff, 914 .vidioc_g_fmt_vid_cap = tw68_g_fmt_vid_cap, 915 .vidioc_try_fmt_vid_cap = tw68_try_fmt_vid_cap, 916 .vidioc_s_fmt_vid_cap = tw68_s_fmt_vid_cap, 917 .vidioc_log_status = vidioc_log_status, 918 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, 919 .vidioc_unsubscribe_event = v4l2_event_unsubscribe, 920 #ifdef CONFIG_VIDEO_ADV_DEBUG 921 .vidioc_g_register = vidioc_g_register, 922 .vidioc_s_register = vidioc_s_register, 923 #endif 924 }; 925 926 static struct video_device tw68_video_template = { 927 .name = "tw68_video", 928 .fops = &video_fops, 929 .ioctl_ops = &video_ioctl_ops, 930 .release = video_device_release_empty, 931 .tvnorms = TW68_NORMS, 932 }; 933 934 /* ------------------------------------------------------------------ */ 935 /* exported stuff */ 936 void tw68_set_tvnorm_hw(struct tw68_dev *dev) 937 { 938 tw_andorb(TW68_SDT, 0x07, dev->tvnorm->format); 939 } 940 941 int tw68_video_init1(struct tw68_dev *dev) 942 { 943 struct v4l2_ctrl_handler *hdl = &dev->hdl; 944 945 v4l2_ctrl_handler_init(hdl, 6); 946 v4l2_ctrl_new_std(hdl, &tw68_ctrl_ops, 947 V4L2_CID_BRIGHTNESS, -128, 127, 1, 20); 948 v4l2_ctrl_new_std(hdl, &tw68_ctrl_ops, 949 V4L2_CID_CONTRAST, 0, 255, 1, 100); 950 v4l2_ctrl_new_std(hdl, &tw68_ctrl_ops, 951 V4L2_CID_SATURATION, 0, 255, 1, 128); 952 /* NTSC only */ 953 v4l2_ctrl_new_std(hdl, &tw68_ctrl_ops, 954 V4L2_CID_HUE, -128, 127, 1, 0); 955 v4l2_ctrl_new_std(hdl, &tw68_ctrl_ops, 956 V4L2_CID_COLOR_KILLER, 0, 1, 1, 0); 957 v4l2_ctrl_new_std(hdl, &tw68_ctrl_ops, 958 V4L2_CID_CHROMA_AGC, 0, 1, 1, 1); 959 if (hdl->error) { 960 v4l2_ctrl_handler_free(hdl); 961 return hdl->error; 962 } 963 dev->v4l2_dev.ctrl_handler = hdl; 964 v4l2_ctrl_handler_setup(hdl); 965 return 0; 966 } 967 968 int tw68_video_init2(struct tw68_dev *dev, int video_nr) 969 { 970 int ret; 971 972 set_tvnorm(dev, &tvnorms[0]); 973 974 dev->fmt = format_by_fourcc(V4L2_PIX_FMT_BGR24); 975 dev->width = 720; 976 dev->height = 576; 977 dev->field = V4L2_FIELD_INTERLACED; 978 979 INIT_LIST_HEAD(&dev->active); 980 dev->vidq.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; 981 dev->vidq.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; 982 dev->vidq.io_modes = VB2_MMAP | VB2_USERPTR | VB2_READ | VB2_DMABUF; 983 dev->vidq.ops = &tw68_video_qops; 984 dev->vidq.mem_ops = &vb2_dma_sg_memops; 985 dev->vidq.drv_priv = dev; 986 dev->vidq.gfp_flags = __GFP_DMA32; 987 dev->vidq.buf_struct_size = sizeof(struct tw68_buf); 988 dev->vidq.lock = &dev->lock; 989 dev->vidq.min_buffers_needed = 2; 990 ret = vb2_queue_init(&dev->vidq); 991 if (ret) 992 return ret; 993 dev->vdev = tw68_video_template; 994 dev->vdev.v4l2_dev = &dev->v4l2_dev; 995 dev->vdev.lock = &dev->lock; 996 dev->vdev.queue = &dev->vidq; 997 video_set_drvdata(&dev->vdev, dev); 998 return video_register_device(&dev->vdev, VFL_TYPE_GRABBER, video_nr); 999 } 1000 1001 /* 1002 * tw68_irq_video_done 1003 */ 1004 void tw68_irq_video_done(struct tw68_dev *dev, unsigned long status) 1005 { 1006 __u32 reg; 1007 1008 /* reset interrupts handled by this routine */ 1009 tw_writel(TW68_INTSTAT, status); 1010 /* 1011 * Check most likely first 1012 * 1013 * DMAPI shows we have reached the end of the risc code 1014 * for the current buffer. 1015 */ 1016 if (status & TW68_DMAPI) { 1017 struct tw68_buf *buf; 1018 1019 spin_lock(&dev->slock); 1020 buf = list_entry(dev->active.next, struct tw68_buf, list); 1021 list_del(&buf->list); 1022 spin_unlock(&dev->slock); 1023 v4l2_get_timestamp(&buf->vb.v4l2_buf.timestamp); 1024 buf->vb.v4l2_buf.field = dev->field; 1025 buf->vb.v4l2_buf.sequence = dev->seqnr++; 1026 vb2_buffer_done(&buf->vb, VB2_BUF_STATE_DONE); 1027 status &= ~(TW68_DMAPI); 1028 if (0 == status) 1029 return; 1030 } 1031 if (status & (TW68_VLOCK | TW68_HLOCK)) 1032 dev_dbg(&dev->pci->dev, "Lost sync\n"); 1033 if (status & TW68_PABORT) 1034 dev_err(&dev->pci->dev, "PABORT interrupt\n"); 1035 if (status & TW68_DMAPERR) 1036 dev_err(&dev->pci->dev, "DMAPERR interrupt\n"); 1037 /* 1038 * On TW6800, FDMIS is apparently generated if video input is switched 1039 * during operation. Therefore, it is not enabled for that chip. 1040 */ 1041 if (status & TW68_FDMIS) 1042 dev_dbg(&dev->pci->dev, "FDMIS interrupt\n"); 1043 if (status & TW68_FFOF) { 1044 /* probably a logic error */ 1045 reg = tw_readl(TW68_DMAC) & TW68_FIFO_EN; 1046 tw_clearl(TW68_DMAC, TW68_FIFO_EN); 1047 dev_dbg(&dev->pci->dev, "FFOF interrupt\n"); 1048 tw_setl(TW68_DMAC, reg); 1049 } 1050 if (status & TW68_FFERR) 1051 dev_dbg(&dev->pci->dev, "FFERR interrupt\n"); 1052 } 1053