1 /* 2 * budget-ci.c: driver for the SAA7146 based Budget DVB cards 3 * 4 * Compiled from various sources by Michael Hunold <michael@mihu.de> 5 * 6 * msp430 IR support contributed by Jack Thomasson <jkt@Helius.COM> 7 * partially based on the Siemens DVB driver by Ralph+Marcus Metzler 8 * 9 * CI interface support (c) 2004 Andrew de Quincey <adq_dvb@lidskialf.net> 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License 13 * as published by the Free Software Foundation; either version 2 14 * of the License, or (at your option) any later version. 15 * 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * To obtain the license, point your browser to 23 * http://www.gnu.org/copyleft/gpl.html 24 * 25 * 26 * the project's page is at https://linuxtv.org 27 */ 28 29 #include <linux/module.h> 30 #include <linux/errno.h> 31 #include <linux/slab.h> 32 #include <linux/interrupt.h> 33 #include <linux/spinlock.h> 34 #include <media/rc-core.h> 35 36 #include "budget.h" 37 38 #include "dvb_ca_en50221.h" 39 #include "stv0299.h" 40 #include "stv0297.h" 41 #include "tda1004x.h" 42 #include "stb0899_drv.h" 43 #include "stb0899_reg.h" 44 #include "stb0899_cfg.h" 45 #include "stb6100.h" 46 #include "stb6100_cfg.h" 47 #include "lnbp21.h" 48 #include "bsbe1.h" 49 #include "bsru6.h" 50 #include "tda1002x.h" 51 #include "tda827x.h" 52 #include "bsbe1-d01a.h" 53 54 #define MODULE_NAME "budget_ci" 55 56 /* 57 * Regarding DEBIADDR_IR: 58 * Some CI modules hang if random addresses are read. 59 * Using address 0x4000 for the IR read means that we 60 * use the same address as for CI version, which should 61 * be a safe default. 62 */ 63 #define DEBIADDR_IR 0x4000 64 #define DEBIADDR_CICONTROL 0x0000 65 #define DEBIADDR_CIVERSION 0x4000 66 #define DEBIADDR_IO 0x1000 67 #define DEBIADDR_ATTR 0x3000 68 69 #define CICONTROL_RESET 0x01 70 #define CICONTROL_ENABLETS 0x02 71 #define CICONTROL_CAMDETECT 0x08 72 73 #define DEBICICTL 0x00420000 74 #define DEBICICAM 0x02420000 75 76 #define SLOTSTATUS_NONE 1 77 #define SLOTSTATUS_PRESENT 2 78 #define SLOTSTATUS_RESET 4 79 #define SLOTSTATUS_READY 8 80 #define SLOTSTATUS_OCCUPIED (SLOTSTATUS_PRESENT|SLOTSTATUS_RESET|SLOTSTATUS_READY) 81 82 /* RC5 device wildcard */ 83 #define IR_DEVICE_ANY 255 84 85 static int rc5_device = -1; 86 module_param(rc5_device, int, 0644); 87 MODULE_PARM_DESC(rc5_device, "only IR commands to given RC5 device (device = 0 - 31, any device = 255, default: autodetect)"); 88 89 static int ir_debug; 90 module_param(ir_debug, int, 0644); 91 MODULE_PARM_DESC(ir_debug, "enable debugging information for IR decoding"); 92 93 DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr); 94 95 struct budget_ci_ir { 96 struct rc_dev *dev; 97 struct tasklet_struct msp430_irq_tasklet; 98 char name[72]; /* 40 + 32 for (struct saa7146_dev).name */ 99 char phys[32]; 100 int rc5_device; 101 u32 ir_key; 102 bool have_command; 103 bool full_rc5; /* Outputs a full RC5 code */ 104 }; 105 106 struct budget_ci { 107 struct budget budget; 108 struct tasklet_struct ciintf_irq_tasklet; 109 int slot_status; 110 int ci_irq; 111 struct dvb_ca_en50221 ca; 112 struct budget_ci_ir ir; 113 u8 tuner_pll_address; /* used for philips_tdm1316l configs */ 114 }; 115 116 static void msp430_ir_interrupt(unsigned long data) 117 { 118 struct budget_ci *budget_ci = (struct budget_ci *) data; 119 struct rc_dev *dev = budget_ci->ir.dev; 120 u32 command = ttpci_budget_debiread(&budget_ci->budget, DEBINOSWAP, DEBIADDR_IR, 2, 1, 0) >> 8; 121 122 /* 123 * The msp430 chip can generate two different bytes, command and device 124 * 125 * type1: X1CCCCCC, C = command bits (0 - 63) 126 * type2: X0TDDDDD, D = device bits (0 - 31), T = RC5 toggle bit 127 * 128 * Each signal from the remote control can generate one or more command 129 * bytes and one or more device bytes. For the repeated bytes, the 130 * highest bit (X) is set. The first command byte is always generated 131 * before the first device byte. Other than that, no specific order 132 * seems to apply. To make life interesting, bytes can also be lost. 133 * 134 * Only when we have a command and device byte, a keypress is 135 * generated. 136 */ 137 138 if (ir_debug) 139 printk("budget_ci: received byte 0x%02x\n", command); 140 141 /* Remove repeat bit, we use every command */ 142 command = command & 0x7f; 143 144 /* Is this a RC5 command byte? */ 145 if (command & 0x40) { 146 budget_ci->ir.have_command = true; 147 budget_ci->ir.ir_key = command & 0x3f; 148 return; 149 } 150 151 /* It's a RC5 device byte */ 152 if (!budget_ci->ir.have_command) 153 return; 154 budget_ci->ir.have_command = false; 155 156 if (budget_ci->ir.rc5_device != IR_DEVICE_ANY && 157 budget_ci->ir.rc5_device != (command & 0x1f)) 158 return; 159 160 if (budget_ci->ir.full_rc5) { 161 rc_keydown(dev, RC_TYPE_RC5, 162 RC_SCANCODE_RC5(budget_ci->ir.rc5_device, budget_ci->ir.ir_key), 163 !!(command & 0x20)); 164 return; 165 } 166 167 /* FIXME: We should generate complete scancodes for all devices */ 168 rc_keydown(dev, RC_TYPE_UNKNOWN, budget_ci->ir.ir_key, !!(command & 0x20)); 169 } 170 171 static int msp430_ir_init(struct budget_ci *budget_ci) 172 { 173 struct saa7146_dev *saa = budget_ci->budget.dev; 174 struct rc_dev *dev; 175 int error; 176 177 dev = rc_allocate_device(RC_DRIVER_SCANCODE); 178 if (!dev) { 179 printk(KERN_ERR "budget_ci: IR interface initialisation failed\n"); 180 return -ENOMEM; 181 } 182 183 snprintf(budget_ci->ir.name, sizeof(budget_ci->ir.name), 184 "Budget-CI dvb ir receiver %s", saa->name); 185 snprintf(budget_ci->ir.phys, sizeof(budget_ci->ir.phys), 186 "pci-%s/ir0", pci_name(saa->pci)); 187 188 dev->driver_name = MODULE_NAME; 189 dev->input_name = budget_ci->ir.name; 190 dev->input_phys = budget_ci->ir.phys; 191 dev->input_id.bustype = BUS_PCI; 192 dev->input_id.version = 1; 193 if (saa->pci->subsystem_vendor) { 194 dev->input_id.vendor = saa->pci->subsystem_vendor; 195 dev->input_id.product = saa->pci->subsystem_device; 196 } else { 197 dev->input_id.vendor = saa->pci->vendor; 198 dev->input_id.product = saa->pci->device; 199 } 200 dev->dev.parent = &saa->pci->dev; 201 202 if (rc5_device < 0) 203 budget_ci->ir.rc5_device = IR_DEVICE_ANY; 204 else 205 budget_ci->ir.rc5_device = rc5_device; 206 207 /* Select keymap and address */ 208 switch (budget_ci->budget.dev->pci->subsystem_device) { 209 case 0x100c: 210 case 0x100f: 211 case 0x1011: 212 case 0x1012: 213 /* The hauppauge keymap is a superset of these remotes */ 214 dev->map_name = RC_MAP_HAUPPAUGE; 215 budget_ci->ir.full_rc5 = true; 216 217 if (rc5_device < 0) 218 budget_ci->ir.rc5_device = 0x1f; 219 break; 220 case 0x1010: 221 case 0x1017: 222 case 0x1019: 223 case 0x101a: 224 case 0x101b: 225 /* for the Technotrend 1500 bundled remote */ 226 dev->map_name = RC_MAP_TT_1500; 227 break; 228 default: 229 /* unknown remote */ 230 dev->map_name = RC_MAP_BUDGET_CI_OLD; 231 break; 232 } 233 if (!budget_ci->ir.full_rc5) 234 dev->scancode_mask = 0xff; 235 236 error = rc_register_device(dev); 237 if (error) { 238 printk(KERN_ERR "budget_ci: could not init driver for IR device (code %d)\n", error); 239 rc_free_device(dev); 240 return error; 241 } 242 243 budget_ci->ir.dev = dev; 244 245 tasklet_init(&budget_ci->ir.msp430_irq_tasklet, msp430_ir_interrupt, 246 (unsigned long) budget_ci); 247 248 SAA7146_IER_ENABLE(saa, MASK_06); 249 saa7146_setgpio(saa, 3, SAA7146_GPIO_IRQHI); 250 251 return 0; 252 } 253 254 static void msp430_ir_deinit(struct budget_ci *budget_ci) 255 { 256 struct saa7146_dev *saa = budget_ci->budget.dev; 257 258 SAA7146_IER_DISABLE(saa, MASK_06); 259 saa7146_setgpio(saa, 3, SAA7146_GPIO_INPUT); 260 tasklet_kill(&budget_ci->ir.msp430_irq_tasklet); 261 262 rc_unregister_device(budget_ci->ir.dev); 263 } 264 265 static int ciintf_read_attribute_mem(struct dvb_ca_en50221 *ca, int slot, int address) 266 { 267 struct budget_ci *budget_ci = (struct budget_ci *) ca->data; 268 269 if (slot != 0) 270 return -EINVAL; 271 272 return ttpci_budget_debiread(&budget_ci->budget, DEBICICAM, 273 DEBIADDR_ATTR | (address & 0xfff), 1, 1, 0); 274 } 275 276 static int ciintf_write_attribute_mem(struct dvb_ca_en50221 *ca, int slot, int address, u8 value) 277 { 278 struct budget_ci *budget_ci = (struct budget_ci *) ca->data; 279 280 if (slot != 0) 281 return -EINVAL; 282 283 return ttpci_budget_debiwrite(&budget_ci->budget, DEBICICAM, 284 DEBIADDR_ATTR | (address & 0xfff), 1, value, 1, 0); 285 } 286 287 static int ciintf_read_cam_control(struct dvb_ca_en50221 *ca, int slot, u8 address) 288 { 289 struct budget_ci *budget_ci = (struct budget_ci *) ca->data; 290 291 if (slot != 0) 292 return -EINVAL; 293 294 return ttpci_budget_debiread(&budget_ci->budget, DEBICICAM, 295 DEBIADDR_IO | (address & 3), 1, 1, 0); 296 } 297 298 static int ciintf_write_cam_control(struct dvb_ca_en50221 *ca, int slot, u8 address, u8 value) 299 { 300 struct budget_ci *budget_ci = (struct budget_ci *) ca->data; 301 302 if (slot != 0) 303 return -EINVAL; 304 305 return ttpci_budget_debiwrite(&budget_ci->budget, DEBICICAM, 306 DEBIADDR_IO | (address & 3), 1, value, 1, 0); 307 } 308 309 static int ciintf_slot_reset(struct dvb_ca_en50221 *ca, int slot) 310 { 311 struct budget_ci *budget_ci = (struct budget_ci *) ca->data; 312 struct saa7146_dev *saa = budget_ci->budget.dev; 313 314 if (slot != 0) 315 return -EINVAL; 316 317 if (budget_ci->ci_irq) { 318 // trigger on RISING edge during reset so we know when READY is re-asserted 319 saa7146_setgpio(saa, 0, SAA7146_GPIO_IRQHI); 320 } 321 budget_ci->slot_status = SLOTSTATUS_RESET; 322 ttpci_budget_debiwrite(&budget_ci->budget, DEBICICTL, DEBIADDR_CICONTROL, 1, 0, 1, 0); 323 msleep(1); 324 ttpci_budget_debiwrite(&budget_ci->budget, DEBICICTL, DEBIADDR_CICONTROL, 1, 325 CICONTROL_RESET, 1, 0); 326 327 saa7146_setgpio(saa, 1, SAA7146_GPIO_OUTHI); 328 ttpci_budget_set_video_port(saa, BUDGET_VIDEO_PORTB); 329 return 0; 330 } 331 332 static int ciintf_slot_shutdown(struct dvb_ca_en50221 *ca, int slot) 333 { 334 struct budget_ci *budget_ci = (struct budget_ci *) ca->data; 335 struct saa7146_dev *saa = budget_ci->budget.dev; 336 337 if (slot != 0) 338 return -EINVAL; 339 340 saa7146_setgpio(saa, 1, SAA7146_GPIO_OUTHI); 341 ttpci_budget_set_video_port(saa, BUDGET_VIDEO_PORTB); 342 return 0; 343 } 344 345 static int ciintf_slot_ts_enable(struct dvb_ca_en50221 *ca, int slot) 346 { 347 struct budget_ci *budget_ci = (struct budget_ci *) ca->data; 348 struct saa7146_dev *saa = budget_ci->budget.dev; 349 int tmp; 350 351 if (slot != 0) 352 return -EINVAL; 353 354 saa7146_setgpio(saa, 1, SAA7146_GPIO_OUTLO); 355 356 tmp = ttpci_budget_debiread(&budget_ci->budget, DEBICICTL, DEBIADDR_CICONTROL, 1, 1, 0); 357 ttpci_budget_debiwrite(&budget_ci->budget, DEBICICTL, DEBIADDR_CICONTROL, 1, 358 tmp | CICONTROL_ENABLETS, 1, 0); 359 360 ttpci_budget_set_video_port(saa, BUDGET_VIDEO_PORTA); 361 return 0; 362 } 363 364 static void ciintf_interrupt(unsigned long data) 365 { 366 struct budget_ci *budget_ci = (struct budget_ci *) data; 367 struct saa7146_dev *saa = budget_ci->budget.dev; 368 unsigned int flags; 369 370 // ensure we don't get spurious IRQs during initialisation 371 if (!budget_ci->budget.ci_present) 372 return; 373 374 // read the CAM status 375 flags = ttpci_budget_debiread(&budget_ci->budget, DEBICICTL, DEBIADDR_CICONTROL, 1, 1, 0); 376 if (flags & CICONTROL_CAMDETECT) { 377 378 // GPIO should be set to trigger on falling edge if a CAM is present 379 saa7146_setgpio(saa, 0, SAA7146_GPIO_IRQLO); 380 381 if (budget_ci->slot_status & SLOTSTATUS_NONE) { 382 // CAM insertion IRQ 383 budget_ci->slot_status = SLOTSTATUS_PRESENT; 384 dvb_ca_en50221_camchange_irq(&budget_ci->ca, 0, 385 DVB_CA_EN50221_CAMCHANGE_INSERTED); 386 387 } else if (budget_ci->slot_status & SLOTSTATUS_RESET) { 388 // CAM ready (reset completed) 389 budget_ci->slot_status = SLOTSTATUS_READY; 390 dvb_ca_en50221_camready_irq(&budget_ci->ca, 0); 391 392 } else if (budget_ci->slot_status & SLOTSTATUS_READY) { 393 // FR/DA IRQ 394 dvb_ca_en50221_frda_irq(&budget_ci->ca, 0); 395 } 396 } else { 397 398 // trigger on rising edge if a CAM is not present - when a CAM is inserted, we 399 // only want to get the IRQ when it sets READY. If we trigger on the falling edge, 400 // the CAM might not actually be ready yet. 401 saa7146_setgpio(saa, 0, SAA7146_GPIO_IRQHI); 402 403 // generate a CAM removal IRQ if we haven't already 404 if (budget_ci->slot_status & SLOTSTATUS_OCCUPIED) { 405 // CAM removal IRQ 406 budget_ci->slot_status = SLOTSTATUS_NONE; 407 dvb_ca_en50221_camchange_irq(&budget_ci->ca, 0, 408 DVB_CA_EN50221_CAMCHANGE_REMOVED); 409 } 410 } 411 } 412 413 static int ciintf_poll_slot_status(struct dvb_ca_en50221 *ca, int slot, int open) 414 { 415 struct budget_ci *budget_ci = (struct budget_ci *) ca->data; 416 unsigned int flags; 417 418 // ensure we don't get spurious IRQs during initialisation 419 if (!budget_ci->budget.ci_present) 420 return -EINVAL; 421 422 // read the CAM status 423 flags = ttpci_budget_debiread(&budget_ci->budget, DEBICICTL, DEBIADDR_CICONTROL, 1, 1, 0); 424 if (flags & CICONTROL_CAMDETECT) { 425 // mark it as present if it wasn't before 426 if (budget_ci->slot_status & SLOTSTATUS_NONE) { 427 budget_ci->slot_status = SLOTSTATUS_PRESENT; 428 } 429 430 // during a RESET, we check if we can read from IO memory to see when CAM is ready 431 if (budget_ci->slot_status & SLOTSTATUS_RESET) { 432 if (ciintf_read_attribute_mem(ca, slot, 0) == 0x1d) { 433 budget_ci->slot_status = SLOTSTATUS_READY; 434 } 435 } 436 } else { 437 budget_ci->slot_status = SLOTSTATUS_NONE; 438 } 439 440 if (budget_ci->slot_status != SLOTSTATUS_NONE) { 441 if (budget_ci->slot_status & SLOTSTATUS_READY) { 442 return DVB_CA_EN50221_POLL_CAM_PRESENT | DVB_CA_EN50221_POLL_CAM_READY; 443 } 444 return DVB_CA_EN50221_POLL_CAM_PRESENT; 445 } 446 447 return 0; 448 } 449 450 static int ciintf_init(struct budget_ci *budget_ci) 451 { 452 struct saa7146_dev *saa = budget_ci->budget.dev; 453 int flags; 454 int result; 455 int ci_version; 456 int ca_flags; 457 458 memset(&budget_ci->ca, 0, sizeof(struct dvb_ca_en50221)); 459 460 // enable DEBI pins 461 saa7146_write(saa, MC1, MASK_27 | MASK_11); 462 463 // test if it is there 464 ci_version = ttpci_budget_debiread(&budget_ci->budget, DEBICICTL, DEBIADDR_CIVERSION, 1, 1, 0); 465 if ((ci_version & 0xa0) != 0xa0) { 466 result = -ENODEV; 467 goto error; 468 } 469 470 // determine whether a CAM is present or not 471 flags = ttpci_budget_debiread(&budget_ci->budget, DEBICICTL, DEBIADDR_CICONTROL, 1, 1, 0); 472 budget_ci->slot_status = SLOTSTATUS_NONE; 473 if (flags & CICONTROL_CAMDETECT) 474 budget_ci->slot_status = SLOTSTATUS_PRESENT; 475 476 // version 0xa2 of the CI firmware doesn't generate interrupts 477 if (ci_version == 0xa2) { 478 ca_flags = 0; 479 budget_ci->ci_irq = 0; 480 } else { 481 ca_flags = DVB_CA_EN50221_FLAG_IRQ_CAMCHANGE | 482 DVB_CA_EN50221_FLAG_IRQ_FR | 483 DVB_CA_EN50221_FLAG_IRQ_DA; 484 budget_ci->ci_irq = 1; 485 } 486 487 // register CI interface 488 budget_ci->ca.owner = THIS_MODULE; 489 budget_ci->ca.read_attribute_mem = ciintf_read_attribute_mem; 490 budget_ci->ca.write_attribute_mem = ciintf_write_attribute_mem; 491 budget_ci->ca.read_cam_control = ciintf_read_cam_control; 492 budget_ci->ca.write_cam_control = ciintf_write_cam_control; 493 budget_ci->ca.slot_reset = ciintf_slot_reset; 494 budget_ci->ca.slot_shutdown = ciintf_slot_shutdown; 495 budget_ci->ca.slot_ts_enable = ciintf_slot_ts_enable; 496 budget_ci->ca.poll_slot_status = ciintf_poll_slot_status; 497 budget_ci->ca.data = budget_ci; 498 if ((result = dvb_ca_en50221_init(&budget_ci->budget.dvb_adapter, 499 &budget_ci->ca, 500 ca_flags, 1)) != 0) { 501 printk("budget_ci: CI interface detected, but initialisation failed.\n"); 502 goto error; 503 } 504 505 // Setup CI slot IRQ 506 if (budget_ci->ci_irq) { 507 tasklet_init(&budget_ci->ciintf_irq_tasklet, ciintf_interrupt, (unsigned long) budget_ci); 508 if (budget_ci->slot_status != SLOTSTATUS_NONE) { 509 saa7146_setgpio(saa, 0, SAA7146_GPIO_IRQLO); 510 } else { 511 saa7146_setgpio(saa, 0, SAA7146_GPIO_IRQHI); 512 } 513 SAA7146_IER_ENABLE(saa, MASK_03); 514 } 515 516 // enable interface 517 ttpci_budget_debiwrite(&budget_ci->budget, DEBICICTL, DEBIADDR_CICONTROL, 1, 518 CICONTROL_RESET, 1, 0); 519 520 // success! 521 printk("budget_ci: CI interface initialised\n"); 522 budget_ci->budget.ci_present = 1; 523 524 // forge a fake CI IRQ so the CAM state is setup correctly 525 if (budget_ci->ci_irq) { 526 flags = DVB_CA_EN50221_CAMCHANGE_REMOVED; 527 if (budget_ci->slot_status != SLOTSTATUS_NONE) 528 flags = DVB_CA_EN50221_CAMCHANGE_INSERTED; 529 dvb_ca_en50221_camchange_irq(&budget_ci->ca, 0, flags); 530 } 531 532 return 0; 533 534 error: 535 saa7146_write(saa, MC1, MASK_27); 536 return result; 537 } 538 539 static void ciintf_deinit(struct budget_ci *budget_ci) 540 { 541 struct saa7146_dev *saa = budget_ci->budget.dev; 542 543 // disable CI interrupts 544 if (budget_ci->ci_irq) { 545 SAA7146_IER_DISABLE(saa, MASK_03); 546 saa7146_setgpio(saa, 0, SAA7146_GPIO_INPUT); 547 tasklet_kill(&budget_ci->ciintf_irq_tasklet); 548 } 549 550 // reset interface 551 ttpci_budget_debiwrite(&budget_ci->budget, DEBICICTL, DEBIADDR_CICONTROL, 1, 0, 1, 0); 552 msleep(1); 553 ttpci_budget_debiwrite(&budget_ci->budget, DEBICICTL, DEBIADDR_CICONTROL, 1, 554 CICONTROL_RESET, 1, 0); 555 556 // disable TS data stream to CI interface 557 saa7146_setgpio(saa, 1, SAA7146_GPIO_INPUT); 558 559 // release the CA device 560 dvb_ca_en50221_release(&budget_ci->ca); 561 562 // disable DEBI pins 563 saa7146_write(saa, MC1, MASK_27); 564 } 565 566 static void budget_ci_irq(struct saa7146_dev *dev, u32 * isr) 567 { 568 struct budget_ci *budget_ci = (struct budget_ci *) dev->ext_priv; 569 570 dprintk(8, "dev: %p, budget_ci: %p\n", dev, budget_ci); 571 572 if (*isr & MASK_06) 573 tasklet_schedule(&budget_ci->ir.msp430_irq_tasklet); 574 575 if (*isr & MASK_10) 576 ttpci_budget_irq10_handler(dev, isr); 577 578 if ((*isr & MASK_03) && (budget_ci->budget.ci_present) && (budget_ci->ci_irq)) 579 tasklet_schedule(&budget_ci->ciintf_irq_tasklet); 580 } 581 582 static u8 philips_su1278_tt_inittab[] = { 583 0x01, 0x0f, 584 0x02, 0x30, 585 0x03, 0x00, 586 0x04, 0x5b, 587 0x05, 0x85, 588 0x06, 0x02, 589 0x07, 0x00, 590 0x08, 0x02, 591 0x09, 0x00, 592 0x0C, 0x01, 593 0x0D, 0x81, 594 0x0E, 0x44, 595 0x0f, 0x14, 596 0x10, 0x3c, 597 0x11, 0x84, 598 0x12, 0xda, 599 0x13, 0x97, 600 0x14, 0x95, 601 0x15, 0xc9, 602 0x16, 0x19, 603 0x17, 0x8c, 604 0x18, 0x59, 605 0x19, 0xf8, 606 0x1a, 0xfe, 607 0x1c, 0x7f, 608 0x1d, 0x00, 609 0x1e, 0x00, 610 0x1f, 0x50, 611 0x20, 0x00, 612 0x21, 0x00, 613 0x22, 0x00, 614 0x23, 0x00, 615 0x28, 0x00, 616 0x29, 0x28, 617 0x2a, 0x14, 618 0x2b, 0x0f, 619 0x2c, 0x09, 620 0x2d, 0x09, 621 0x31, 0x1f, 622 0x32, 0x19, 623 0x33, 0xfc, 624 0x34, 0x93, 625 0xff, 0xff 626 }; 627 628 static int philips_su1278_tt_set_symbol_rate(struct dvb_frontend *fe, u32 srate, u32 ratio) 629 { 630 stv0299_writereg(fe, 0x0e, 0x44); 631 if (srate >= 10000000) { 632 stv0299_writereg(fe, 0x13, 0x97); 633 stv0299_writereg(fe, 0x14, 0x95); 634 stv0299_writereg(fe, 0x15, 0xc9); 635 stv0299_writereg(fe, 0x17, 0x8c); 636 stv0299_writereg(fe, 0x1a, 0xfe); 637 stv0299_writereg(fe, 0x1c, 0x7f); 638 stv0299_writereg(fe, 0x2d, 0x09); 639 } else { 640 stv0299_writereg(fe, 0x13, 0x99); 641 stv0299_writereg(fe, 0x14, 0x8d); 642 stv0299_writereg(fe, 0x15, 0xce); 643 stv0299_writereg(fe, 0x17, 0x43); 644 stv0299_writereg(fe, 0x1a, 0x1d); 645 stv0299_writereg(fe, 0x1c, 0x12); 646 stv0299_writereg(fe, 0x2d, 0x05); 647 } 648 stv0299_writereg(fe, 0x0e, 0x23); 649 stv0299_writereg(fe, 0x0f, 0x94); 650 stv0299_writereg(fe, 0x10, 0x39); 651 stv0299_writereg(fe, 0x15, 0xc9); 652 653 stv0299_writereg(fe, 0x1f, (ratio >> 16) & 0xff); 654 stv0299_writereg(fe, 0x20, (ratio >> 8) & 0xff); 655 stv0299_writereg(fe, 0x21, (ratio) & 0xf0); 656 657 return 0; 658 } 659 660 static int philips_su1278_tt_tuner_set_params(struct dvb_frontend *fe) 661 { 662 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 663 struct budget_ci *budget_ci = (struct budget_ci *) fe->dvb->priv; 664 u32 div; 665 u8 buf[4]; 666 struct i2c_msg msg = {.addr = 0x60,.flags = 0,.buf = buf,.len = sizeof(buf) }; 667 668 if ((p->frequency < 950000) || (p->frequency > 2150000)) 669 return -EINVAL; 670 671 div = (p->frequency + (500 - 1)) / 500; /* round correctly */ 672 buf[0] = (div >> 8) & 0x7f; 673 buf[1] = div & 0xff; 674 buf[2] = 0x80 | ((div & 0x18000) >> 10) | 2; 675 buf[3] = 0x20; 676 677 if (p->symbol_rate < 4000000) 678 buf[3] |= 1; 679 680 if (p->frequency < 1250000) 681 buf[3] |= 0; 682 else if (p->frequency < 1550000) 683 buf[3] |= 0x40; 684 else if (p->frequency < 2050000) 685 buf[3] |= 0x80; 686 else if (p->frequency < 2150000) 687 buf[3] |= 0xC0; 688 689 if (fe->ops.i2c_gate_ctrl) 690 fe->ops.i2c_gate_ctrl(fe, 1); 691 if (i2c_transfer(&budget_ci->budget.i2c_adap, &msg, 1) != 1) 692 return -EIO; 693 return 0; 694 } 695 696 static const struct stv0299_config philips_su1278_tt_config = { 697 698 .demod_address = 0x68, 699 .inittab = philips_su1278_tt_inittab, 700 .mclk = 64000000UL, 701 .invert = 0, 702 .skip_reinit = 1, 703 .lock_output = STV0299_LOCKOUTPUT_1, 704 .volt13_op0_op1 = STV0299_VOLT13_OP1, 705 .min_delay_ms = 50, 706 .set_symbol_rate = philips_su1278_tt_set_symbol_rate, 707 }; 708 709 710 711 static int philips_tdm1316l_tuner_init(struct dvb_frontend *fe) 712 { 713 struct budget_ci *budget_ci = (struct budget_ci *) fe->dvb->priv; 714 static u8 td1316_init[] = { 0x0b, 0xf5, 0x85, 0xab }; 715 static u8 disable_mc44BC374c[] = { 0x1d, 0x74, 0xa0, 0x68 }; 716 struct i2c_msg tuner_msg = {.addr = budget_ci->tuner_pll_address,.flags = 0,.buf = td1316_init,.len = 717 sizeof(td1316_init) }; 718 719 // setup PLL configuration 720 if (fe->ops.i2c_gate_ctrl) 721 fe->ops.i2c_gate_ctrl(fe, 1); 722 if (i2c_transfer(&budget_ci->budget.i2c_adap, &tuner_msg, 1) != 1) 723 return -EIO; 724 msleep(1); 725 726 // disable the mc44BC374c (do not check for errors) 727 tuner_msg.addr = 0x65; 728 tuner_msg.buf = disable_mc44BC374c; 729 tuner_msg.len = sizeof(disable_mc44BC374c); 730 if (fe->ops.i2c_gate_ctrl) 731 fe->ops.i2c_gate_ctrl(fe, 1); 732 if (i2c_transfer(&budget_ci->budget.i2c_adap, &tuner_msg, 1) != 1) { 733 if (fe->ops.i2c_gate_ctrl) 734 fe->ops.i2c_gate_ctrl(fe, 1); 735 i2c_transfer(&budget_ci->budget.i2c_adap, &tuner_msg, 1); 736 } 737 738 return 0; 739 } 740 741 static int philips_tdm1316l_tuner_set_params(struct dvb_frontend *fe) 742 { 743 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 744 struct budget_ci *budget_ci = (struct budget_ci *) fe->dvb->priv; 745 u8 tuner_buf[4]; 746 struct i2c_msg tuner_msg = {.addr = budget_ci->tuner_pll_address,.flags = 0,.buf = tuner_buf,.len = sizeof(tuner_buf) }; 747 int tuner_frequency = 0; 748 u8 band, cp, filter; 749 750 // determine charge pump 751 tuner_frequency = p->frequency + 36130000; 752 if (tuner_frequency < 87000000) 753 return -EINVAL; 754 else if (tuner_frequency < 130000000) 755 cp = 3; 756 else if (tuner_frequency < 160000000) 757 cp = 5; 758 else if (tuner_frequency < 200000000) 759 cp = 6; 760 else if (tuner_frequency < 290000000) 761 cp = 3; 762 else if (tuner_frequency < 420000000) 763 cp = 5; 764 else if (tuner_frequency < 480000000) 765 cp = 6; 766 else if (tuner_frequency < 620000000) 767 cp = 3; 768 else if (tuner_frequency < 830000000) 769 cp = 5; 770 else if (tuner_frequency < 895000000) 771 cp = 7; 772 else 773 return -EINVAL; 774 775 // determine band 776 if (p->frequency < 49000000) 777 return -EINVAL; 778 else if (p->frequency < 159000000) 779 band = 1; 780 else if (p->frequency < 444000000) 781 band = 2; 782 else if (p->frequency < 861000000) 783 band = 4; 784 else 785 return -EINVAL; 786 787 // setup PLL filter and TDA9889 788 switch (p->bandwidth_hz) { 789 case 6000000: 790 tda1004x_writereg(fe, 0x0C, 0x14); 791 filter = 0; 792 break; 793 794 case 7000000: 795 tda1004x_writereg(fe, 0x0C, 0x80); 796 filter = 0; 797 break; 798 799 case 8000000: 800 tda1004x_writereg(fe, 0x0C, 0x14); 801 filter = 1; 802 break; 803 804 default: 805 return -EINVAL; 806 } 807 808 // calculate divisor 809 // ((36130000+((1000000/6)/2)) + Finput)/(1000000/6) 810 tuner_frequency = (((p->frequency / 1000) * 6) + 217280) / 1000; 811 812 // setup tuner buffer 813 tuner_buf[0] = tuner_frequency >> 8; 814 tuner_buf[1] = tuner_frequency & 0xff; 815 tuner_buf[2] = 0xca; 816 tuner_buf[3] = (cp << 5) | (filter << 3) | band; 817 818 if (fe->ops.i2c_gate_ctrl) 819 fe->ops.i2c_gate_ctrl(fe, 1); 820 if (i2c_transfer(&budget_ci->budget.i2c_adap, &tuner_msg, 1) != 1) 821 return -EIO; 822 823 msleep(1); 824 return 0; 825 } 826 827 static int philips_tdm1316l_request_firmware(struct dvb_frontend *fe, 828 const struct firmware **fw, char *name) 829 { 830 struct budget_ci *budget_ci = (struct budget_ci *) fe->dvb->priv; 831 832 return request_firmware(fw, name, &budget_ci->budget.dev->pci->dev); 833 } 834 835 static struct tda1004x_config philips_tdm1316l_config = { 836 837 .demod_address = 0x8, 838 .invert = 0, 839 .invert_oclk = 0, 840 .xtal_freq = TDA10046_XTAL_4M, 841 .agc_config = TDA10046_AGC_DEFAULT, 842 .if_freq = TDA10046_FREQ_3617, 843 .request_firmware = philips_tdm1316l_request_firmware, 844 }; 845 846 static struct tda1004x_config philips_tdm1316l_config_invert = { 847 848 .demod_address = 0x8, 849 .invert = 1, 850 .invert_oclk = 0, 851 .xtal_freq = TDA10046_XTAL_4M, 852 .agc_config = TDA10046_AGC_DEFAULT, 853 .if_freq = TDA10046_FREQ_3617, 854 .request_firmware = philips_tdm1316l_request_firmware, 855 }; 856 857 static int dvbc_philips_tdm1316l_tuner_set_params(struct dvb_frontend *fe) 858 { 859 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 860 struct budget_ci *budget_ci = (struct budget_ci *) fe->dvb->priv; 861 u8 tuner_buf[5]; 862 struct i2c_msg tuner_msg = {.addr = budget_ci->tuner_pll_address, 863 .flags = 0, 864 .buf = tuner_buf, 865 .len = sizeof(tuner_buf) }; 866 int tuner_frequency = 0; 867 u8 band, cp, filter; 868 869 // determine charge pump 870 tuner_frequency = p->frequency + 36125000; 871 if (tuner_frequency < 87000000) 872 return -EINVAL; 873 else if (tuner_frequency < 130000000) { 874 cp = 3; 875 band = 1; 876 } else if (tuner_frequency < 160000000) { 877 cp = 5; 878 band = 1; 879 } else if (tuner_frequency < 200000000) { 880 cp = 6; 881 band = 1; 882 } else if (tuner_frequency < 290000000) { 883 cp = 3; 884 band = 2; 885 } else if (tuner_frequency < 420000000) { 886 cp = 5; 887 band = 2; 888 } else if (tuner_frequency < 480000000) { 889 cp = 6; 890 band = 2; 891 } else if (tuner_frequency < 620000000) { 892 cp = 3; 893 band = 4; 894 } else if (tuner_frequency < 830000000) { 895 cp = 5; 896 band = 4; 897 } else if (tuner_frequency < 895000000) { 898 cp = 7; 899 band = 4; 900 } else 901 return -EINVAL; 902 903 // assume PLL filter should always be 8MHz for the moment. 904 filter = 1; 905 906 // calculate divisor 907 tuner_frequency = (p->frequency + 36125000 + (62500/2)) / 62500; 908 909 // setup tuner buffer 910 tuner_buf[0] = tuner_frequency >> 8; 911 tuner_buf[1] = tuner_frequency & 0xff; 912 tuner_buf[2] = 0xc8; 913 tuner_buf[3] = (cp << 5) | (filter << 3) | band; 914 tuner_buf[4] = 0x80; 915 916 if (fe->ops.i2c_gate_ctrl) 917 fe->ops.i2c_gate_ctrl(fe, 1); 918 if (i2c_transfer(&budget_ci->budget.i2c_adap, &tuner_msg, 1) != 1) 919 return -EIO; 920 921 msleep(50); 922 923 if (fe->ops.i2c_gate_ctrl) 924 fe->ops.i2c_gate_ctrl(fe, 1); 925 if (i2c_transfer(&budget_ci->budget.i2c_adap, &tuner_msg, 1) != 1) 926 return -EIO; 927 928 msleep(1); 929 930 return 0; 931 } 932 933 static u8 dvbc_philips_tdm1316l_inittab[] = { 934 0x80, 0x01, 935 0x80, 0x00, 936 0x81, 0x01, 937 0x81, 0x00, 938 0x00, 0x09, 939 0x01, 0x69, 940 0x03, 0x00, 941 0x04, 0x00, 942 0x07, 0x00, 943 0x08, 0x00, 944 0x20, 0x00, 945 0x21, 0x40, 946 0x22, 0x00, 947 0x23, 0x00, 948 0x24, 0x40, 949 0x25, 0x88, 950 0x30, 0xff, 951 0x31, 0x00, 952 0x32, 0xff, 953 0x33, 0x00, 954 0x34, 0x50, 955 0x35, 0x7f, 956 0x36, 0x00, 957 0x37, 0x20, 958 0x38, 0x00, 959 0x40, 0x1c, 960 0x41, 0xff, 961 0x42, 0x29, 962 0x43, 0x20, 963 0x44, 0xff, 964 0x45, 0x00, 965 0x46, 0x00, 966 0x49, 0x04, 967 0x4a, 0x00, 968 0x4b, 0x7b, 969 0x52, 0x30, 970 0x55, 0xae, 971 0x56, 0x47, 972 0x57, 0xe1, 973 0x58, 0x3a, 974 0x5a, 0x1e, 975 0x5b, 0x34, 976 0x60, 0x00, 977 0x63, 0x00, 978 0x64, 0x00, 979 0x65, 0x00, 980 0x66, 0x00, 981 0x67, 0x00, 982 0x68, 0x00, 983 0x69, 0x00, 984 0x6a, 0x02, 985 0x6b, 0x00, 986 0x70, 0xff, 987 0x71, 0x00, 988 0x72, 0x00, 989 0x73, 0x00, 990 0x74, 0x0c, 991 0x80, 0x00, 992 0x81, 0x00, 993 0x82, 0x00, 994 0x83, 0x00, 995 0x84, 0x04, 996 0x85, 0x80, 997 0x86, 0x24, 998 0x87, 0x78, 999 0x88, 0x10, 1000 0x89, 0x00, 1001 0x90, 0x01, 1002 0x91, 0x01, 1003 0xa0, 0x04, 1004 0xa1, 0x00, 1005 0xa2, 0x00, 1006 0xb0, 0x91, 1007 0xb1, 0x0b, 1008 0xc0, 0x53, 1009 0xc1, 0x70, 1010 0xc2, 0x12, 1011 0xd0, 0x00, 1012 0xd1, 0x00, 1013 0xd2, 0x00, 1014 0xd3, 0x00, 1015 0xd4, 0x00, 1016 0xd5, 0x00, 1017 0xde, 0x00, 1018 0xdf, 0x00, 1019 0x61, 0x38, 1020 0x62, 0x0a, 1021 0x53, 0x13, 1022 0x59, 0x08, 1023 0xff, 0xff, 1024 }; 1025 1026 static struct stv0297_config dvbc_philips_tdm1316l_config = { 1027 .demod_address = 0x1c, 1028 .inittab = dvbc_philips_tdm1316l_inittab, 1029 .invert = 0, 1030 .stop_during_read = 1, 1031 }; 1032 1033 static struct tda10023_config tda10023_config = { 1034 .demod_address = 0xc, 1035 .invert = 0, 1036 .xtal = 16000000, 1037 .pll_m = 11, 1038 .pll_p = 3, 1039 .pll_n = 1, 1040 .deltaf = 0xa511, 1041 }; 1042 1043 static struct tda827x_config tda827x_config = { 1044 .config = 0, 1045 }; 1046 1047 /* TT S2-3200 DVB-S (STB0899) Inittab */ 1048 static const struct stb0899_s1_reg tt3200_stb0899_s1_init_1[] = { 1049 1050 { STB0899_DEV_ID , 0x81 }, 1051 { STB0899_DISCNTRL1 , 0x32 }, 1052 { STB0899_DISCNTRL2 , 0x80 }, 1053 { STB0899_DISRX_ST0 , 0x04 }, 1054 { STB0899_DISRX_ST1 , 0x00 }, 1055 { STB0899_DISPARITY , 0x00 }, 1056 { STB0899_DISSTATUS , 0x20 }, 1057 { STB0899_DISF22 , 0x8c }, 1058 { STB0899_DISF22RX , 0x9a }, 1059 { STB0899_SYSREG , 0x0b }, 1060 { STB0899_ACRPRESC , 0x11 }, 1061 { STB0899_ACRDIV1 , 0x0a }, 1062 { STB0899_ACRDIV2 , 0x05 }, 1063 { STB0899_DACR1 , 0x00 }, 1064 { STB0899_DACR2 , 0x00 }, 1065 { STB0899_OUTCFG , 0x00 }, 1066 { STB0899_MODECFG , 0x00 }, 1067 { STB0899_IRQSTATUS_3 , 0x30 }, 1068 { STB0899_IRQSTATUS_2 , 0x00 }, 1069 { STB0899_IRQSTATUS_1 , 0x00 }, 1070 { STB0899_IRQSTATUS_0 , 0x00 }, 1071 { STB0899_IRQMSK_3 , 0xf3 }, 1072 { STB0899_IRQMSK_2 , 0xfc }, 1073 { STB0899_IRQMSK_1 , 0xff }, 1074 { STB0899_IRQMSK_0 , 0xff }, 1075 { STB0899_IRQCFG , 0x00 }, 1076 { STB0899_I2CCFG , 0x88 }, 1077 { STB0899_I2CRPT , 0x48 }, /* 12k Pullup, Repeater=16, Stop=disabled */ 1078 { STB0899_IOPVALUE5 , 0x00 }, 1079 { STB0899_IOPVALUE4 , 0x20 }, 1080 { STB0899_IOPVALUE3 , 0xc9 }, 1081 { STB0899_IOPVALUE2 , 0x90 }, 1082 { STB0899_IOPVALUE1 , 0x40 }, 1083 { STB0899_IOPVALUE0 , 0x00 }, 1084 { STB0899_GPIO00CFG , 0x82 }, 1085 { STB0899_GPIO01CFG , 0x82 }, 1086 { STB0899_GPIO02CFG , 0x82 }, 1087 { STB0899_GPIO03CFG , 0x82 }, 1088 { STB0899_GPIO04CFG , 0x82 }, 1089 { STB0899_GPIO05CFG , 0x82 }, 1090 { STB0899_GPIO06CFG , 0x82 }, 1091 { STB0899_GPIO07CFG , 0x82 }, 1092 { STB0899_GPIO08CFG , 0x82 }, 1093 { STB0899_GPIO09CFG , 0x82 }, 1094 { STB0899_GPIO10CFG , 0x82 }, 1095 { STB0899_GPIO11CFG , 0x82 }, 1096 { STB0899_GPIO12CFG , 0x82 }, 1097 { STB0899_GPIO13CFG , 0x82 }, 1098 { STB0899_GPIO14CFG , 0x82 }, 1099 { STB0899_GPIO15CFG , 0x82 }, 1100 { STB0899_GPIO16CFG , 0x82 }, 1101 { STB0899_GPIO17CFG , 0x82 }, 1102 { STB0899_GPIO18CFG , 0x82 }, 1103 { STB0899_GPIO19CFG , 0x82 }, 1104 { STB0899_GPIO20CFG , 0x82 }, 1105 { STB0899_SDATCFG , 0xb8 }, 1106 { STB0899_SCLTCFG , 0xba }, 1107 { STB0899_AGCRFCFG , 0x1c }, /* 0x11 */ 1108 { STB0899_GPIO22 , 0x82 }, /* AGCBB2CFG */ 1109 { STB0899_GPIO21 , 0x91 }, /* AGCBB1CFG */ 1110 { STB0899_DIRCLKCFG , 0x82 }, 1111 { STB0899_CLKOUT27CFG , 0x7e }, 1112 { STB0899_STDBYCFG , 0x82 }, 1113 { STB0899_CS0CFG , 0x82 }, 1114 { STB0899_CS1CFG , 0x82 }, 1115 { STB0899_DISEQCOCFG , 0x20 }, 1116 { STB0899_GPIO32CFG , 0x82 }, 1117 { STB0899_GPIO33CFG , 0x82 }, 1118 { STB0899_GPIO34CFG , 0x82 }, 1119 { STB0899_GPIO35CFG , 0x82 }, 1120 { STB0899_GPIO36CFG , 0x82 }, 1121 { STB0899_GPIO37CFG , 0x82 }, 1122 { STB0899_GPIO38CFG , 0x82 }, 1123 { STB0899_GPIO39CFG , 0x82 }, 1124 { STB0899_NCOARSE , 0x15 }, /* 0x15 = 27 Mhz Clock, F/3 = 198MHz, F/6 = 99MHz */ 1125 { STB0899_SYNTCTRL , 0x02 }, /* 0x00 = CLK from CLKI, 0x02 = CLK from XTALI */ 1126 { STB0899_FILTCTRL , 0x00 }, 1127 { STB0899_SYSCTRL , 0x00 }, 1128 { STB0899_STOPCLK1 , 0x20 }, 1129 { STB0899_STOPCLK2 , 0x00 }, 1130 { STB0899_INTBUFSTATUS , 0x00 }, 1131 { STB0899_INTBUFCTRL , 0x0a }, 1132 { 0xffff , 0xff }, 1133 }; 1134 1135 static const struct stb0899_s1_reg tt3200_stb0899_s1_init_3[] = { 1136 { STB0899_DEMOD , 0x00 }, 1137 { STB0899_RCOMPC , 0xc9 }, 1138 { STB0899_AGC1CN , 0x41 }, 1139 { STB0899_AGC1REF , 0x10 }, 1140 { STB0899_RTC , 0x7a }, 1141 { STB0899_TMGCFG , 0x4e }, 1142 { STB0899_AGC2REF , 0x34 }, 1143 { STB0899_TLSR , 0x84 }, 1144 { STB0899_CFD , 0xc7 }, 1145 { STB0899_ACLC , 0x87 }, 1146 { STB0899_BCLC , 0x94 }, 1147 { STB0899_EQON , 0x41 }, 1148 { STB0899_LDT , 0xdd }, 1149 { STB0899_LDT2 , 0xc9 }, 1150 { STB0899_EQUALREF , 0xb4 }, 1151 { STB0899_TMGRAMP , 0x10 }, 1152 { STB0899_TMGTHD , 0x30 }, 1153 { STB0899_IDCCOMP , 0xfb }, 1154 { STB0899_QDCCOMP , 0x03 }, 1155 { STB0899_POWERI , 0x3b }, 1156 { STB0899_POWERQ , 0x3d }, 1157 { STB0899_RCOMP , 0x81 }, 1158 { STB0899_AGCIQIN , 0x80 }, 1159 { STB0899_AGC2I1 , 0x04 }, 1160 { STB0899_AGC2I2 , 0xf5 }, 1161 { STB0899_TLIR , 0x25 }, 1162 { STB0899_RTF , 0x80 }, 1163 { STB0899_DSTATUS , 0x00 }, 1164 { STB0899_LDI , 0xca }, 1165 { STB0899_CFRM , 0xf1 }, 1166 { STB0899_CFRL , 0xf3 }, 1167 { STB0899_NIRM , 0x2a }, 1168 { STB0899_NIRL , 0x05 }, 1169 { STB0899_ISYMB , 0x17 }, 1170 { STB0899_QSYMB , 0xfa }, 1171 { STB0899_SFRH , 0x2f }, 1172 { STB0899_SFRM , 0x68 }, 1173 { STB0899_SFRL , 0x40 }, 1174 { STB0899_SFRUPH , 0x2f }, 1175 { STB0899_SFRUPM , 0x68 }, 1176 { STB0899_SFRUPL , 0x40 }, 1177 { STB0899_EQUAI1 , 0xfd }, 1178 { STB0899_EQUAQ1 , 0x04 }, 1179 { STB0899_EQUAI2 , 0x0f }, 1180 { STB0899_EQUAQ2 , 0xff }, 1181 { STB0899_EQUAI3 , 0xdf }, 1182 { STB0899_EQUAQ3 , 0xfa }, 1183 { STB0899_EQUAI4 , 0x37 }, 1184 { STB0899_EQUAQ4 , 0x0d }, 1185 { STB0899_EQUAI5 , 0xbd }, 1186 { STB0899_EQUAQ5 , 0xf7 }, 1187 { STB0899_DSTATUS2 , 0x00 }, 1188 { STB0899_VSTATUS , 0x00 }, 1189 { STB0899_VERROR , 0xff }, 1190 { STB0899_IQSWAP , 0x2a }, 1191 { STB0899_ECNT1M , 0x00 }, 1192 { STB0899_ECNT1L , 0x00 }, 1193 { STB0899_ECNT2M , 0x00 }, 1194 { STB0899_ECNT2L , 0x00 }, 1195 { STB0899_ECNT3M , 0x00 }, 1196 { STB0899_ECNT3L , 0x00 }, 1197 { STB0899_FECAUTO1 , 0x06 }, 1198 { STB0899_FECM , 0x01 }, 1199 { STB0899_VTH12 , 0xf0 }, 1200 { STB0899_VTH23 , 0xa0 }, 1201 { STB0899_VTH34 , 0x78 }, 1202 { STB0899_VTH56 , 0x4e }, 1203 { STB0899_VTH67 , 0x48 }, 1204 { STB0899_VTH78 , 0x38 }, 1205 { STB0899_PRVIT , 0xff }, 1206 { STB0899_VITSYNC , 0x19 }, 1207 { STB0899_RSULC , 0xb1 }, /* DVB = 0xb1, DSS = 0xa1 */ 1208 { STB0899_TSULC , 0x42 }, 1209 { STB0899_RSLLC , 0x40 }, 1210 { STB0899_TSLPL , 0x12 }, 1211 { STB0899_TSCFGH , 0x0c }, 1212 { STB0899_TSCFGM , 0x00 }, 1213 { STB0899_TSCFGL , 0x0c }, 1214 { STB0899_TSOUT , 0x4d }, /* 0x0d for CAM */ 1215 { STB0899_RSSYNCDEL , 0x00 }, 1216 { STB0899_TSINHDELH , 0x02 }, 1217 { STB0899_TSINHDELM , 0x00 }, 1218 { STB0899_TSINHDELL , 0x00 }, 1219 { STB0899_TSLLSTKM , 0x00 }, 1220 { STB0899_TSLLSTKL , 0x00 }, 1221 { STB0899_TSULSTKM , 0x00 }, 1222 { STB0899_TSULSTKL , 0xab }, 1223 { STB0899_PCKLENUL , 0x00 }, 1224 { STB0899_PCKLENLL , 0xcc }, 1225 { STB0899_RSPCKLEN , 0xcc }, 1226 { STB0899_TSSTATUS , 0x80 }, 1227 { STB0899_ERRCTRL1 , 0xb6 }, 1228 { STB0899_ERRCTRL2 , 0x96 }, 1229 { STB0899_ERRCTRL3 , 0x89 }, 1230 { STB0899_DMONMSK1 , 0x27 }, 1231 { STB0899_DMONMSK0 , 0x03 }, 1232 { STB0899_DEMAPVIT , 0x5c }, 1233 { STB0899_PLPARM , 0x1f }, 1234 { STB0899_PDELCTRL , 0x48 }, 1235 { STB0899_PDELCTRL2 , 0x00 }, 1236 { STB0899_BBHCTRL1 , 0x00 }, 1237 { STB0899_BBHCTRL2 , 0x00 }, 1238 { STB0899_HYSTTHRESH , 0x77 }, 1239 { STB0899_MATCSTM , 0x00 }, 1240 { STB0899_MATCSTL , 0x00 }, 1241 { STB0899_UPLCSTM , 0x00 }, 1242 { STB0899_UPLCSTL , 0x00 }, 1243 { STB0899_DFLCSTM , 0x00 }, 1244 { STB0899_DFLCSTL , 0x00 }, 1245 { STB0899_SYNCCST , 0x00 }, 1246 { STB0899_SYNCDCSTM , 0x00 }, 1247 { STB0899_SYNCDCSTL , 0x00 }, 1248 { STB0899_ISI_ENTRY , 0x00 }, 1249 { STB0899_ISI_BIT_EN , 0x00 }, 1250 { STB0899_MATSTRM , 0x00 }, 1251 { STB0899_MATSTRL , 0x00 }, 1252 { STB0899_UPLSTRM , 0x00 }, 1253 { STB0899_UPLSTRL , 0x00 }, 1254 { STB0899_DFLSTRM , 0x00 }, 1255 { STB0899_DFLSTRL , 0x00 }, 1256 { STB0899_SYNCSTR , 0x00 }, 1257 { STB0899_SYNCDSTRM , 0x00 }, 1258 { STB0899_SYNCDSTRL , 0x00 }, 1259 { STB0899_CFGPDELSTATUS1 , 0x10 }, 1260 { STB0899_CFGPDELSTATUS2 , 0x00 }, 1261 { STB0899_BBFERRORM , 0x00 }, 1262 { STB0899_BBFERRORL , 0x00 }, 1263 { STB0899_UPKTERRORM , 0x00 }, 1264 { STB0899_UPKTERRORL , 0x00 }, 1265 { 0xffff , 0xff }, 1266 }; 1267 1268 static struct stb0899_config tt3200_config = { 1269 .init_dev = tt3200_stb0899_s1_init_1, 1270 .init_s2_demod = stb0899_s2_init_2, 1271 .init_s1_demod = tt3200_stb0899_s1_init_3, 1272 .init_s2_fec = stb0899_s2_init_4, 1273 .init_tst = stb0899_s1_init_5, 1274 1275 .postproc = NULL, 1276 1277 .demod_address = 0x68, 1278 1279 .xtal_freq = 27000000, 1280 .inversion = IQ_SWAP_ON, 1281 1282 .lo_clk = 76500000, 1283 .hi_clk = 99000000, 1284 1285 .esno_ave = STB0899_DVBS2_ESNO_AVE, 1286 .esno_quant = STB0899_DVBS2_ESNO_QUANT, 1287 .avframes_coarse = STB0899_DVBS2_AVFRAMES_COARSE, 1288 .avframes_fine = STB0899_DVBS2_AVFRAMES_FINE, 1289 .miss_threshold = STB0899_DVBS2_MISS_THRESHOLD, 1290 .uwp_threshold_acq = STB0899_DVBS2_UWP_THRESHOLD_ACQ, 1291 .uwp_threshold_track = STB0899_DVBS2_UWP_THRESHOLD_TRACK, 1292 .uwp_threshold_sof = STB0899_DVBS2_UWP_THRESHOLD_SOF, 1293 .sof_search_timeout = STB0899_DVBS2_SOF_SEARCH_TIMEOUT, 1294 1295 .btr_nco_bits = STB0899_DVBS2_BTR_NCO_BITS, 1296 .btr_gain_shift_offset = STB0899_DVBS2_BTR_GAIN_SHIFT_OFFSET, 1297 .crl_nco_bits = STB0899_DVBS2_CRL_NCO_BITS, 1298 .ldpc_max_iter = STB0899_DVBS2_LDPC_MAX_ITER, 1299 1300 .tuner_get_frequency = stb6100_get_frequency, 1301 .tuner_set_frequency = stb6100_set_frequency, 1302 .tuner_set_bandwidth = stb6100_set_bandwidth, 1303 .tuner_get_bandwidth = stb6100_get_bandwidth, 1304 .tuner_set_rfsiggain = NULL 1305 }; 1306 1307 static struct stb6100_config tt3200_stb6100_config = { 1308 .tuner_address = 0x60, 1309 .refclock = 27000000, 1310 }; 1311 1312 static void frontend_init(struct budget_ci *budget_ci) 1313 { 1314 switch (budget_ci->budget.dev->pci->subsystem_device) { 1315 case 0x100c: // Hauppauge/TT Nova-CI budget (stv0299/ALPS BSRU6(tsa5059)) 1316 budget_ci->budget.dvb_frontend = 1317 dvb_attach(stv0299_attach, &alps_bsru6_config, &budget_ci->budget.i2c_adap); 1318 if (budget_ci->budget.dvb_frontend) { 1319 budget_ci->budget.dvb_frontend->ops.tuner_ops.set_params = alps_bsru6_tuner_set_params; 1320 budget_ci->budget.dvb_frontend->tuner_priv = &budget_ci->budget.i2c_adap; 1321 break; 1322 } 1323 break; 1324 1325 case 0x100f: // Hauppauge/TT Nova-CI budget (stv0299b/Philips su1278(tsa5059)) 1326 budget_ci->budget.dvb_frontend = 1327 dvb_attach(stv0299_attach, &philips_su1278_tt_config, &budget_ci->budget.i2c_adap); 1328 if (budget_ci->budget.dvb_frontend) { 1329 budget_ci->budget.dvb_frontend->ops.tuner_ops.set_params = philips_su1278_tt_tuner_set_params; 1330 break; 1331 } 1332 break; 1333 1334 case 0x1010: // TT DVB-C CI budget (stv0297/Philips tdm1316l(tda6651tt)) 1335 budget_ci->tuner_pll_address = 0x61; 1336 budget_ci->budget.dvb_frontend = 1337 dvb_attach(stv0297_attach, &dvbc_philips_tdm1316l_config, &budget_ci->budget.i2c_adap); 1338 if (budget_ci->budget.dvb_frontend) { 1339 budget_ci->budget.dvb_frontend->ops.tuner_ops.set_params = dvbc_philips_tdm1316l_tuner_set_params; 1340 break; 1341 } 1342 break; 1343 1344 case 0x1011: // Hauppauge/TT Nova-T budget (tda10045/Philips tdm1316l(tda6651tt) + TDA9889) 1345 budget_ci->tuner_pll_address = 0x63; 1346 budget_ci->budget.dvb_frontend = 1347 dvb_attach(tda10045_attach, &philips_tdm1316l_config, &budget_ci->budget.i2c_adap); 1348 if (budget_ci->budget.dvb_frontend) { 1349 budget_ci->budget.dvb_frontend->ops.tuner_ops.init = philips_tdm1316l_tuner_init; 1350 budget_ci->budget.dvb_frontend->ops.tuner_ops.set_params = philips_tdm1316l_tuner_set_params; 1351 break; 1352 } 1353 break; 1354 1355 case 0x1012: // TT DVB-T CI budget (tda10046/Philips tdm1316l(tda6651tt)) 1356 budget_ci->tuner_pll_address = 0x60; 1357 budget_ci->budget.dvb_frontend = 1358 dvb_attach(tda10046_attach, &philips_tdm1316l_config_invert, &budget_ci->budget.i2c_adap); 1359 if (budget_ci->budget.dvb_frontend) { 1360 budget_ci->budget.dvb_frontend->ops.tuner_ops.init = philips_tdm1316l_tuner_init; 1361 budget_ci->budget.dvb_frontend->ops.tuner_ops.set_params = philips_tdm1316l_tuner_set_params; 1362 break; 1363 } 1364 break; 1365 1366 case 0x1017: // TT S-1500 PCI 1367 budget_ci->budget.dvb_frontend = dvb_attach(stv0299_attach, &alps_bsbe1_config, &budget_ci->budget.i2c_adap); 1368 if (budget_ci->budget.dvb_frontend) { 1369 budget_ci->budget.dvb_frontend->ops.tuner_ops.set_params = alps_bsbe1_tuner_set_params; 1370 budget_ci->budget.dvb_frontend->tuner_priv = &budget_ci->budget.i2c_adap; 1371 1372 budget_ci->budget.dvb_frontend->ops.dishnetwork_send_legacy_command = NULL; 1373 if (dvb_attach(lnbp21_attach, budget_ci->budget.dvb_frontend, &budget_ci->budget.i2c_adap, LNBP21_LLC, 0) == NULL) { 1374 printk("%s: No LNBP21 found!\n", __func__); 1375 dvb_frontend_detach(budget_ci->budget.dvb_frontend); 1376 budget_ci->budget.dvb_frontend = NULL; 1377 } 1378 } 1379 break; 1380 1381 case 0x101a: /* TT Budget-C-1501 (philips tda10023/philips tda8274A) */ 1382 budget_ci->budget.dvb_frontend = dvb_attach(tda10023_attach, &tda10023_config, &budget_ci->budget.i2c_adap, 0x48); 1383 if (budget_ci->budget.dvb_frontend) { 1384 if (dvb_attach(tda827x_attach, budget_ci->budget.dvb_frontend, 0x61, &budget_ci->budget.i2c_adap, &tda827x_config) == NULL) { 1385 printk(KERN_ERR "%s: No tda827x found!\n", __func__); 1386 dvb_frontend_detach(budget_ci->budget.dvb_frontend); 1387 budget_ci->budget.dvb_frontend = NULL; 1388 } 1389 } 1390 break; 1391 1392 case 0x101b: /* TT S-1500B (BSBE1-D01A - STV0288/STB6000/LNBP21) */ 1393 budget_ci->budget.dvb_frontend = dvb_attach(stv0288_attach, &stv0288_bsbe1_d01a_config, &budget_ci->budget.i2c_adap); 1394 if (budget_ci->budget.dvb_frontend) { 1395 if (dvb_attach(stb6000_attach, budget_ci->budget.dvb_frontend, 0x63, &budget_ci->budget.i2c_adap)) { 1396 if (!dvb_attach(lnbp21_attach, budget_ci->budget.dvb_frontend, &budget_ci->budget.i2c_adap, 0, 0)) { 1397 printk(KERN_ERR "%s: No LNBP21 found!\n", __func__); 1398 dvb_frontend_detach(budget_ci->budget.dvb_frontend); 1399 budget_ci->budget.dvb_frontend = NULL; 1400 } 1401 } else { 1402 printk(KERN_ERR "%s: No STB6000 found!\n", __func__); 1403 dvb_frontend_detach(budget_ci->budget.dvb_frontend); 1404 budget_ci->budget.dvb_frontend = NULL; 1405 } 1406 } 1407 break; 1408 1409 case 0x1019: // TT S2-3200 PCI 1410 /* 1411 * NOTE! on some STB0899 versions, the internal PLL takes a longer time 1412 * to settle, aka LOCK. On the older revisions of the chip, we don't see 1413 * this, as a result on the newer chips the entire clock tree, will not 1414 * be stable after a freshly POWER 'ed up situation. 1415 * In this case, we should RESET the STB0899 (Active LOW) and wait for 1416 * PLL stabilization. 1417 * 1418 * On the TT S2 3200 and clones, the STB0899 demodulator's RESETB is 1419 * connected to the SAA7146 GPIO, GPIO2, Pin 142 1420 */ 1421 /* Reset Demodulator */ 1422 saa7146_setgpio(budget_ci->budget.dev, 2, SAA7146_GPIO_OUTLO); 1423 /* Wait for everything to die */ 1424 msleep(50); 1425 /* Pull it up out of Reset state */ 1426 saa7146_setgpio(budget_ci->budget.dev, 2, SAA7146_GPIO_OUTHI); 1427 /* Wait for PLL to stabilize */ 1428 msleep(250); 1429 /* 1430 * PLL state should be stable now. Ideally, we should check 1431 * for PLL LOCK status. But well, never mind! 1432 */ 1433 budget_ci->budget.dvb_frontend = dvb_attach(stb0899_attach, &tt3200_config, &budget_ci->budget.i2c_adap); 1434 if (budget_ci->budget.dvb_frontend) { 1435 if (dvb_attach(stb6100_attach, budget_ci->budget.dvb_frontend, &tt3200_stb6100_config, &budget_ci->budget.i2c_adap)) { 1436 if (!dvb_attach(lnbp21_attach, budget_ci->budget.dvb_frontend, &budget_ci->budget.i2c_adap, 0, 0)) { 1437 printk("%s: No LNBP21 found!\n", __func__); 1438 dvb_frontend_detach(budget_ci->budget.dvb_frontend); 1439 budget_ci->budget.dvb_frontend = NULL; 1440 } 1441 } else { 1442 dvb_frontend_detach(budget_ci->budget.dvb_frontend); 1443 budget_ci->budget.dvb_frontend = NULL; 1444 } 1445 } 1446 break; 1447 1448 } 1449 1450 if (budget_ci->budget.dvb_frontend == NULL) { 1451 printk("budget-ci: A frontend driver was not found for device [%04x:%04x] subsystem [%04x:%04x]\n", 1452 budget_ci->budget.dev->pci->vendor, 1453 budget_ci->budget.dev->pci->device, 1454 budget_ci->budget.dev->pci->subsystem_vendor, 1455 budget_ci->budget.dev->pci->subsystem_device); 1456 } else { 1457 if (dvb_register_frontend 1458 (&budget_ci->budget.dvb_adapter, budget_ci->budget.dvb_frontend)) { 1459 printk("budget-ci: Frontend registration failed!\n"); 1460 dvb_frontend_detach(budget_ci->budget.dvb_frontend); 1461 budget_ci->budget.dvb_frontend = NULL; 1462 } 1463 } 1464 } 1465 1466 static int budget_ci_attach(struct saa7146_dev *dev, struct saa7146_pci_extension_data *info) 1467 { 1468 struct budget_ci *budget_ci; 1469 int err; 1470 1471 budget_ci = kzalloc(sizeof(struct budget_ci), GFP_KERNEL); 1472 if (!budget_ci) { 1473 err = -ENOMEM; 1474 goto out1; 1475 } 1476 1477 dprintk(2, "budget_ci: %p\n", budget_ci); 1478 1479 dev->ext_priv = budget_ci; 1480 1481 err = ttpci_budget_init(&budget_ci->budget, dev, info, THIS_MODULE, 1482 adapter_nr); 1483 if (err) 1484 goto out2; 1485 1486 err = msp430_ir_init(budget_ci); 1487 if (err) 1488 goto out3; 1489 1490 ciintf_init(budget_ci); 1491 1492 budget_ci->budget.dvb_adapter.priv = budget_ci; 1493 frontend_init(budget_ci); 1494 1495 ttpci_budget_init_hooks(&budget_ci->budget); 1496 1497 return 0; 1498 1499 out3: 1500 ttpci_budget_deinit(&budget_ci->budget); 1501 out2: 1502 kfree(budget_ci); 1503 out1: 1504 return err; 1505 } 1506 1507 static int budget_ci_detach(struct saa7146_dev *dev) 1508 { 1509 struct budget_ci *budget_ci = (struct budget_ci *) dev->ext_priv; 1510 struct saa7146_dev *saa = budget_ci->budget.dev; 1511 int err; 1512 1513 if (budget_ci->budget.ci_present) 1514 ciintf_deinit(budget_ci); 1515 msp430_ir_deinit(budget_ci); 1516 if (budget_ci->budget.dvb_frontend) { 1517 dvb_unregister_frontend(budget_ci->budget.dvb_frontend); 1518 dvb_frontend_detach(budget_ci->budget.dvb_frontend); 1519 } 1520 err = ttpci_budget_deinit(&budget_ci->budget); 1521 1522 // disable frontend and CI interface 1523 saa7146_setgpio(saa, 2, SAA7146_GPIO_INPUT); 1524 1525 kfree(budget_ci); 1526 1527 return err; 1528 } 1529 1530 static struct saa7146_extension budget_extension; 1531 1532 MAKE_BUDGET_INFO(ttbs2, "TT-Budget/S-1500 PCI", BUDGET_TT); 1533 MAKE_BUDGET_INFO(ttbci, "TT-Budget/WinTV-NOVA-CI PCI", BUDGET_TT_HW_DISEQC); 1534 MAKE_BUDGET_INFO(ttbt2, "TT-Budget/WinTV-NOVA-T PCI", BUDGET_TT); 1535 MAKE_BUDGET_INFO(ttbtci, "TT-Budget-T-CI PCI", BUDGET_TT); 1536 MAKE_BUDGET_INFO(ttbcci, "TT-Budget-C-CI PCI", BUDGET_TT); 1537 MAKE_BUDGET_INFO(ttc1501, "TT-Budget C-1501 PCI", BUDGET_TT); 1538 MAKE_BUDGET_INFO(tt3200, "TT-Budget S2-3200 PCI", BUDGET_TT); 1539 MAKE_BUDGET_INFO(ttbs1500b, "TT-Budget S-1500B PCI", BUDGET_TT); 1540 1541 static struct pci_device_id pci_tbl[] = { 1542 MAKE_EXTENSION_PCI(ttbci, 0x13c2, 0x100c), 1543 MAKE_EXTENSION_PCI(ttbci, 0x13c2, 0x100f), 1544 MAKE_EXTENSION_PCI(ttbcci, 0x13c2, 0x1010), 1545 MAKE_EXTENSION_PCI(ttbt2, 0x13c2, 0x1011), 1546 MAKE_EXTENSION_PCI(ttbtci, 0x13c2, 0x1012), 1547 MAKE_EXTENSION_PCI(ttbs2, 0x13c2, 0x1017), 1548 MAKE_EXTENSION_PCI(ttc1501, 0x13c2, 0x101a), 1549 MAKE_EXTENSION_PCI(tt3200, 0x13c2, 0x1019), 1550 MAKE_EXTENSION_PCI(ttbs1500b, 0x13c2, 0x101b), 1551 { 1552 .vendor = 0, 1553 } 1554 }; 1555 1556 MODULE_DEVICE_TABLE(pci, pci_tbl); 1557 1558 static struct saa7146_extension budget_extension = { 1559 .name = "budget_ci dvb", 1560 .flags = SAA7146_USE_I2C_IRQ, 1561 1562 .module = THIS_MODULE, 1563 .pci_tbl = &pci_tbl[0], 1564 .attach = budget_ci_attach, 1565 .detach = budget_ci_detach, 1566 1567 .irq_mask = MASK_03 | MASK_06 | MASK_10, 1568 .irq_func = budget_ci_irq, 1569 }; 1570 1571 static int __init budget_ci_init(void) 1572 { 1573 return saa7146_register_extension(&budget_extension); 1574 } 1575 1576 static void __exit budget_ci_exit(void) 1577 { 1578 saa7146_unregister_extension(&budget_extension); 1579 } 1580 1581 module_init(budget_ci_init); 1582 module_exit(budget_ci_exit); 1583 1584 MODULE_LICENSE("GPL"); 1585 MODULE_AUTHOR("Michael Hunold, Jack Thomasson, Andrew de Quincey, others"); 1586 MODULE_DESCRIPTION("driver for the SAA7146 based so-called budget PCI DVB cards w/ CI-module produced by Siemens, Technotrend, Hauppauge"); 1587