1c942fddfSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */
2b285192aSMauro Carvalho Chehab /*
3b285192aSMauro Carvalho Chehab  *  Driver for the NXP SAA7164 PCIe bridge
4b285192aSMauro Carvalho Chehab  *
563a412ecSSteven Toth  *  Copyright (c) 2010-2015 Steven Toth <stoth@kernellabs.com>
6b285192aSMauro Carvalho Chehab  */
7b285192aSMauro Carvalho Chehab 
8b285192aSMauro Carvalho Chehab /* TODO: Retest the driver with errors expressed as negatives */
9b285192aSMauro Carvalho Chehab 
10b285192aSMauro Carvalho Chehab /* Result codes */
11b285192aSMauro Carvalho Chehab #define SAA_OK				0
12b285192aSMauro Carvalho Chehab #define SAA_ERR_BAD_PARAMETER		0x09
13b285192aSMauro Carvalho Chehab #define SAA_ERR_NO_RESOURCES		0x0c
14b285192aSMauro Carvalho Chehab #define SAA_ERR_NOT_SUPPORTED		0x13
15b285192aSMauro Carvalho Chehab #define SAA_ERR_BUSY			0x15
16b285192aSMauro Carvalho Chehab #define SAA_ERR_READ			0x17
17b285192aSMauro Carvalho Chehab #define SAA_ERR_TIMEOUT			0x1f
18b285192aSMauro Carvalho Chehab #define SAA_ERR_OVERFLOW		0x20
19b285192aSMauro Carvalho Chehab #define SAA_ERR_EMPTY			0x22
20b285192aSMauro Carvalho Chehab #define SAA_ERR_NOT_STARTED		0x23
21b285192aSMauro Carvalho Chehab #define SAA_ERR_ALREADY_STARTED		0x24
22b285192aSMauro Carvalho Chehab #define SAA_ERR_NOT_STOPPED		0x25
23b285192aSMauro Carvalho Chehab #define SAA_ERR_ALREADY_STOPPED		0x26
24b285192aSMauro Carvalho Chehab #define SAA_ERR_INVALID_COMMAND		0x3e
25b285192aSMauro Carvalho Chehab #define SAA_ERR_NULL_PACKET		0x59
26b285192aSMauro Carvalho Chehab 
27b285192aSMauro Carvalho Chehab /* Errors and flags from the silicon */
28b285192aSMauro Carvalho Chehab #define PVC_ERRORCODE_UNKNOWN		0x00
29b285192aSMauro Carvalho Chehab #define PVC_ERRORCODE_INVALID_COMMAND	0x01
30b285192aSMauro Carvalho Chehab #define PVC_ERRORCODE_INVALID_CONTROL	0x02
31b285192aSMauro Carvalho Chehab #define PVC_ERRORCODE_INVALID_DATA	0x03
32b285192aSMauro Carvalho Chehab #define PVC_ERRORCODE_TIMEOUT		0x04
33b285192aSMauro Carvalho Chehab #define PVC_ERRORCODE_NAK		0x05
34b285192aSMauro Carvalho Chehab #define PVC_RESPONSEFLAG_ERROR		0x01
35b285192aSMauro Carvalho Chehab #define PVC_RESPONSEFLAG_OVERFLOW	0x02
36b285192aSMauro Carvalho Chehab #define PVC_RESPONSEFLAG_RESET		0x04
37b285192aSMauro Carvalho Chehab #define PVC_RESPONSEFLAG_INTERFACE	0x08
38b285192aSMauro Carvalho Chehab #define PVC_RESPONSEFLAG_CONTINUED	0x10
39b285192aSMauro Carvalho Chehab #define PVC_CMDFLAG_INTERRUPT		0x02
40b285192aSMauro Carvalho Chehab #define PVC_CMDFLAG_INTERFACE		0x04
41b285192aSMauro Carvalho Chehab #define PVC_CMDFLAG_SERIALIZE		0x08
42b285192aSMauro Carvalho Chehab #define PVC_CMDFLAG_CONTINUE		0x10
43b285192aSMauro Carvalho Chehab 
44b285192aSMauro Carvalho Chehab /* Silicon Commands */
45b285192aSMauro Carvalho Chehab #define GET_DESCRIPTORS_CONTROL		0x01
46b285192aSMauro Carvalho Chehab #define GET_STRING_CONTROL		0x03
47b285192aSMauro Carvalho Chehab #define GET_LANGUAGE_CONTROL		0x05
48b285192aSMauro Carvalho Chehab #define SET_POWER_CONTROL		0x07
49b285192aSMauro Carvalho Chehab #define GET_FW_STATUS_CONTROL		0x08
50b285192aSMauro Carvalho Chehab #define GET_FW_VERSION_CONTROL		0x09
51b285192aSMauro Carvalho Chehab #define SET_DEBUG_LEVEL_CONTROL		0x0B
52b285192aSMauro Carvalho Chehab #define GET_DEBUG_DATA_CONTROL		0x0C
53b285192aSMauro Carvalho Chehab #define GET_PRODUCTION_INFO_CONTROL	0x0D
54b285192aSMauro Carvalho Chehab 
55b285192aSMauro Carvalho Chehab /* cmd defines */
56b285192aSMauro Carvalho Chehab #define SAA_CMDFLAG_CONTINUE		0x10
57b285192aSMauro Carvalho Chehab #define SAA_CMD_MAX_MSG_UNITS		256
58b285192aSMauro Carvalho Chehab 
59b285192aSMauro Carvalho Chehab /* Some defines */
60b285192aSMauro Carvalho Chehab #define SAA_BUS_TIMEOUT			50
61b285192aSMauro Carvalho Chehab #define SAA_DEVICE_TIMEOUT		5000
62b285192aSMauro Carvalho Chehab #define SAA_DEVICE_MAXREQUESTSIZE	256
63b285192aSMauro Carvalho Chehab 
64b285192aSMauro Carvalho Chehab /* Register addresses */
65b285192aSMauro Carvalho Chehab #define SAA_DEVICE_VERSION		0x30
66b285192aSMauro Carvalho Chehab #define SAA_DOWNLOAD_FLAGS		0x34
67b285192aSMauro Carvalho Chehab #define SAA_DOWNLOAD_FLAG		0x34
68b285192aSMauro Carvalho Chehab #define SAA_DOWNLOAD_FLAG_ACK		0x38
69b285192aSMauro Carvalho Chehab #define SAA_DATAREADY_FLAG		0x3C
70b285192aSMauro Carvalho Chehab #define SAA_DATAREADY_FLAG_ACK		0x40
71b285192aSMauro Carvalho Chehab 
72b285192aSMauro Carvalho Chehab /* Boot loader register and bit definitions */
73b285192aSMauro Carvalho Chehab #define SAA_BOOTLOADERERROR_FLAGS	0x44
74b285192aSMauro Carvalho Chehab #define SAA_DEVICE_IMAGE_SEARCHING	0x01
75b285192aSMauro Carvalho Chehab #define SAA_DEVICE_IMAGE_LOADING	0x02
76b285192aSMauro Carvalho Chehab #define SAA_DEVICE_IMAGE_BOOTING	0x03
77b285192aSMauro Carvalho Chehab #define SAA_DEVICE_IMAGE_CORRUPT	0x04
78b285192aSMauro Carvalho Chehab #define SAA_DEVICE_MEMORY_CORRUPT	0x08
79b285192aSMauro Carvalho Chehab #define SAA_DEVICE_NO_IMAGE		0x10
80b285192aSMauro Carvalho Chehab 
81b285192aSMauro Carvalho Chehab /* Register addresses */
82b285192aSMauro Carvalho Chehab #define SAA_DEVICE_2ND_VERSION			0x50
83b285192aSMauro Carvalho Chehab #define SAA_DEVICE_2ND_DOWNLOADFLAG_OFFSET	0x54
84b285192aSMauro Carvalho Chehab 
85b285192aSMauro Carvalho Chehab /* Register addresses */
86b285192aSMauro Carvalho Chehab #define SAA_SECONDSTAGEERROR_FLAGS		0x64
87b285192aSMauro Carvalho Chehab 
88b285192aSMauro Carvalho Chehab /* Bootloader regs and flags */
89b285192aSMauro Carvalho Chehab #define SAA_DEVICE_DEADLOCK_DETECTED_OFFSET	0x6C
90b285192aSMauro Carvalho Chehab #define SAA_DEVICE_DEADLOCK_DETECTED		0xDEADDEAD
91b285192aSMauro Carvalho Chehab 
92b285192aSMauro Carvalho Chehab /* Basic firmware status registers */
93b285192aSMauro Carvalho Chehab #define SAA_DEVICE_SYSINIT_STATUS_OFFSET	0x70
94b285192aSMauro Carvalho Chehab #define SAA_DEVICE_SYSINIT_STATUS		0x70
95b285192aSMauro Carvalho Chehab #define SAA_DEVICE_SYSINIT_MODE			0x74
96b285192aSMauro Carvalho Chehab #define SAA_DEVICE_SYSINIT_SPEC			0x78
97b285192aSMauro Carvalho Chehab #define SAA_DEVICE_SYSINIT_INST			0x7C
98b285192aSMauro Carvalho Chehab #define SAA_DEVICE_SYSINIT_CPULOAD		0x80
99b285192aSMauro Carvalho Chehab #define SAA_DEVICE_SYSINIT_REMAINHEAP		0x84
100b285192aSMauro Carvalho Chehab 
101b285192aSMauro Carvalho Chehab #define SAA_DEVICE_DOWNLOAD_OFFSET		0x1000
102b285192aSMauro Carvalho Chehab #define SAA_DEVICE_BUFFERBLOCKSIZE		0x1000
103b285192aSMauro Carvalho Chehab 
104b285192aSMauro Carvalho Chehab #define SAA_DEVICE_2ND_BUFFERBLOCKSIZE		0x100000
105b285192aSMauro Carvalho Chehab #define SAA_DEVICE_2ND_DOWNLOAD_OFFSET		0x200000
106b285192aSMauro Carvalho Chehab 
107b285192aSMauro Carvalho Chehab /* Descriptors */
108b285192aSMauro Carvalho Chehab #define CS_INTERFACE	0x24
109b285192aSMauro Carvalho Chehab 
110b285192aSMauro Carvalho Chehab /* Descriptor subtypes */
111b285192aSMauro Carvalho Chehab #define VC_INPUT_TERMINAL		0x02
112b285192aSMauro Carvalho Chehab #define VC_OUTPUT_TERMINAL		0x03
113b285192aSMauro Carvalho Chehab #define VC_SELECTOR_UNIT		0x04
114b285192aSMauro Carvalho Chehab #define VC_PROCESSING_UNIT		0x05
115b285192aSMauro Carvalho Chehab #define FEATURE_UNIT			0x06
116b285192aSMauro Carvalho Chehab #define TUNER_UNIT			0x09
117b285192aSMauro Carvalho Chehab #define ENCODER_UNIT			0x0A
118b285192aSMauro Carvalho Chehab #define EXTENSION_UNIT			0x0B
119b285192aSMauro Carvalho Chehab #define VC_TUNER_PATH			0xF0
120b285192aSMauro Carvalho Chehab #define PVC_HARDWARE_DESCRIPTOR		0xF1
121b285192aSMauro Carvalho Chehab #define PVC_INTERFACE_DESCRIPTOR	0xF2
122b285192aSMauro Carvalho Chehab #define PVC_INFRARED_UNIT		0xF3
123b285192aSMauro Carvalho Chehab #define DRM_UNIT			0xF4
124b285192aSMauro Carvalho Chehab #define GENERAL_REQUEST			0xF5
125b285192aSMauro Carvalho Chehab 
126b285192aSMauro Carvalho Chehab /* Format Types */
127b285192aSMauro Carvalho Chehab #define VS_FORMAT_TYPE         0x02
128b285192aSMauro Carvalho Chehab #define VS_FORMAT_TYPE_I       0x01
129b285192aSMauro Carvalho Chehab #define VS_FORMAT_UNCOMPRESSED 0x04
130b285192aSMauro Carvalho Chehab #define VS_FRAME_UNCOMPRESSED  0x05
131b285192aSMauro Carvalho Chehab #define VS_FORMAT_MPEG2PS      0x09
132b285192aSMauro Carvalho Chehab #define VS_FORMAT_MPEG2TS      0x0A
133b285192aSMauro Carvalho Chehab #define VS_FORMAT_MPEG4SL      0x0B
134b285192aSMauro Carvalho Chehab #define VS_FORMAT_WM9          0x0C
135b285192aSMauro Carvalho Chehab #define VS_FORMAT_DIVX         0x0D
136b285192aSMauro Carvalho Chehab #define VS_FORMAT_VBI          0x0E
137b285192aSMauro Carvalho Chehab #define VS_FORMAT_RDS          0x0F
138b285192aSMauro Carvalho Chehab 
139b285192aSMauro Carvalho Chehab /* Device extension commands */
140b285192aSMauro Carvalho Chehab #define EXU_REGISTER_ACCESS_CONTROL	0x00
141b285192aSMauro Carvalho Chehab #define EXU_GPIO_CONTROL		0x01
142b285192aSMauro Carvalho Chehab #define EXU_GPIO_GROUP_CONTROL		0x02
143b285192aSMauro Carvalho Chehab #define EXU_INTERRUPT_CONTROL		0x03
144b285192aSMauro Carvalho Chehab 
145b285192aSMauro Carvalho Chehab /* State Transition and args */
146b285192aSMauro Carvalho Chehab #define SAA_PROBE_CONTROL	0x01
147b285192aSMauro Carvalho Chehab #define SAA_COMMIT_CONTROL	0x02
148b285192aSMauro Carvalho Chehab #define SAA_STATE_CONTROL	0x03
149b285192aSMauro Carvalho Chehab #define SAA_DMASTATE_STOP	0x00
150b285192aSMauro Carvalho Chehab #define SAA_DMASTATE_ACQUIRE	0x01
151b285192aSMauro Carvalho Chehab #define SAA_DMASTATE_PAUSE	0x02
152b285192aSMauro Carvalho Chehab #define SAA_DMASTATE_RUN	0x03
153b285192aSMauro Carvalho Chehab 
154b285192aSMauro Carvalho Chehab /* A/V Mux Input Selector */
155b285192aSMauro Carvalho Chehab #define SU_INPUT_SELECT_CONTROL 0x01
156b285192aSMauro Carvalho Chehab 
157b285192aSMauro Carvalho Chehab /* Encoder Profiles */
158b285192aSMauro Carvalho Chehab #define EU_PROFILE_PS_DVD	0x06
159b285192aSMauro Carvalho Chehab #define EU_PROFILE_TS_HQ	0x09
160b285192aSMauro Carvalho Chehab #define EU_VIDEO_FORMAT_MPEG_2	0x02
161b285192aSMauro Carvalho Chehab 
162b285192aSMauro Carvalho Chehab /* Tuner */
163b285192aSMauro Carvalho Chehab #define TU_AUDIO_MODE_CONTROL  0x17
164b285192aSMauro Carvalho Chehab 
165b285192aSMauro Carvalho Chehab /* Video Formats */
166b285192aSMauro Carvalho Chehab #define TU_STANDARD_CONTROL		0x00
167b285192aSMauro Carvalho Chehab #define TU_STANDARD_AUTO_CONTROL	0x01
168b285192aSMauro Carvalho Chehab #define TU_STANDARD_NONE		0x00
169b285192aSMauro Carvalho Chehab #define TU_STANDARD_NTSC_M		0x01
170b285192aSMauro Carvalho Chehab #define TU_STANDARD_PAL_I		0x08
171b285192aSMauro Carvalho Chehab #define TU_STANDARD_MANUAL		0x00
172b285192aSMauro Carvalho Chehab #define TU_STANDARD_AUTO		0x01
173b285192aSMauro Carvalho Chehab 
174b285192aSMauro Carvalho Chehab /* Video Controls */
175b285192aSMauro Carvalho Chehab #define PU_BRIGHTNESS_CONTROL	0x02
176b285192aSMauro Carvalho Chehab #define PU_CONTRAST_CONTROL	0x03
177b285192aSMauro Carvalho Chehab #define PU_HUE_CONTROL		0x06
178b285192aSMauro Carvalho Chehab #define PU_SATURATION_CONTROL	0x07
179b285192aSMauro Carvalho Chehab #define PU_SHARPNESS_CONTROL	0x08
180b285192aSMauro Carvalho Chehab 
181b285192aSMauro Carvalho Chehab /* Audio Controls */
182b285192aSMauro Carvalho Chehab #define MUTE_CONTROL		0x01
183b285192aSMauro Carvalho Chehab #define VOLUME_CONTROL		0x02
184b285192aSMauro Carvalho Chehab #define AUDIO_DEFAULT_CONTROL	0x0D
185b285192aSMauro Carvalho Chehab 
186b285192aSMauro Carvalho Chehab /* Default Volume Levels */
187b285192aSMauro Carvalho Chehab #define TMHW_LEV_ADJ_DECLEV_DEFAULT     0x00
188b285192aSMauro Carvalho Chehab #define TMHW_LEV_ADJ_MONOLEV_DEFAULT    0x00
189b285192aSMauro Carvalho Chehab #define TMHW_LEV_ADJ_NICLEV_DEFAULT     0x00
190b285192aSMauro Carvalho Chehab #define TMHW_LEV_ADJ_SAPLEV_DEFAULT     0x00
191b285192aSMauro Carvalho Chehab #define TMHW_LEV_ADJ_ADCLEV_DEFAULT     0x00
192b285192aSMauro Carvalho Chehab 
193b285192aSMauro Carvalho Chehab /* Encoder Related Commands */
194b285192aSMauro Carvalho Chehab #define EU_PROFILE_CONTROL		0x00
195b285192aSMauro Carvalho Chehab #define EU_VIDEO_FORMAT_CONTROL		0x01
196b285192aSMauro Carvalho Chehab #define EU_VIDEO_BIT_RATE_CONTROL	0x02
197b285192aSMauro Carvalho Chehab #define EU_VIDEO_RESOLUTION_CONTROL	0x03
198b285192aSMauro Carvalho Chehab #define EU_VIDEO_GOP_STRUCTURE_CONTROL	0x04
199b285192aSMauro Carvalho Chehab #define EU_VIDEO_INPUT_ASPECT_CONTROL	0x0A
200b285192aSMauro Carvalho Chehab #define EU_AUDIO_FORMAT_CONTROL		0x0C
201b285192aSMauro Carvalho Chehab #define EU_AUDIO_BIT_RATE_CONTROL	0x0D
202b285192aSMauro Carvalho Chehab 
203b285192aSMauro Carvalho Chehab /* Firmware Debugging */
204b285192aSMauro Carvalho Chehab #define SET_DEBUG_LEVEL_CONTROL	0x0B
205b285192aSMauro Carvalho Chehab #define GET_DEBUG_DATA_CONTROL	0x0C
206