1 /* 2 * 3 * device driver for philips saa7134 based TV cards 4 * video4linux video interface 5 * 6 * (c) 2001,02 Gerd Knorr <kraxel@bytesex.org> [SuSE Labs] 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19 #include "saa7134.h" 20 #include "saa7134-reg.h" 21 22 #include <linux/init.h> 23 #include <linux/list.h> 24 #include <linux/module.h> 25 #include <linux/kernel.h> 26 #include <linux/delay.h> 27 28 /* ------------------------------------------------------------------ */ 29 30 static unsigned int ts_debug; 31 module_param(ts_debug, int, 0644); 32 MODULE_PARM_DESC(ts_debug,"enable debug messages [ts]"); 33 34 #define ts_dbg(fmt, arg...) do { \ 35 if (ts_debug) \ 36 printk(KERN_DEBUG pr_fmt("ts: " fmt), ## arg); \ 37 } while (0) 38 39 /* ------------------------------------------------------------------ */ 40 static int buffer_activate(struct saa7134_dev *dev, 41 struct saa7134_buf *buf, 42 struct saa7134_buf *next) 43 { 44 45 ts_dbg("buffer_activate [%p]", buf); 46 buf->top_seen = 0; 47 48 if (!dev->ts_started) 49 dev->ts_field = V4L2_FIELD_TOP; 50 51 if (NULL == next) 52 next = buf; 53 if (V4L2_FIELD_TOP == dev->ts_field) { 54 ts_dbg("- [top] buf=%p next=%p\n", buf, next); 55 saa_writel(SAA7134_RS_BA1(5),saa7134_buffer_base(buf)); 56 saa_writel(SAA7134_RS_BA2(5),saa7134_buffer_base(next)); 57 dev->ts_field = V4L2_FIELD_BOTTOM; 58 } else { 59 ts_dbg("- [bottom] buf=%p next=%p\n", buf, next); 60 saa_writel(SAA7134_RS_BA1(5),saa7134_buffer_base(next)); 61 saa_writel(SAA7134_RS_BA2(5),saa7134_buffer_base(buf)); 62 dev->ts_field = V4L2_FIELD_TOP; 63 } 64 65 /* start DMA */ 66 saa7134_set_dmabits(dev); 67 68 mod_timer(&dev->ts_q.timeout, jiffies+TS_BUFFER_TIMEOUT); 69 70 if (!dev->ts_started) 71 saa7134_ts_start(dev); 72 73 return 0; 74 } 75 76 int saa7134_ts_buffer_init(struct vb2_buffer *vb2) 77 { 78 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb2); 79 struct saa7134_dmaqueue *dmaq = vb2->vb2_queue->drv_priv; 80 struct saa7134_buf *buf = container_of(vbuf, struct saa7134_buf, vb2); 81 82 dmaq->curr = NULL; 83 buf->activate = buffer_activate; 84 85 return 0; 86 } 87 EXPORT_SYMBOL_GPL(saa7134_ts_buffer_init); 88 89 int saa7134_ts_buffer_prepare(struct vb2_buffer *vb2) 90 { 91 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb2); 92 struct saa7134_dmaqueue *dmaq = vb2->vb2_queue->drv_priv; 93 struct saa7134_dev *dev = dmaq->dev; 94 struct saa7134_buf *buf = container_of(vbuf, struct saa7134_buf, vb2); 95 struct sg_table *dma = vb2_dma_sg_plane_desc(vb2, 0); 96 unsigned int lines, llength, size; 97 98 ts_dbg("buffer_prepare [%p]\n", buf); 99 100 llength = TS_PACKET_SIZE; 101 lines = dev->ts.nr_packets; 102 103 size = lines * llength; 104 if (vb2_plane_size(vb2, 0) < size) 105 return -EINVAL; 106 107 vb2_set_plane_payload(vb2, 0, size); 108 vbuf->field = dev->field; 109 110 return saa7134_pgtable_build(dev->pci, &dmaq->pt, dma->sgl, dma->nents, 111 saa7134_buffer_startpage(buf)); 112 } 113 EXPORT_SYMBOL_GPL(saa7134_ts_buffer_prepare); 114 115 int saa7134_ts_queue_setup(struct vb2_queue *q, 116 unsigned int *nbuffers, unsigned int *nplanes, 117 unsigned int sizes[], struct device *alloc_devs[]) 118 { 119 struct saa7134_dmaqueue *dmaq = q->drv_priv; 120 struct saa7134_dev *dev = dmaq->dev; 121 int size = TS_PACKET_SIZE * dev->ts.nr_packets; 122 123 if (0 == *nbuffers) 124 *nbuffers = dev->ts.nr_bufs; 125 *nbuffers = saa7134_buffer_count(size, *nbuffers); 126 if (*nbuffers < 3) 127 *nbuffers = 3; 128 *nplanes = 1; 129 sizes[0] = size; 130 return 0; 131 } 132 EXPORT_SYMBOL_GPL(saa7134_ts_queue_setup); 133 134 int saa7134_ts_start_streaming(struct vb2_queue *vq, unsigned int count) 135 { 136 struct saa7134_dmaqueue *dmaq = vq->drv_priv; 137 struct saa7134_dev *dev = dmaq->dev; 138 139 /* 140 * Planar video capture and TS share the same DMA channel, 141 * so only one can be active at a time. 142 */ 143 if (vb2_is_busy(&dev->video_vbq) && dev->fmt->planar) { 144 struct saa7134_buf *buf, *tmp; 145 146 list_for_each_entry_safe(buf, tmp, &dmaq->queue, entry) { 147 list_del(&buf->entry); 148 vb2_buffer_done(&buf->vb2.vb2_buf, 149 VB2_BUF_STATE_QUEUED); 150 } 151 if (dmaq->curr) { 152 vb2_buffer_done(&dmaq->curr->vb2.vb2_buf, 153 VB2_BUF_STATE_QUEUED); 154 dmaq->curr = NULL; 155 } 156 return -EBUSY; 157 } 158 dmaq->seq_nr = 0; 159 return 0; 160 } 161 EXPORT_SYMBOL_GPL(saa7134_ts_start_streaming); 162 163 void saa7134_ts_stop_streaming(struct vb2_queue *vq) 164 { 165 struct saa7134_dmaqueue *dmaq = vq->drv_priv; 166 struct saa7134_dev *dev = dmaq->dev; 167 168 saa7134_ts_stop(dev); 169 saa7134_stop_streaming(dev, dmaq); 170 } 171 EXPORT_SYMBOL_GPL(saa7134_ts_stop_streaming); 172 173 struct vb2_ops saa7134_ts_qops = { 174 .queue_setup = saa7134_ts_queue_setup, 175 .buf_init = saa7134_ts_buffer_init, 176 .buf_prepare = saa7134_ts_buffer_prepare, 177 .buf_queue = saa7134_vb2_buffer_queue, 178 .wait_prepare = vb2_ops_wait_prepare, 179 .wait_finish = vb2_ops_wait_finish, 180 .stop_streaming = saa7134_ts_stop_streaming, 181 }; 182 EXPORT_SYMBOL_GPL(saa7134_ts_qops); 183 184 /* ----------------------------------------------------------- */ 185 /* exported stuff */ 186 187 static unsigned int tsbufs = 8; 188 module_param(tsbufs, int, 0444); 189 MODULE_PARM_DESC(tsbufs, "number of ts buffers for read/write IO, range 2-32"); 190 191 static unsigned int ts_nr_packets = 64; 192 module_param(ts_nr_packets, int, 0444); 193 MODULE_PARM_DESC(ts_nr_packets,"size of a ts buffers (in ts packets)"); 194 195 int saa7134_ts_init_hw(struct saa7134_dev *dev) 196 { 197 /* deactivate TS softreset */ 198 saa_writeb(SAA7134_TS_SERIAL1, 0x00); 199 /* TSSOP high active, TSVAL high active, TSLOCK ignored */ 200 saa_writeb(SAA7134_TS_PARALLEL, 0x6c); 201 saa_writeb(SAA7134_TS_PARALLEL_SERIAL, (TS_PACKET_SIZE-1)); 202 saa_writeb(SAA7134_TS_DMA0, ((dev->ts.nr_packets-1)&0xff)); 203 saa_writeb(SAA7134_TS_DMA1, (((dev->ts.nr_packets-1)>>8)&0xff)); 204 /* TSNOPIT=0, TSCOLAP=0 */ 205 saa_writeb(SAA7134_TS_DMA2, 206 ((((dev->ts.nr_packets-1)>>16)&0x3f) | 0x00)); 207 208 return 0; 209 } 210 211 int saa7134_ts_init1(struct saa7134_dev *dev) 212 { 213 /* sanitycheck insmod options */ 214 if (tsbufs < 2) 215 tsbufs = 2; 216 if (tsbufs > VIDEO_MAX_FRAME) 217 tsbufs = VIDEO_MAX_FRAME; 218 if (ts_nr_packets < 4) 219 ts_nr_packets = 4; 220 if (ts_nr_packets > 312) 221 ts_nr_packets = 312; 222 dev->ts.nr_bufs = tsbufs; 223 dev->ts.nr_packets = ts_nr_packets; 224 225 INIT_LIST_HEAD(&dev->ts_q.queue); 226 init_timer(&dev->ts_q.timeout); 227 dev->ts_q.timeout.function = saa7134_buffer_timeout; 228 dev->ts_q.timeout.data = (unsigned long)(&dev->ts_q); 229 dev->ts_q.dev = dev; 230 dev->ts_q.need_two = 1; 231 dev->ts_started = 0; 232 saa7134_pgtable_alloc(dev->pci, &dev->ts_q.pt); 233 234 /* init TS hw */ 235 saa7134_ts_init_hw(dev); 236 237 return 0; 238 } 239 240 /* Function for stop TS */ 241 int saa7134_ts_stop(struct saa7134_dev *dev) 242 { 243 ts_dbg("TS stop\n"); 244 245 if (!dev->ts_started) 246 return 0; 247 248 /* Stop TS stream */ 249 switch (saa7134_boards[dev->board].ts_type) { 250 case SAA7134_MPEG_TS_PARALLEL: 251 saa_writeb(SAA7134_TS_PARALLEL, 0x6c); 252 dev->ts_started = 0; 253 break; 254 case SAA7134_MPEG_TS_SERIAL: 255 saa_writeb(SAA7134_TS_SERIAL0, 0x40); 256 dev->ts_started = 0; 257 break; 258 } 259 return 0; 260 } 261 262 /* Function for start TS */ 263 int saa7134_ts_start(struct saa7134_dev *dev) 264 { 265 ts_dbg("TS start\n"); 266 267 if (WARN_ON(dev->ts_started)) 268 return 0; 269 270 /* dma: setup channel 5 (= TS) */ 271 saa_writeb(SAA7134_TS_DMA0, (dev->ts.nr_packets - 1) & 0xff); 272 saa_writeb(SAA7134_TS_DMA1, 273 ((dev->ts.nr_packets - 1) >> 8) & 0xff); 274 /* TSNOPIT=0, TSCOLAP=0 */ 275 saa_writeb(SAA7134_TS_DMA2, 276 (((dev->ts.nr_packets - 1) >> 16) & 0x3f) | 0x00); 277 saa_writel(SAA7134_RS_PITCH(5), TS_PACKET_SIZE); 278 saa_writel(SAA7134_RS_CONTROL(5), SAA7134_RS_CONTROL_BURST_16 | 279 SAA7134_RS_CONTROL_ME | 280 (dev->ts_q.pt.dma >> 12)); 281 282 /* reset hardware TS buffers */ 283 saa_writeb(SAA7134_TS_SERIAL1, 0x00); 284 saa_writeb(SAA7134_TS_SERIAL1, 0x03); 285 saa_writeb(SAA7134_TS_SERIAL1, 0x00); 286 saa_writeb(SAA7134_TS_SERIAL1, 0x01); 287 288 /* TS clock non-inverted */ 289 saa_writeb(SAA7134_TS_SERIAL1, 0x00); 290 291 /* Start TS stream */ 292 switch (saa7134_boards[dev->board].ts_type) { 293 case SAA7134_MPEG_TS_PARALLEL: 294 saa_writeb(SAA7134_TS_SERIAL0, 0x40); 295 saa_writeb(SAA7134_TS_PARALLEL, 0xec | 296 (saa7134_boards[dev->board].ts_force_val << 4)); 297 break; 298 case SAA7134_MPEG_TS_SERIAL: 299 saa_writeb(SAA7134_TS_SERIAL0, 0xd8); 300 saa_writeb(SAA7134_TS_PARALLEL, 0x6c | 301 (saa7134_boards[dev->board].ts_force_val << 4)); 302 saa_writeb(SAA7134_TS_PARALLEL_SERIAL, 0xbc); 303 saa_writeb(SAA7134_TS_SERIAL1, 0x02); 304 break; 305 } 306 307 dev->ts_started = 1; 308 309 return 0; 310 } 311 312 int saa7134_ts_fini(struct saa7134_dev *dev) 313 { 314 saa7134_pgtable_free(dev->pci, &dev->ts_q.pt); 315 return 0; 316 } 317 318 void saa7134_irq_ts_done(struct saa7134_dev *dev, unsigned long status) 319 { 320 enum v4l2_field field; 321 322 spin_lock(&dev->slock); 323 if (dev->ts_q.curr) { 324 field = dev->ts_field; 325 if (field != V4L2_FIELD_TOP) { 326 if ((status & 0x100000) != 0x000000) 327 goto done; 328 } else { 329 if ((status & 0x100000) != 0x100000) 330 goto done; 331 } 332 saa7134_buffer_finish(dev, &dev->ts_q, VB2_BUF_STATE_DONE); 333 } 334 saa7134_buffer_next(dev,&dev->ts_q); 335 336 done: 337 spin_unlock(&dev->slock); 338 } 339