1 /* 2 * 3 * device driver for philips saa7134 based TV cards 4 * video4linux video interface 5 * 6 * (c) 2001,02 Gerd Knorr <kraxel@bytesex.org> [SuSE Labs] 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23 #include "saa7134.h" 24 #include "saa7134-reg.h" 25 26 #include <linux/init.h> 27 #include <linux/list.h> 28 #include <linux/module.h> 29 #include <linux/kernel.h> 30 #include <linux/delay.h> 31 32 /* ------------------------------------------------------------------ */ 33 34 static unsigned int ts_debug; 35 module_param(ts_debug, int, 0644); 36 MODULE_PARM_DESC(ts_debug,"enable debug messages [ts]"); 37 38 #define ts_dbg(fmt, arg...) do { \ 39 if (ts_debug) \ 40 printk(KERN_DEBUG pr_fmt("ts: " fmt), ## arg); \ 41 } while (0) 42 43 /* ------------------------------------------------------------------ */ 44 static int buffer_activate(struct saa7134_dev *dev, 45 struct saa7134_buf *buf, 46 struct saa7134_buf *next) 47 { 48 49 ts_dbg("buffer_activate [%p]",buf); 50 buf->top_seen = 0; 51 52 if (!dev->ts_started) 53 dev->ts_field = V4L2_FIELD_TOP; 54 55 if (NULL == next) 56 next = buf; 57 if (V4L2_FIELD_TOP == dev->ts_field) { 58 ts_dbg("- [top] buf=%p next=%p\n",buf,next); 59 saa_writel(SAA7134_RS_BA1(5),saa7134_buffer_base(buf)); 60 saa_writel(SAA7134_RS_BA2(5),saa7134_buffer_base(next)); 61 dev->ts_field = V4L2_FIELD_BOTTOM; 62 } else { 63 ts_dbg("- [bottom] buf=%p next=%p\n",buf,next); 64 saa_writel(SAA7134_RS_BA1(5),saa7134_buffer_base(next)); 65 saa_writel(SAA7134_RS_BA2(5),saa7134_buffer_base(buf)); 66 dev->ts_field = V4L2_FIELD_TOP; 67 } 68 69 /* start DMA */ 70 saa7134_set_dmabits(dev); 71 72 mod_timer(&dev->ts_q.timeout, jiffies+TS_BUFFER_TIMEOUT); 73 74 if (!dev->ts_started) 75 saa7134_ts_start(dev); 76 77 return 0; 78 } 79 80 int saa7134_ts_buffer_init(struct vb2_buffer *vb2) 81 { 82 struct saa7134_dmaqueue *dmaq = vb2->vb2_queue->drv_priv; 83 struct saa7134_buf *buf = container_of(vb2, struct saa7134_buf, vb2); 84 85 dmaq->curr = NULL; 86 buf->activate = buffer_activate; 87 88 return 0; 89 } 90 EXPORT_SYMBOL_GPL(saa7134_ts_buffer_init); 91 92 int saa7134_ts_buffer_prepare(struct vb2_buffer *vb2) 93 { 94 struct saa7134_dmaqueue *dmaq = vb2->vb2_queue->drv_priv; 95 struct saa7134_dev *dev = dmaq->dev; 96 struct saa7134_buf *buf = container_of(vb2, struct saa7134_buf, vb2); 97 struct sg_table *dma = vb2_dma_sg_plane_desc(vb2, 0); 98 unsigned int lines, llength, size; 99 100 ts_dbg("buffer_prepare [%p]\n", buf); 101 102 llength = TS_PACKET_SIZE; 103 lines = dev->ts.nr_packets; 104 105 size = lines * llength; 106 if (vb2_plane_size(vb2, 0) < size) 107 return -EINVAL; 108 109 vb2_set_plane_payload(vb2, 0, size); 110 vb2->v4l2_buf.field = dev->field; 111 112 return saa7134_pgtable_build(dev->pci, &dmaq->pt, dma->sgl, dma->nents, 113 saa7134_buffer_startpage(buf)); 114 } 115 EXPORT_SYMBOL_GPL(saa7134_ts_buffer_prepare); 116 117 int saa7134_ts_queue_setup(struct vb2_queue *q, const struct v4l2_format *fmt, 118 unsigned int *nbuffers, unsigned int *nplanes, 119 unsigned int sizes[], void *alloc_ctxs[]) 120 { 121 struct saa7134_dmaqueue *dmaq = q->drv_priv; 122 struct saa7134_dev *dev = dmaq->dev; 123 int size = TS_PACKET_SIZE * dev->ts.nr_packets; 124 125 if (0 == *nbuffers) 126 *nbuffers = dev->ts.nr_bufs; 127 *nbuffers = saa7134_buffer_count(size, *nbuffers); 128 if (*nbuffers < 3) 129 *nbuffers = 3; 130 *nplanes = 1; 131 sizes[0] = size; 132 alloc_ctxs[0] = dev->alloc_ctx; 133 return 0; 134 } 135 EXPORT_SYMBOL_GPL(saa7134_ts_queue_setup); 136 137 int saa7134_ts_start_streaming(struct vb2_queue *vq, unsigned int count) 138 { 139 struct saa7134_dmaqueue *dmaq = vq->drv_priv; 140 struct saa7134_dev *dev = dmaq->dev; 141 142 /* 143 * Planar video capture and TS share the same DMA channel, 144 * so only one can be active at a time. 145 */ 146 if (vb2_is_busy(&dev->video_vbq) && dev->fmt->planar) { 147 struct saa7134_buf *buf, *tmp; 148 149 list_for_each_entry_safe(buf, tmp, &dmaq->queue, entry) { 150 list_del(&buf->entry); 151 vb2_buffer_done(&buf->vb2, VB2_BUF_STATE_QUEUED); 152 } 153 if (dmaq->curr) { 154 vb2_buffer_done(&dmaq->curr->vb2, VB2_BUF_STATE_QUEUED); 155 dmaq->curr = NULL; 156 } 157 return -EBUSY; 158 } 159 dmaq->seq_nr = 0; 160 return 0; 161 } 162 EXPORT_SYMBOL_GPL(saa7134_ts_start_streaming); 163 164 void saa7134_ts_stop_streaming(struct vb2_queue *vq) 165 { 166 struct saa7134_dmaqueue *dmaq = vq->drv_priv; 167 struct saa7134_dev *dev = dmaq->dev; 168 169 saa7134_ts_stop(dev); 170 saa7134_stop_streaming(dev, dmaq); 171 } 172 EXPORT_SYMBOL_GPL(saa7134_ts_stop_streaming); 173 174 struct vb2_ops saa7134_ts_qops = { 175 .queue_setup = saa7134_ts_queue_setup, 176 .buf_init = saa7134_ts_buffer_init, 177 .buf_prepare = saa7134_ts_buffer_prepare, 178 .buf_queue = saa7134_vb2_buffer_queue, 179 .wait_prepare = vb2_ops_wait_prepare, 180 .wait_finish = vb2_ops_wait_finish, 181 .stop_streaming = saa7134_ts_stop_streaming, 182 }; 183 EXPORT_SYMBOL_GPL(saa7134_ts_qops); 184 185 /* ----------------------------------------------------------- */ 186 /* exported stuff */ 187 188 static unsigned int tsbufs = 8; 189 module_param(tsbufs, int, 0444); 190 MODULE_PARM_DESC(tsbufs, "number of ts buffers for read/write IO, range 2-32"); 191 192 static unsigned int ts_nr_packets = 64; 193 module_param(ts_nr_packets, int, 0444); 194 MODULE_PARM_DESC(ts_nr_packets,"size of a ts buffers (in ts packets)"); 195 196 int saa7134_ts_init_hw(struct saa7134_dev *dev) 197 { 198 /* deactivate TS softreset */ 199 saa_writeb(SAA7134_TS_SERIAL1, 0x00); 200 /* TSSOP high active, TSVAL high active, TSLOCK ignored */ 201 saa_writeb(SAA7134_TS_PARALLEL, 0x6c); 202 saa_writeb(SAA7134_TS_PARALLEL_SERIAL, (TS_PACKET_SIZE-1)); 203 saa_writeb(SAA7134_TS_DMA0, ((dev->ts.nr_packets-1)&0xff)); 204 saa_writeb(SAA7134_TS_DMA1, (((dev->ts.nr_packets-1)>>8)&0xff)); 205 /* TSNOPIT=0, TSCOLAP=0 */ 206 saa_writeb(SAA7134_TS_DMA2, 207 ((((dev->ts.nr_packets-1)>>16)&0x3f) | 0x00)); 208 209 return 0; 210 } 211 212 int saa7134_ts_init1(struct saa7134_dev *dev) 213 { 214 /* sanitycheck insmod options */ 215 if (tsbufs < 2) 216 tsbufs = 2; 217 if (tsbufs > VIDEO_MAX_FRAME) 218 tsbufs = VIDEO_MAX_FRAME; 219 if (ts_nr_packets < 4) 220 ts_nr_packets = 4; 221 if (ts_nr_packets > 312) 222 ts_nr_packets = 312; 223 dev->ts.nr_bufs = tsbufs; 224 dev->ts.nr_packets = ts_nr_packets; 225 226 INIT_LIST_HEAD(&dev->ts_q.queue); 227 init_timer(&dev->ts_q.timeout); 228 dev->ts_q.timeout.function = saa7134_buffer_timeout; 229 dev->ts_q.timeout.data = (unsigned long)(&dev->ts_q); 230 dev->ts_q.dev = dev; 231 dev->ts_q.need_two = 1; 232 dev->ts_started = 0; 233 saa7134_pgtable_alloc(dev->pci, &dev->ts_q.pt); 234 235 /* init TS hw */ 236 saa7134_ts_init_hw(dev); 237 238 return 0; 239 } 240 241 /* Function for stop TS */ 242 int saa7134_ts_stop(struct saa7134_dev *dev) 243 { 244 ts_dbg("TS stop\n"); 245 246 if (!dev->ts_started) 247 return 0; 248 249 /* Stop TS stream */ 250 switch (saa7134_boards[dev->board].ts_type) { 251 case SAA7134_MPEG_TS_PARALLEL: 252 saa_writeb(SAA7134_TS_PARALLEL, 0x6c); 253 dev->ts_started = 0; 254 break; 255 case SAA7134_MPEG_TS_SERIAL: 256 saa_writeb(SAA7134_TS_SERIAL0, 0x40); 257 dev->ts_started = 0; 258 break; 259 } 260 return 0; 261 } 262 263 /* Function for start TS */ 264 int saa7134_ts_start(struct saa7134_dev *dev) 265 { 266 ts_dbg("TS start\n"); 267 268 if (WARN_ON(dev->ts_started)) 269 return 0; 270 271 /* dma: setup channel 5 (= TS) */ 272 saa_writeb(SAA7134_TS_DMA0, (dev->ts.nr_packets - 1) & 0xff); 273 saa_writeb(SAA7134_TS_DMA1, 274 ((dev->ts.nr_packets - 1) >> 8) & 0xff); 275 /* TSNOPIT=0, TSCOLAP=0 */ 276 saa_writeb(SAA7134_TS_DMA2, 277 (((dev->ts.nr_packets - 1) >> 16) & 0x3f) | 0x00); 278 saa_writel(SAA7134_RS_PITCH(5), TS_PACKET_SIZE); 279 saa_writel(SAA7134_RS_CONTROL(5), SAA7134_RS_CONTROL_BURST_16 | 280 SAA7134_RS_CONTROL_ME | 281 (dev->ts_q.pt.dma >> 12)); 282 283 /* reset hardware TS buffers */ 284 saa_writeb(SAA7134_TS_SERIAL1, 0x00); 285 saa_writeb(SAA7134_TS_SERIAL1, 0x03); 286 saa_writeb(SAA7134_TS_SERIAL1, 0x00); 287 saa_writeb(SAA7134_TS_SERIAL1, 0x01); 288 289 /* TS clock non-inverted */ 290 saa_writeb(SAA7134_TS_SERIAL1, 0x00); 291 292 /* Start TS stream */ 293 switch (saa7134_boards[dev->board].ts_type) { 294 case SAA7134_MPEG_TS_PARALLEL: 295 saa_writeb(SAA7134_TS_SERIAL0, 0x40); 296 saa_writeb(SAA7134_TS_PARALLEL, 0xec | 297 (saa7134_boards[dev->board].ts_force_val << 4)); 298 break; 299 case SAA7134_MPEG_TS_SERIAL: 300 saa_writeb(SAA7134_TS_SERIAL0, 0xd8); 301 saa_writeb(SAA7134_TS_PARALLEL, 0x6c | 302 (saa7134_boards[dev->board].ts_force_val << 4)); 303 saa_writeb(SAA7134_TS_PARALLEL_SERIAL, 0xbc); 304 saa_writeb(SAA7134_TS_SERIAL1, 0x02); 305 break; 306 } 307 308 dev->ts_started = 1; 309 310 return 0; 311 } 312 313 int saa7134_ts_fini(struct saa7134_dev *dev) 314 { 315 saa7134_pgtable_free(dev->pci, &dev->ts_q.pt); 316 return 0; 317 } 318 319 void saa7134_irq_ts_done(struct saa7134_dev *dev, unsigned long status) 320 { 321 enum v4l2_field field; 322 323 spin_lock(&dev->slock); 324 if (dev->ts_q.curr) { 325 field = dev->ts_field; 326 if (field != V4L2_FIELD_TOP) { 327 if ((status & 0x100000) != 0x000000) 328 goto done; 329 } else { 330 if ((status & 0x100000) != 0x100000) 331 goto done; 332 } 333 saa7134_buffer_finish(dev, &dev->ts_q, VB2_BUF_STATE_DONE); 334 } 335 saa7134_buffer_next(dev,&dev->ts_q); 336 337 done: 338 spin_unlock(&dev->slock); 339 } 340