1a296f7bfSAkihiro Tsukada /* SPDX-License-Identifier: GPL-2.0 */ 2f5a98f37SAkihiro Tsukada /* 3f5a98f37SAkihiro Tsukada * Earthsoft PT3 driver 4f5a98f37SAkihiro Tsukada * 5f5a98f37SAkihiro Tsukada * Copyright (C) 2014 Akihiro Tsukada <tskd08@gmail.com> 6f5a98f37SAkihiro Tsukada */ 7f5a98f37SAkihiro Tsukada 8f5a98f37SAkihiro Tsukada #ifndef PT3_H 9f5a98f37SAkihiro Tsukada #define PT3_H 10f5a98f37SAkihiro Tsukada 11f5a98f37SAkihiro Tsukada #include <linux/atomic.h> 12f5a98f37SAkihiro Tsukada #include <linux/types.h> 13f5a98f37SAkihiro Tsukada 14fada1935SMauro Carvalho Chehab #include <media/dvb_demux.h> 15fada1935SMauro Carvalho Chehab #include <media/dvb_frontend.h> 16fada1935SMauro Carvalho Chehab #include <media/dmxdev.h> 17f5a98f37SAkihiro Tsukada 18f5a98f37SAkihiro Tsukada #include "tc90522.h" 19f5a98f37SAkihiro Tsukada #include "mxl301rf.h" 20f5a98f37SAkihiro Tsukada #include "qm1d1c0042.h" 21f5a98f37SAkihiro Tsukada 22f5a98f37SAkihiro Tsukada #define DRV_NAME KBUILD_MODNAME 23f5a98f37SAkihiro Tsukada 24f5a98f37SAkihiro Tsukada #define PT3_NUM_FE 4 25f5a98f37SAkihiro Tsukada 26f5a98f37SAkihiro Tsukada /* 27f5a98f37SAkihiro Tsukada * register index of the FPGA chip 28f5a98f37SAkihiro Tsukada */ 29f5a98f37SAkihiro Tsukada #define REG_VERSION 0x00 30f5a98f37SAkihiro Tsukada #define REG_BUS 0x04 31f5a98f37SAkihiro Tsukada #define REG_SYSTEM_W 0x08 32f5a98f37SAkihiro Tsukada #define REG_SYSTEM_R 0x0c 33f5a98f37SAkihiro Tsukada #define REG_I2C_W 0x10 34f5a98f37SAkihiro Tsukada #define REG_I2C_R 0x14 35f5a98f37SAkihiro Tsukada #define REG_RAM_W 0x18 36f5a98f37SAkihiro Tsukada #define REG_RAM_R 0x1c 37f5a98f37SAkihiro Tsukada #define REG_DMA_BASE 0x40 /* regs for FE[i] = REG_DMA_BASE + 0x18 * i */ 38f5a98f37SAkihiro Tsukada #define OFST_DMA_DESC_L 0x00 39f5a98f37SAkihiro Tsukada #define OFST_DMA_DESC_H 0x04 40f5a98f37SAkihiro Tsukada #define OFST_DMA_CTL 0x08 41f5a98f37SAkihiro Tsukada #define OFST_TS_CTL 0x0c 42f5a98f37SAkihiro Tsukada #define OFST_STATUS 0x10 43f5a98f37SAkihiro Tsukada #define OFST_TS_ERR 0x14 44f5a98f37SAkihiro Tsukada 45f5a98f37SAkihiro Tsukada /* 46f5a98f37SAkihiro Tsukada * internal buffer for I2C 47f5a98f37SAkihiro Tsukada */ 48f5a98f37SAkihiro Tsukada #define PT3_I2C_MAX 4091 49f5a98f37SAkihiro Tsukada struct pt3_i2cbuf { 50f5a98f37SAkihiro Tsukada u8 data[PT3_I2C_MAX]; 51f5a98f37SAkihiro Tsukada u8 tmp; 52f5a98f37SAkihiro Tsukada u32 num_cmds; 53f5a98f37SAkihiro Tsukada }; 54f5a98f37SAkihiro Tsukada 55f5a98f37SAkihiro Tsukada /* 56f5a98f37SAkihiro Tsukada * DMA things 57f5a98f37SAkihiro Tsukada */ 58f5a98f37SAkihiro Tsukada #define TS_PACKET_SZ 188 59f5a98f37SAkihiro Tsukada /* DMA transfers must not cross 4GiB, so use one page / transfer */ 60f5a98f37SAkihiro Tsukada #define DATA_XFER_SZ 4096 61f5a98f37SAkihiro Tsukada #define DATA_BUF_XFERS 47 62f5a98f37SAkihiro Tsukada /* (num_bufs * DATA_BUF_SZ) % TS_PACKET_SZ must be 0 */ 63f5a98f37SAkihiro Tsukada #define DATA_BUF_SZ (DATA_BUF_XFERS * DATA_XFER_SZ) 64f5a98f37SAkihiro Tsukada #define MAX_DATA_BUFS 16 65f5a98f37SAkihiro Tsukada #define MIN_DATA_BUFS 2 66f5a98f37SAkihiro Tsukada 67f5a98f37SAkihiro Tsukada #define DESCS_IN_PAGE (PAGE_SIZE / sizeof(struct xfer_desc)) 68f5a98f37SAkihiro Tsukada #define MAX_NUM_XFERS (MAX_DATA_BUFS * DATA_BUF_XFERS) 69f5a98f37SAkihiro Tsukada #define MAX_DESC_BUFS DIV_ROUND_UP(MAX_NUM_XFERS, DESCS_IN_PAGE) 70f5a98f37SAkihiro Tsukada 71f5a98f37SAkihiro Tsukada /* DMA transfer description. 72f5a98f37SAkihiro Tsukada * device is passed a pointer to this struct, dma-reads it, 73f5a98f37SAkihiro Tsukada * and gets the DMA buffer ring for storing TS data. 74f5a98f37SAkihiro Tsukada */ 75f5a98f37SAkihiro Tsukada struct xfer_desc { 76f5a98f37SAkihiro Tsukada u32 addr_l; /* bus address of target data buffer */ 77f5a98f37SAkihiro Tsukada u32 addr_h; 78f5a98f37SAkihiro Tsukada u32 size; 7916790554SMauro Carvalho Chehab u32 next_l; /* bus address of the next xfer_desc */ 80f5a98f37SAkihiro Tsukada u32 next_h; 81f5a98f37SAkihiro Tsukada }; 82f5a98f37SAkihiro Tsukada 83f5a98f37SAkihiro Tsukada /* A DMA mapping of a page containing xfer_desc's */ 84f5a98f37SAkihiro Tsukada struct xfer_desc_buffer { 85f5a98f37SAkihiro Tsukada dma_addr_t b_addr; 86f5a98f37SAkihiro Tsukada struct xfer_desc *descs; /* PAGE_SIZE (xfer_desc[DESCS_IN_PAGE]) */ 87f5a98f37SAkihiro Tsukada }; 88f5a98f37SAkihiro Tsukada 89f5a98f37SAkihiro Tsukada /* A DMA mapping of a data buffer */ 90f5a98f37SAkihiro Tsukada struct dma_data_buffer { 91f5a98f37SAkihiro Tsukada dma_addr_t b_addr; 92f5a98f37SAkihiro Tsukada u8 *data; /* size: u8[PAGE_SIZE] */ 93f5a98f37SAkihiro Tsukada }; 94f5a98f37SAkihiro Tsukada 95f5a98f37SAkihiro Tsukada /* 96f5a98f37SAkihiro Tsukada * device things 97f5a98f37SAkihiro Tsukada */ 98f5a98f37SAkihiro Tsukada struct pt3_adap_config { 99f5a98f37SAkihiro Tsukada struct i2c_board_info demod_info; 100f5a98f37SAkihiro Tsukada struct tc90522_config demod_cfg; 101f5a98f37SAkihiro Tsukada 102f5a98f37SAkihiro Tsukada struct i2c_board_info tuner_info; 103f5a98f37SAkihiro Tsukada union tuner_config { 104f5a98f37SAkihiro Tsukada struct qm1d1c0042_config qm1d1c0042; 105f5a98f37SAkihiro Tsukada struct mxl301rf_config mxl301rf; 106f5a98f37SAkihiro Tsukada } tuner_cfg; 107f5a98f37SAkihiro Tsukada u32 init_freq; 108f5a98f37SAkihiro Tsukada }; 109f5a98f37SAkihiro Tsukada 110f5a98f37SAkihiro Tsukada struct pt3_adapter { 111f5a98f37SAkihiro Tsukada struct dvb_adapter dvb_adap; /* dvb_adap.priv => struct pt3_board */ 112f5a98f37SAkihiro Tsukada int adap_idx; 113f5a98f37SAkihiro Tsukada 114f5a98f37SAkihiro Tsukada struct dvb_demux demux; 115f5a98f37SAkihiro Tsukada struct dmxdev dmxdev; 116f5a98f37SAkihiro Tsukada struct dvb_frontend *fe; 117f5a98f37SAkihiro Tsukada struct i2c_client *i2c_demod; 118f5a98f37SAkihiro Tsukada struct i2c_client *i2c_tuner; 119f5a98f37SAkihiro Tsukada 120f5a98f37SAkihiro Tsukada /* data fetch thread */ 121f5a98f37SAkihiro Tsukada struct task_struct *thread; 122f5a98f37SAkihiro Tsukada int num_feeds; 123f5a98f37SAkihiro Tsukada 124f5a98f37SAkihiro Tsukada bool cur_lna; 125f5a98f37SAkihiro Tsukada bool cur_lnb; /* current LNB power status (on/off) */ 126f5a98f37SAkihiro Tsukada 127f5a98f37SAkihiro Tsukada /* items below are for DMA */ 128f5a98f37SAkihiro Tsukada struct dma_data_buffer buffer[MAX_DATA_BUFS]; 129f5a98f37SAkihiro Tsukada int buf_idx; 130f5a98f37SAkihiro Tsukada int buf_ofs; 131f5a98f37SAkihiro Tsukada int num_bufs; /* == pt3_board->num_bufs */ 132f5a98f37SAkihiro Tsukada int num_discard; /* how many access units to discard initially */ 133f5a98f37SAkihiro Tsukada 134f5a98f37SAkihiro Tsukada struct xfer_desc_buffer desc_buf[MAX_DESC_BUFS]; 135f5a98f37SAkihiro Tsukada int num_desc_bufs; /* == num_bufs * DATA_BUF_XFERS / DESCS_IN_PAGE */ 136f5a98f37SAkihiro Tsukada }; 137f5a98f37SAkihiro Tsukada 138f5a98f37SAkihiro Tsukada 139f5a98f37SAkihiro Tsukada struct pt3_board { 140f5a98f37SAkihiro Tsukada struct pci_dev *pdev; 141f5a98f37SAkihiro Tsukada void __iomem *regs[2]; 142f5a98f37SAkihiro Tsukada /* regs[0]: registers, regs[1]: internal memory, used for I2C */ 143f5a98f37SAkihiro Tsukada 144f5a98f37SAkihiro Tsukada struct mutex lock; 145f5a98f37SAkihiro Tsukada 146f5a98f37SAkihiro Tsukada /* LNB power shared among sat-FEs */ 147f5a98f37SAkihiro Tsukada int lnb_on_cnt; /* LNB power on count */ 148f5a98f37SAkihiro Tsukada 149f5a98f37SAkihiro Tsukada /* LNA shared among terr-FEs */ 150f5a98f37SAkihiro Tsukada int lna_on_cnt; /* booster enabled count */ 151f5a98f37SAkihiro Tsukada 152f5a98f37SAkihiro Tsukada int num_bufs; /* number of DMA buffers allocated/mapped per FE */ 153f5a98f37SAkihiro Tsukada 154f5a98f37SAkihiro Tsukada struct i2c_adapter i2c_adap; 155f5a98f37SAkihiro Tsukada struct pt3_i2cbuf *i2c_buf; 156f5a98f37SAkihiro Tsukada 157f5a98f37SAkihiro Tsukada struct pt3_adapter *adaps[PT3_NUM_FE]; 158f5a98f37SAkihiro Tsukada }; 159f5a98f37SAkihiro Tsukada 160f5a98f37SAkihiro Tsukada 161f5a98f37SAkihiro Tsukada /* 162f5a98f37SAkihiro Tsukada * prototypes 163f5a98f37SAkihiro Tsukada */ 164f5a98f37SAkihiro Tsukada extern int pt3_alloc_dmabuf(struct pt3_adapter *adap); 165f5a98f37SAkihiro Tsukada extern void pt3_init_dmabuf(struct pt3_adapter *adap); 166f5a98f37SAkihiro Tsukada extern void pt3_free_dmabuf(struct pt3_adapter *adap); 167f5a98f37SAkihiro Tsukada extern int pt3_start_dma(struct pt3_adapter *adap); 168f5a98f37SAkihiro Tsukada extern int pt3_stop_dma(struct pt3_adapter *adap); 169f5a98f37SAkihiro Tsukada extern int pt3_proc_dma(struct pt3_adapter *adap); 170f5a98f37SAkihiro Tsukada 171f5a98f37SAkihiro Tsukada extern int pt3_i2c_master_xfer(struct i2c_adapter *adap, 172f5a98f37SAkihiro Tsukada struct i2c_msg *msgs, int num); 173f5a98f37SAkihiro Tsukada extern u32 pt3_i2c_functionality(struct i2c_adapter *adap); 174f5a98f37SAkihiro Tsukada extern void pt3_i2c_reset(struct pt3_board *pt3); 175f5a98f37SAkihiro Tsukada extern int pt3_init_all_demods(struct pt3_board *pt3); 176f5a98f37SAkihiro Tsukada extern int pt3_init_all_mxl301rf(struct pt3_board *pt3); 177f5a98f37SAkihiro Tsukada #endif /* PT3_H */ 178