1 /* 2 * driver for Earthsoft PT1/PT2 3 * 4 * Copyright (C) 2009 HIRANO Takahito <hiranotaka@zng.info> 5 * 6 * based on pt1dvr - http://pt1dvr.sourceforge.jp/ 7 * by Tomoaki Ishikawa <tomy@users.sourceforge.jp> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 */ 19 20 #include <linux/kernel.h> 21 #include <linux/sched.h> 22 #include <linux/sched/signal.h> 23 #include <linux/hrtimer.h> 24 #include <linux/delay.h> 25 #include <linux/module.h> 26 #include <linux/slab.h> 27 #include <linux/vmalloc.h> 28 #include <linux/pci.h> 29 #include <linux/kthread.h> 30 #include <linux/freezer.h> 31 #include <linux/ratelimit.h> 32 #include <linux/string.h> 33 #include <linux/i2c.h> 34 35 #include <media/dvbdev.h> 36 #include <media/dvb_demux.h> 37 #include <media/dmxdev.h> 38 #include <media/dvb_net.h> 39 #include <media/dvb_frontend.h> 40 41 #include "tc90522.h" 42 #include "qm1d1b0004.h" 43 #include "dvb-pll.h" 44 45 #define DRIVER_NAME "earth-pt1" 46 47 #define PT1_PAGE_SHIFT 12 48 #define PT1_PAGE_SIZE (1 << PT1_PAGE_SHIFT) 49 #define PT1_NR_UPACKETS 1024 50 #define PT1_NR_BUFS 511 51 52 struct pt1_buffer_page { 53 __le32 upackets[PT1_NR_UPACKETS]; 54 }; 55 56 struct pt1_table_page { 57 __le32 next_pfn; 58 __le32 buf_pfns[PT1_NR_BUFS]; 59 }; 60 61 struct pt1_buffer { 62 struct pt1_buffer_page *page; 63 dma_addr_t addr; 64 }; 65 66 struct pt1_table { 67 struct pt1_table_page *page; 68 dma_addr_t addr; 69 struct pt1_buffer bufs[PT1_NR_BUFS]; 70 }; 71 72 enum pt1_fe_clk { 73 PT1_FE_CLK_20MHZ, /* PT1 */ 74 PT1_FE_CLK_25MHZ, /* PT2 */ 75 }; 76 77 #define PT1_NR_ADAPS 4 78 79 struct pt1_adapter; 80 81 struct pt1 { 82 struct pci_dev *pdev; 83 void __iomem *regs; 84 struct i2c_adapter i2c_adap; 85 int i2c_running; 86 struct pt1_adapter *adaps[PT1_NR_ADAPS]; 87 struct pt1_table *tables; 88 struct task_struct *kthread; 89 int table_index; 90 int buf_index; 91 92 struct mutex lock; 93 int power; 94 int reset; 95 96 enum pt1_fe_clk fe_clk; 97 }; 98 99 struct pt1_adapter { 100 struct pt1 *pt1; 101 int index; 102 103 u8 *buf; 104 int upacket_count; 105 int packet_count; 106 int st_count; 107 108 struct dvb_adapter adap; 109 struct dvb_demux demux; 110 int users; 111 struct dmxdev dmxdev; 112 struct dvb_frontend *fe; 113 struct i2c_client *demod_i2c_client; 114 struct i2c_client *tuner_i2c_client; 115 int (*orig_set_voltage)(struct dvb_frontend *fe, 116 enum fe_sec_voltage voltage); 117 int (*orig_sleep)(struct dvb_frontend *fe); 118 int (*orig_init)(struct dvb_frontend *fe); 119 120 enum fe_sec_voltage voltage; 121 int sleep; 122 }; 123 124 union pt1_tuner_config { 125 struct qm1d1b0004_config qm1d1b0004; 126 struct dvb_pll_config tda6651; 127 }; 128 129 struct pt1_config { 130 struct i2c_board_info demod_info; 131 struct tc90522_config demod_cfg; 132 133 struct i2c_board_info tuner_info; 134 union pt1_tuner_config tuner_cfg; 135 }; 136 137 static const struct pt1_config pt1_configs[PT1_NR_ADAPS] = { 138 { 139 .demod_info = { 140 I2C_BOARD_INFO(TC90522_I2C_DEV_SAT, 0x1b), 141 }, 142 .tuner_info = { 143 I2C_BOARD_INFO("qm1d1b0004", 0x60), 144 }, 145 }, 146 { 147 .demod_info = { 148 I2C_BOARD_INFO(TC90522_I2C_DEV_TER, 0x1a), 149 }, 150 .tuner_info = { 151 I2C_BOARD_INFO("tda665x_earthpt1", 0x61), 152 }, 153 }, 154 { 155 .demod_info = { 156 I2C_BOARD_INFO(TC90522_I2C_DEV_SAT, 0x19), 157 }, 158 .tuner_info = { 159 I2C_BOARD_INFO("qm1d1b0004", 0x60), 160 }, 161 }, 162 { 163 .demod_info = { 164 I2C_BOARD_INFO(TC90522_I2C_DEV_TER, 0x18), 165 }, 166 .tuner_info = { 167 I2C_BOARD_INFO("tda665x_earthpt1", 0x61), 168 }, 169 }, 170 }; 171 172 static const u8 va1j5jf8007s_20mhz_configs[][2] = { 173 {0x04, 0x02}, {0x0d, 0x55}, {0x11, 0x40}, {0x13, 0x80}, {0x17, 0x01}, 174 {0x1c, 0x0a}, {0x1d, 0xaa}, {0x1e, 0x20}, {0x1f, 0x88}, {0x51, 0xb0}, 175 {0x52, 0x89}, {0x53, 0xb3}, {0x5a, 0x2d}, {0x5b, 0xd3}, {0x85, 0x69}, 176 {0x87, 0x04}, {0x8e, 0x02}, {0xa3, 0xf7}, {0xa5, 0xc0}, 177 }; 178 179 static const u8 va1j5jf8007s_25mhz_configs[][2] = { 180 {0x04, 0x02}, {0x11, 0x40}, {0x13, 0x80}, {0x17, 0x01}, {0x1c, 0x0a}, 181 {0x1d, 0xaa}, {0x1e, 0x20}, {0x1f, 0x88}, {0x51, 0xb0}, {0x52, 0x89}, 182 {0x53, 0xb3}, {0x5a, 0x2d}, {0x5b, 0xd3}, {0x85, 0x69}, {0x87, 0x04}, 183 {0x8e, 0x26}, {0xa3, 0xf7}, {0xa5, 0xc0}, 184 }; 185 186 static const u8 va1j5jf8007t_20mhz_configs[][2] = { 187 {0x03, 0x90}, {0x14, 0x8f}, {0x1c, 0x2a}, {0x1d, 0xa8}, {0x1e, 0xa2}, 188 {0x22, 0x83}, {0x31, 0x0d}, {0x32, 0xe0}, {0x39, 0xd3}, {0x3a, 0x00}, 189 {0x3b, 0x11}, {0x3c, 0x3f}, 190 {0x5c, 0x40}, {0x5f, 0x80}, {0x75, 0x02}, {0x76, 0x4e}, {0x77, 0x03}, 191 {0xef, 0x01} 192 }; 193 194 static const u8 va1j5jf8007t_25mhz_configs[][2] = { 195 {0x03, 0x90}, {0x1c, 0x2a}, {0x1d, 0xa8}, {0x1e, 0xa2}, {0x22, 0x83}, 196 {0x3a, 0x04}, {0x3b, 0x11}, {0x3c, 0x3f}, {0x5c, 0x40}, {0x5f, 0x80}, 197 {0x75, 0x0a}, {0x76, 0x4c}, {0x77, 0x03}, {0xef, 0x01} 198 }; 199 200 static int config_demod(struct i2c_client *cl, enum pt1_fe_clk clk) 201 { 202 int ret; 203 bool is_sat; 204 const u8 (*cfg_data)[2]; 205 int i, len; 206 207 is_sat = !strncmp(cl->name, TC90522_I2C_DEV_SAT, 208 strlen(TC90522_I2C_DEV_SAT)); 209 if (is_sat) { 210 struct i2c_msg msg[2]; 211 u8 wbuf, rbuf; 212 213 wbuf = 0x07; 214 msg[0].addr = cl->addr; 215 msg[0].flags = 0; 216 msg[0].len = 1; 217 msg[0].buf = &wbuf; 218 219 msg[1].addr = cl->addr; 220 msg[1].flags = I2C_M_RD; 221 msg[1].len = 1; 222 msg[1].buf = &rbuf; 223 ret = i2c_transfer(cl->adapter, msg, 2); 224 if (ret < 0) 225 return ret; 226 if (rbuf != 0x41) 227 return -EIO; 228 } 229 230 /* frontend init */ 231 if (clk == PT1_FE_CLK_20MHZ) { 232 if (is_sat) { 233 cfg_data = va1j5jf8007s_20mhz_configs; 234 len = ARRAY_SIZE(va1j5jf8007s_20mhz_configs); 235 } else { 236 cfg_data = va1j5jf8007t_20mhz_configs; 237 len = ARRAY_SIZE(va1j5jf8007t_20mhz_configs); 238 } 239 } else { 240 if (is_sat) { 241 cfg_data = va1j5jf8007s_25mhz_configs; 242 len = ARRAY_SIZE(va1j5jf8007s_25mhz_configs); 243 } else { 244 cfg_data = va1j5jf8007t_25mhz_configs; 245 len = ARRAY_SIZE(va1j5jf8007t_25mhz_configs); 246 } 247 } 248 249 for (i = 0; i < len; i++) { 250 ret = i2c_master_send(cl, cfg_data[i], 2); 251 if (ret < 0) 252 return ret; 253 } 254 return 0; 255 } 256 257 /* 258 * Init registers for (each pair of) terrestrial/satellite block in demod. 259 * Note that resetting terr. block also resets its peer sat. block as well. 260 * This function must be called before configuring any demod block 261 * (before pt1_wakeup(), fe->ops.init()). 262 */ 263 static int pt1_demod_block_init(struct pt1 *pt1) 264 { 265 struct i2c_client *cl; 266 u8 buf[2] = {0x01, 0x80}; 267 int ret; 268 int i; 269 270 /* reset all terr. & sat. pairs first */ 271 for (i = 0; i < PT1_NR_ADAPS; i++) { 272 cl = pt1->adaps[i]->demod_i2c_client; 273 if (strncmp(cl->name, TC90522_I2C_DEV_TER, 274 strlen(TC90522_I2C_DEV_TER))) 275 continue; 276 277 ret = i2c_master_send(cl, buf, 2); 278 if (ret < 0) 279 return ret; 280 usleep_range(30000, 50000); 281 } 282 283 for (i = 0; i < PT1_NR_ADAPS; i++) { 284 cl = pt1->adaps[i]->demod_i2c_client; 285 if (strncmp(cl->name, TC90522_I2C_DEV_SAT, 286 strlen(TC90522_I2C_DEV_SAT))) 287 continue; 288 289 ret = i2c_master_send(cl, buf, 2); 290 if (ret < 0) 291 return ret; 292 usleep_range(30000, 50000); 293 } 294 return 0; 295 } 296 297 static void pt1_write_reg(struct pt1 *pt1, int reg, u32 data) 298 { 299 writel(data, pt1->regs + reg * 4); 300 } 301 302 static u32 pt1_read_reg(struct pt1 *pt1, int reg) 303 { 304 return readl(pt1->regs + reg * 4); 305 } 306 307 static unsigned int pt1_nr_tables = 8; 308 module_param_named(nr_tables, pt1_nr_tables, uint, 0); 309 310 static void pt1_increment_table_count(struct pt1 *pt1) 311 { 312 pt1_write_reg(pt1, 0, 0x00000020); 313 } 314 315 static void pt1_init_table_count(struct pt1 *pt1) 316 { 317 pt1_write_reg(pt1, 0, 0x00000010); 318 } 319 320 static void pt1_register_tables(struct pt1 *pt1, u32 first_pfn) 321 { 322 pt1_write_reg(pt1, 5, first_pfn); 323 pt1_write_reg(pt1, 0, 0x0c000040); 324 } 325 326 static void pt1_unregister_tables(struct pt1 *pt1) 327 { 328 pt1_write_reg(pt1, 0, 0x08080000); 329 } 330 331 static int pt1_sync(struct pt1 *pt1) 332 { 333 int i; 334 for (i = 0; i < 57; i++) { 335 if (pt1_read_reg(pt1, 0) & 0x20000000) 336 return 0; 337 pt1_write_reg(pt1, 0, 0x00000008); 338 } 339 dev_err(&pt1->pdev->dev, "could not sync\n"); 340 return -EIO; 341 } 342 343 static u64 pt1_identify(struct pt1 *pt1) 344 { 345 int i; 346 u64 id; 347 id = 0; 348 for (i = 0; i < 57; i++) { 349 id |= (u64)(pt1_read_reg(pt1, 0) >> 30 & 1) << i; 350 pt1_write_reg(pt1, 0, 0x00000008); 351 } 352 return id; 353 } 354 355 static int pt1_unlock(struct pt1 *pt1) 356 { 357 int i; 358 pt1_write_reg(pt1, 0, 0x00000008); 359 for (i = 0; i < 3; i++) { 360 if (pt1_read_reg(pt1, 0) & 0x80000000) 361 return 0; 362 usleep_range(1000, 2000); 363 } 364 dev_err(&pt1->pdev->dev, "could not unlock\n"); 365 return -EIO; 366 } 367 368 static int pt1_reset_pci(struct pt1 *pt1) 369 { 370 int i; 371 pt1_write_reg(pt1, 0, 0x01010000); 372 pt1_write_reg(pt1, 0, 0x01000000); 373 for (i = 0; i < 10; i++) { 374 if (pt1_read_reg(pt1, 0) & 0x00000001) 375 return 0; 376 usleep_range(1000, 2000); 377 } 378 dev_err(&pt1->pdev->dev, "could not reset PCI\n"); 379 return -EIO; 380 } 381 382 static int pt1_reset_ram(struct pt1 *pt1) 383 { 384 int i; 385 pt1_write_reg(pt1, 0, 0x02020000); 386 pt1_write_reg(pt1, 0, 0x02000000); 387 for (i = 0; i < 10; i++) { 388 if (pt1_read_reg(pt1, 0) & 0x00000002) 389 return 0; 390 usleep_range(1000, 2000); 391 } 392 dev_err(&pt1->pdev->dev, "could not reset RAM\n"); 393 return -EIO; 394 } 395 396 static int pt1_do_enable_ram(struct pt1 *pt1) 397 { 398 int i, j; 399 u32 status; 400 status = pt1_read_reg(pt1, 0) & 0x00000004; 401 pt1_write_reg(pt1, 0, 0x00000002); 402 for (i = 0; i < 10; i++) { 403 for (j = 0; j < 1024; j++) { 404 if ((pt1_read_reg(pt1, 0) & 0x00000004) != status) 405 return 0; 406 } 407 usleep_range(1000, 2000); 408 } 409 dev_err(&pt1->pdev->dev, "could not enable RAM\n"); 410 return -EIO; 411 } 412 413 static int pt1_enable_ram(struct pt1 *pt1) 414 { 415 int i, ret; 416 int phase; 417 usleep_range(1000, 2000); 418 phase = pt1->pdev->device == 0x211a ? 128 : 166; 419 for (i = 0; i < phase; i++) { 420 ret = pt1_do_enable_ram(pt1); 421 if (ret < 0) 422 return ret; 423 } 424 return 0; 425 } 426 427 static void pt1_disable_ram(struct pt1 *pt1) 428 { 429 pt1_write_reg(pt1, 0, 0x0b0b0000); 430 } 431 432 static void pt1_set_stream(struct pt1 *pt1, int index, int enabled) 433 { 434 pt1_write_reg(pt1, 2, 1 << (index + 8) | enabled << index); 435 } 436 437 static void pt1_init_streams(struct pt1 *pt1) 438 { 439 int i; 440 for (i = 0; i < PT1_NR_ADAPS; i++) 441 pt1_set_stream(pt1, i, 0); 442 } 443 444 static int pt1_filter(struct pt1 *pt1, struct pt1_buffer_page *page) 445 { 446 u32 upacket; 447 int i; 448 int index; 449 struct pt1_adapter *adap; 450 int offset; 451 u8 *buf; 452 int sc; 453 454 if (!page->upackets[PT1_NR_UPACKETS - 1]) 455 return 0; 456 457 for (i = 0; i < PT1_NR_UPACKETS; i++) { 458 upacket = le32_to_cpu(page->upackets[i]); 459 index = (upacket >> 29) - 1; 460 if (index < 0 || index >= PT1_NR_ADAPS) 461 continue; 462 463 adap = pt1->adaps[index]; 464 if (upacket >> 25 & 1) 465 adap->upacket_count = 0; 466 else if (!adap->upacket_count) 467 continue; 468 469 if (upacket >> 24 & 1) 470 printk_ratelimited(KERN_INFO "earth-pt1: device buffer overflowing. table[%d] buf[%d]\n", 471 pt1->table_index, pt1->buf_index); 472 sc = upacket >> 26 & 0x7; 473 if (adap->st_count != -1 && sc != ((adap->st_count + 1) & 0x7)) 474 printk_ratelimited(KERN_INFO "earth-pt1: data loss in streamID(adapter)[%d]\n", 475 index); 476 adap->st_count = sc; 477 478 buf = adap->buf; 479 offset = adap->packet_count * 188 + adap->upacket_count * 3; 480 buf[offset] = upacket >> 16; 481 buf[offset + 1] = upacket >> 8; 482 if (adap->upacket_count != 62) 483 buf[offset + 2] = upacket; 484 485 if (++adap->upacket_count >= 63) { 486 adap->upacket_count = 0; 487 if (++adap->packet_count >= 21) { 488 dvb_dmx_swfilter_packets(&adap->demux, buf, 21); 489 adap->packet_count = 0; 490 } 491 } 492 } 493 494 page->upackets[PT1_NR_UPACKETS - 1] = 0; 495 return 1; 496 } 497 498 static int pt1_thread(void *data) 499 { 500 struct pt1 *pt1; 501 struct pt1_buffer_page *page; 502 bool was_frozen; 503 504 #define PT1_FETCH_DELAY 10 505 #define PT1_FETCH_DELAY_DELTA 2 506 507 pt1 = data; 508 set_freezable(); 509 510 while (!kthread_freezable_should_stop(&was_frozen)) { 511 if (was_frozen) { 512 int i; 513 514 for (i = 0; i < PT1_NR_ADAPS; i++) 515 pt1_set_stream(pt1, i, !!pt1->adaps[i]->users); 516 } 517 518 page = pt1->tables[pt1->table_index].bufs[pt1->buf_index].page; 519 if (!pt1_filter(pt1, page)) { 520 ktime_t delay; 521 522 delay = ktime_set(0, PT1_FETCH_DELAY * NSEC_PER_MSEC); 523 set_current_state(TASK_INTERRUPTIBLE); 524 schedule_hrtimeout_range(&delay, 525 PT1_FETCH_DELAY_DELTA * NSEC_PER_MSEC, 526 HRTIMER_MODE_REL); 527 continue; 528 } 529 530 if (++pt1->buf_index >= PT1_NR_BUFS) { 531 pt1_increment_table_count(pt1); 532 pt1->buf_index = 0; 533 if (++pt1->table_index >= pt1_nr_tables) 534 pt1->table_index = 0; 535 } 536 } 537 538 return 0; 539 } 540 541 static void pt1_free_page(struct pt1 *pt1, void *page, dma_addr_t addr) 542 { 543 dma_free_coherent(&pt1->pdev->dev, PT1_PAGE_SIZE, page, addr); 544 } 545 546 static void *pt1_alloc_page(struct pt1 *pt1, dma_addr_t *addrp, u32 *pfnp) 547 { 548 void *page; 549 dma_addr_t addr; 550 551 page = dma_alloc_coherent(&pt1->pdev->dev, PT1_PAGE_SIZE, &addr, 552 GFP_KERNEL); 553 if (page == NULL) 554 return NULL; 555 556 BUG_ON(addr & (PT1_PAGE_SIZE - 1)); 557 BUG_ON(addr >> PT1_PAGE_SHIFT >> 31 >> 1); 558 559 *addrp = addr; 560 *pfnp = addr >> PT1_PAGE_SHIFT; 561 return page; 562 } 563 564 static void pt1_cleanup_buffer(struct pt1 *pt1, struct pt1_buffer *buf) 565 { 566 pt1_free_page(pt1, buf->page, buf->addr); 567 } 568 569 static int 570 pt1_init_buffer(struct pt1 *pt1, struct pt1_buffer *buf, u32 *pfnp) 571 { 572 struct pt1_buffer_page *page; 573 dma_addr_t addr; 574 575 page = pt1_alloc_page(pt1, &addr, pfnp); 576 if (page == NULL) 577 return -ENOMEM; 578 579 page->upackets[PT1_NR_UPACKETS - 1] = 0; 580 581 buf->page = page; 582 buf->addr = addr; 583 return 0; 584 } 585 586 static void pt1_cleanup_table(struct pt1 *pt1, struct pt1_table *table) 587 { 588 int i; 589 590 for (i = 0; i < PT1_NR_BUFS; i++) 591 pt1_cleanup_buffer(pt1, &table->bufs[i]); 592 593 pt1_free_page(pt1, table->page, table->addr); 594 } 595 596 static int 597 pt1_init_table(struct pt1 *pt1, struct pt1_table *table, u32 *pfnp) 598 { 599 struct pt1_table_page *page; 600 dma_addr_t addr; 601 int i, ret; 602 u32 buf_pfn; 603 604 page = pt1_alloc_page(pt1, &addr, pfnp); 605 if (page == NULL) 606 return -ENOMEM; 607 608 for (i = 0; i < PT1_NR_BUFS; i++) { 609 ret = pt1_init_buffer(pt1, &table->bufs[i], &buf_pfn); 610 if (ret < 0) 611 goto err; 612 613 page->buf_pfns[i] = cpu_to_le32(buf_pfn); 614 } 615 616 pt1_increment_table_count(pt1); 617 table->page = page; 618 table->addr = addr; 619 return 0; 620 621 err: 622 while (i--) 623 pt1_cleanup_buffer(pt1, &table->bufs[i]); 624 625 pt1_free_page(pt1, page, addr); 626 return ret; 627 } 628 629 static void pt1_cleanup_tables(struct pt1 *pt1) 630 { 631 struct pt1_table *tables; 632 int i; 633 634 tables = pt1->tables; 635 pt1_unregister_tables(pt1); 636 637 for (i = 0; i < pt1_nr_tables; i++) 638 pt1_cleanup_table(pt1, &tables[i]); 639 640 vfree(tables); 641 } 642 643 static int pt1_init_tables(struct pt1 *pt1) 644 { 645 struct pt1_table *tables; 646 int i, ret; 647 u32 first_pfn, pfn; 648 649 if (!pt1_nr_tables) 650 return 0; 651 652 tables = vmalloc(array_size(pt1_nr_tables, sizeof(struct pt1_table))); 653 if (tables == NULL) 654 return -ENOMEM; 655 656 pt1_init_table_count(pt1); 657 658 i = 0; 659 ret = pt1_init_table(pt1, &tables[0], &first_pfn); 660 if (ret) 661 goto err; 662 i++; 663 664 while (i < pt1_nr_tables) { 665 ret = pt1_init_table(pt1, &tables[i], &pfn); 666 if (ret) 667 goto err; 668 tables[i - 1].page->next_pfn = cpu_to_le32(pfn); 669 i++; 670 } 671 672 tables[pt1_nr_tables - 1].page->next_pfn = cpu_to_le32(first_pfn); 673 674 pt1_register_tables(pt1, first_pfn); 675 pt1->tables = tables; 676 return 0; 677 678 err: 679 while (i--) 680 pt1_cleanup_table(pt1, &tables[i]); 681 682 vfree(tables); 683 return ret; 684 } 685 686 static int pt1_start_polling(struct pt1 *pt1) 687 { 688 int ret = 0; 689 690 mutex_lock(&pt1->lock); 691 if (!pt1->kthread) { 692 pt1->kthread = kthread_run(pt1_thread, pt1, "earth-pt1"); 693 if (IS_ERR(pt1->kthread)) { 694 ret = PTR_ERR(pt1->kthread); 695 pt1->kthread = NULL; 696 } 697 } 698 mutex_unlock(&pt1->lock); 699 return ret; 700 } 701 702 static int pt1_start_feed(struct dvb_demux_feed *feed) 703 { 704 struct pt1_adapter *adap; 705 adap = container_of(feed->demux, struct pt1_adapter, demux); 706 if (!adap->users++) { 707 int ret; 708 709 ret = pt1_start_polling(adap->pt1); 710 if (ret) 711 return ret; 712 pt1_set_stream(adap->pt1, adap->index, 1); 713 } 714 return 0; 715 } 716 717 static void pt1_stop_polling(struct pt1 *pt1) 718 { 719 int i, count; 720 721 mutex_lock(&pt1->lock); 722 for (i = 0, count = 0; i < PT1_NR_ADAPS; i++) 723 count += pt1->adaps[i]->users; 724 725 if (count == 0 && pt1->kthread) { 726 kthread_stop(pt1->kthread); 727 pt1->kthread = NULL; 728 } 729 mutex_unlock(&pt1->lock); 730 } 731 732 static int pt1_stop_feed(struct dvb_demux_feed *feed) 733 { 734 struct pt1_adapter *adap; 735 adap = container_of(feed->demux, struct pt1_adapter, demux); 736 if (!--adap->users) { 737 pt1_set_stream(adap->pt1, adap->index, 0); 738 pt1_stop_polling(adap->pt1); 739 } 740 return 0; 741 } 742 743 static void 744 pt1_update_power(struct pt1 *pt1) 745 { 746 int bits; 747 int i; 748 struct pt1_adapter *adap; 749 static const int sleep_bits[] = { 750 1 << 4, 751 1 << 6 | 1 << 7, 752 1 << 5, 753 1 << 6 | 1 << 8, 754 }; 755 756 bits = pt1->power | !pt1->reset << 3; 757 mutex_lock(&pt1->lock); 758 for (i = 0; i < PT1_NR_ADAPS; i++) { 759 adap = pt1->adaps[i]; 760 switch (adap->voltage) { 761 case SEC_VOLTAGE_13: /* actually 11V */ 762 bits |= 1 << 2; 763 break; 764 case SEC_VOLTAGE_18: /* actually 15V */ 765 bits |= 1 << 1 | 1 << 2; 766 break; 767 default: 768 break; 769 } 770 771 /* XXX: The bits should be changed depending on adap->sleep. */ 772 bits |= sleep_bits[i]; 773 } 774 pt1_write_reg(pt1, 1, bits); 775 mutex_unlock(&pt1->lock); 776 } 777 778 static int pt1_set_voltage(struct dvb_frontend *fe, enum fe_sec_voltage voltage) 779 { 780 struct pt1_adapter *adap; 781 782 adap = container_of(fe->dvb, struct pt1_adapter, adap); 783 adap->voltage = voltage; 784 pt1_update_power(adap->pt1); 785 786 if (adap->orig_set_voltage) 787 return adap->orig_set_voltage(fe, voltage); 788 else 789 return 0; 790 } 791 792 static int pt1_sleep(struct dvb_frontend *fe) 793 { 794 struct pt1_adapter *adap; 795 int ret; 796 797 adap = container_of(fe->dvb, struct pt1_adapter, adap); 798 799 ret = 0; 800 if (adap->orig_sleep) 801 ret = adap->orig_sleep(fe); 802 803 adap->sleep = 1; 804 pt1_update_power(adap->pt1); 805 return ret; 806 } 807 808 static int pt1_wakeup(struct dvb_frontend *fe) 809 { 810 struct pt1_adapter *adap; 811 int ret; 812 813 adap = container_of(fe->dvb, struct pt1_adapter, adap); 814 adap->sleep = 0; 815 pt1_update_power(adap->pt1); 816 usleep_range(1000, 2000); 817 818 ret = config_demod(adap->demod_i2c_client, adap->pt1->fe_clk); 819 if (ret == 0 && adap->orig_init) 820 ret = adap->orig_init(fe); 821 return ret; 822 } 823 824 static void pt1_free_adapter(struct pt1_adapter *adap) 825 { 826 adap->demux.dmx.close(&adap->demux.dmx); 827 dvb_dmxdev_release(&adap->dmxdev); 828 dvb_dmx_release(&adap->demux); 829 dvb_unregister_adapter(&adap->adap); 830 free_page((unsigned long)adap->buf); 831 kfree(adap); 832 } 833 834 DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr); 835 836 static struct pt1_adapter * 837 pt1_alloc_adapter(struct pt1 *pt1) 838 { 839 struct pt1_adapter *adap; 840 void *buf; 841 struct dvb_adapter *dvb_adap; 842 struct dvb_demux *demux; 843 struct dmxdev *dmxdev; 844 int ret; 845 846 adap = kzalloc(sizeof(struct pt1_adapter), GFP_KERNEL); 847 if (!adap) { 848 ret = -ENOMEM; 849 goto err; 850 } 851 852 adap->pt1 = pt1; 853 854 adap->voltage = SEC_VOLTAGE_OFF; 855 adap->sleep = 1; 856 857 buf = (u8 *)__get_free_page(GFP_KERNEL); 858 if (!buf) { 859 ret = -ENOMEM; 860 goto err_kfree; 861 } 862 863 adap->buf = buf; 864 adap->upacket_count = 0; 865 adap->packet_count = 0; 866 adap->st_count = -1; 867 868 dvb_adap = &adap->adap; 869 dvb_adap->priv = adap; 870 ret = dvb_register_adapter(dvb_adap, DRIVER_NAME, THIS_MODULE, 871 &pt1->pdev->dev, adapter_nr); 872 if (ret < 0) 873 goto err_free_page; 874 875 demux = &adap->demux; 876 demux->dmx.capabilities = DMX_TS_FILTERING | DMX_SECTION_FILTERING; 877 demux->priv = adap; 878 demux->feednum = 256; 879 demux->filternum = 256; 880 demux->start_feed = pt1_start_feed; 881 demux->stop_feed = pt1_stop_feed; 882 demux->write_to_decoder = NULL; 883 ret = dvb_dmx_init(demux); 884 if (ret < 0) 885 goto err_unregister_adapter; 886 887 dmxdev = &adap->dmxdev; 888 dmxdev->filternum = 256; 889 dmxdev->demux = &demux->dmx; 890 dmxdev->capabilities = 0; 891 ret = dvb_dmxdev_init(dmxdev, dvb_adap); 892 if (ret < 0) 893 goto err_dmx_release; 894 895 return adap; 896 897 err_dmx_release: 898 dvb_dmx_release(demux); 899 err_unregister_adapter: 900 dvb_unregister_adapter(dvb_adap); 901 err_free_page: 902 free_page((unsigned long)buf); 903 err_kfree: 904 kfree(adap); 905 err: 906 return ERR_PTR(ret); 907 } 908 909 static void pt1_cleanup_adapters(struct pt1 *pt1) 910 { 911 int i; 912 for (i = 0; i < PT1_NR_ADAPS; i++) 913 pt1_free_adapter(pt1->adaps[i]); 914 } 915 916 static int pt1_init_adapters(struct pt1 *pt1) 917 { 918 int i; 919 struct pt1_adapter *adap; 920 int ret; 921 922 for (i = 0; i < PT1_NR_ADAPS; i++) { 923 adap = pt1_alloc_adapter(pt1); 924 if (IS_ERR(adap)) { 925 ret = PTR_ERR(adap); 926 goto err; 927 } 928 929 adap->index = i; 930 pt1->adaps[i] = adap; 931 } 932 return 0; 933 934 err: 935 while (i--) 936 pt1_free_adapter(pt1->adaps[i]); 937 938 return ret; 939 } 940 941 static void pt1_cleanup_frontend(struct pt1_adapter *adap) 942 { 943 dvb_unregister_frontend(adap->fe); 944 dvb_module_release(adap->tuner_i2c_client); 945 dvb_module_release(adap->demod_i2c_client); 946 } 947 948 static int pt1_init_frontend(struct pt1_adapter *adap, struct dvb_frontend *fe) 949 { 950 int ret; 951 952 adap->orig_set_voltage = fe->ops.set_voltage; 953 adap->orig_sleep = fe->ops.sleep; 954 adap->orig_init = fe->ops.init; 955 fe->ops.set_voltage = pt1_set_voltage; 956 fe->ops.sleep = pt1_sleep; 957 fe->ops.init = pt1_wakeup; 958 959 ret = dvb_register_frontend(&adap->adap, fe); 960 if (ret < 0) 961 return ret; 962 963 adap->fe = fe; 964 return 0; 965 } 966 967 static void pt1_cleanup_frontends(struct pt1 *pt1) 968 { 969 int i; 970 for (i = 0; i < PT1_NR_ADAPS; i++) 971 pt1_cleanup_frontend(pt1->adaps[i]); 972 } 973 974 static int pt1_init_frontends(struct pt1 *pt1) 975 { 976 int i; 977 int ret; 978 979 for (i = 0; i < ARRAY_SIZE(pt1_configs); i++) { 980 const struct i2c_board_info *info; 981 struct tc90522_config dcfg; 982 struct i2c_client *cl; 983 984 info = &pt1_configs[i].demod_info; 985 dcfg = pt1_configs[i].demod_cfg; 986 dcfg.tuner_i2c = NULL; 987 988 ret = -ENODEV; 989 cl = dvb_module_probe("tc90522", info->type, &pt1->i2c_adap, 990 info->addr, &dcfg); 991 if (!cl) 992 goto fe_unregister; 993 pt1->adaps[i]->demod_i2c_client = cl; 994 995 if (!strncmp(cl->name, TC90522_I2C_DEV_SAT, 996 strlen(TC90522_I2C_DEV_SAT))) { 997 struct qm1d1b0004_config tcfg; 998 999 info = &pt1_configs[i].tuner_info; 1000 tcfg = pt1_configs[i].tuner_cfg.qm1d1b0004; 1001 tcfg.fe = dcfg.fe; 1002 cl = dvb_module_probe("qm1d1b0004", 1003 info->type, dcfg.tuner_i2c, 1004 info->addr, &tcfg); 1005 } else { 1006 struct dvb_pll_config tcfg; 1007 1008 info = &pt1_configs[i].tuner_info; 1009 tcfg = pt1_configs[i].tuner_cfg.tda6651; 1010 tcfg.fe = dcfg.fe; 1011 cl = dvb_module_probe("dvb_pll", 1012 info->type, dcfg.tuner_i2c, 1013 info->addr, &tcfg); 1014 } 1015 if (!cl) 1016 goto demod_release; 1017 pt1->adaps[i]->tuner_i2c_client = cl; 1018 1019 ret = pt1_init_frontend(pt1->adaps[i], dcfg.fe); 1020 if (ret < 0) 1021 goto tuner_release; 1022 } 1023 1024 ret = pt1_demod_block_init(pt1); 1025 if (ret < 0) 1026 goto fe_unregister; 1027 1028 return 0; 1029 1030 tuner_release: 1031 dvb_module_release(pt1->adaps[i]->tuner_i2c_client); 1032 demod_release: 1033 dvb_module_release(pt1->adaps[i]->demod_i2c_client); 1034 fe_unregister: 1035 dev_warn(&pt1->pdev->dev, "failed to init FE(%d).\n", i); 1036 i--; 1037 for (; i >= 0; i--) { 1038 dvb_unregister_frontend(pt1->adaps[i]->fe); 1039 dvb_module_release(pt1->adaps[i]->tuner_i2c_client); 1040 dvb_module_release(pt1->adaps[i]->demod_i2c_client); 1041 } 1042 return ret; 1043 } 1044 1045 static void pt1_i2c_emit(struct pt1 *pt1, int addr, int busy, int read_enable, 1046 int clock, int data, int next_addr) 1047 { 1048 pt1_write_reg(pt1, 4, addr << 18 | busy << 13 | read_enable << 12 | 1049 !clock << 11 | !data << 10 | next_addr); 1050 } 1051 1052 static void pt1_i2c_write_bit(struct pt1 *pt1, int addr, int *addrp, int data) 1053 { 1054 pt1_i2c_emit(pt1, addr, 1, 0, 0, data, addr + 1); 1055 pt1_i2c_emit(pt1, addr + 1, 1, 0, 1, data, addr + 2); 1056 pt1_i2c_emit(pt1, addr + 2, 1, 0, 0, data, addr + 3); 1057 *addrp = addr + 3; 1058 } 1059 1060 static void pt1_i2c_read_bit(struct pt1 *pt1, int addr, int *addrp) 1061 { 1062 pt1_i2c_emit(pt1, addr, 1, 0, 0, 1, addr + 1); 1063 pt1_i2c_emit(pt1, addr + 1, 1, 0, 1, 1, addr + 2); 1064 pt1_i2c_emit(pt1, addr + 2, 1, 1, 1, 1, addr + 3); 1065 pt1_i2c_emit(pt1, addr + 3, 1, 0, 0, 1, addr + 4); 1066 *addrp = addr + 4; 1067 } 1068 1069 static void pt1_i2c_write_byte(struct pt1 *pt1, int addr, int *addrp, int data) 1070 { 1071 int i; 1072 for (i = 0; i < 8; i++) 1073 pt1_i2c_write_bit(pt1, addr, &addr, data >> (7 - i) & 1); 1074 pt1_i2c_write_bit(pt1, addr, &addr, 1); 1075 *addrp = addr; 1076 } 1077 1078 static void pt1_i2c_read_byte(struct pt1 *pt1, int addr, int *addrp, int last) 1079 { 1080 int i; 1081 for (i = 0; i < 8; i++) 1082 pt1_i2c_read_bit(pt1, addr, &addr); 1083 pt1_i2c_write_bit(pt1, addr, &addr, last); 1084 *addrp = addr; 1085 } 1086 1087 static void pt1_i2c_prepare(struct pt1 *pt1, int addr, int *addrp) 1088 { 1089 pt1_i2c_emit(pt1, addr, 1, 0, 1, 1, addr + 1); 1090 pt1_i2c_emit(pt1, addr + 1, 1, 0, 1, 0, addr + 2); 1091 pt1_i2c_emit(pt1, addr + 2, 1, 0, 0, 0, addr + 3); 1092 *addrp = addr + 3; 1093 } 1094 1095 static void 1096 pt1_i2c_write_msg(struct pt1 *pt1, int addr, int *addrp, struct i2c_msg *msg) 1097 { 1098 int i; 1099 pt1_i2c_prepare(pt1, addr, &addr); 1100 pt1_i2c_write_byte(pt1, addr, &addr, msg->addr << 1); 1101 for (i = 0; i < msg->len; i++) 1102 pt1_i2c_write_byte(pt1, addr, &addr, msg->buf[i]); 1103 *addrp = addr; 1104 } 1105 1106 static void 1107 pt1_i2c_read_msg(struct pt1 *pt1, int addr, int *addrp, struct i2c_msg *msg) 1108 { 1109 int i; 1110 pt1_i2c_prepare(pt1, addr, &addr); 1111 pt1_i2c_write_byte(pt1, addr, &addr, msg->addr << 1 | 1); 1112 for (i = 0; i < msg->len; i++) 1113 pt1_i2c_read_byte(pt1, addr, &addr, i == msg->len - 1); 1114 *addrp = addr; 1115 } 1116 1117 static int pt1_i2c_end(struct pt1 *pt1, int addr) 1118 { 1119 pt1_i2c_emit(pt1, addr, 1, 0, 0, 0, addr + 1); 1120 pt1_i2c_emit(pt1, addr + 1, 1, 0, 1, 0, addr + 2); 1121 pt1_i2c_emit(pt1, addr + 2, 1, 0, 1, 1, 0); 1122 1123 pt1_write_reg(pt1, 0, 0x00000004); 1124 do { 1125 if (signal_pending(current)) 1126 return -EINTR; 1127 usleep_range(1000, 2000); 1128 } while (pt1_read_reg(pt1, 0) & 0x00000080); 1129 return 0; 1130 } 1131 1132 static void pt1_i2c_begin(struct pt1 *pt1, int *addrp) 1133 { 1134 int addr; 1135 addr = 0; 1136 1137 pt1_i2c_emit(pt1, addr, 0, 0, 1, 1, addr /* itself */); 1138 addr = addr + 1; 1139 1140 if (!pt1->i2c_running) { 1141 pt1_i2c_emit(pt1, addr, 1, 0, 1, 1, addr + 1); 1142 pt1_i2c_emit(pt1, addr + 1, 1, 0, 1, 0, addr + 2); 1143 addr = addr + 2; 1144 pt1->i2c_running = 1; 1145 } 1146 *addrp = addr; 1147 } 1148 1149 static int pt1_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) 1150 { 1151 struct pt1 *pt1; 1152 int i; 1153 struct i2c_msg *msg, *next_msg; 1154 int addr, ret; 1155 u16 len; 1156 u32 word; 1157 1158 pt1 = i2c_get_adapdata(adap); 1159 1160 for (i = 0; i < num; i++) { 1161 msg = &msgs[i]; 1162 if (msg->flags & I2C_M_RD) 1163 return -ENOTSUPP; 1164 1165 if (i + 1 < num) 1166 next_msg = &msgs[i + 1]; 1167 else 1168 next_msg = NULL; 1169 1170 if (next_msg && next_msg->flags & I2C_M_RD) { 1171 i++; 1172 1173 len = next_msg->len; 1174 if (len > 4) 1175 return -ENOTSUPP; 1176 1177 pt1_i2c_begin(pt1, &addr); 1178 pt1_i2c_write_msg(pt1, addr, &addr, msg); 1179 pt1_i2c_read_msg(pt1, addr, &addr, next_msg); 1180 ret = pt1_i2c_end(pt1, addr); 1181 if (ret < 0) 1182 return ret; 1183 1184 word = pt1_read_reg(pt1, 2); 1185 while (len--) { 1186 next_msg->buf[len] = word; 1187 word >>= 8; 1188 } 1189 } else { 1190 pt1_i2c_begin(pt1, &addr); 1191 pt1_i2c_write_msg(pt1, addr, &addr, msg); 1192 ret = pt1_i2c_end(pt1, addr); 1193 if (ret < 0) 1194 return ret; 1195 } 1196 } 1197 1198 return num; 1199 } 1200 1201 static u32 pt1_i2c_func(struct i2c_adapter *adap) 1202 { 1203 return I2C_FUNC_I2C; 1204 } 1205 1206 static const struct i2c_algorithm pt1_i2c_algo = { 1207 .master_xfer = pt1_i2c_xfer, 1208 .functionality = pt1_i2c_func, 1209 }; 1210 1211 static void pt1_i2c_wait(struct pt1 *pt1) 1212 { 1213 int i; 1214 for (i = 0; i < 128; i++) 1215 pt1_i2c_emit(pt1, 0, 0, 0, 1, 1, 0); 1216 } 1217 1218 static void pt1_i2c_init(struct pt1 *pt1) 1219 { 1220 int i; 1221 for (i = 0; i < 1024; i++) 1222 pt1_i2c_emit(pt1, i, 0, 0, 1, 1, 0); 1223 } 1224 1225 #ifdef CONFIG_PM_SLEEP 1226 1227 static int pt1_suspend(struct device *dev) 1228 { 1229 struct pci_dev *pdev = to_pci_dev(dev); 1230 struct pt1 *pt1 = pci_get_drvdata(pdev); 1231 1232 pt1_init_streams(pt1); 1233 pt1_disable_ram(pt1); 1234 pt1->power = 0; 1235 pt1->reset = 1; 1236 pt1_update_power(pt1); 1237 return 0; 1238 } 1239 1240 static int pt1_resume(struct device *dev) 1241 { 1242 struct pci_dev *pdev = to_pci_dev(dev); 1243 struct pt1 *pt1 = pci_get_drvdata(pdev); 1244 int ret; 1245 int i; 1246 1247 pt1->power = 0; 1248 pt1->reset = 1; 1249 pt1_update_power(pt1); 1250 1251 pt1_i2c_init(pt1); 1252 pt1_i2c_wait(pt1); 1253 1254 ret = pt1_sync(pt1); 1255 if (ret < 0) 1256 goto resume_err; 1257 1258 pt1_identify(pt1); 1259 1260 ret = pt1_unlock(pt1); 1261 if (ret < 0) 1262 goto resume_err; 1263 1264 ret = pt1_reset_pci(pt1); 1265 if (ret < 0) 1266 goto resume_err; 1267 1268 ret = pt1_reset_ram(pt1); 1269 if (ret < 0) 1270 goto resume_err; 1271 1272 ret = pt1_enable_ram(pt1); 1273 if (ret < 0) 1274 goto resume_err; 1275 1276 pt1_init_streams(pt1); 1277 1278 pt1->power = 1; 1279 pt1_update_power(pt1); 1280 msleep(20); 1281 1282 pt1->reset = 0; 1283 pt1_update_power(pt1); 1284 usleep_range(1000, 2000); 1285 1286 ret = pt1_demod_block_init(pt1); 1287 if (ret < 0) 1288 goto resume_err; 1289 1290 for (i = 0; i < PT1_NR_ADAPS; i++) 1291 dvb_frontend_reinitialise(pt1->adaps[i]->fe); 1292 1293 pt1_init_table_count(pt1); 1294 for (i = 0; i < pt1_nr_tables; i++) { 1295 int j; 1296 1297 for (j = 0; j < PT1_NR_BUFS; j++) 1298 pt1->tables[i].bufs[j].page->upackets[PT1_NR_UPACKETS-1] 1299 = 0; 1300 pt1_increment_table_count(pt1); 1301 } 1302 pt1_register_tables(pt1, pt1->tables[0].addr >> PT1_PAGE_SHIFT); 1303 1304 pt1->table_index = 0; 1305 pt1->buf_index = 0; 1306 for (i = 0; i < PT1_NR_ADAPS; i++) { 1307 pt1->adaps[i]->upacket_count = 0; 1308 pt1->adaps[i]->packet_count = 0; 1309 pt1->adaps[i]->st_count = -1; 1310 } 1311 1312 return 0; 1313 1314 resume_err: 1315 dev_info(&pt1->pdev->dev, "failed to resume PT1/PT2."); 1316 return 0; /* resume anyway */ 1317 } 1318 1319 #endif /* CONFIG_PM_SLEEP */ 1320 1321 static void pt1_remove(struct pci_dev *pdev) 1322 { 1323 struct pt1 *pt1; 1324 void __iomem *regs; 1325 1326 pt1 = pci_get_drvdata(pdev); 1327 regs = pt1->regs; 1328 1329 if (pt1->kthread) 1330 kthread_stop(pt1->kthread); 1331 pt1_cleanup_tables(pt1); 1332 pt1_cleanup_frontends(pt1); 1333 pt1_disable_ram(pt1); 1334 pt1->power = 0; 1335 pt1->reset = 1; 1336 pt1_update_power(pt1); 1337 pt1_cleanup_adapters(pt1); 1338 i2c_del_adapter(&pt1->i2c_adap); 1339 kfree(pt1); 1340 pci_iounmap(pdev, regs); 1341 pci_release_regions(pdev); 1342 pci_disable_device(pdev); 1343 } 1344 1345 static int pt1_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1346 { 1347 int ret; 1348 void __iomem *regs; 1349 struct pt1 *pt1; 1350 struct i2c_adapter *i2c_adap; 1351 1352 ret = pci_enable_device(pdev); 1353 if (ret < 0) 1354 goto err; 1355 1356 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 1357 if (ret < 0) 1358 goto err_pci_disable_device; 1359 1360 pci_set_master(pdev); 1361 1362 ret = pci_request_regions(pdev, DRIVER_NAME); 1363 if (ret < 0) 1364 goto err_pci_disable_device; 1365 1366 regs = pci_iomap(pdev, 0, 0); 1367 if (!regs) { 1368 ret = -EIO; 1369 goto err_pci_release_regions; 1370 } 1371 1372 pt1 = kzalloc(sizeof(struct pt1), GFP_KERNEL); 1373 if (!pt1) { 1374 ret = -ENOMEM; 1375 goto err_pci_iounmap; 1376 } 1377 1378 mutex_init(&pt1->lock); 1379 pt1->pdev = pdev; 1380 pt1->regs = regs; 1381 pt1->fe_clk = (pdev->device == 0x211a) ? 1382 PT1_FE_CLK_20MHZ : PT1_FE_CLK_25MHZ; 1383 pci_set_drvdata(pdev, pt1); 1384 1385 ret = pt1_init_adapters(pt1); 1386 if (ret < 0) 1387 goto err_kfree; 1388 1389 mutex_init(&pt1->lock); 1390 1391 pt1->power = 0; 1392 pt1->reset = 1; 1393 pt1_update_power(pt1); 1394 1395 i2c_adap = &pt1->i2c_adap; 1396 i2c_adap->algo = &pt1_i2c_algo; 1397 i2c_adap->algo_data = NULL; 1398 i2c_adap->dev.parent = &pdev->dev; 1399 strscpy(i2c_adap->name, DRIVER_NAME, sizeof(i2c_adap->name)); 1400 i2c_set_adapdata(i2c_adap, pt1); 1401 ret = i2c_add_adapter(i2c_adap); 1402 if (ret < 0) 1403 goto err_pt1_cleanup_adapters; 1404 1405 pt1_i2c_init(pt1); 1406 pt1_i2c_wait(pt1); 1407 1408 ret = pt1_sync(pt1); 1409 if (ret < 0) 1410 goto err_i2c_del_adapter; 1411 1412 pt1_identify(pt1); 1413 1414 ret = pt1_unlock(pt1); 1415 if (ret < 0) 1416 goto err_i2c_del_adapter; 1417 1418 ret = pt1_reset_pci(pt1); 1419 if (ret < 0) 1420 goto err_i2c_del_adapter; 1421 1422 ret = pt1_reset_ram(pt1); 1423 if (ret < 0) 1424 goto err_i2c_del_adapter; 1425 1426 ret = pt1_enable_ram(pt1); 1427 if (ret < 0) 1428 goto err_i2c_del_adapter; 1429 1430 pt1_init_streams(pt1); 1431 1432 pt1->power = 1; 1433 pt1_update_power(pt1); 1434 msleep(20); 1435 1436 pt1->reset = 0; 1437 pt1_update_power(pt1); 1438 usleep_range(1000, 2000); 1439 1440 ret = pt1_init_frontends(pt1); 1441 if (ret < 0) 1442 goto err_pt1_disable_ram; 1443 1444 ret = pt1_init_tables(pt1); 1445 if (ret < 0) 1446 goto err_pt1_cleanup_frontends; 1447 1448 return 0; 1449 1450 err_pt1_cleanup_frontends: 1451 pt1_cleanup_frontends(pt1); 1452 err_pt1_disable_ram: 1453 pt1_disable_ram(pt1); 1454 pt1->power = 0; 1455 pt1->reset = 1; 1456 pt1_update_power(pt1); 1457 err_i2c_del_adapter: 1458 i2c_del_adapter(i2c_adap); 1459 err_pt1_cleanup_adapters: 1460 pt1_cleanup_adapters(pt1); 1461 err_kfree: 1462 kfree(pt1); 1463 err_pci_iounmap: 1464 pci_iounmap(pdev, regs); 1465 err_pci_release_regions: 1466 pci_release_regions(pdev); 1467 err_pci_disable_device: 1468 pci_disable_device(pdev); 1469 err: 1470 return ret; 1471 1472 } 1473 1474 static const struct pci_device_id pt1_id_table[] = { 1475 { PCI_DEVICE(0x10ee, 0x211a) }, 1476 { PCI_DEVICE(0x10ee, 0x222a) }, 1477 { }, 1478 }; 1479 MODULE_DEVICE_TABLE(pci, pt1_id_table); 1480 1481 static SIMPLE_DEV_PM_OPS(pt1_pm_ops, pt1_suspend, pt1_resume); 1482 1483 static struct pci_driver pt1_driver = { 1484 .name = DRIVER_NAME, 1485 .probe = pt1_probe, 1486 .remove = pt1_remove, 1487 .id_table = pt1_id_table, 1488 .driver.pm = &pt1_pm_ops, 1489 }; 1490 1491 module_pci_driver(pt1_driver); 1492 1493 MODULE_AUTHOR("Takahito HIRANO <hiranotaka@zng.info>"); 1494 MODULE_DESCRIPTION("Earthsoft PT1/PT2 Driver"); 1495 MODULE_LICENSE("GPL"); 1496