1 /* 2 * ngene.h: nGene PCIe bridge driver 3 * 4 * Copyright (C) 2005-2007 Micronas 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * version 2 only, as published by the Free Software Foundation. 9 * 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * To obtain the license, point your browser to 17 * http://www.gnu.org/copyleft/gpl.html 18 */ 19 20 #ifndef _NGENE_H_ 21 #define _NGENE_H_ 22 23 #include <linux/types.h> 24 #include <linux/sched.h> 25 #include <linux/interrupt.h> 26 #include <linux/i2c.h> 27 #include <asm/dma.h> 28 #include <linux/scatterlist.h> 29 30 #include <linux/dvb/frontend.h> 31 32 #include "dmxdev.h" 33 #include "dvbdev.h" 34 #include "dvb_demux.h" 35 #include "dvb_ca_en50221.h" 36 #include "dvb_frontend.h" 37 #include "dvb_ringbuffer.h" 38 #include "dvb_net.h" 39 #include "cxd2099.h" 40 41 #define DEVICE_NAME "ngene" 42 43 #define NGENE_VID 0x18c3 44 #define NGENE_PID 0x0720 45 46 #ifndef VIDEO_CAP_VC1 47 #define VIDEO_CAP_AVC 128 48 #define VIDEO_CAP_H264 128 49 #define VIDEO_CAP_VC1 256 50 #define VIDEO_CAP_WMV9 256 51 #define VIDEO_CAP_MPEG4 512 52 #endif 53 54 enum STREAM { 55 STREAM_VIDEOIN1 = 0, /* ITU656 or TS Input */ 56 STREAM_VIDEOIN2, 57 STREAM_AUDIOIN1, /* I2S or SPI Input */ 58 STREAM_AUDIOIN2, 59 STREAM_AUDIOOUT, 60 MAX_STREAM 61 }; 62 63 enum SMODE_BITS { 64 SMODE_AUDIO_SPDIF = 0x20, 65 SMODE_AVSYNC = 0x10, 66 SMODE_TRANSPORT_STREAM = 0x08, 67 SMODE_AUDIO_CAPTURE = 0x04, 68 SMODE_VBI_CAPTURE = 0x02, 69 SMODE_VIDEO_CAPTURE = 0x01 70 }; 71 72 enum STREAM_FLAG_BITS { 73 SFLAG_CHROMA_FORMAT_2COMP = 0x01, /* Chroma Format : 2's complement */ 74 SFLAG_CHROMA_FORMAT_OFFSET = 0x00, /* Chroma Format : Binary offset */ 75 SFLAG_ORDER_LUMA_CHROMA = 0x02, /* Byte order: Y,Cb,Y,Cr */ 76 SFLAG_ORDER_CHROMA_LUMA = 0x00, /* Byte order: Cb,Y,Cr,Y */ 77 SFLAG_COLORBAR = 0x04, /* Select colorbar */ 78 }; 79 80 #define PROGRAM_ROM 0x0000 81 #define PROGRAM_SRAM 0x1000 82 #define PERIPHERALS0 0x8000 83 #define PERIPHERALS1 0x9000 84 #define SHARED_BUFFER 0xC000 85 86 #define HOST_TO_NGENE (SHARED_BUFFER+0x0000) 87 #define NGENE_TO_HOST (SHARED_BUFFER+0x0100) 88 #define NGENE_COMMAND (SHARED_BUFFER+0x0200) 89 #define NGENE_COMMAND_HI (SHARED_BUFFER+0x0204) 90 #define NGENE_STATUS (SHARED_BUFFER+0x0208) 91 #define NGENE_STATUS_HI (SHARED_BUFFER+0x020C) 92 #define NGENE_EVENT (SHARED_BUFFER+0x0210) 93 #define NGENE_EVENT_HI (SHARED_BUFFER+0x0214) 94 #define VARIABLES (SHARED_BUFFER+0x0210) 95 96 #define NGENE_INT_COUNTS (SHARED_BUFFER+0x0260) 97 #define NGENE_INT_ENABLE (SHARED_BUFFER+0x0264) 98 #define NGENE_VBI_LINE_COUNT (SHARED_BUFFER+0x0268) 99 100 #define BUFFER_GP_XMIT (SHARED_BUFFER+0x0800) 101 #define BUFFER_GP_RECV (SHARED_BUFFER+0x0900) 102 #define EEPROM_AREA (SHARED_BUFFER+0x0A00) 103 104 #define SG_V_IN_1 (SHARED_BUFFER+0x0A80) 105 #define SG_VBI_1 (SHARED_BUFFER+0x0B00) 106 #define SG_A_IN_1 (SHARED_BUFFER+0x0B80) 107 #define SG_V_IN_2 (SHARED_BUFFER+0x0C00) 108 #define SG_VBI_2 (SHARED_BUFFER+0x0C80) 109 #define SG_A_IN_2 (SHARED_BUFFER+0x0D00) 110 #define SG_V_OUT (SHARED_BUFFER+0x0D80) 111 #define SG_A_OUT2 (SHARED_BUFFER+0x0E00) 112 113 #define DATA_A_IN_1 (SHARED_BUFFER+0x0E80) 114 #define DATA_A_IN_2 (SHARED_BUFFER+0x0F00) 115 #define DATA_A_OUT (SHARED_BUFFER+0x0F80) 116 #define DATA_V_IN_1 (SHARED_BUFFER+0x1000) 117 #define DATA_V_IN_2 (SHARED_BUFFER+0x2000) 118 #define DATA_V_OUT (SHARED_BUFFER+0x3000) 119 120 #define DATA_FIFO_AREA (SHARED_BUFFER+0x1000) 121 122 #define TIMESTAMPS 0xA000 123 #define SCRATCHPAD 0xA080 124 #define FORCE_INT 0xA088 125 #define FORCE_NMI 0xA090 126 #define INT_STATUS 0xA0A0 127 128 #define DEV_VER 0x9004 129 130 #define FW_DEBUG_DEFAULT (PROGRAM_SRAM+0x00FF) 131 132 struct SG_ADDR { 133 u64 start; 134 u64 curr; 135 u16 curr_ptr; 136 u16 elements; 137 u32 pad[3]; 138 } __attribute__ ((__packed__)); 139 140 struct SHARED_MEMORY { 141 /* C000 */ 142 u32 HostToNgene[64]; 143 144 /* C100 */ 145 u32 NgeneToHost[64]; 146 147 /* C200 */ 148 u64 NgeneCommand; 149 u64 NgeneStatus; 150 u64 NgeneEvent; 151 152 /* C210 */ 153 u8 pad1[0xc260 - 0xc218]; 154 155 /* C260 */ 156 u32 IntCounts; 157 u32 IntEnable; 158 159 /* C268 */ 160 u8 pad2[0xd000 - 0xc268]; 161 162 } __attribute__ ((__packed__)); 163 164 struct BUFFER_STREAM_RESULTS { 165 u32 Clock; /* Stream time in 100ns units */ 166 u16 RemainingLines; /* Remaining lines in this field. 167 0 for complete field */ 168 u8 FieldCount; /* Video field number */ 169 u8 Flags; /* Bit 7 = Done, Bit 6 = seen, Bit 5 = overflow, 170 Bit 0 = FieldID */ 171 u16 BlockCount; /* Audio block count (unused) */ 172 u8 Reserved[2]; 173 u32 DTOUpdate; 174 } __attribute__ ((__packed__)); 175 176 struct HW_SCATTER_GATHER_ELEMENT { 177 u64 Address; 178 u32 Length; 179 u32 Reserved; 180 } __attribute__ ((__packed__)); 181 182 struct BUFFER_HEADER { 183 u64 Next; 184 struct BUFFER_STREAM_RESULTS SR; 185 186 u32 Number_of_entries_1; 187 u32 Reserved5; 188 u64 Address_of_first_entry_1; 189 190 u32 Number_of_entries_2; 191 u32 Reserved7; 192 u64 Address_of_first_entry_2; 193 } __attribute__ ((__packed__)); 194 195 struct EVENT_BUFFER { 196 u32 TimeStamp; 197 u8 GPIOStatus; 198 u8 UARTStatus; 199 u8 RXCharacter; 200 u8 EventStatus; 201 u32 Reserved[2]; 202 } __attribute__ ((__packed__)); 203 204 /* Firmware commands. */ 205 206 enum OPCODES { 207 CMD_NOP = 0, 208 CMD_FWLOAD_PREPARE = 0x01, 209 CMD_FWLOAD_FINISH = 0x02, 210 CMD_I2C_READ = 0x03, 211 CMD_I2C_WRITE = 0x04, 212 213 CMD_I2C_WRITE_NOSTOP = 0x05, 214 CMD_I2C_CONTINUE_WRITE = 0x06, 215 CMD_I2C_CONTINUE_WRITE_NOSTOP = 0x07, 216 217 CMD_DEBUG_OUTPUT = 0x09, 218 219 CMD_CONTROL = 0x10, 220 CMD_CONFIGURE_BUFFER = 0x11, 221 CMD_CONFIGURE_FREE_BUFFER = 0x12, 222 223 CMD_SPI_READ = 0x13, 224 CMD_SPI_WRITE = 0x14, 225 226 CMD_MEM_READ = 0x20, 227 CMD_MEM_WRITE = 0x21, 228 CMD_SFR_READ = 0x22, 229 CMD_SFR_WRITE = 0x23, 230 CMD_IRAM_READ = 0x24, 231 CMD_IRAM_WRITE = 0x25, 232 CMD_SET_GPIO_PIN = 0x26, 233 CMD_SET_GPIO_INT = 0x27, 234 CMD_CONFIGURE_UART = 0x28, 235 CMD_WRITE_UART = 0x29, 236 MAX_CMD 237 }; 238 239 enum RESPONSES { 240 OK = 0, 241 ERROR = 1 242 }; 243 244 struct FW_HEADER { 245 u8 Opcode; 246 u8 Length; 247 } __attribute__ ((__packed__)); 248 249 struct FW_I2C_WRITE { 250 struct FW_HEADER hdr; 251 u8 Device; 252 u8 Data[250]; 253 } __attribute__ ((__packed__)); 254 255 struct FW_I2C_CONTINUE_WRITE { 256 struct FW_HEADER hdr; 257 u8 Data[250]; 258 } __attribute__ ((__packed__)); 259 260 struct FW_I2C_READ { 261 struct FW_HEADER hdr; 262 u8 Device; 263 u8 Data[252]; /* followed by two bytes of read data count */ 264 } __attribute__ ((__packed__)); 265 266 struct FW_SPI_WRITE { 267 struct FW_HEADER hdr; 268 u8 ModeSelect; 269 u8 Data[250]; 270 } __attribute__ ((__packed__)); 271 272 struct FW_SPI_READ { 273 struct FW_HEADER hdr; 274 u8 ModeSelect; 275 u8 Data[252]; /* followed by two bytes of read data count */ 276 } __attribute__ ((__packed__)); 277 278 struct FW_FWLOAD_PREPARE { 279 struct FW_HEADER hdr; 280 } __attribute__ ((__packed__)); 281 282 struct FW_FWLOAD_FINISH { 283 struct FW_HEADER hdr; 284 u16 Address; /* address of final block */ 285 u16 Length; 286 } __attribute__ ((__packed__)); 287 288 /* 289 * Meaning of FW_STREAM_CONTROL::Mode bits: 290 * Bit 7: Loopback PEXin to PEXout using TVOut channel 291 * Bit 6: AVLOOP 292 * Bit 5: Audio select; 0=I2S, 1=SPDIF 293 * Bit 4: AVSYNC 294 * Bit 3: Enable transport stream 295 * Bit 2: Enable audio capture 296 * Bit 1: Enable ITU-Video VBI capture 297 * Bit 0: Enable ITU-Video capture 298 * 299 * Meaning of FW_STREAM_CONTROL::Control bits (see UVI1_CTL) 300 * Bit 7: continuous capture 301 * Bit 6: capture one field 302 * Bit 5: capture one frame 303 * Bit 4: unused 304 * Bit 3: starting field; 0=odd, 1=even 305 * Bit 2: sample size; 0=8-bit, 1=10-bit 306 * Bit 1: data format; 0=UYVY, 1=YUY2 307 * Bit 0: resets buffer pointers 308 */ 309 310 enum FSC_MODE_BITS { 311 SMODE_LOOPBACK = 0x80, 312 SMODE_AVLOOP = 0x40, 313 _SMODE_AUDIO_SPDIF = 0x20, 314 _SMODE_AVSYNC = 0x10, 315 _SMODE_TRANSPORT_STREAM = 0x08, 316 _SMODE_AUDIO_CAPTURE = 0x04, 317 _SMODE_VBI_CAPTURE = 0x02, 318 _SMODE_VIDEO_CAPTURE = 0x01 319 }; 320 321 322 /* Meaning of FW_STREAM_CONTROL::Stream bits: 323 * Bit 3: Audio sample count: 0 = relative, 1 = absolute 324 * Bit 2: color bar select; 1=color bars, 0=CV3 decoder 325 * Bits 1-0: stream select, UVI1, UVI2, TVOUT 326 */ 327 328 struct FW_STREAM_CONTROL { 329 struct FW_HEADER hdr; 330 u8 Stream; /* Stream number (UVI1, UVI2, TVOUT) */ 331 u8 Control; /* Value written to UVI1_CTL */ 332 u8 Mode; /* Controls clock source */ 333 u8 SetupDataLen; /* Length of setup data, MSB=1 write 334 backwards */ 335 u16 CaptureBlockCount; /* Blocks (a 256 Bytes) to capture per buffer 336 for TS and Audio */ 337 u64 Buffer_Address; /* Address of first buffer header */ 338 u16 BytesPerVideoLine; 339 u16 MaxLinesPerField; 340 u16 MinLinesPerField; 341 u16 Reserved_1; 342 u16 BytesPerVBILine; 343 u16 MaxVBILinesPerField; 344 u16 MinVBILinesPerField; 345 u16 SetupDataAddr; /* ngene relative address of setup data */ 346 u8 SetupData[32]; /* setup data */ 347 } __attribute__((__packed__)); 348 349 #define AUDIO_BLOCK_SIZE 256 350 #define TS_BLOCK_SIZE 256 351 352 struct FW_MEM_READ { 353 struct FW_HEADER hdr; 354 u16 address; 355 } __attribute__ ((__packed__)); 356 357 struct FW_MEM_WRITE { 358 struct FW_HEADER hdr; 359 u16 address; 360 u8 data; 361 } __attribute__ ((__packed__)); 362 363 struct FW_SFR_IRAM_READ { 364 struct FW_HEADER hdr; 365 u8 address; 366 } __attribute__ ((__packed__)); 367 368 struct FW_SFR_IRAM_WRITE { 369 struct FW_HEADER hdr; 370 u8 address; 371 u8 data; 372 } __attribute__ ((__packed__)); 373 374 struct FW_SET_GPIO_PIN { 375 struct FW_HEADER hdr; 376 u8 select; 377 } __attribute__ ((__packed__)); 378 379 struct FW_SET_GPIO_INT { 380 struct FW_HEADER hdr; 381 u8 select; 382 } __attribute__ ((__packed__)); 383 384 struct FW_SET_DEBUGMODE { 385 struct FW_HEADER hdr; 386 u8 debug_flags; 387 } __attribute__ ((__packed__)); 388 389 struct FW_CONFIGURE_BUFFERS { 390 struct FW_HEADER hdr; 391 u8 config; 392 } __attribute__ ((__packed__)); 393 394 enum _BUFFER_CONFIGS { 395 /* 4k UVI1, 4k UVI2, 2k AUD1, 2k AUD2 (standard usage) */ 396 BUFFER_CONFIG_4422 = 0, 397 /* 3k UVI1, 3k UVI2, 3k AUD1, 3k AUD2 (4x TS input usage) */ 398 BUFFER_CONFIG_3333 = 1, 399 /* 8k UVI1, 0k UVI2, 2k AUD1, 2k I2SOut (HDTV decoder usage) */ 400 BUFFER_CONFIG_8022 = 2, 401 BUFFER_CONFIG_FW17 = 255, /* Use new FW 17 command */ 402 }; 403 404 struct FW_CONFIGURE_FREE_BUFFERS { 405 struct FW_HEADER hdr; 406 u8 UVI1_BufferLength; 407 u8 UVI2_BufferLength; 408 u8 TVO_BufferLength; 409 u8 AUD1_BufferLength; 410 u8 AUD2_BufferLength; 411 u8 TVA_BufferLength; 412 } __attribute__ ((__packed__)); 413 414 struct FW_CONFIGURE_UART { 415 struct FW_HEADER hdr; 416 u8 UartControl; 417 } __attribute__ ((__packed__)); 418 419 enum _UART_CONFIG { 420 _UART_BAUDRATE_19200 = 0, 421 _UART_BAUDRATE_9600 = 1, 422 _UART_BAUDRATE_4800 = 2, 423 _UART_BAUDRATE_2400 = 3, 424 _UART_RX_ENABLE = 0x40, 425 _UART_TX_ENABLE = 0x80, 426 }; 427 428 struct FW_WRITE_UART { 429 struct FW_HEADER hdr; 430 u8 Data[252]; 431 } __attribute__ ((__packed__)); 432 433 434 struct ngene_command { 435 u32 in_len; 436 u32 out_len; 437 union { 438 u32 raw[64]; 439 u8 raw8[256]; 440 struct FW_HEADER hdr; 441 struct FW_I2C_WRITE I2CWrite; 442 struct FW_I2C_CONTINUE_WRITE I2CContinueWrite; 443 struct FW_I2C_READ I2CRead; 444 struct FW_STREAM_CONTROL StreamControl; 445 struct FW_FWLOAD_PREPARE FWLoadPrepare; 446 struct FW_FWLOAD_FINISH FWLoadFinish; 447 struct FW_MEM_READ MemoryRead; 448 struct FW_MEM_WRITE MemoryWrite; 449 struct FW_SFR_IRAM_READ SfrIramRead; 450 struct FW_SFR_IRAM_WRITE SfrIramWrite; 451 struct FW_SPI_WRITE SPIWrite; 452 struct FW_SPI_READ SPIRead; 453 struct FW_SET_GPIO_PIN SetGpioPin; 454 struct FW_SET_GPIO_INT SetGpioInt; 455 struct FW_SET_DEBUGMODE SetDebugMode; 456 struct FW_CONFIGURE_BUFFERS ConfigureBuffers; 457 struct FW_CONFIGURE_FREE_BUFFERS ConfigureFreeBuffers; 458 struct FW_CONFIGURE_UART ConfigureUart; 459 struct FW_WRITE_UART WriteUart; 460 } cmd; 461 } __attribute__ ((__packed__)); 462 463 #define NGENE_INTERFACE_VERSION 0x103 464 #define MAX_VIDEO_BUFFER_SIZE (417792) /* 288*1440 rounded up to next page */ 465 #define MAX_AUDIO_BUFFER_SIZE (8192) /* Gives room for about 23msec@48KHz */ 466 #define MAX_VBI_BUFFER_SIZE (28672) /* 1144*18 rounded up to next page */ 467 #define MAX_TS_BUFFER_SIZE (98304) /* 512*188 rounded up to next page */ 468 #define MAX_HDTV_BUFFER_SIZE (2080768) /* 541*1920*2 rounded up to next page 469 Max: (1920x1080i60) */ 470 471 #define OVERFLOW_BUFFER_SIZE (8192) 472 473 #define RING_SIZE_VIDEO 4 474 #define RING_SIZE_AUDIO 8 475 #define RING_SIZE_TS 8 476 477 #define NUM_SCATTER_GATHER_ENTRIES 8 478 479 #define MAX_DMA_LENGTH (((MAX_VIDEO_BUFFER_SIZE + MAX_VBI_BUFFER_SIZE) * \ 480 RING_SIZE_VIDEO * 2) + \ 481 (MAX_AUDIO_BUFFER_SIZE * RING_SIZE_AUDIO * 2) + \ 482 (MAX_TS_BUFFER_SIZE * RING_SIZE_TS * 4) + \ 483 (RING_SIZE_VIDEO * PAGE_SIZE * 2) + \ 484 (RING_SIZE_AUDIO * PAGE_SIZE * 2) + \ 485 (RING_SIZE_TS * PAGE_SIZE * 4) + \ 486 8 * PAGE_SIZE + OVERFLOW_BUFFER_SIZE + PAGE_SIZE) 487 488 #define EVENT_QUEUE_SIZE 16 489 490 /* Gathers the current state of a single channel. */ 491 492 struct SBufferHeader { 493 struct BUFFER_HEADER ngeneBuffer; /* Physical descriptor */ 494 struct SBufferHeader *Next; 495 void *Buffer1; 496 struct HW_SCATTER_GATHER_ELEMENT *scList1; 497 void *Buffer2; 498 struct HW_SCATTER_GATHER_ELEMENT *scList2; 499 }; 500 501 /* Sizeof SBufferHeader aligned to next 64 Bit boundary (hw restriction) */ 502 #define SIZEOF_SBufferHeader ((sizeof(struct SBufferHeader) + 63) & ~63) 503 504 enum HWSTATE { 505 HWSTATE_STOP, 506 HWSTATE_STARTUP, 507 HWSTATE_RUN, 508 HWSTATE_PAUSE, 509 }; 510 511 enum KSSTATE { 512 KSSTATE_STOP, 513 KSSTATE_ACQUIRE, 514 KSSTATE_PAUSE, 515 KSSTATE_RUN, 516 }; 517 518 struct SRingBufferDescriptor { 519 struct SBufferHeader *Head; /* Points to first buffer in ring buffer 520 structure*/ 521 u64 PAHead; /* Physical address of first buffer */ 522 u32 MemSize; /* Memory size of allocated ring buffers 523 (needed for freeing) */ 524 u32 NumBuffers; /* Number of buffers in the ring */ 525 u32 Buffer1Length; /* Allocated length of Buffer 1 */ 526 u32 Buffer2Length; /* Allocated length of Buffer 2 */ 527 void *SCListMem; /* Memory to hold scatter gather lists for this 528 ring */ 529 u64 PASCListMem; /* Physical address .. */ 530 u32 SCListMemSize; /* Size of this memory */ 531 }; 532 533 enum STREAMMODEFLAGS { 534 StreamMode_NONE = 0, /* Stream not used */ 535 StreamMode_ANALOG = 1, /* Analog: Stream 0,1 = Video, 2,3 = Audio */ 536 StreamMode_TSIN = 2, /* Transport stream input (all) */ 537 StreamMode_HDTV = 4, /* HDTV: Maximum 1920x1080p30,1920x1080i60 538 (only stream 0) */ 539 StreamMode_TSOUT = 8, /* Transport stream output (only stream 3) */ 540 }; 541 542 543 enum BufferExchangeFlags { 544 BEF_EVEN_FIELD = 0x00000001, 545 BEF_CONTINUATION = 0x00000002, 546 BEF_MORE_DATA = 0x00000004, 547 BEF_OVERFLOW = 0x00000008, 548 DF_SWAP32 = 0x00010000, 549 }; 550 551 typedef void *(IBufferExchange)(void *, void *, u32, u32, u32); 552 553 struct MICI_STREAMINFO { 554 IBufferExchange *pExchange; 555 IBufferExchange *pExchangeVBI; /* Secondary (VBI, ancillary) */ 556 u8 Stream; 557 u8 Flags; 558 u8 Mode; 559 u8 Reserved; 560 u16 nLinesVideo; 561 u16 nBytesPerLineVideo; 562 u16 nLinesVBI; 563 u16 nBytesPerLineVBI; 564 u32 CaptureLength; /* Used for audio and transport stream */ 565 }; 566 567 /****************************************************************************/ 568 /* STRUCTS ******************************************************************/ 569 /****************************************************************************/ 570 571 /* sound hardware definition */ 572 #define MIXER_ADDR_TVTUNER 0 573 #define MIXER_ADDR_LAST 0 574 575 struct ngene_channel; 576 577 /*struct sound chip*/ 578 579 struct mychip { 580 struct ngene_channel *chan; 581 struct snd_card *card; 582 struct pci_dev *pci; 583 struct snd_pcm_substream *substream; 584 struct snd_pcm *pcm; 585 unsigned long port; 586 int irq; 587 spinlock_t mixer_lock; 588 spinlock_t lock; 589 int mixer_volume[MIXER_ADDR_LAST + 1][2]; 590 int capture_source[MIXER_ADDR_LAST + 1][2]; 591 }; 592 593 #ifdef NGENE_V4L 594 struct ngene_overlay { 595 int tvnorm; 596 struct v4l2_rect w; 597 enum v4l2_field field; 598 struct v4l2_clip *clips; 599 int nclips; 600 int setup_ok; 601 }; 602 603 struct ngene_tvnorm { 604 int v4l2_id; 605 char *name; 606 u16 swidth, sheight; /* scaled standard width, height */ 607 int tuner_norm; 608 int soundstd; 609 }; 610 611 struct ngene_vopen { 612 struct ngene_channel *ch; 613 enum v4l2_priority prio; 614 int width; 615 int height; 616 int depth; 617 struct videobuf_queue vbuf_q; 618 struct videobuf_queue vbi; 619 int fourcc; 620 int picxcount; 621 int resources; 622 enum v4l2_buf_type type; 623 const struct ngene_format *fmt; 624 625 const struct ngene_format *ovfmt; 626 struct ngene_overlay ov; 627 }; 628 #endif 629 630 struct ngene_channel { 631 struct device device; 632 struct i2c_adapter i2c_adapter; 633 634 struct ngene *dev; 635 int number; 636 int type; 637 int mode; 638 bool has_adapter; 639 bool has_demux; 640 int demod_type; 641 int (*gate_ctrl)(struct dvb_frontend *, int); 642 643 struct dvb_frontend *fe; 644 struct dvb_frontend *fe2; 645 struct dmxdev dmxdev; 646 struct dvb_demux demux; 647 struct dvb_net dvbnet; 648 struct dmx_frontend hw_frontend; 649 struct dmx_frontend mem_frontend; 650 int users; 651 struct video_device *v4l_dev; 652 struct dvb_device *ci_dev; 653 struct tasklet_struct demux_tasklet; 654 655 struct SBufferHeader *nextBuffer; 656 enum KSSTATE State; 657 enum HWSTATE HWState; 658 u8 Stream; 659 u8 Flags; 660 u8 Mode; 661 IBufferExchange *pBufferExchange; 662 IBufferExchange *pBufferExchange2; 663 664 spinlock_t state_lock; 665 u16 nLines; 666 u16 nBytesPerLine; 667 u16 nVBILines; 668 u16 nBytesPerVBILine; 669 u16 itumode; 670 u32 Capture1Length; 671 u32 Capture2Length; 672 struct SRingBufferDescriptor RingBuffer; 673 struct SRingBufferDescriptor TSRingBuffer; 674 struct SRingBufferDescriptor TSIdleBuffer; 675 676 u32 DataFormatFlags; 677 678 int AudioDTOUpdated; 679 u32 AudioDTOValue; 680 681 int (*set_tone)(struct dvb_frontend *, enum fe_sec_tone_mode); 682 u8 lnbh; 683 684 /* stuff from analog driver */ 685 686 int minor; 687 struct mychip *mychip; 688 struct snd_card *soundcard; 689 u8 *evenbuffer; 690 u8 dma_on; 691 int soundstreamon; 692 int audiomute; 693 int soundbuffisallocated; 694 int sndbuffflag; 695 int tun_rdy; 696 int dec_rdy; 697 int tun_dec_rdy; 698 int lastbufferflag; 699 700 struct ngene_tvnorm *tvnorms; 701 int tvnorm_num; 702 int tvnorm; 703 704 #ifdef NGENE_V4L 705 int videousers; 706 struct v4l2_prio_state prio; 707 struct ngene_vopen init; 708 int resources; 709 struct v4l2_framebuffer fbuf; 710 struct ngene_buffer *screen; /* overlay */ 711 struct list_head capture; /* video capture queue */ 712 spinlock_t s_lock; 713 struct semaphore reslock; 714 #endif 715 716 int running; 717 }; 718 719 720 struct ngene_ci { 721 struct device device; 722 struct i2c_adapter i2c_adapter; 723 724 struct ngene *dev; 725 struct dvb_ca_en50221 *en; 726 }; 727 728 struct ngene; 729 730 typedef void (rx_cb_t)(struct ngene *, u32, u8); 731 typedef void (tx_cb_t)(struct ngene *, u32); 732 733 struct ngene { 734 int nr; 735 struct pci_dev *pci_dev; 736 unsigned char __iomem *iomem; 737 738 /*struct i2c_adapter i2c_adapter;*/ 739 740 u32 device_version; 741 u32 fw_interface_version; 742 u32 icounts; 743 bool msi_enabled; 744 bool cmd_timeout_workaround; 745 746 u8 *CmdDoneByte; 747 int BootFirmware; 748 void *OverflowBuffer; 749 dma_addr_t PAOverflowBuffer; 750 void *FWInterfaceBuffer; 751 dma_addr_t PAFWInterfaceBuffer; 752 u8 *ngenetohost; 753 u8 *hosttongene; 754 755 struct EVENT_BUFFER EventQueue[EVENT_QUEUE_SIZE]; 756 int EventQueueOverflowCount; 757 int EventQueueOverflowFlag; 758 struct tasklet_struct event_tasklet; 759 struct EVENT_BUFFER *EventBuffer; 760 int EventQueueWriteIndex; 761 int EventQueueReadIndex; 762 763 wait_queue_head_t cmd_wq; 764 int cmd_done; 765 struct semaphore cmd_mutex; 766 struct semaphore stream_mutex; 767 struct semaphore pll_mutex; 768 struct semaphore i2c_switch_mutex; 769 int i2c_current_channel; 770 int i2c_current_bus; 771 spinlock_t cmd_lock; 772 773 struct dvb_adapter adapter[MAX_STREAM]; 774 struct dvb_adapter *first_adapter; /* "one_adapter" modprobe opt */ 775 struct ngene_channel channel[MAX_STREAM]; 776 777 struct ngene_info *card_info; 778 779 tx_cb_t *TxEventNotify; 780 rx_cb_t *RxEventNotify; 781 int tx_busy; 782 wait_queue_head_t tx_wq; 783 wait_queue_head_t rx_wq; 784 #define UART_RBUF_LEN 4096 785 u8 uart_rbuf[UART_RBUF_LEN]; 786 int uart_rp, uart_wp; 787 788 #define TS_FILLER 0x6f 789 790 u8 *tsout_buf; 791 #define TSOUT_BUF_SIZE (512*188*8) 792 struct dvb_ringbuffer tsout_rbuf; 793 794 u8 *tsin_buf; 795 #define TSIN_BUF_SIZE (512*188*8) 796 struct dvb_ringbuffer tsin_rbuf; 797 798 u8 *ain_buf; 799 #define AIN_BUF_SIZE (128*1024) 800 struct dvb_ringbuffer ain_rbuf; 801 802 803 u8 *vin_buf; 804 #define VIN_BUF_SIZE (4*1920*1080) 805 struct dvb_ringbuffer vin_rbuf; 806 807 unsigned long exp_val; 808 int prev_cmd; 809 810 struct ngene_ci ci; 811 }; 812 813 struct ngene_info { 814 int type; 815 #define NGENE_APP 0 816 #define NGENE_TERRATEC 1 817 #define NGENE_SIDEWINDER 2 818 #define NGENE_RACER 3 819 #define NGENE_VIPER 4 820 #define NGENE_PYTHON 5 821 #define NGENE_VBOX_V1 6 822 #define NGENE_VBOX_V2 7 823 824 int fw_version; 825 bool msi_supported; 826 char *name; 827 828 int io_type[MAX_STREAM]; 829 #define NGENE_IO_NONE 0 830 #define NGENE_IO_TV 1 831 #define NGENE_IO_HDTV 2 832 #define NGENE_IO_TSIN 4 833 #define NGENE_IO_TSOUT 8 834 #define NGENE_IO_AIN 16 835 836 void *fe_config[4]; 837 void *tuner_config[4]; 838 839 int (*demod_attach[4])(struct ngene_channel *); 840 int (*tuner_attach[4])(struct ngene_channel *); 841 842 u8 avf[4]; 843 u8 msp[4]; 844 u8 demoda[4]; 845 u8 lnb[4]; 846 int i2c_access; 847 u8 ntsc; 848 u8 tsf[4]; 849 u8 i2s[4]; 850 851 int (*gate_ctrl)(struct dvb_frontend *, int); 852 int (*switch_ctrl)(struct ngene_channel *, int, int); 853 }; 854 855 #ifdef NGENE_V4L 856 struct ngene_format { 857 char *name; 858 int fourcc; /* video4linux 2 */ 859 int btformat; /* BT848_COLOR_FMT_* */ 860 int format; 861 int btswap; /* BT848_COLOR_CTL_* */ 862 int depth; /* bit/pixel */ 863 int flags; 864 int hshift, vshift; /* for planar modes */ 865 int palette; 866 }; 867 868 #define RESOURCE_OVERLAY 1 869 #define RESOURCE_VIDEO 2 870 #define RESOURCE_VBI 4 871 872 struct ngene_buffer { 873 /* common v4l buffer stuff -- must be first */ 874 struct videobuf_buffer vb; 875 876 /* ngene specific */ 877 const struct ngene_format *fmt; 878 int tvnorm; 879 int btformat; 880 int btswap; 881 }; 882 #endif 883 884 885 /* Provided by ngene-core.c */ 886 int ngene_probe(struct pci_dev *pci_dev, const struct pci_device_id *id); 887 void ngene_remove(struct pci_dev *pdev); 888 void ngene_shutdown(struct pci_dev *pdev); 889 int ngene_command(struct ngene *dev, struct ngene_command *com); 890 int ngene_command_gpio_set(struct ngene *dev, u8 select, u8 level); 891 void set_transfer(struct ngene_channel *chan, int state); 892 void FillTSBuffer(void *Buffer, int Length, u32 Flags); 893 894 /* Provided by ngene-i2c.c */ 895 int ngene_i2c_init(struct ngene *dev, int dev_nr); 896 897 /* Provided by ngene-dvb.c */ 898 extern struct dvb_device ngene_dvbdev_ci; 899 void *tsout_exchange(void *priv, void *buf, u32 len, u32 clock, u32 flags); 900 void *tsin_exchange(void *priv, void *buf, u32 len, u32 clock, u32 flags); 901 int ngene_start_feed(struct dvb_demux_feed *dvbdmxfeed); 902 int ngene_stop_feed(struct dvb_demux_feed *dvbdmxfeed); 903 int my_dvb_dmx_ts_card_init(struct dvb_demux *dvbdemux, char *id, 904 int (*start_feed)(struct dvb_demux_feed *), 905 int (*stop_feed)(struct dvb_demux_feed *), 906 void *priv); 907 int my_dvb_dmxdev_ts_card_init(struct dmxdev *dmxdev, 908 struct dvb_demux *dvbdemux, 909 struct dmx_frontend *hw_frontend, 910 struct dmx_frontend *mem_frontend, 911 struct dvb_adapter *dvb_adapter); 912 913 #endif 914 915 /* LocalWords: Endif 916 */ 917