1 /* 2 * ngene.c: nGene PCIe bridge driver 3 * 4 * Copyright (C) 2005-2007 Micronas 5 * 6 * Copyright (C) 2008-2009 Ralph Metzler <rjkm@metzlerbros.de> 7 * Modifications for new nGene firmware, 8 * support for EEPROM-copying, 9 * support for new dual DVB-S2 card prototype 10 * 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License 14 * version 2 only, as published by the Free Software Foundation. 15 * 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * 23 * You should have received a copy of the GNU General Public License 24 * along with this program; if not, write to the Free Software 25 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 26 * 02110-1301, USA 27 * Or, point your browser to http://www.gnu.org/copyleft/gpl.html 28 */ 29 30 #include <linux/module.h> 31 #include <linux/init.h> 32 #include <linux/delay.h> 33 #include <linux/poll.h> 34 #include <linux/io.h> 35 #include <asm/div64.h> 36 #include <linux/pci.h> 37 #include <linux/timer.h> 38 #include <linux/byteorder/generic.h> 39 #include <linux/firmware.h> 40 #include <linux/vmalloc.h> 41 42 #include "ngene.h" 43 44 static int one_adapter; 45 module_param(one_adapter, int, 0444); 46 MODULE_PARM_DESC(one_adapter, "Use only one adapter."); 47 48 static int shutdown_workaround; 49 module_param(shutdown_workaround, int, 0644); 50 MODULE_PARM_DESC(shutdown_workaround, "Activate workaround for shutdown problem with some chipsets."); 51 52 static int debug; 53 module_param(debug, int, 0444); 54 MODULE_PARM_DESC(debug, "Print debugging information."); 55 56 DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr); 57 58 #define dprintk if (debug) printk 59 60 #define ngwriteb(dat, adr) writeb((dat), (char *)(dev->iomem + (adr))) 61 #define ngwritel(dat, adr) writel((dat), (char *)(dev->iomem + (adr))) 62 #define ngwriteb(dat, adr) writeb((dat), (char *)(dev->iomem + (adr))) 63 #define ngreadl(adr) readl(dev->iomem + (adr)) 64 #define ngreadb(adr) readb(dev->iomem + (adr)) 65 #define ngcpyto(adr, src, count) memcpy_toio((char *) \ 66 (dev->iomem + (adr)), (src), (count)) 67 #define ngcpyfrom(dst, adr, count) memcpy_fromio((dst), (char *) \ 68 (dev->iomem + (adr)), (count)) 69 70 /****************************************************************************/ 71 /* nGene interrupt handler **************************************************/ 72 /****************************************************************************/ 73 74 static void event_tasklet(unsigned long data) 75 { 76 struct ngene *dev = (struct ngene *)data; 77 78 while (dev->EventQueueReadIndex != dev->EventQueueWriteIndex) { 79 struct EVENT_BUFFER Event = 80 dev->EventQueue[dev->EventQueueReadIndex]; 81 dev->EventQueueReadIndex = 82 (dev->EventQueueReadIndex + 1) & (EVENT_QUEUE_SIZE - 1); 83 84 if ((Event.UARTStatus & 0x01) && (dev->TxEventNotify)) 85 dev->TxEventNotify(dev, Event.TimeStamp); 86 if ((Event.UARTStatus & 0x02) && (dev->RxEventNotify)) 87 dev->RxEventNotify(dev, Event.TimeStamp, 88 Event.RXCharacter); 89 } 90 } 91 92 static void demux_tasklet(unsigned long data) 93 { 94 struct ngene_channel *chan = (struct ngene_channel *)data; 95 struct SBufferHeader *Cur = chan->nextBuffer; 96 97 spin_lock_irq(&chan->state_lock); 98 99 while (Cur->ngeneBuffer.SR.Flags & 0x80) { 100 if (chan->mode & NGENE_IO_TSOUT) { 101 u32 Flags = chan->DataFormatFlags; 102 if (Cur->ngeneBuffer.SR.Flags & 0x20) 103 Flags |= BEF_OVERFLOW; 104 if (chan->pBufferExchange) { 105 if (!chan->pBufferExchange(chan, 106 Cur->Buffer1, 107 chan->Capture1Length, 108 Cur->ngeneBuffer.SR. 109 Clock, Flags)) { 110 /* 111 We didn't get data 112 Clear in service flag to make sure we 113 get called on next interrupt again. 114 leave fill/empty (0x80) flag alone 115 to avoid hardware running out of 116 buffers during startup, we hold only 117 in run state ( the source may be late 118 delivering data ) 119 */ 120 121 if (chan->HWState == HWSTATE_RUN) { 122 Cur->ngeneBuffer.SR.Flags &= 123 ~0x40; 124 break; 125 /* Stop processing stream */ 126 } 127 } else { 128 /* We got a valid buffer, 129 so switch to run state */ 130 chan->HWState = HWSTATE_RUN; 131 } 132 } else { 133 printk(KERN_ERR DEVICE_NAME ": OOPS\n"); 134 if (chan->HWState == HWSTATE_RUN) { 135 Cur->ngeneBuffer.SR.Flags &= ~0x40; 136 break; /* Stop processing stream */ 137 } 138 } 139 if (chan->AudioDTOUpdated) { 140 printk(KERN_INFO DEVICE_NAME 141 ": Update AudioDTO = %d\n", 142 chan->AudioDTOValue); 143 Cur->ngeneBuffer.SR.DTOUpdate = 144 chan->AudioDTOValue; 145 chan->AudioDTOUpdated = 0; 146 } 147 } else { 148 if (chan->HWState == HWSTATE_RUN) { 149 u32 Flags = chan->DataFormatFlags; 150 IBufferExchange *exch1 = chan->pBufferExchange; 151 IBufferExchange *exch2 = chan->pBufferExchange2; 152 if (Cur->ngeneBuffer.SR.Flags & 0x01) 153 Flags |= BEF_EVEN_FIELD; 154 if (Cur->ngeneBuffer.SR.Flags & 0x20) 155 Flags |= BEF_OVERFLOW; 156 spin_unlock_irq(&chan->state_lock); 157 if (exch1) 158 exch1(chan, Cur->Buffer1, 159 chan->Capture1Length, 160 Cur->ngeneBuffer.SR.Clock, 161 Flags); 162 if (exch2) 163 exch2(chan, Cur->Buffer2, 164 chan->Capture2Length, 165 Cur->ngeneBuffer.SR.Clock, 166 Flags); 167 spin_lock_irq(&chan->state_lock); 168 } else if (chan->HWState != HWSTATE_STOP) 169 chan->HWState = HWSTATE_RUN; 170 } 171 Cur->ngeneBuffer.SR.Flags = 0x00; 172 Cur = Cur->Next; 173 } 174 chan->nextBuffer = Cur; 175 176 spin_unlock_irq(&chan->state_lock); 177 } 178 179 static irqreturn_t irq_handler(int irq, void *dev_id) 180 { 181 struct ngene *dev = (struct ngene *)dev_id; 182 u32 icounts = 0; 183 irqreturn_t rc = IRQ_NONE; 184 u32 i = MAX_STREAM; 185 u8 *tmpCmdDoneByte; 186 187 if (dev->BootFirmware) { 188 icounts = ngreadl(NGENE_INT_COUNTS); 189 if (icounts != dev->icounts) { 190 ngwritel(0, FORCE_NMI); 191 dev->cmd_done = 1; 192 wake_up(&dev->cmd_wq); 193 dev->icounts = icounts; 194 rc = IRQ_HANDLED; 195 } 196 return rc; 197 } 198 199 ngwritel(0, FORCE_NMI); 200 201 spin_lock(&dev->cmd_lock); 202 tmpCmdDoneByte = dev->CmdDoneByte; 203 if (tmpCmdDoneByte && 204 (*tmpCmdDoneByte || 205 (dev->ngenetohost[0] == 1 && dev->ngenetohost[1] != 0))) { 206 dev->CmdDoneByte = NULL; 207 dev->cmd_done = 1; 208 wake_up(&dev->cmd_wq); 209 rc = IRQ_HANDLED; 210 } 211 spin_unlock(&dev->cmd_lock); 212 213 if (dev->EventBuffer->EventStatus & 0x80) { 214 u8 nextWriteIndex = 215 (dev->EventQueueWriteIndex + 1) & 216 (EVENT_QUEUE_SIZE - 1); 217 if (nextWriteIndex != dev->EventQueueReadIndex) { 218 dev->EventQueue[dev->EventQueueWriteIndex] = 219 *(dev->EventBuffer); 220 dev->EventQueueWriteIndex = nextWriteIndex; 221 } else { 222 printk(KERN_ERR DEVICE_NAME ": event overflow\n"); 223 dev->EventQueueOverflowCount += 1; 224 dev->EventQueueOverflowFlag = 1; 225 } 226 dev->EventBuffer->EventStatus &= ~0x80; 227 tasklet_schedule(&dev->event_tasklet); 228 rc = IRQ_HANDLED; 229 } 230 231 while (i > 0) { 232 i--; 233 spin_lock(&dev->channel[i].state_lock); 234 /* if (dev->channel[i].State>=KSSTATE_RUN) { */ 235 if (dev->channel[i].nextBuffer) { 236 if ((dev->channel[i].nextBuffer-> 237 ngeneBuffer.SR.Flags & 0xC0) == 0x80) { 238 dev->channel[i].nextBuffer-> 239 ngeneBuffer.SR.Flags |= 0x40; 240 tasklet_schedule( 241 &dev->channel[i].demux_tasklet); 242 rc = IRQ_HANDLED; 243 } 244 } 245 spin_unlock(&dev->channel[i].state_lock); 246 } 247 248 /* Request might have been processed by a previous call. */ 249 return IRQ_HANDLED; 250 } 251 252 /****************************************************************************/ 253 /* nGene command interface **************************************************/ 254 /****************************************************************************/ 255 256 static void dump_command_io(struct ngene *dev) 257 { 258 u8 buf[8], *b; 259 260 ngcpyfrom(buf, HOST_TO_NGENE, 8); 261 printk(KERN_ERR "host_to_ngene (%04x): %*ph\n", HOST_TO_NGENE, 8, buf); 262 263 ngcpyfrom(buf, NGENE_TO_HOST, 8); 264 printk(KERN_ERR "ngene_to_host (%04x): %*ph\n", NGENE_TO_HOST, 8, buf); 265 266 b = dev->hosttongene; 267 printk(KERN_ERR "dev->hosttongene (%p): %*ph\n", b, 8, b); 268 269 b = dev->ngenetohost; 270 printk(KERN_ERR "dev->ngenetohost (%p): %*ph\n", b, 8, b); 271 } 272 273 static int ngene_command_mutex(struct ngene *dev, struct ngene_command *com) 274 { 275 int ret; 276 u8 *tmpCmdDoneByte; 277 278 dev->cmd_done = 0; 279 280 if (com->cmd.hdr.Opcode == CMD_FWLOAD_PREPARE) { 281 dev->BootFirmware = 1; 282 dev->icounts = ngreadl(NGENE_INT_COUNTS); 283 ngwritel(0, NGENE_COMMAND); 284 ngwritel(0, NGENE_COMMAND_HI); 285 ngwritel(0, NGENE_STATUS); 286 ngwritel(0, NGENE_STATUS_HI); 287 ngwritel(0, NGENE_EVENT); 288 ngwritel(0, NGENE_EVENT_HI); 289 } else if (com->cmd.hdr.Opcode == CMD_FWLOAD_FINISH) { 290 u64 fwio = dev->PAFWInterfaceBuffer; 291 292 ngwritel(fwio & 0xffffffff, NGENE_COMMAND); 293 ngwritel(fwio >> 32, NGENE_COMMAND_HI); 294 ngwritel((fwio + 256) & 0xffffffff, NGENE_STATUS); 295 ngwritel((fwio + 256) >> 32, NGENE_STATUS_HI); 296 ngwritel((fwio + 512) & 0xffffffff, NGENE_EVENT); 297 ngwritel((fwio + 512) >> 32, NGENE_EVENT_HI); 298 } 299 300 memcpy(dev->FWInterfaceBuffer, com->cmd.raw8, com->in_len + 2); 301 302 if (dev->BootFirmware) 303 ngcpyto(HOST_TO_NGENE, com->cmd.raw8, com->in_len + 2); 304 305 spin_lock_irq(&dev->cmd_lock); 306 tmpCmdDoneByte = dev->ngenetohost + com->out_len; 307 if (!com->out_len) 308 tmpCmdDoneByte++; 309 *tmpCmdDoneByte = 0; 310 dev->ngenetohost[0] = 0; 311 dev->ngenetohost[1] = 0; 312 dev->CmdDoneByte = tmpCmdDoneByte; 313 spin_unlock_irq(&dev->cmd_lock); 314 315 /* Notify 8051. */ 316 ngwritel(1, FORCE_INT); 317 318 ret = wait_event_timeout(dev->cmd_wq, dev->cmd_done == 1, 2 * HZ); 319 if (!ret) { 320 /*ngwritel(0, FORCE_NMI);*/ 321 322 printk(KERN_ERR DEVICE_NAME 323 ": Command timeout cmd=%02x prev=%02x\n", 324 com->cmd.hdr.Opcode, dev->prev_cmd); 325 dump_command_io(dev); 326 return -1; 327 } 328 if (com->cmd.hdr.Opcode == CMD_FWLOAD_FINISH) 329 dev->BootFirmware = 0; 330 331 dev->prev_cmd = com->cmd.hdr.Opcode; 332 333 if (!com->out_len) 334 return 0; 335 336 memcpy(com->cmd.raw8, dev->ngenetohost, com->out_len); 337 338 return 0; 339 } 340 341 int ngene_command(struct ngene *dev, struct ngene_command *com) 342 { 343 int result; 344 345 down(&dev->cmd_mutex); 346 result = ngene_command_mutex(dev, com); 347 up(&dev->cmd_mutex); 348 return result; 349 } 350 351 352 static int ngene_command_load_firmware(struct ngene *dev, 353 u8 *ngene_fw, u32 size) 354 { 355 #define FIRSTCHUNK (1024) 356 u32 cleft; 357 struct ngene_command com; 358 359 com.cmd.hdr.Opcode = CMD_FWLOAD_PREPARE; 360 com.cmd.hdr.Length = 0; 361 com.in_len = 0; 362 com.out_len = 0; 363 364 ngene_command(dev, &com); 365 366 cleft = (size + 3) & ~3; 367 if (cleft > FIRSTCHUNK) { 368 ngcpyto(PROGRAM_SRAM + FIRSTCHUNK, ngene_fw + FIRSTCHUNK, 369 cleft - FIRSTCHUNK); 370 cleft = FIRSTCHUNK; 371 } 372 ngcpyto(DATA_FIFO_AREA, ngene_fw, cleft); 373 374 memset(&com, 0, sizeof(struct ngene_command)); 375 com.cmd.hdr.Opcode = CMD_FWLOAD_FINISH; 376 com.cmd.hdr.Length = 4; 377 com.cmd.FWLoadFinish.Address = DATA_FIFO_AREA; 378 com.cmd.FWLoadFinish.Length = (unsigned short)cleft; 379 com.in_len = 4; 380 com.out_len = 0; 381 382 return ngene_command(dev, &com); 383 } 384 385 386 static int ngene_command_config_buf(struct ngene *dev, u8 config) 387 { 388 struct ngene_command com; 389 390 com.cmd.hdr.Opcode = CMD_CONFIGURE_BUFFER; 391 com.cmd.hdr.Length = 1; 392 com.cmd.ConfigureBuffers.config = config; 393 com.in_len = 1; 394 com.out_len = 0; 395 396 if (ngene_command(dev, &com) < 0) 397 return -EIO; 398 return 0; 399 } 400 401 static int ngene_command_config_free_buf(struct ngene *dev, u8 *config) 402 { 403 struct ngene_command com; 404 405 com.cmd.hdr.Opcode = CMD_CONFIGURE_FREE_BUFFER; 406 com.cmd.hdr.Length = 6; 407 memcpy(&com.cmd.ConfigureBuffers.config, config, 6); 408 com.in_len = 6; 409 com.out_len = 0; 410 411 if (ngene_command(dev, &com) < 0) 412 return -EIO; 413 414 return 0; 415 } 416 417 int ngene_command_gpio_set(struct ngene *dev, u8 select, u8 level) 418 { 419 struct ngene_command com; 420 421 com.cmd.hdr.Opcode = CMD_SET_GPIO_PIN; 422 com.cmd.hdr.Length = 1; 423 com.cmd.SetGpioPin.select = select | (level << 7); 424 com.in_len = 1; 425 com.out_len = 0; 426 427 return ngene_command(dev, &com); 428 } 429 430 431 /* 432 02000640 is sample on rising edge. 433 02000740 is sample on falling edge. 434 02000040 is ignore "valid" signal 435 436 0: FD_CTL1 Bit 7,6 must be 0,1 437 7 disable(fw controlled) 438 6 0-AUX,1-TS 439 5 0-par,1-ser 440 4 0-lsb/1-msb 441 3,2 reserved 442 1,0 0-no sync, 1-use ext. start, 2-use 0x47, 3-both 443 1: FD_CTL2 has 3-valid must be hi, 2-use valid, 1-edge 444 2: FD_STA is read-only. 0-sync 445 3: FD_INSYNC is number of 47s to trigger "in sync". 446 4: FD_OUTSYNC is number of 47s to trigger "out of sync". 447 5: FD_MAXBYTE1 is low-order of bytes per packet. 448 6: FD_MAXBYTE2 is high-order of bytes per packet. 449 7: Top byte is unused. 450 */ 451 452 /****************************************************************************/ 453 454 static u8 TSFeatureDecoderSetup[8 * 5] = { 455 0x42, 0x00, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, 456 0x40, 0x06, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* DRXH */ 457 0x71, 0x07, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* DRXHser */ 458 0x72, 0x00, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* S2ser */ 459 0x40, 0x07, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* LGDT3303 */ 460 }; 461 462 /* Set NGENE I2S Config to 16 bit packed */ 463 static u8 I2SConfiguration[] = { 464 0x00, 0x10, 0x00, 0x00, 465 0x80, 0x10, 0x00, 0x00, 466 }; 467 468 static u8 SPDIFConfiguration[10] = { 469 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 470 }; 471 472 /* Set NGENE I2S Config to transport stream compatible mode */ 473 474 static u8 TS_I2SConfiguration[4] = { 0x3E, 0x18, 0x00, 0x00 }; 475 476 static u8 TS_I2SOutConfiguration[4] = { 0x80, 0x04, 0x00, 0x00 }; 477 478 static u8 ITUDecoderSetup[4][16] = { 479 {0x1c, 0x13, 0x01, 0x68, 0x3d, 0x90, 0x14, 0x20, /* SDTV */ 480 0x00, 0x00, 0x01, 0xb0, 0x9c, 0x00, 0x00, 0x00}, 481 {0x9c, 0x03, 0x23, 0xC0, 0x60, 0x0E, 0x13, 0x00, 482 0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00}, 483 {0x9f, 0x00, 0x23, 0xC0, 0x60, 0x0F, 0x13, 0x00, /* HDTV 1080i50 */ 484 0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00}, 485 {0x9c, 0x01, 0x23, 0xC0, 0x60, 0x0E, 0x13, 0x00, /* HDTV 1080i60 */ 486 0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00}, 487 }; 488 489 /* 490 * 50 48 60 gleich 491 * 27p50 9f 00 22 80 42 69 18 ... 492 * 27p60 93 00 22 80 82 69 1c ... 493 */ 494 495 /* Maxbyte to 1144 (for raw data) */ 496 static u8 ITUFeatureDecoderSetup[8] = { 497 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x04, 0x00 498 }; 499 500 void FillTSBuffer(void *Buffer, int Length, u32 Flags) 501 { 502 u32 *ptr = Buffer; 503 504 memset(Buffer, TS_FILLER, Length); 505 while (Length > 0) { 506 if (Flags & DF_SWAP32) 507 *ptr = 0x471FFF10; 508 else 509 *ptr = 0x10FF1F47; 510 ptr += (188 / 4); 511 Length -= 188; 512 } 513 } 514 515 516 static void flush_buffers(struct ngene_channel *chan) 517 { 518 u8 val; 519 520 do { 521 msleep(1); 522 spin_lock_irq(&chan->state_lock); 523 val = chan->nextBuffer->ngeneBuffer.SR.Flags & 0x80; 524 spin_unlock_irq(&chan->state_lock); 525 } while (val); 526 } 527 528 static void clear_buffers(struct ngene_channel *chan) 529 { 530 struct SBufferHeader *Cur = chan->nextBuffer; 531 532 do { 533 memset(&Cur->ngeneBuffer.SR, 0, sizeof(Cur->ngeneBuffer.SR)); 534 if (chan->mode & NGENE_IO_TSOUT) 535 FillTSBuffer(Cur->Buffer1, 536 chan->Capture1Length, 537 chan->DataFormatFlags); 538 Cur = Cur->Next; 539 } while (Cur != chan->nextBuffer); 540 541 if (chan->mode & NGENE_IO_TSOUT) { 542 chan->nextBuffer->ngeneBuffer.SR.DTOUpdate = 543 chan->AudioDTOValue; 544 chan->AudioDTOUpdated = 0; 545 546 Cur = chan->TSIdleBuffer.Head; 547 548 do { 549 memset(&Cur->ngeneBuffer.SR, 0, 550 sizeof(Cur->ngeneBuffer.SR)); 551 FillTSBuffer(Cur->Buffer1, 552 chan->Capture1Length, 553 chan->DataFormatFlags); 554 Cur = Cur->Next; 555 } while (Cur != chan->TSIdleBuffer.Head); 556 } 557 } 558 559 static int ngene_command_stream_control(struct ngene *dev, u8 stream, 560 u8 control, u8 mode, u8 flags) 561 { 562 struct ngene_channel *chan = &dev->channel[stream]; 563 struct ngene_command com; 564 u16 BsUVI = ((stream & 1) ? 0x9400 : 0x9300); 565 u16 BsSDI = ((stream & 1) ? 0x9600 : 0x9500); 566 u16 BsSPI = ((stream & 1) ? 0x9800 : 0x9700); 567 u16 BsSDO = 0x9B00; 568 569 down(&dev->stream_mutex); 570 memset(&com, 0, sizeof(com)); 571 com.cmd.hdr.Opcode = CMD_CONTROL; 572 com.cmd.hdr.Length = sizeof(struct FW_STREAM_CONTROL) - 2; 573 com.cmd.StreamControl.Stream = stream | (control ? 8 : 0); 574 if (chan->mode & NGENE_IO_TSOUT) 575 com.cmd.StreamControl.Stream |= 0x07; 576 com.cmd.StreamControl.Control = control | 577 (flags & SFLAG_ORDER_LUMA_CHROMA); 578 com.cmd.StreamControl.Mode = mode; 579 com.in_len = sizeof(struct FW_STREAM_CONTROL); 580 com.out_len = 0; 581 582 dprintk(KERN_INFO DEVICE_NAME 583 ": Stream=%02x, Control=%02x, Mode=%02x\n", 584 com.cmd.StreamControl.Stream, com.cmd.StreamControl.Control, 585 com.cmd.StreamControl.Mode); 586 587 chan->Mode = mode; 588 589 if (!(control & 0x80)) { 590 spin_lock_irq(&chan->state_lock); 591 if (chan->State == KSSTATE_RUN) { 592 chan->State = KSSTATE_ACQUIRE; 593 chan->HWState = HWSTATE_STOP; 594 spin_unlock_irq(&chan->state_lock); 595 if (ngene_command(dev, &com) < 0) { 596 up(&dev->stream_mutex); 597 return -1; 598 } 599 /* clear_buffers(chan); */ 600 flush_buffers(chan); 601 up(&dev->stream_mutex); 602 return 0; 603 } 604 spin_unlock_irq(&chan->state_lock); 605 up(&dev->stream_mutex); 606 return 0; 607 } 608 609 if (mode & SMODE_AUDIO_CAPTURE) { 610 com.cmd.StreamControl.CaptureBlockCount = 611 chan->Capture1Length / AUDIO_BLOCK_SIZE; 612 com.cmd.StreamControl.Buffer_Address = chan->RingBuffer.PAHead; 613 } else if (mode & SMODE_TRANSPORT_STREAM) { 614 com.cmd.StreamControl.CaptureBlockCount = 615 chan->Capture1Length / TS_BLOCK_SIZE; 616 com.cmd.StreamControl.MaxLinesPerField = 617 chan->Capture1Length / TS_BLOCK_SIZE; 618 com.cmd.StreamControl.Buffer_Address = 619 chan->TSRingBuffer.PAHead; 620 if (chan->mode & NGENE_IO_TSOUT) { 621 com.cmd.StreamControl.BytesPerVBILine = 622 chan->Capture1Length / TS_BLOCK_SIZE; 623 com.cmd.StreamControl.Stream |= 0x07; 624 } 625 } else { 626 com.cmd.StreamControl.BytesPerVideoLine = chan->nBytesPerLine; 627 com.cmd.StreamControl.MaxLinesPerField = chan->nLines; 628 com.cmd.StreamControl.MinLinesPerField = 100; 629 com.cmd.StreamControl.Buffer_Address = chan->RingBuffer.PAHead; 630 631 if (mode & SMODE_VBI_CAPTURE) { 632 com.cmd.StreamControl.MaxVBILinesPerField = 633 chan->nVBILines; 634 com.cmd.StreamControl.MinVBILinesPerField = 0; 635 com.cmd.StreamControl.BytesPerVBILine = 636 chan->nBytesPerVBILine; 637 } 638 if (flags & SFLAG_COLORBAR) 639 com.cmd.StreamControl.Stream |= 0x04; 640 } 641 642 spin_lock_irq(&chan->state_lock); 643 if (mode & SMODE_AUDIO_CAPTURE) { 644 chan->nextBuffer = chan->RingBuffer.Head; 645 if (mode & SMODE_AUDIO_SPDIF) { 646 com.cmd.StreamControl.SetupDataLen = 647 sizeof(SPDIFConfiguration); 648 com.cmd.StreamControl.SetupDataAddr = BsSPI; 649 memcpy(com.cmd.StreamControl.SetupData, 650 SPDIFConfiguration, sizeof(SPDIFConfiguration)); 651 } else { 652 com.cmd.StreamControl.SetupDataLen = 4; 653 com.cmd.StreamControl.SetupDataAddr = BsSDI; 654 memcpy(com.cmd.StreamControl.SetupData, 655 I2SConfiguration + 656 4 * dev->card_info->i2s[stream], 4); 657 } 658 } else if (mode & SMODE_TRANSPORT_STREAM) { 659 chan->nextBuffer = chan->TSRingBuffer.Head; 660 if (stream >= STREAM_AUDIOIN1) { 661 if (chan->mode & NGENE_IO_TSOUT) { 662 com.cmd.StreamControl.SetupDataLen = 663 sizeof(TS_I2SOutConfiguration); 664 com.cmd.StreamControl.SetupDataAddr = BsSDO; 665 memcpy(com.cmd.StreamControl.SetupData, 666 TS_I2SOutConfiguration, 667 sizeof(TS_I2SOutConfiguration)); 668 } else { 669 com.cmd.StreamControl.SetupDataLen = 670 sizeof(TS_I2SConfiguration); 671 com.cmd.StreamControl.SetupDataAddr = BsSDI; 672 memcpy(com.cmd.StreamControl.SetupData, 673 TS_I2SConfiguration, 674 sizeof(TS_I2SConfiguration)); 675 } 676 } else { 677 com.cmd.StreamControl.SetupDataLen = 8; 678 com.cmd.StreamControl.SetupDataAddr = BsUVI + 0x10; 679 memcpy(com.cmd.StreamControl.SetupData, 680 TSFeatureDecoderSetup + 681 8 * dev->card_info->tsf[stream], 8); 682 } 683 } else { 684 chan->nextBuffer = chan->RingBuffer.Head; 685 com.cmd.StreamControl.SetupDataLen = 686 16 + sizeof(ITUFeatureDecoderSetup); 687 com.cmd.StreamControl.SetupDataAddr = BsUVI; 688 memcpy(com.cmd.StreamControl.SetupData, 689 ITUDecoderSetup[chan->itumode], 16); 690 memcpy(com.cmd.StreamControl.SetupData + 16, 691 ITUFeatureDecoderSetup, sizeof(ITUFeatureDecoderSetup)); 692 } 693 clear_buffers(chan); 694 chan->State = KSSTATE_RUN; 695 if (mode & SMODE_TRANSPORT_STREAM) 696 chan->HWState = HWSTATE_RUN; 697 else 698 chan->HWState = HWSTATE_STARTUP; 699 spin_unlock_irq(&chan->state_lock); 700 701 if (ngene_command(dev, &com) < 0) { 702 up(&dev->stream_mutex); 703 return -1; 704 } 705 up(&dev->stream_mutex); 706 return 0; 707 } 708 709 void set_transfer(struct ngene_channel *chan, int state) 710 { 711 u8 control = 0, mode = 0, flags = 0; 712 struct ngene *dev = chan->dev; 713 int ret; 714 715 /* 716 printk(KERN_INFO DEVICE_NAME ": st %d\n", state); 717 msleep(100); 718 */ 719 720 if (state) { 721 if (chan->running) { 722 printk(KERN_INFO DEVICE_NAME ": already running\n"); 723 return; 724 } 725 } else { 726 if (!chan->running) { 727 printk(KERN_INFO DEVICE_NAME ": already stopped\n"); 728 return; 729 } 730 } 731 732 if (dev->card_info->switch_ctrl) 733 dev->card_info->switch_ctrl(chan, 1, state ^ 1); 734 735 if (state) { 736 spin_lock_irq(&chan->state_lock); 737 738 /* printk(KERN_INFO DEVICE_NAME ": lock=%08x\n", 739 ngreadl(0x9310)); */ 740 dvb_ringbuffer_flush(&dev->tsout_rbuf); 741 control = 0x80; 742 if (chan->mode & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) { 743 chan->Capture1Length = 512 * 188; 744 mode = SMODE_TRANSPORT_STREAM; 745 } 746 if (chan->mode & NGENE_IO_TSOUT) { 747 chan->pBufferExchange = tsout_exchange; 748 /* 0x66666666 = 50MHz *2^33 /250MHz */ 749 chan->AudioDTOValue = 0x80000000; 750 chan->AudioDTOUpdated = 1; 751 } 752 if (chan->mode & NGENE_IO_TSIN) 753 chan->pBufferExchange = tsin_exchange; 754 spin_unlock_irq(&chan->state_lock); 755 } 756 /* else printk(KERN_INFO DEVICE_NAME ": lock=%08x\n", 757 ngreadl(0x9310)); */ 758 759 ret = ngene_command_stream_control(dev, chan->number, 760 control, mode, flags); 761 if (!ret) 762 chan->running = state; 763 else 764 printk(KERN_ERR DEVICE_NAME ": set_transfer %d failed\n", 765 state); 766 if (!state) { 767 spin_lock_irq(&chan->state_lock); 768 chan->pBufferExchange = NULL; 769 dvb_ringbuffer_flush(&dev->tsout_rbuf); 770 spin_unlock_irq(&chan->state_lock); 771 } 772 } 773 774 775 /****************************************************************************/ 776 /* nGene hardware init and release functions ********************************/ 777 /****************************************************************************/ 778 779 static void free_ringbuffer(struct ngene *dev, struct SRingBufferDescriptor *rb) 780 { 781 struct SBufferHeader *Cur = rb->Head; 782 u32 j; 783 784 if (!Cur) 785 return; 786 787 for (j = 0; j < rb->NumBuffers; j++, Cur = Cur->Next) { 788 if (Cur->Buffer1) 789 pci_free_consistent(dev->pci_dev, 790 rb->Buffer1Length, 791 Cur->Buffer1, 792 Cur->scList1->Address); 793 794 if (Cur->Buffer2) 795 pci_free_consistent(dev->pci_dev, 796 rb->Buffer2Length, 797 Cur->Buffer2, 798 Cur->scList2->Address); 799 } 800 801 if (rb->SCListMem) 802 pci_free_consistent(dev->pci_dev, rb->SCListMemSize, 803 rb->SCListMem, rb->PASCListMem); 804 805 pci_free_consistent(dev->pci_dev, rb->MemSize, rb->Head, rb->PAHead); 806 } 807 808 static void free_idlebuffer(struct ngene *dev, 809 struct SRingBufferDescriptor *rb, 810 struct SRingBufferDescriptor *tb) 811 { 812 int j; 813 struct SBufferHeader *Cur = tb->Head; 814 815 if (!rb->Head) 816 return; 817 free_ringbuffer(dev, rb); 818 for (j = 0; j < tb->NumBuffers; j++, Cur = Cur->Next) { 819 Cur->Buffer2 = NULL; 820 Cur->scList2 = NULL; 821 Cur->ngeneBuffer.Address_of_first_entry_2 = 0; 822 Cur->ngeneBuffer.Number_of_entries_2 = 0; 823 } 824 } 825 826 static void free_common_buffers(struct ngene *dev) 827 { 828 u32 i; 829 struct ngene_channel *chan; 830 831 for (i = STREAM_VIDEOIN1; i < MAX_STREAM; i++) { 832 chan = &dev->channel[i]; 833 free_idlebuffer(dev, &chan->TSIdleBuffer, &chan->TSRingBuffer); 834 free_ringbuffer(dev, &chan->RingBuffer); 835 free_ringbuffer(dev, &chan->TSRingBuffer); 836 } 837 838 if (dev->OverflowBuffer) 839 pci_free_consistent(dev->pci_dev, 840 OVERFLOW_BUFFER_SIZE, 841 dev->OverflowBuffer, dev->PAOverflowBuffer); 842 843 if (dev->FWInterfaceBuffer) 844 pci_free_consistent(dev->pci_dev, 845 4096, 846 dev->FWInterfaceBuffer, 847 dev->PAFWInterfaceBuffer); 848 } 849 850 /****************************************************************************/ 851 /* Ring buffer handling *****************************************************/ 852 /****************************************************************************/ 853 854 static int create_ring_buffer(struct pci_dev *pci_dev, 855 struct SRingBufferDescriptor *descr, u32 NumBuffers) 856 { 857 dma_addr_t tmp; 858 struct SBufferHeader *Head; 859 u32 i; 860 u32 MemSize = SIZEOF_SBufferHeader * NumBuffers; 861 u64 PARingBufferHead; 862 u64 PARingBufferCur; 863 u64 PARingBufferNext; 864 struct SBufferHeader *Cur, *Next; 865 866 descr->Head = NULL; 867 descr->MemSize = 0; 868 descr->PAHead = 0; 869 descr->NumBuffers = 0; 870 871 if (MemSize < 4096) 872 MemSize = 4096; 873 874 Head = pci_alloc_consistent(pci_dev, MemSize, &tmp); 875 PARingBufferHead = tmp; 876 877 if (!Head) 878 return -ENOMEM; 879 880 memset(Head, 0, MemSize); 881 882 PARingBufferCur = PARingBufferHead; 883 Cur = Head; 884 885 for (i = 0; i < NumBuffers - 1; i++) { 886 Next = (struct SBufferHeader *) 887 (((u8 *) Cur) + SIZEOF_SBufferHeader); 888 PARingBufferNext = PARingBufferCur + SIZEOF_SBufferHeader; 889 Cur->Next = Next; 890 Cur->ngeneBuffer.Next = PARingBufferNext; 891 Cur = Next; 892 PARingBufferCur = PARingBufferNext; 893 } 894 /* Last Buffer points back to first one */ 895 Cur->Next = Head; 896 Cur->ngeneBuffer.Next = PARingBufferHead; 897 898 descr->Head = Head; 899 descr->MemSize = MemSize; 900 descr->PAHead = PARingBufferHead; 901 descr->NumBuffers = NumBuffers; 902 903 return 0; 904 } 905 906 static int AllocateRingBuffers(struct pci_dev *pci_dev, 907 dma_addr_t of, 908 struct SRingBufferDescriptor *pRingBuffer, 909 u32 Buffer1Length, u32 Buffer2Length) 910 { 911 dma_addr_t tmp; 912 u32 i, j; 913 u32 SCListMemSize = pRingBuffer->NumBuffers 914 * ((Buffer2Length != 0) ? (NUM_SCATTER_GATHER_ENTRIES * 2) : 915 NUM_SCATTER_GATHER_ENTRIES) 916 * sizeof(struct HW_SCATTER_GATHER_ELEMENT); 917 918 u64 PASCListMem; 919 struct HW_SCATTER_GATHER_ELEMENT *SCListEntry; 920 u64 PASCListEntry; 921 struct SBufferHeader *Cur; 922 void *SCListMem; 923 924 if (SCListMemSize < 4096) 925 SCListMemSize = 4096; 926 927 SCListMem = pci_alloc_consistent(pci_dev, SCListMemSize, &tmp); 928 929 PASCListMem = tmp; 930 if (SCListMem == NULL) 931 return -ENOMEM; 932 933 memset(SCListMem, 0, SCListMemSize); 934 935 pRingBuffer->SCListMem = SCListMem; 936 pRingBuffer->PASCListMem = PASCListMem; 937 pRingBuffer->SCListMemSize = SCListMemSize; 938 pRingBuffer->Buffer1Length = Buffer1Length; 939 pRingBuffer->Buffer2Length = Buffer2Length; 940 941 SCListEntry = SCListMem; 942 PASCListEntry = PASCListMem; 943 Cur = pRingBuffer->Head; 944 945 for (i = 0; i < pRingBuffer->NumBuffers; i += 1, Cur = Cur->Next) { 946 u64 PABuffer; 947 948 void *Buffer = pci_alloc_consistent(pci_dev, Buffer1Length, 949 &tmp); 950 PABuffer = tmp; 951 952 if (Buffer == NULL) 953 return -ENOMEM; 954 955 Cur->Buffer1 = Buffer; 956 957 SCListEntry->Address = PABuffer; 958 SCListEntry->Length = Buffer1Length; 959 960 Cur->scList1 = SCListEntry; 961 Cur->ngeneBuffer.Address_of_first_entry_1 = PASCListEntry; 962 Cur->ngeneBuffer.Number_of_entries_1 = 963 NUM_SCATTER_GATHER_ENTRIES; 964 965 SCListEntry += 1; 966 PASCListEntry += sizeof(struct HW_SCATTER_GATHER_ELEMENT); 967 968 #if NUM_SCATTER_GATHER_ENTRIES > 1 969 for (j = 0; j < NUM_SCATTER_GATHER_ENTRIES - 1; j += 1) { 970 SCListEntry->Address = of; 971 SCListEntry->Length = OVERFLOW_BUFFER_SIZE; 972 SCListEntry += 1; 973 PASCListEntry += 974 sizeof(struct HW_SCATTER_GATHER_ELEMENT); 975 } 976 #endif 977 978 if (!Buffer2Length) 979 continue; 980 981 Buffer = pci_alloc_consistent(pci_dev, Buffer2Length, &tmp); 982 PABuffer = tmp; 983 984 if (Buffer == NULL) 985 return -ENOMEM; 986 987 Cur->Buffer2 = Buffer; 988 989 SCListEntry->Address = PABuffer; 990 SCListEntry->Length = Buffer2Length; 991 992 Cur->scList2 = SCListEntry; 993 Cur->ngeneBuffer.Address_of_first_entry_2 = PASCListEntry; 994 Cur->ngeneBuffer.Number_of_entries_2 = 995 NUM_SCATTER_GATHER_ENTRIES; 996 997 SCListEntry += 1; 998 PASCListEntry += sizeof(struct HW_SCATTER_GATHER_ELEMENT); 999 1000 #if NUM_SCATTER_GATHER_ENTRIES > 1 1001 for (j = 0; j < NUM_SCATTER_GATHER_ENTRIES - 1; j++) { 1002 SCListEntry->Address = of; 1003 SCListEntry->Length = OVERFLOW_BUFFER_SIZE; 1004 SCListEntry += 1; 1005 PASCListEntry += 1006 sizeof(struct HW_SCATTER_GATHER_ELEMENT); 1007 } 1008 #endif 1009 1010 } 1011 1012 return 0; 1013 } 1014 1015 static int FillTSIdleBuffer(struct SRingBufferDescriptor *pIdleBuffer, 1016 struct SRingBufferDescriptor *pRingBuffer) 1017 { 1018 /* Copy pointer to scatter gather list in TSRingbuffer 1019 structure for buffer 2 1020 Load number of buffer 1021 */ 1022 u32 n = pRingBuffer->NumBuffers; 1023 1024 /* Point to first buffer entry */ 1025 struct SBufferHeader *Cur = pRingBuffer->Head; 1026 int i; 1027 /* Loop thru all buffer and set Buffer 2 pointers to TSIdlebuffer */ 1028 for (i = 0; i < n; i++) { 1029 Cur->Buffer2 = pIdleBuffer->Head->Buffer1; 1030 Cur->scList2 = pIdleBuffer->Head->scList1; 1031 Cur->ngeneBuffer.Address_of_first_entry_2 = 1032 pIdleBuffer->Head->ngeneBuffer. 1033 Address_of_first_entry_1; 1034 Cur->ngeneBuffer.Number_of_entries_2 = 1035 pIdleBuffer->Head->ngeneBuffer.Number_of_entries_1; 1036 Cur = Cur->Next; 1037 } 1038 return 0; 1039 } 1040 1041 static u32 RingBufferSizes[MAX_STREAM] = { 1042 RING_SIZE_VIDEO, 1043 RING_SIZE_VIDEO, 1044 RING_SIZE_AUDIO, 1045 RING_SIZE_AUDIO, 1046 RING_SIZE_AUDIO, 1047 }; 1048 1049 static u32 Buffer1Sizes[MAX_STREAM] = { 1050 MAX_VIDEO_BUFFER_SIZE, 1051 MAX_VIDEO_BUFFER_SIZE, 1052 MAX_AUDIO_BUFFER_SIZE, 1053 MAX_AUDIO_BUFFER_SIZE, 1054 MAX_AUDIO_BUFFER_SIZE 1055 }; 1056 1057 static u32 Buffer2Sizes[MAX_STREAM] = { 1058 MAX_VBI_BUFFER_SIZE, 1059 MAX_VBI_BUFFER_SIZE, 1060 0, 1061 0, 1062 0 1063 }; 1064 1065 1066 static int AllocCommonBuffers(struct ngene *dev) 1067 { 1068 int status = 0, i; 1069 1070 dev->FWInterfaceBuffer = pci_alloc_consistent(dev->pci_dev, 4096, 1071 &dev->PAFWInterfaceBuffer); 1072 if (!dev->FWInterfaceBuffer) 1073 return -ENOMEM; 1074 dev->hosttongene = dev->FWInterfaceBuffer; 1075 dev->ngenetohost = dev->FWInterfaceBuffer + 256; 1076 dev->EventBuffer = dev->FWInterfaceBuffer + 512; 1077 1078 dev->OverflowBuffer = pci_alloc_consistent(dev->pci_dev, 1079 OVERFLOW_BUFFER_SIZE, 1080 &dev->PAOverflowBuffer); 1081 if (!dev->OverflowBuffer) 1082 return -ENOMEM; 1083 memset(dev->OverflowBuffer, 0, OVERFLOW_BUFFER_SIZE); 1084 1085 for (i = STREAM_VIDEOIN1; i < MAX_STREAM; i++) { 1086 int type = dev->card_info->io_type[i]; 1087 1088 dev->channel[i].State = KSSTATE_STOP; 1089 1090 if (type & (NGENE_IO_TV | NGENE_IO_HDTV | NGENE_IO_AIN)) { 1091 status = create_ring_buffer(dev->pci_dev, 1092 &dev->channel[i].RingBuffer, 1093 RingBufferSizes[i]); 1094 if (status < 0) 1095 break; 1096 1097 if (type & (NGENE_IO_TV | NGENE_IO_AIN)) { 1098 status = AllocateRingBuffers(dev->pci_dev, 1099 dev-> 1100 PAOverflowBuffer, 1101 &dev->channel[i]. 1102 RingBuffer, 1103 Buffer1Sizes[i], 1104 Buffer2Sizes[i]); 1105 if (status < 0) 1106 break; 1107 } else if (type & NGENE_IO_HDTV) { 1108 status = AllocateRingBuffers(dev->pci_dev, 1109 dev-> 1110 PAOverflowBuffer, 1111 &dev->channel[i]. 1112 RingBuffer, 1113 MAX_HDTV_BUFFER_SIZE, 1114 0); 1115 if (status < 0) 1116 break; 1117 } 1118 } 1119 1120 if (type & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) { 1121 1122 status = create_ring_buffer(dev->pci_dev, 1123 &dev->channel[i]. 1124 TSRingBuffer, RING_SIZE_TS); 1125 if (status < 0) 1126 break; 1127 1128 status = AllocateRingBuffers(dev->pci_dev, 1129 dev->PAOverflowBuffer, 1130 &dev->channel[i]. 1131 TSRingBuffer, 1132 MAX_TS_BUFFER_SIZE, 0); 1133 if (status) 1134 break; 1135 } 1136 1137 if (type & NGENE_IO_TSOUT) { 1138 status = create_ring_buffer(dev->pci_dev, 1139 &dev->channel[i]. 1140 TSIdleBuffer, 1); 1141 if (status < 0) 1142 break; 1143 status = AllocateRingBuffers(dev->pci_dev, 1144 dev->PAOverflowBuffer, 1145 &dev->channel[i]. 1146 TSIdleBuffer, 1147 MAX_TS_BUFFER_SIZE, 0); 1148 if (status) 1149 break; 1150 FillTSIdleBuffer(&dev->channel[i].TSIdleBuffer, 1151 &dev->channel[i].TSRingBuffer); 1152 } 1153 } 1154 return status; 1155 } 1156 1157 static void ngene_release_buffers(struct ngene *dev) 1158 { 1159 if (dev->iomem) 1160 iounmap(dev->iomem); 1161 free_common_buffers(dev); 1162 vfree(dev->tsout_buf); 1163 vfree(dev->tsin_buf); 1164 vfree(dev->ain_buf); 1165 vfree(dev->vin_buf); 1166 vfree(dev); 1167 } 1168 1169 static int ngene_get_buffers(struct ngene *dev) 1170 { 1171 if (AllocCommonBuffers(dev)) 1172 return -ENOMEM; 1173 if (dev->card_info->io_type[4] & NGENE_IO_TSOUT) { 1174 dev->tsout_buf = vmalloc(TSOUT_BUF_SIZE); 1175 if (!dev->tsout_buf) 1176 return -ENOMEM; 1177 dvb_ringbuffer_init(&dev->tsout_rbuf, 1178 dev->tsout_buf, TSOUT_BUF_SIZE); 1179 } 1180 if (dev->card_info->io_type[2]&NGENE_IO_TSIN) { 1181 dev->tsin_buf = vmalloc(TSIN_BUF_SIZE); 1182 if (!dev->tsin_buf) 1183 return -ENOMEM; 1184 dvb_ringbuffer_init(&dev->tsin_rbuf, 1185 dev->tsin_buf, TSIN_BUF_SIZE); 1186 } 1187 if (dev->card_info->io_type[2] & NGENE_IO_AIN) { 1188 dev->ain_buf = vmalloc(AIN_BUF_SIZE); 1189 if (!dev->ain_buf) 1190 return -ENOMEM; 1191 dvb_ringbuffer_init(&dev->ain_rbuf, dev->ain_buf, AIN_BUF_SIZE); 1192 } 1193 if (dev->card_info->io_type[0] & NGENE_IO_HDTV) { 1194 dev->vin_buf = vmalloc(VIN_BUF_SIZE); 1195 if (!dev->vin_buf) 1196 return -ENOMEM; 1197 dvb_ringbuffer_init(&dev->vin_rbuf, dev->vin_buf, VIN_BUF_SIZE); 1198 } 1199 dev->iomem = ioremap(pci_resource_start(dev->pci_dev, 0), 1200 pci_resource_len(dev->pci_dev, 0)); 1201 if (!dev->iomem) 1202 return -ENOMEM; 1203 1204 return 0; 1205 } 1206 1207 static void ngene_init(struct ngene *dev) 1208 { 1209 int i; 1210 1211 tasklet_init(&dev->event_tasklet, event_tasklet, (unsigned long)dev); 1212 1213 memset_io(dev->iomem + 0xc000, 0x00, 0x220); 1214 memset_io(dev->iomem + 0xc400, 0x00, 0x100); 1215 1216 for (i = 0; i < MAX_STREAM; i++) { 1217 dev->channel[i].dev = dev; 1218 dev->channel[i].number = i; 1219 } 1220 1221 dev->fw_interface_version = 0; 1222 1223 ngwritel(0, NGENE_INT_ENABLE); 1224 1225 dev->icounts = ngreadl(NGENE_INT_COUNTS); 1226 1227 dev->device_version = ngreadl(DEV_VER) & 0x0f; 1228 printk(KERN_INFO DEVICE_NAME ": Device version %d\n", 1229 dev->device_version); 1230 } 1231 1232 static int ngene_load_firm(struct ngene *dev) 1233 { 1234 u32 size; 1235 const struct firmware *fw = NULL; 1236 u8 *ngene_fw; 1237 char *fw_name; 1238 int err, version; 1239 1240 version = dev->card_info->fw_version; 1241 1242 switch (version) { 1243 default: 1244 case 15: 1245 version = 15; 1246 size = 23466; 1247 fw_name = "ngene_15.fw"; 1248 dev->cmd_timeout_workaround = true; 1249 break; 1250 case 16: 1251 size = 23498; 1252 fw_name = "ngene_16.fw"; 1253 dev->cmd_timeout_workaround = true; 1254 break; 1255 case 17: 1256 size = 24446; 1257 fw_name = "ngene_17.fw"; 1258 dev->cmd_timeout_workaround = true; 1259 break; 1260 case 18: 1261 size = 0; 1262 fw_name = "ngene_18.fw"; 1263 break; 1264 } 1265 1266 if (request_firmware(&fw, fw_name, &dev->pci_dev->dev) < 0) { 1267 printk(KERN_ERR DEVICE_NAME 1268 ": Could not load firmware file %s.\n", fw_name); 1269 printk(KERN_INFO DEVICE_NAME 1270 ": Copy %s to your hotplug directory!\n", fw_name); 1271 return -1; 1272 } 1273 if (size == 0) 1274 size = fw->size; 1275 if (size != fw->size) { 1276 printk(KERN_ERR DEVICE_NAME 1277 ": Firmware %s has invalid size!", fw_name); 1278 err = -1; 1279 } else { 1280 printk(KERN_INFO DEVICE_NAME 1281 ": Loading firmware file %s.\n", fw_name); 1282 ngene_fw = (u8 *) fw->data; 1283 err = ngene_command_load_firmware(dev, ngene_fw, size); 1284 } 1285 1286 release_firmware(fw); 1287 1288 return err; 1289 } 1290 1291 static void ngene_stop(struct ngene *dev) 1292 { 1293 down(&dev->cmd_mutex); 1294 i2c_del_adapter(&(dev->channel[0].i2c_adapter)); 1295 i2c_del_adapter(&(dev->channel[1].i2c_adapter)); 1296 ngwritel(0, NGENE_INT_ENABLE); 1297 ngwritel(0, NGENE_COMMAND); 1298 ngwritel(0, NGENE_COMMAND_HI); 1299 ngwritel(0, NGENE_STATUS); 1300 ngwritel(0, NGENE_STATUS_HI); 1301 ngwritel(0, NGENE_EVENT); 1302 ngwritel(0, NGENE_EVENT_HI); 1303 free_irq(dev->pci_dev->irq, dev); 1304 #ifdef CONFIG_PCI_MSI 1305 if (dev->msi_enabled) 1306 pci_disable_msi(dev->pci_dev); 1307 #endif 1308 } 1309 1310 static int ngene_buffer_config(struct ngene *dev) 1311 { 1312 int stat; 1313 1314 if (dev->card_info->fw_version >= 17) { 1315 u8 tsin12_config[6] = { 0x60, 0x60, 0x00, 0x00, 0x00, 0x00 }; 1316 u8 tsin1234_config[6] = { 0x30, 0x30, 0x00, 0x30, 0x30, 0x00 }; 1317 u8 tsio1235_config[6] = { 0x30, 0x30, 0x00, 0x28, 0x00, 0x38 }; 1318 u8 *bconf = tsin12_config; 1319 1320 if (dev->card_info->io_type[2]&NGENE_IO_TSIN && 1321 dev->card_info->io_type[3]&NGENE_IO_TSIN) { 1322 bconf = tsin1234_config; 1323 if (dev->card_info->io_type[4]&NGENE_IO_TSOUT && 1324 dev->ci.en) 1325 bconf = tsio1235_config; 1326 } 1327 stat = ngene_command_config_free_buf(dev, bconf); 1328 } else { 1329 int bconf = BUFFER_CONFIG_4422; 1330 1331 if (dev->card_info->io_type[3] == NGENE_IO_TSIN) 1332 bconf = BUFFER_CONFIG_3333; 1333 stat = ngene_command_config_buf(dev, bconf); 1334 } 1335 return stat; 1336 } 1337 1338 1339 static int ngene_start(struct ngene *dev) 1340 { 1341 int stat; 1342 int i; 1343 1344 pci_set_master(dev->pci_dev); 1345 ngene_init(dev); 1346 1347 stat = request_irq(dev->pci_dev->irq, irq_handler, 1348 IRQF_SHARED, "nGene", 1349 (void *)dev); 1350 if (stat < 0) 1351 return stat; 1352 1353 init_waitqueue_head(&dev->cmd_wq); 1354 init_waitqueue_head(&dev->tx_wq); 1355 init_waitqueue_head(&dev->rx_wq); 1356 sema_init(&dev->cmd_mutex, 1); 1357 sema_init(&dev->stream_mutex, 1); 1358 sema_init(&dev->pll_mutex, 1); 1359 sema_init(&dev->i2c_switch_mutex, 1); 1360 spin_lock_init(&dev->cmd_lock); 1361 for (i = 0; i < MAX_STREAM; i++) 1362 spin_lock_init(&dev->channel[i].state_lock); 1363 ngwritel(1, TIMESTAMPS); 1364 1365 ngwritel(1, NGENE_INT_ENABLE); 1366 1367 stat = ngene_load_firm(dev); 1368 if (stat < 0) 1369 goto fail; 1370 1371 #ifdef CONFIG_PCI_MSI 1372 /* enable MSI if kernel and card support it */ 1373 if (pci_msi_enabled() && dev->card_info->msi_supported) { 1374 unsigned long flags; 1375 1376 ngwritel(0, NGENE_INT_ENABLE); 1377 free_irq(dev->pci_dev->irq, dev); 1378 stat = pci_enable_msi(dev->pci_dev); 1379 if (stat) { 1380 printk(KERN_INFO DEVICE_NAME 1381 ": MSI not available\n"); 1382 flags = IRQF_SHARED; 1383 } else { 1384 flags = 0; 1385 dev->msi_enabled = true; 1386 } 1387 stat = request_irq(dev->pci_dev->irq, irq_handler, 1388 flags, "nGene", dev); 1389 if (stat < 0) 1390 goto fail2; 1391 ngwritel(1, NGENE_INT_ENABLE); 1392 } 1393 #endif 1394 1395 stat = ngene_i2c_init(dev, 0); 1396 if (stat < 0) 1397 goto fail; 1398 1399 stat = ngene_i2c_init(dev, 1); 1400 if (stat < 0) 1401 goto fail; 1402 1403 return 0; 1404 1405 fail: 1406 ngwritel(0, NGENE_INT_ENABLE); 1407 free_irq(dev->pci_dev->irq, dev); 1408 #ifdef CONFIG_PCI_MSI 1409 fail2: 1410 if (dev->msi_enabled) 1411 pci_disable_msi(dev->pci_dev); 1412 #endif 1413 return stat; 1414 } 1415 1416 /****************************************************************************/ 1417 /****************************************************************************/ 1418 /****************************************************************************/ 1419 1420 static void release_channel(struct ngene_channel *chan) 1421 { 1422 struct dvb_demux *dvbdemux = &chan->demux; 1423 struct ngene *dev = chan->dev; 1424 1425 if (chan->running) 1426 set_transfer(chan, 0); 1427 1428 tasklet_kill(&chan->demux_tasklet); 1429 1430 if (chan->ci_dev) { 1431 dvb_unregister_device(chan->ci_dev); 1432 chan->ci_dev = NULL; 1433 } 1434 1435 if (chan->fe2) 1436 dvb_unregister_frontend(chan->fe2); 1437 1438 if (chan->fe) { 1439 dvb_unregister_frontend(chan->fe); 1440 dvb_frontend_detach(chan->fe); 1441 chan->fe = NULL; 1442 } 1443 1444 if (chan->has_demux) { 1445 dvb_net_release(&chan->dvbnet); 1446 dvbdemux->dmx.close(&dvbdemux->dmx); 1447 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, 1448 &chan->hw_frontend); 1449 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, 1450 &chan->mem_frontend); 1451 dvb_dmxdev_release(&chan->dmxdev); 1452 dvb_dmx_release(&chan->demux); 1453 chan->has_demux = false; 1454 } 1455 1456 if (chan->has_adapter) { 1457 dvb_unregister_adapter(&dev->adapter[chan->number]); 1458 chan->has_adapter = false; 1459 } 1460 } 1461 1462 static int init_channel(struct ngene_channel *chan) 1463 { 1464 int ret = 0, nr = chan->number; 1465 struct dvb_adapter *adapter = NULL; 1466 struct dvb_demux *dvbdemux = &chan->demux; 1467 struct ngene *dev = chan->dev; 1468 struct ngene_info *ni = dev->card_info; 1469 int io = ni->io_type[nr]; 1470 1471 tasklet_init(&chan->demux_tasklet, demux_tasklet, (unsigned long)chan); 1472 chan->users = 0; 1473 chan->type = io; 1474 chan->mode = chan->type; /* for now only one mode */ 1475 1476 if (io & NGENE_IO_TSIN) { 1477 chan->fe = NULL; 1478 if (ni->demod_attach[nr]) { 1479 ret = ni->demod_attach[nr](chan); 1480 if (ret < 0) 1481 goto err; 1482 } 1483 if (chan->fe && ni->tuner_attach[nr]) { 1484 ret = ni->tuner_attach[nr](chan); 1485 if (ret < 0) 1486 goto err; 1487 } 1488 } 1489 1490 if (!dev->ci.en && (io & NGENE_IO_TSOUT)) 1491 return 0; 1492 1493 if (io & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) { 1494 if (nr >= STREAM_AUDIOIN1) 1495 chan->DataFormatFlags = DF_SWAP32; 1496 1497 if (nr == 0 || !one_adapter || dev->first_adapter == NULL) { 1498 adapter = &dev->adapter[nr]; 1499 ret = dvb_register_adapter(adapter, "nGene", 1500 THIS_MODULE, 1501 &chan->dev->pci_dev->dev, 1502 adapter_nr); 1503 if (ret < 0) 1504 goto err; 1505 if (dev->first_adapter == NULL) 1506 dev->first_adapter = adapter; 1507 chan->has_adapter = true; 1508 } else 1509 adapter = dev->first_adapter; 1510 } 1511 1512 if (dev->ci.en && (io & NGENE_IO_TSOUT)) { 1513 dvb_ca_en50221_init(adapter, dev->ci.en, 0, 1); 1514 set_transfer(chan, 1); 1515 chan->dev->channel[2].DataFormatFlags = DF_SWAP32; 1516 set_transfer(&chan->dev->channel[2], 1); 1517 dvb_register_device(adapter, &chan->ci_dev, 1518 &ngene_dvbdev_ci, (void *) chan, 1519 DVB_DEVICE_SEC); 1520 if (!chan->ci_dev) 1521 goto err; 1522 } 1523 1524 if (chan->fe) { 1525 if (dvb_register_frontend(adapter, chan->fe) < 0) 1526 goto err; 1527 chan->has_demux = true; 1528 } 1529 if (chan->fe2) { 1530 if (dvb_register_frontend(adapter, chan->fe2) < 0) 1531 goto err; 1532 chan->fe2->tuner_priv = chan->fe->tuner_priv; 1533 memcpy(&chan->fe2->ops.tuner_ops, 1534 &chan->fe->ops.tuner_ops, 1535 sizeof(struct dvb_tuner_ops)); 1536 } 1537 1538 if (chan->has_demux) { 1539 ret = my_dvb_dmx_ts_card_init(dvbdemux, "SW demux", 1540 ngene_start_feed, 1541 ngene_stop_feed, chan); 1542 ret = my_dvb_dmxdev_ts_card_init(&chan->dmxdev, &chan->demux, 1543 &chan->hw_frontend, 1544 &chan->mem_frontend, adapter); 1545 ret = dvb_net_init(adapter, &chan->dvbnet, &chan->demux.dmx); 1546 } 1547 1548 return ret; 1549 1550 err: 1551 if (chan->fe) { 1552 dvb_frontend_detach(chan->fe); 1553 chan->fe = NULL; 1554 } 1555 release_channel(chan); 1556 return 0; 1557 } 1558 1559 static int init_channels(struct ngene *dev) 1560 { 1561 int i, j; 1562 1563 for (i = 0; i < MAX_STREAM; i++) { 1564 dev->channel[i].number = i; 1565 if (init_channel(&dev->channel[i]) < 0) { 1566 for (j = i - 1; j >= 0; j--) 1567 release_channel(&dev->channel[j]); 1568 return -1; 1569 } 1570 } 1571 return 0; 1572 } 1573 1574 static struct cxd2099_cfg cxd_cfg = { 1575 .bitrate = 62000, 1576 .adr = 0x40, 1577 .polarity = 0, 1578 .clock_mode = 0, 1579 }; 1580 1581 static void cxd_attach(struct ngene *dev) 1582 { 1583 struct ngene_ci *ci = &dev->ci; 1584 1585 ci->en = cxd2099_attach(&cxd_cfg, dev, &dev->channel[0].i2c_adapter); 1586 ci->dev = dev; 1587 return; 1588 } 1589 1590 static void cxd_detach(struct ngene *dev) 1591 { 1592 struct ngene_ci *ci = &dev->ci; 1593 1594 dvb_ca_en50221_release(ci->en); 1595 kfree(ci->en); 1596 ci->en = 0; 1597 } 1598 1599 /***********************************/ 1600 /* workaround for shutdown failure */ 1601 /***********************************/ 1602 1603 static void ngene_unlink(struct ngene *dev) 1604 { 1605 struct ngene_command com; 1606 1607 com.cmd.hdr.Opcode = CMD_MEM_WRITE; 1608 com.cmd.hdr.Length = 3; 1609 com.cmd.MemoryWrite.address = 0x910c; 1610 com.cmd.MemoryWrite.data = 0xff; 1611 com.in_len = 3; 1612 com.out_len = 1; 1613 1614 down(&dev->cmd_mutex); 1615 ngwritel(0, NGENE_INT_ENABLE); 1616 ngene_command_mutex(dev, &com); 1617 up(&dev->cmd_mutex); 1618 } 1619 1620 void ngene_shutdown(struct pci_dev *pdev) 1621 { 1622 struct ngene *dev = pci_get_drvdata(pdev); 1623 1624 if (!dev || !shutdown_workaround) 1625 return; 1626 1627 printk(KERN_INFO DEVICE_NAME ": shutdown workaround...\n"); 1628 ngene_unlink(dev); 1629 pci_disable_device(pdev); 1630 } 1631 1632 /****************************************************************************/ 1633 /* device probe/remove calls ************************************************/ 1634 /****************************************************************************/ 1635 1636 void ngene_remove(struct pci_dev *pdev) 1637 { 1638 struct ngene *dev = pci_get_drvdata(pdev); 1639 int i; 1640 1641 tasklet_kill(&dev->event_tasklet); 1642 for (i = MAX_STREAM - 1; i >= 0; i--) 1643 release_channel(&dev->channel[i]); 1644 if (dev->ci.en) 1645 cxd_detach(dev); 1646 ngene_stop(dev); 1647 ngene_release_buffers(dev); 1648 pci_disable_device(pdev); 1649 } 1650 1651 int ngene_probe(struct pci_dev *pci_dev, const struct pci_device_id *id) 1652 { 1653 struct ngene *dev; 1654 int stat = 0; 1655 1656 if (pci_enable_device(pci_dev) < 0) 1657 return -ENODEV; 1658 1659 dev = vzalloc(sizeof(struct ngene)); 1660 if (dev == NULL) { 1661 stat = -ENOMEM; 1662 goto fail0; 1663 } 1664 1665 dev->pci_dev = pci_dev; 1666 dev->card_info = (struct ngene_info *)id->driver_data; 1667 printk(KERN_INFO DEVICE_NAME ": Found %s\n", dev->card_info->name); 1668 1669 pci_set_drvdata(pci_dev, dev); 1670 1671 /* Alloc buffers and start nGene */ 1672 stat = ngene_get_buffers(dev); 1673 if (stat < 0) 1674 goto fail1; 1675 stat = ngene_start(dev); 1676 if (stat < 0) 1677 goto fail1; 1678 1679 cxd_attach(dev); 1680 1681 stat = ngene_buffer_config(dev); 1682 if (stat < 0) 1683 goto fail1; 1684 1685 1686 dev->i2c_current_bus = -1; 1687 1688 /* Register DVB adapters and devices for both channels */ 1689 stat = init_channels(dev); 1690 if (stat < 0) 1691 goto fail2; 1692 1693 return 0; 1694 1695 fail2: 1696 ngene_stop(dev); 1697 fail1: 1698 ngene_release_buffers(dev); 1699 fail0: 1700 pci_disable_device(pci_dev); 1701 return stat; 1702 } 1703