1 /* 2 * ngene.c: nGene PCIe bridge driver 3 * 4 * Copyright (C) 2005-2007 Micronas 5 * 6 * Copyright (C) 2008-2009 Ralph Metzler <rjkm@metzlerbros.de> 7 * Modifications for new nGene firmware, 8 * support for EEPROM-copying, 9 * support for new dual DVB-S2 card prototype 10 * 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License 14 * version 2 only, as published by the Free Software Foundation. 15 * 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * To obtain the license, point your browser to 23 * http://www.gnu.org/copyleft/gpl.html 24 */ 25 26 #include <linux/module.h> 27 #include <linux/init.h> 28 #include <linux/delay.h> 29 #include <linux/poll.h> 30 #include <linux/io.h> 31 #include <asm/div64.h> 32 #include <linux/pci.h> 33 #include <linux/timer.h> 34 #include <linux/byteorder/generic.h> 35 #include <linux/firmware.h> 36 #include <linux/vmalloc.h> 37 38 #include "ngene.h" 39 40 static int one_adapter; 41 module_param(one_adapter, int, 0444); 42 MODULE_PARM_DESC(one_adapter, "Use only one adapter."); 43 44 static int shutdown_workaround; 45 module_param(shutdown_workaround, int, 0644); 46 MODULE_PARM_DESC(shutdown_workaround, "Activate workaround for shutdown problem with some chipsets."); 47 48 static int debug; 49 module_param(debug, int, 0444); 50 MODULE_PARM_DESC(debug, "Print debugging information."); 51 52 DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr); 53 54 #define dprintk if (debug) printk 55 56 #define ngwriteb(dat, adr) writeb((dat), dev->iomem + (adr)) 57 #define ngwritel(dat, adr) writel((dat), dev->iomem + (adr)) 58 #define ngwriteb(dat, adr) writeb((dat), dev->iomem + (adr)) 59 #define ngreadl(adr) readl(dev->iomem + (adr)) 60 #define ngreadb(adr) readb(dev->iomem + (adr)) 61 #define ngcpyto(adr, src, count) memcpy_toio(dev->iomem + (adr), (src), (count)) 62 #define ngcpyfrom(dst, adr, count) memcpy_fromio((dst), dev->iomem + (adr), (count)) 63 64 /****************************************************************************/ 65 /* nGene interrupt handler **************************************************/ 66 /****************************************************************************/ 67 68 static void event_tasklet(unsigned long data) 69 { 70 struct ngene *dev = (struct ngene *)data; 71 72 while (dev->EventQueueReadIndex != dev->EventQueueWriteIndex) { 73 struct EVENT_BUFFER Event = 74 dev->EventQueue[dev->EventQueueReadIndex]; 75 dev->EventQueueReadIndex = 76 (dev->EventQueueReadIndex + 1) & (EVENT_QUEUE_SIZE - 1); 77 78 if ((Event.UARTStatus & 0x01) && (dev->TxEventNotify)) 79 dev->TxEventNotify(dev, Event.TimeStamp); 80 if ((Event.UARTStatus & 0x02) && (dev->RxEventNotify)) 81 dev->RxEventNotify(dev, Event.TimeStamp, 82 Event.RXCharacter); 83 } 84 } 85 86 static void demux_tasklet(unsigned long data) 87 { 88 struct ngene_channel *chan = (struct ngene_channel *)data; 89 struct SBufferHeader *Cur = chan->nextBuffer; 90 91 spin_lock_irq(&chan->state_lock); 92 93 while (Cur->ngeneBuffer.SR.Flags & 0x80) { 94 if (chan->mode & NGENE_IO_TSOUT) { 95 u32 Flags = chan->DataFormatFlags; 96 if (Cur->ngeneBuffer.SR.Flags & 0x20) 97 Flags |= BEF_OVERFLOW; 98 if (chan->pBufferExchange) { 99 if (!chan->pBufferExchange(chan, 100 Cur->Buffer1, 101 chan->Capture1Length, 102 Cur->ngeneBuffer.SR. 103 Clock, Flags)) { 104 /* 105 We didn't get data 106 Clear in service flag to make sure we 107 get called on next interrupt again. 108 leave fill/empty (0x80) flag alone 109 to avoid hardware running out of 110 buffers during startup, we hold only 111 in run state ( the source may be late 112 delivering data ) 113 */ 114 115 if (chan->HWState == HWSTATE_RUN) { 116 Cur->ngeneBuffer.SR.Flags &= 117 ~0x40; 118 break; 119 /* Stop processing stream */ 120 } 121 } else { 122 /* We got a valid buffer, 123 so switch to run state */ 124 chan->HWState = HWSTATE_RUN; 125 } 126 } else { 127 printk(KERN_ERR DEVICE_NAME ": OOPS\n"); 128 if (chan->HWState == HWSTATE_RUN) { 129 Cur->ngeneBuffer.SR.Flags &= ~0x40; 130 break; /* Stop processing stream */ 131 } 132 } 133 if (chan->AudioDTOUpdated) { 134 printk(KERN_INFO DEVICE_NAME 135 ": Update AudioDTO = %d\n", 136 chan->AudioDTOValue); 137 Cur->ngeneBuffer.SR.DTOUpdate = 138 chan->AudioDTOValue; 139 chan->AudioDTOUpdated = 0; 140 } 141 } else { 142 if (chan->HWState == HWSTATE_RUN) { 143 u32 Flags = chan->DataFormatFlags; 144 IBufferExchange *exch1 = chan->pBufferExchange; 145 IBufferExchange *exch2 = chan->pBufferExchange2; 146 if (Cur->ngeneBuffer.SR.Flags & 0x01) 147 Flags |= BEF_EVEN_FIELD; 148 if (Cur->ngeneBuffer.SR.Flags & 0x20) 149 Flags |= BEF_OVERFLOW; 150 spin_unlock_irq(&chan->state_lock); 151 if (exch1) 152 exch1(chan, Cur->Buffer1, 153 chan->Capture1Length, 154 Cur->ngeneBuffer.SR.Clock, 155 Flags); 156 if (exch2) 157 exch2(chan, Cur->Buffer2, 158 chan->Capture2Length, 159 Cur->ngeneBuffer.SR.Clock, 160 Flags); 161 spin_lock_irq(&chan->state_lock); 162 } else if (chan->HWState != HWSTATE_STOP) 163 chan->HWState = HWSTATE_RUN; 164 } 165 Cur->ngeneBuffer.SR.Flags = 0x00; 166 Cur = Cur->Next; 167 } 168 chan->nextBuffer = Cur; 169 170 spin_unlock_irq(&chan->state_lock); 171 } 172 173 static irqreturn_t irq_handler(int irq, void *dev_id) 174 { 175 struct ngene *dev = (struct ngene *)dev_id; 176 u32 icounts = 0; 177 irqreturn_t rc = IRQ_NONE; 178 u32 i = MAX_STREAM; 179 u8 *tmpCmdDoneByte; 180 181 if (dev->BootFirmware) { 182 icounts = ngreadl(NGENE_INT_COUNTS); 183 if (icounts != dev->icounts) { 184 ngwritel(0, FORCE_NMI); 185 dev->cmd_done = 1; 186 wake_up(&dev->cmd_wq); 187 dev->icounts = icounts; 188 rc = IRQ_HANDLED; 189 } 190 return rc; 191 } 192 193 ngwritel(0, FORCE_NMI); 194 195 spin_lock(&dev->cmd_lock); 196 tmpCmdDoneByte = dev->CmdDoneByte; 197 if (tmpCmdDoneByte && 198 (*tmpCmdDoneByte || 199 (dev->ngenetohost[0] == 1 && dev->ngenetohost[1] != 0))) { 200 dev->CmdDoneByte = NULL; 201 dev->cmd_done = 1; 202 wake_up(&dev->cmd_wq); 203 rc = IRQ_HANDLED; 204 } 205 spin_unlock(&dev->cmd_lock); 206 207 if (dev->EventBuffer->EventStatus & 0x80) { 208 u8 nextWriteIndex = 209 (dev->EventQueueWriteIndex + 1) & 210 (EVENT_QUEUE_SIZE - 1); 211 if (nextWriteIndex != dev->EventQueueReadIndex) { 212 dev->EventQueue[dev->EventQueueWriteIndex] = 213 *(dev->EventBuffer); 214 dev->EventQueueWriteIndex = nextWriteIndex; 215 } else { 216 printk(KERN_ERR DEVICE_NAME ": event overflow\n"); 217 dev->EventQueueOverflowCount += 1; 218 dev->EventQueueOverflowFlag = 1; 219 } 220 dev->EventBuffer->EventStatus &= ~0x80; 221 tasklet_schedule(&dev->event_tasklet); 222 rc = IRQ_HANDLED; 223 } 224 225 while (i > 0) { 226 i--; 227 spin_lock(&dev->channel[i].state_lock); 228 /* if (dev->channel[i].State>=KSSTATE_RUN) { */ 229 if (dev->channel[i].nextBuffer) { 230 if ((dev->channel[i].nextBuffer-> 231 ngeneBuffer.SR.Flags & 0xC0) == 0x80) { 232 dev->channel[i].nextBuffer-> 233 ngeneBuffer.SR.Flags |= 0x40; 234 tasklet_schedule( 235 &dev->channel[i].demux_tasklet); 236 rc = IRQ_HANDLED; 237 } 238 } 239 spin_unlock(&dev->channel[i].state_lock); 240 } 241 242 /* Request might have been processed by a previous call. */ 243 return IRQ_HANDLED; 244 } 245 246 /****************************************************************************/ 247 /* nGene command interface **************************************************/ 248 /****************************************************************************/ 249 250 static void dump_command_io(struct ngene *dev) 251 { 252 u8 buf[8], *b; 253 254 ngcpyfrom(buf, HOST_TO_NGENE, 8); 255 printk(KERN_ERR "host_to_ngene (%04x): %*ph\n", HOST_TO_NGENE, 8, buf); 256 257 ngcpyfrom(buf, NGENE_TO_HOST, 8); 258 printk(KERN_ERR "ngene_to_host (%04x): %*ph\n", NGENE_TO_HOST, 8, buf); 259 260 b = dev->hosttongene; 261 printk(KERN_ERR "dev->hosttongene (%p): %*ph\n", b, 8, b); 262 263 b = dev->ngenetohost; 264 printk(KERN_ERR "dev->ngenetohost (%p): %*ph\n", b, 8, b); 265 } 266 267 static int ngene_command_mutex(struct ngene *dev, struct ngene_command *com) 268 { 269 int ret; 270 u8 *tmpCmdDoneByte; 271 272 dev->cmd_done = 0; 273 274 if (com->cmd.hdr.Opcode == CMD_FWLOAD_PREPARE) { 275 dev->BootFirmware = 1; 276 dev->icounts = ngreadl(NGENE_INT_COUNTS); 277 ngwritel(0, NGENE_COMMAND); 278 ngwritel(0, NGENE_COMMAND_HI); 279 ngwritel(0, NGENE_STATUS); 280 ngwritel(0, NGENE_STATUS_HI); 281 ngwritel(0, NGENE_EVENT); 282 ngwritel(0, NGENE_EVENT_HI); 283 } else if (com->cmd.hdr.Opcode == CMD_FWLOAD_FINISH) { 284 u64 fwio = dev->PAFWInterfaceBuffer; 285 286 ngwritel(fwio & 0xffffffff, NGENE_COMMAND); 287 ngwritel(fwio >> 32, NGENE_COMMAND_HI); 288 ngwritel((fwio + 256) & 0xffffffff, NGENE_STATUS); 289 ngwritel((fwio + 256) >> 32, NGENE_STATUS_HI); 290 ngwritel((fwio + 512) & 0xffffffff, NGENE_EVENT); 291 ngwritel((fwio + 512) >> 32, NGENE_EVENT_HI); 292 } 293 294 memcpy(dev->FWInterfaceBuffer, com->cmd.raw8, com->in_len + 2); 295 296 if (dev->BootFirmware) 297 ngcpyto(HOST_TO_NGENE, com->cmd.raw8, com->in_len + 2); 298 299 spin_lock_irq(&dev->cmd_lock); 300 tmpCmdDoneByte = dev->ngenetohost + com->out_len; 301 if (!com->out_len) 302 tmpCmdDoneByte++; 303 *tmpCmdDoneByte = 0; 304 dev->ngenetohost[0] = 0; 305 dev->ngenetohost[1] = 0; 306 dev->CmdDoneByte = tmpCmdDoneByte; 307 spin_unlock_irq(&dev->cmd_lock); 308 309 /* Notify 8051. */ 310 ngwritel(1, FORCE_INT); 311 312 ret = wait_event_timeout(dev->cmd_wq, dev->cmd_done == 1, 2 * HZ); 313 if (!ret) { 314 /*ngwritel(0, FORCE_NMI);*/ 315 316 printk(KERN_ERR DEVICE_NAME 317 ": Command timeout cmd=%02x prev=%02x\n", 318 com->cmd.hdr.Opcode, dev->prev_cmd); 319 dump_command_io(dev); 320 return -1; 321 } 322 if (com->cmd.hdr.Opcode == CMD_FWLOAD_FINISH) 323 dev->BootFirmware = 0; 324 325 dev->prev_cmd = com->cmd.hdr.Opcode; 326 327 if (!com->out_len) 328 return 0; 329 330 memcpy(com->cmd.raw8, dev->ngenetohost, com->out_len); 331 332 return 0; 333 } 334 335 int ngene_command(struct ngene *dev, struct ngene_command *com) 336 { 337 int result; 338 339 mutex_lock(&dev->cmd_mutex); 340 result = ngene_command_mutex(dev, com); 341 mutex_unlock(&dev->cmd_mutex); 342 return result; 343 } 344 345 346 static int ngene_command_load_firmware(struct ngene *dev, 347 u8 *ngene_fw, u32 size) 348 { 349 #define FIRSTCHUNK (1024) 350 u32 cleft; 351 struct ngene_command com; 352 353 com.cmd.hdr.Opcode = CMD_FWLOAD_PREPARE; 354 com.cmd.hdr.Length = 0; 355 com.in_len = 0; 356 com.out_len = 0; 357 358 ngene_command(dev, &com); 359 360 cleft = (size + 3) & ~3; 361 if (cleft > FIRSTCHUNK) { 362 ngcpyto(PROGRAM_SRAM + FIRSTCHUNK, ngene_fw + FIRSTCHUNK, 363 cleft - FIRSTCHUNK); 364 cleft = FIRSTCHUNK; 365 } 366 ngcpyto(DATA_FIFO_AREA, ngene_fw, cleft); 367 368 memset(&com, 0, sizeof(struct ngene_command)); 369 com.cmd.hdr.Opcode = CMD_FWLOAD_FINISH; 370 com.cmd.hdr.Length = 4; 371 com.cmd.FWLoadFinish.Address = DATA_FIFO_AREA; 372 com.cmd.FWLoadFinish.Length = (unsigned short)cleft; 373 com.in_len = 4; 374 com.out_len = 0; 375 376 return ngene_command(dev, &com); 377 } 378 379 380 static int ngene_command_config_buf(struct ngene *dev, u8 config) 381 { 382 struct ngene_command com; 383 384 com.cmd.hdr.Opcode = CMD_CONFIGURE_BUFFER; 385 com.cmd.hdr.Length = 1; 386 com.cmd.ConfigureBuffers.config = config; 387 com.in_len = 1; 388 com.out_len = 0; 389 390 if (ngene_command(dev, &com) < 0) 391 return -EIO; 392 return 0; 393 } 394 395 static int ngene_command_config_free_buf(struct ngene *dev, u8 *config) 396 { 397 struct ngene_command com; 398 399 com.cmd.hdr.Opcode = CMD_CONFIGURE_FREE_BUFFER; 400 com.cmd.hdr.Length = 6; 401 memcpy(&com.cmd.ConfigureBuffers.config, config, 6); 402 com.in_len = 6; 403 com.out_len = 0; 404 405 if (ngene_command(dev, &com) < 0) 406 return -EIO; 407 408 return 0; 409 } 410 411 int ngene_command_gpio_set(struct ngene *dev, u8 select, u8 level) 412 { 413 struct ngene_command com; 414 415 com.cmd.hdr.Opcode = CMD_SET_GPIO_PIN; 416 com.cmd.hdr.Length = 1; 417 com.cmd.SetGpioPin.select = select | (level << 7); 418 com.in_len = 1; 419 com.out_len = 0; 420 421 return ngene_command(dev, &com); 422 } 423 424 425 /* 426 02000640 is sample on rising edge. 427 02000740 is sample on falling edge. 428 02000040 is ignore "valid" signal 429 430 0: FD_CTL1 Bit 7,6 must be 0,1 431 7 disable(fw controlled) 432 6 0-AUX,1-TS 433 5 0-par,1-ser 434 4 0-lsb/1-msb 435 3,2 reserved 436 1,0 0-no sync, 1-use ext. start, 2-use 0x47, 3-both 437 1: FD_CTL2 has 3-valid must be hi, 2-use valid, 1-edge 438 2: FD_STA is read-only. 0-sync 439 3: FD_INSYNC is number of 47s to trigger "in sync". 440 4: FD_OUTSYNC is number of 47s to trigger "out of sync". 441 5: FD_MAXBYTE1 is low-order of bytes per packet. 442 6: FD_MAXBYTE2 is high-order of bytes per packet. 443 7: Top byte is unused. 444 */ 445 446 /****************************************************************************/ 447 448 static u8 TSFeatureDecoderSetup[8 * 5] = { 449 0x42, 0x00, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, 450 0x40, 0x06, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* DRXH */ 451 0x71, 0x07, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* DRXHser */ 452 0x72, 0x00, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* S2ser */ 453 0x40, 0x07, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* LGDT3303 */ 454 }; 455 456 /* Set NGENE I2S Config to 16 bit packed */ 457 static u8 I2SConfiguration[] = { 458 0x00, 0x10, 0x00, 0x00, 459 0x80, 0x10, 0x00, 0x00, 460 }; 461 462 static u8 SPDIFConfiguration[10] = { 463 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 464 }; 465 466 /* Set NGENE I2S Config to transport stream compatible mode */ 467 468 static u8 TS_I2SConfiguration[4] = { 0x3E, 0x18, 0x00, 0x00 }; 469 470 static u8 TS_I2SOutConfiguration[4] = { 0x80, 0x04, 0x00, 0x00 }; 471 472 static u8 ITUDecoderSetup[4][16] = { 473 {0x1c, 0x13, 0x01, 0x68, 0x3d, 0x90, 0x14, 0x20, /* SDTV */ 474 0x00, 0x00, 0x01, 0xb0, 0x9c, 0x00, 0x00, 0x00}, 475 {0x9c, 0x03, 0x23, 0xC0, 0x60, 0x0E, 0x13, 0x00, 476 0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00}, 477 {0x9f, 0x00, 0x23, 0xC0, 0x60, 0x0F, 0x13, 0x00, /* HDTV 1080i50 */ 478 0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00}, 479 {0x9c, 0x01, 0x23, 0xC0, 0x60, 0x0E, 0x13, 0x00, /* HDTV 1080i60 */ 480 0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00}, 481 }; 482 483 /* 484 * 50 48 60 gleich 485 * 27p50 9f 00 22 80 42 69 18 ... 486 * 27p60 93 00 22 80 82 69 1c ... 487 */ 488 489 /* Maxbyte to 1144 (for raw data) */ 490 static u8 ITUFeatureDecoderSetup[8] = { 491 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x04, 0x00 492 }; 493 494 void FillTSBuffer(void *Buffer, int Length, u32 Flags) 495 { 496 u32 *ptr = Buffer; 497 498 memset(Buffer, TS_FILLER, Length); 499 while (Length > 0) { 500 if (Flags & DF_SWAP32) 501 *ptr = 0x471FFF10; 502 else 503 *ptr = 0x10FF1F47; 504 ptr += (188 / 4); 505 Length -= 188; 506 } 507 } 508 509 510 static void flush_buffers(struct ngene_channel *chan) 511 { 512 u8 val; 513 514 do { 515 msleep(1); 516 spin_lock_irq(&chan->state_lock); 517 val = chan->nextBuffer->ngeneBuffer.SR.Flags & 0x80; 518 spin_unlock_irq(&chan->state_lock); 519 } while (val); 520 } 521 522 static void clear_buffers(struct ngene_channel *chan) 523 { 524 struct SBufferHeader *Cur = chan->nextBuffer; 525 526 do { 527 memset(&Cur->ngeneBuffer.SR, 0, sizeof(Cur->ngeneBuffer.SR)); 528 if (chan->mode & NGENE_IO_TSOUT) 529 FillTSBuffer(Cur->Buffer1, 530 chan->Capture1Length, 531 chan->DataFormatFlags); 532 Cur = Cur->Next; 533 } while (Cur != chan->nextBuffer); 534 535 if (chan->mode & NGENE_IO_TSOUT) { 536 chan->nextBuffer->ngeneBuffer.SR.DTOUpdate = 537 chan->AudioDTOValue; 538 chan->AudioDTOUpdated = 0; 539 540 Cur = chan->TSIdleBuffer.Head; 541 542 do { 543 memset(&Cur->ngeneBuffer.SR, 0, 544 sizeof(Cur->ngeneBuffer.SR)); 545 FillTSBuffer(Cur->Buffer1, 546 chan->Capture1Length, 547 chan->DataFormatFlags); 548 Cur = Cur->Next; 549 } while (Cur != chan->TSIdleBuffer.Head); 550 } 551 } 552 553 static int ngene_command_stream_control(struct ngene *dev, u8 stream, 554 u8 control, u8 mode, u8 flags) 555 { 556 struct ngene_channel *chan = &dev->channel[stream]; 557 struct ngene_command com; 558 u16 BsUVI = ((stream & 1) ? 0x9400 : 0x9300); 559 u16 BsSDI = ((stream & 1) ? 0x9600 : 0x9500); 560 u16 BsSPI = ((stream & 1) ? 0x9800 : 0x9700); 561 u16 BsSDO = 0x9B00; 562 563 memset(&com, 0, sizeof(com)); 564 com.cmd.hdr.Opcode = CMD_CONTROL; 565 com.cmd.hdr.Length = sizeof(struct FW_STREAM_CONTROL) - 2; 566 com.cmd.StreamControl.Stream = stream | (control ? 8 : 0); 567 if (chan->mode & NGENE_IO_TSOUT) 568 com.cmd.StreamControl.Stream |= 0x07; 569 com.cmd.StreamControl.Control = control | 570 (flags & SFLAG_ORDER_LUMA_CHROMA); 571 com.cmd.StreamControl.Mode = mode; 572 com.in_len = sizeof(struct FW_STREAM_CONTROL); 573 com.out_len = 0; 574 575 dprintk(KERN_INFO DEVICE_NAME 576 ": Stream=%02x, Control=%02x, Mode=%02x\n", 577 com.cmd.StreamControl.Stream, com.cmd.StreamControl.Control, 578 com.cmd.StreamControl.Mode); 579 580 chan->Mode = mode; 581 582 if (!(control & 0x80)) { 583 spin_lock_irq(&chan->state_lock); 584 if (chan->State == KSSTATE_RUN) { 585 chan->State = KSSTATE_ACQUIRE; 586 chan->HWState = HWSTATE_STOP; 587 spin_unlock_irq(&chan->state_lock); 588 if (ngene_command(dev, &com) < 0) 589 return -1; 590 /* clear_buffers(chan); */ 591 flush_buffers(chan); 592 return 0; 593 } 594 spin_unlock_irq(&chan->state_lock); 595 return 0; 596 } 597 598 if (mode & SMODE_AUDIO_CAPTURE) { 599 com.cmd.StreamControl.CaptureBlockCount = 600 chan->Capture1Length / AUDIO_BLOCK_SIZE; 601 com.cmd.StreamControl.Buffer_Address = chan->RingBuffer.PAHead; 602 } else if (mode & SMODE_TRANSPORT_STREAM) { 603 com.cmd.StreamControl.CaptureBlockCount = 604 chan->Capture1Length / TS_BLOCK_SIZE; 605 com.cmd.StreamControl.MaxLinesPerField = 606 chan->Capture1Length / TS_BLOCK_SIZE; 607 com.cmd.StreamControl.Buffer_Address = 608 chan->TSRingBuffer.PAHead; 609 if (chan->mode & NGENE_IO_TSOUT) { 610 com.cmd.StreamControl.BytesPerVBILine = 611 chan->Capture1Length / TS_BLOCK_SIZE; 612 com.cmd.StreamControl.Stream |= 0x07; 613 } 614 } else { 615 com.cmd.StreamControl.BytesPerVideoLine = chan->nBytesPerLine; 616 com.cmd.StreamControl.MaxLinesPerField = chan->nLines; 617 com.cmd.StreamControl.MinLinesPerField = 100; 618 com.cmd.StreamControl.Buffer_Address = chan->RingBuffer.PAHead; 619 620 if (mode & SMODE_VBI_CAPTURE) { 621 com.cmd.StreamControl.MaxVBILinesPerField = 622 chan->nVBILines; 623 com.cmd.StreamControl.MinVBILinesPerField = 0; 624 com.cmd.StreamControl.BytesPerVBILine = 625 chan->nBytesPerVBILine; 626 } 627 if (flags & SFLAG_COLORBAR) 628 com.cmd.StreamControl.Stream |= 0x04; 629 } 630 631 spin_lock_irq(&chan->state_lock); 632 if (mode & SMODE_AUDIO_CAPTURE) { 633 chan->nextBuffer = chan->RingBuffer.Head; 634 if (mode & SMODE_AUDIO_SPDIF) { 635 com.cmd.StreamControl.SetupDataLen = 636 sizeof(SPDIFConfiguration); 637 com.cmd.StreamControl.SetupDataAddr = BsSPI; 638 memcpy(com.cmd.StreamControl.SetupData, 639 SPDIFConfiguration, sizeof(SPDIFConfiguration)); 640 } else { 641 com.cmd.StreamControl.SetupDataLen = 4; 642 com.cmd.StreamControl.SetupDataAddr = BsSDI; 643 memcpy(com.cmd.StreamControl.SetupData, 644 I2SConfiguration + 645 4 * dev->card_info->i2s[stream], 4); 646 } 647 } else if (mode & SMODE_TRANSPORT_STREAM) { 648 chan->nextBuffer = chan->TSRingBuffer.Head; 649 if (stream >= STREAM_AUDIOIN1) { 650 if (chan->mode & NGENE_IO_TSOUT) { 651 com.cmd.StreamControl.SetupDataLen = 652 sizeof(TS_I2SOutConfiguration); 653 com.cmd.StreamControl.SetupDataAddr = BsSDO; 654 memcpy(com.cmd.StreamControl.SetupData, 655 TS_I2SOutConfiguration, 656 sizeof(TS_I2SOutConfiguration)); 657 } else { 658 com.cmd.StreamControl.SetupDataLen = 659 sizeof(TS_I2SConfiguration); 660 com.cmd.StreamControl.SetupDataAddr = BsSDI; 661 memcpy(com.cmd.StreamControl.SetupData, 662 TS_I2SConfiguration, 663 sizeof(TS_I2SConfiguration)); 664 } 665 } else { 666 com.cmd.StreamControl.SetupDataLen = 8; 667 com.cmd.StreamControl.SetupDataAddr = BsUVI + 0x10; 668 memcpy(com.cmd.StreamControl.SetupData, 669 TSFeatureDecoderSetup + 670 8 * dev->card_info->tsf[stream], 8); 671 } 672 } else { 673 chan->nextBuffer = chan->RingBuffer.Head; 674 com.cmd.StreamControl.SetupDataLen = 675 16 + sizeof(ITUFeatureDecoderSetup); 676 com.cmd.StreamControl.SetupDataAddr = BsUVI; 677 memcpy(com.cmd.StreamControl.SetupData, 678 ITUDecoderSetup[chan->itumode], 16); 679 memcpy(com.cmd.StreamControl.SetupData + 16, 680 ITUFeatureDecoderSetup, sizeof(ITUFeatureDecoderSetup)); 681 } 682 clear_buffers(chan); 683 chan->State = KSSTATE_RUN; 684 if (mode & SMODE_TRANSPORT_STREAM) 685 chan->HWState = HWSTATE_RUN; 686 else 687 chan->HWState = HWSTATE_STARTUP; 688 spin_unlock_irq(&chan->state_lock); 689 690 if (ngene_command(dev, &com) < 0) 691 return -1; 692 693 return 0; 694 } 695 696 void set_transfer(struct ngene_channel *chan, int state) 697 { 698 u8 control = 0, mode = 0, flags = 0; 699 struct ngene *dev = chan->dev; 700 int ret; 701 702 /* 703 printk(KERN_INFO DEVICE_NAME ": st %d\n", state); 704 msleep(100); 705 */ 706 707 if (state) { 708 if (chan->running) { 709 printk(KERN_INFO DEVICE_NAME ": already running\n"); 710 return; 711 } 712 } else { 713 if (!chan->running) { 714 printk(KERN_INFO DEVICE_NAME ": already stopped\n"); 715 return; 716 } 717 } 718 719 if (dev->card_info->switch_ctrl) 720 dev->card_info->switch_ctrl(chan, 1, state ^ 1); 721 722 if (state) { 723 spin_lock_irq(&chan->state_lock); 724 725 /* printk(KERN_INFO DEVICE_NAME ": lock=%08x\n", 726 ngreadl(0x9310)); */ 727 dvb_ringbuffer_flush(&dev->tsout_rbuf); 728 control = 0x80; 729 if (chan->mode & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) { 730 chan->Capture1Length = 512 * 188; 731 mode = SMODE_TRANSPORT_STREAM; 732 } 733 if (chan->mode & NGENE_IO_TSOUT) { 734 chan->pBufferExchange = tsout_exchange; 735 /* 0x66666666 = 50MHz *2^33 /250MHz */ 736 chan->AudioDTOValue = 0x80000000; 737 chan->AudioDTOUpdated = 1; 738 } 739 if (chan->mode & NGENE_IO_TSIN) 740 chan->pBufferExchange = tsin_exchange; 741 spin_unlock_irq(&chan->state_lock); 742 } 743 /* else printk(KERN_INFO DEVICE_NAME ": lock=%08x\n", 744 ngreadl(0x9310)); */ 745 746 mutex_lock(&dev->stream_mutex); 747 ret = ngene_command_stream_control(dev, chan->number, 748 control, mode, flags); 749 mutex_unlock(&dev->stream_mutex); 750 751 if (!ret) 752 chan->running = state; 753 else 754 printk(KERN_ERR DEVICE_NAME ": set_transfer %d failed\n", 755 state); 756 if (!state) { 757 spin_lock_irq(&chan->state_lock); 758 chan->pBufferExchange = NULL; 759 dvb_ringbuffer_flush(&dev->tsout_rbuf); 760 spin_unlock_irq(&chan->state_lock); 761 } 762 } 763 764 765 /****************************************************************************/ 766 /* nGene hardware init and release functions ********************************/ 767 /****************************************************************************/ 768 769 static void free_ringbuffer(struct ngene *dev, struct SRingBufferDescriptor *rb) 770 { 771 struct SBufferHeader *Cur = rb->Head; 772 u32 j; 773 774 if (!Cur) 775 return; 776 777 for (j = 0; j < rb->NumBuffers; j++, Cur = Cur->Next) { 778 if (Cur->Buffer1) 779 pci_free_consistent(dev->pci_dev, 780 rb->Buffer1Length, 781 Cur->Buffer1, 782 Cur->scList1->Address); 783 784 if (Cur->Buffer2) 785 pci_free_consistent(dev->pci_dev, 786 rb->Buffer2Length, 787 Cur->Buffer2, 788 Cur->scList2->Address); 789 } 790 791 if (rb->SCListMem) 792 pci_free_consistent(dev->pci_dev, rb->SCListMemSize, 793 rb->SCListMem, rb->PASCListMem); 794 795 pci_free_consistent(dev->pci_dev, rb->MemSize, rb->Head, rb->PAHead); 796 } 797 798 static void free_idlebuffer(struct ngene *dev, 799 struct SRingBufferDescriptor *rb, 800 struct SRingBufferDescriptor *tb) 801 { 802 int j; 803 struct SBufferHeader *Cur = tb->Head; 804 805 if (!rb->Head) 806 return; 807 free_ringbuffer(dev, rb); 808 for (j = 0; j < tb->NumBuffers; j++, Cur = Cur->Next) { 809 Cur->Buffer2 = NULL; 810 Cur->scList2 = NULL; 811 Cur->ngeneBuffer.Address_of_first_entry_2 = 0; 812 Cur->ngeneBuffer.Number_of_entries_2 = 0; 813 } 814 } 815 816 static void free_common_buffers(struct ngene *dev) 817 { 818 u32 i; 819 struct ngene_channel *chan; 820 821 for (i = STREAM_VIDEOIN1; i < MAX_STREAM; i++) { 822 chan = &dev->channel[i]; 823 free_idlebuffer(dev, &chan->TSIdleBuffer, &chan->TSRingBuffer); 824 free_ringbuffer(dev, &chan->RingBuffer); 825 free_ringbuffer(dev, &chan->TSRingBuffer); 826 } 827 828 if (dev->OverflowBuffer) 829 pci_free_consistent(dev->pci_dev, 830 OVERFLOW_BUFFER_SIZE, 831 dev->OverflowBuffer, dev->PAOverflowBuffer); 832 833 if (dev->FWInterfaceBuffer) 834 pci_free_consistent(dev->pci_dev, 835 4096, 836 dev->FWInterfaceBuffer, 837 dev->PAFWInterfaceBuffer); 838 } 839 840 /****************************************************************************/ 841 /* Ring buffer handling *****************************************************/ 842 /****************************************************************************/ 843 844 static int create_ring_buffer(struct pci_dev *pci_dev, 845 struct SRingBufferDescriptor *descr, u32 NumBuffers) 846 { 847 dma_addr_t tmp; 848 struct SBufferHeader *Head; 849 u32 i; 850 u32 MemSize = SIZEOF_SBufferHeader * NumBuffers; 851 u64 PARingBufferHead; 852 u64 PARingBufferCur; 853 u64 PARingBufferNext; 854 struct SBufferHeader *Cur, *Next; 855 856 descr->Head = NULL; 857 descr->MemSize = 0; 858 descr->PAHead = 0; 859 descr->NumBuffers = 0; 860 861 if (MemSize < 4096) 862 MemSize = 4096; 863 864 Head = pci_alloc_consistent(pci_dev, MemSize, &tmp); 865 PARingBufferHead = tmp; 866 867 if (!Head) 868 return -ENOMEM; 869 870 memset(Head, 0, MemSize); 871 872 PARingBufferCur = PARingBufferHead; 873 Cur = Head; 874 875 for (i = 0; i < NumBuffers - 1; i++) { 876 Next = (struct SBufferHeader *) 877 (((u8 *) Cur) + SIZEOF_SBufferHeader); 878 PARingBufferNext = PARingBufferCur + SIZEOF_SBufferHeader; 879 Cur->Next = Next; 880 Cur->ngeneBuffer.Next = PARingBufferNext; 881 Cur = Next; 882 PARingBufferCur = PARingBufferNext; 883 } 884 /* Last Buffer points back to first one */ 885 Cur->Next = Head; 886 Cur->ngeneBuffer.Next = PARingBufferHead; 887 888 descr->Head = Head; 889 descr->MemSize = MemSize; 890 descr->PAHead = PARingBufferHead; 891 descr->NumBuffers = NumBuffers; 892 893 return 0; 894 } 895 896 static int AllocateRingBuffers(struct pci_dev *pci_dev, 897 dma_addr_t of, 898 struct SRingBufferDescriptor *pRingBuffer, 899 u32 Buffer1Length, u32 Buffer2Length) 900 { 901 dma_addr_t tmp; 902 u32 i, j; 903 u32 SCListMemSize = pRingBuffer->NumBuffers 904 * ((Buffer2Length != 0) ? (NUM_SCATTER_GATHER_ENTRIES * 2) : 905 NUM_SCATTER_GATHER_ENTRIES) 906 * sizeof(struct HW_SCATTER_GATHER_ELEMENT); 907 908 u64 PASCListMem; 909 struct HW_SCATTER_GATHER_ELEMENT *SCListEntry; 910 u64 PASCListEntry; 911 struct SBufferHeader *Cur; 912 void *SCListMem; 913 914 if (SCListMemSize < 4096) 915 SCListMemSize = 4096; 916 917 SCListMem = pci_alloc_consistent(pci_dev, SCListMemSize, &tmp); 918 919 PASCListMem = tmp; 920 if (SCListMem == NULL) 921 return -ENOMEM; 922 923 memset(SCListMem, 0, SCListMemSize); 924 925 pRingBuffer->SCListMem = SCListMem; 926 pRingBuffer->PASCListMem = PASCListMem; 927 pRingBuffer->SCListMemSize = SCListMemSize; 928 pRingBuffer->Buffer1Length = Buffer1Length; 929 pRingBuffer->Buffer2Length = Buffer2Length; 930 931 SCListEntry = SCListMem; 932 PASCListEntry = PASCListMem; 933 Cur = pRingBuffer->Head; 934 935 for (i = 0; i < pRingBuffer->NumBuffers; i += 1, Cur = Cur->Next) { 936 u64 PABuffer; 937 938 void *Buffer = pci_alloc_consistent(pci_dev, Buffer1Length, 939 &tmp); 940 PABuffer = tmp; 941 942 if (Buffer == NULL) 943 return -ENOMEM; 944 945 Cur->Buffer1 = Buffer; 946 947 SCListEntry->Address = PABuffer; 948 SCListEntry->Length = Buffer1Length; 949 950 Cur->scList1 = SCListEntry; 951 Cur->ngeneBuffer.Address_of_first_entry_1 = PASCListEntry; 952 Cur->ngeneBuffer.Number_of_entries_1 = 953 NUM_SCATTER_GATHER_ENTRIES; 954 955 SCListEntry += 1; 956 PASCListEntry += sizeof(struct HW_SCATTER_GATHER_ELEMENT); 957 958 #if NUM_SCATTER_GATHER_ENTRIES > 1 959 for (j = 0; j < NUM_SCATTER_GATHER_ENTRIES - 1; j += 1) { 960 SCListEntry->Address = of; 961 SCListEntry->Length = OVERFLOW_BUFFER_SIZE; 962 SCListEntry += 1; 963 PASCListEntry += 964 sizeof(struct HW_SCATTER_GATHER_ELEMENT); 965 } 966 #endif 967 968 if (!Buffer2Length) 969 continue; 970 971 Buffer = pci_alloc_consistent(pci_dev, Buffer2Length, &tmp); 972 PABuffer = tmp; 973 974 if (Buffer == NULL) 975 return -ENOMEM; 976 977 Cur->Buffer2 = Buffer; 978 979 SCListEntry->Address = PABuffer; 980 SCListEntry->Length = Buffer2Length; 981 982 Cur->scList2 = SCListEntry; 983 Cur->ngeneBuffer.Address_of_first_entry_2 = PASCListEntry; 984 Cur->ngeneBuffer.Number_of_entries_2 = 985 NUM_SCATTER_GATHER_ENTRIES; 986 987 SCListEntry += 1; 988 PASCListEntry += sizeof(struct HW_SCATTER_GATHER_ELEMENT); 989 990 #if NUM_SCATTER_GATHER_ENTRIES > 1 991 for (j = 0; j < NUM_SCATTER_GATHER_ENTRIES - 1; j++) { 992 SCListEntry->Address = of; 993 SCListEntry->Length = OVERFLOW_BUFFER_SIZE; 994 SCListEntry += 1; 995 PASCListEntry += 996 sizeof(struct HW_SCATTER_GATHER_ELEMENT); 997 } 998 #endif 999 1000 } 1001 1002 return 0; 1003 } 1004 1005 static int FillTSIdleBuffer(struct SRingBufferDescriptor *pIdleBuffer, 1006 struct SRingBufferDescriptor *pRingBuffer) 1007 { 1008 /* Copy pointer to scatter gather list in TSRingbuffer 1009 structure for buffer 2 1010 Load number of buffer 1011 */ 1012 u32 n = pRingBuffer->NumBuffers; 1013 1014 /* Point to first buffer entry */ 1015 struct SBufferHeader *Cur = pRingBuffer->Head; 1016 int i; 1017 /* Loop thru all buffer and set Buffer 2 pointers to TSIdlebuffer */ 1018 for (i = 0; i < n; i++) { 1019 Cur->Buffer2 = pIdleBuffer->Head->Buffer1; 1020 Cur->scList2 = pIdleBuffer->Head->scList1; 1021 Cur->ngeneBuffer.Address_of_first_entry_2 = 1022 pIdleBuffer->Head->ngeneBuffer. 1023 Address_of_first_entry_1; 1024 Cur->ngeneBuffer.Number_of_entries_2 = 1025 pIdleBuffer->Head->ngeneBuffer.Number_of_entries_1; 1026 Cur = Cur->Next; 1027 } 1028 return 0; 1029 } 1030 1031 static u32 RingBufferSizes[MAX_STREAM] = { 1032 RING_SIZE_VIDEO, 1033 RING_SIZE_VIDEO, 1034 RING_SIZE_AUDIO, 1035 RING_SIZE_AUDIO, 1036 RING_SIZE_AUDIO, 1037 }; 1038 1039 static u32 Buffer1Sizes[MAX_STREAM] = { 1040 MAX_VIDEO_BUFFER_SIZE, 1041 MAX_VIDEO_BUFFER_SIZE, 1042 MAX_AUDIO_BUFFER_SIZE, 1043 MAX_AUDIO_BUFFER_SIZE, 1044 MAX_AUDIO_BUFFER_SIZE 1045 }; 1046 1047 static u32 Buffer2Sizes[MAX_STREAM] = { 1048 MAX_VBI_BUFFER_SIZE, 1049 MAX_VBI_BUFFER_SIZE, 1050 0, 1051 0, 1052 0 1053 }; 1054 1055 1056 static int AllocCommonBuffers(struct ngene *dev) 1057 { 1058 int status = 0, i; 1059 1060 dev->FWInterfaceBuffer = pci_alloc_consistent(dev->pci_dev, 4096, 1061 &dev->PAFWInterfaceBuffer); 1062 if (!dev->FWInterfaceBuffer) 1063 return -ENOMEM; 1064 dev->hosttongene = dev->FWInterfaceBuffer; 1065 dev->ngenetohost = dev->FWInterfaceBuffer + 256; 1066 dev->EventBuffer = dev->FWInterfaceBuffer + 512; 1067 1068 dev->OverflowBuffer = pci_zalloc_consistent(dev->pci_dev, 1069 OVERFLOW_BUFFER_SIZE, 1070 &dev->PAOverflowBuffer); 1071 if (!dev->OverflowBuffer) 1072 return -ENOMEM; 1073 1074 for (i = STREAM_VIDEOIN1; i < MAX_STREAM; i++) { 1075 int type = dev->card_info->io_type[i]; 1076 1077 dev->channel[i].State = KSSTATE_STOP; 1078 1079 if (type & (NGENE_IO_TV | NGENE_IO_HDTV | NGENE_IO_AIN)) { 1080 status = create_ring_buffer(dev->pci_dev, 1081 &dev->channel[i].RingBuffer, 1082 RingBufferSizes[i]); 1083 if (status < 0) 1084 break; 1085 1086 if (type & (NGENE_IO_TV | NGENE_IO_AIN)) { 1087 status = AllocateRingBuffers(dev->pci_dev, 1088 dev-> 1089 PAOverflowBuffer, 1090 &dev->channel[i]. 1091 RingBuffer, 1092 Buffer1Sizes[i], 1093 Buffer2Sizes[i]); 1094 if (status < 0) 1095 break; 1096 } else if (type & NGENE_IO_HDTV) { 1097 status = AllocateRingBuffers(dev->pci_dev, 1098 dev-> 1099 PAOverflowBuffer, 1100 &dev->channel[i]. 1101 RingBuffer, 1102 MAX_HDTV_BUFFER_SIZE, 1103 0); 1104 if (status < 0) 1105 break; 1106 } 1107 } 1108 1109 if (type & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) { 1110 1111 status = create_ring_buffer(dev->pci_dev, 1112 &dev->channel[i]. 1113 TSRingBuffer, RING_SIZE_TS); 1114 if (status < 0) 1115 break; 1116 1117 status = AllocateRingBuffers(dev->pci_dev, 1118 dev->PAOverflowBuffer, 1119 &dev->channel[i]. 1120 TSRingBuffer, 1121 MAX_TS_BUFFER_SIZE, 0); 1122 if (status) 1123 break; 1124 } 1125 1126 if (type & NGENE_IO_TSOUT) { 1127 status = create_ring_buffer(dev->pci_dev, 1128 &dev->channel[i]. 1129 TSIdleBuffer, 1); 1130 if (status < 0) 1131 break; 1132 status = AllocateRingBuffers(dev->pci_dev, 1133 dev->PAOverflowBuffer, 1134 &dev->channel[i]. 1135 TSIdleBuffer, 1136 MAX_TS_BUFFER_SIZE, 0); 1137 if (status) 1138 break; 1139 FillTSIdleBuffer(&dev->channel[i].TSIdleBuffer, 1140 &dev->channel[i].TSRingBuffer); 1141 } 1142 } 1143 return status; 1144 } 1145 1146 static void ngene_release_buffers(struct ngene *dev) 1147 { 1148 if (dev->iomem) 1149 iounmap(dev->iomem); 1150 free_common_buffers(dev); 1151 vfree(dev->tsout_buf); 1152 vfree(dev->tsin_buf); 1153 vfree(dev->ain_buf); 1154 vfree(dev->vin_buf); 1155 vfree(dev); 1156 } 1157 1158 static int ngene_get_buffers(struct ngene *dev) 1159 { 1160 if (AllocCommonBuffers(dev)) 1161 return -ENOMEM; 1162 if (dev->card_info->io_type[4] & NGENE_IO_TSOUT) { 1163 dev->tsout_buf = vmalloc(TSOUT_BUF_SIZE); 1164 if (!dev->tsout_buf) 1165 return -ENOMEM; 1166 dvb_ringbuffer_init(&dev->tsout_rbuf, 1167 dev->tsout_buf, TSOUT_BUF_SIZE); 1168 } 1169 if (dev->card_info->io_type[2]&NGENE_IO_TSIN) { 1170 dev->tsin_buf = vmalloc(TSIN_BUF_SIZE); 1171 if (!dev->tsin_buf) 1172 return -ENOMEM; 1173 dvb_ringbuffer_init(&dev->tsin_rbuf, 1174 dev->tsin_buf, TSIN_BUF_SIZE); 1175 } 1176 if (dev->card_info->io_type[2] & NGENE_IO_AIN) { 1177 dev->ain_buf = vmalloc(AIN_BUF_SIZE); 1178 if (!dev->ain_buf) 1179 return -ENOMEM; 1180 dvb_ringbuffer_init(&dev->ain_rbuf, dev->ain_buf, AIN_BUF_SIZE); 1181 } 1182 if (dev->card_info->io_type[0] & NGENE_IO_HDTV) { 1183 dev->vin_buf = vmalloc(VIN_BUF_SIZE); 1184 if (!dev->vin_buf) 1185 return -ENOMEM; 1186 dvb_ringbuffer_init(&dev->vin_rbuf, dev->vin_buf, VIN_BUF_SIZE); 1187 } 1188 dev->iomem = ioremap(pci_resource_start(dev->pci_dev, 0), 1189 pci_resource_len(dev->pci_dev, 0)); 1190 if (!dev->iomem) 1191 return -ENOMEM; 1192 1193 return 0; 1194 } 1195 1196 static void ngene_init(struct ngene *dev) 1197 { 1198 int i; 1199 1200 tasklet_init(&dev->event_tasklet, event_tasklet, (unsigned long)dev); 1201 1202 memset_io(dev->iomem + 0xc000, 0x00, 0x220); 1203 memset_io(dev->iomem + 0xc400, 0x00, 0x100); 1204 1205 for (i = 0; i < MAX_STREAM; i++) { 1206 dev->channel[i].dev = dev; 1207 dev->channel[i].number = i; 1208 } 1209 1210 dev->fw_interface_version = 0; 1211 1212 ngwritel(0, NGENE_INT_ENABLE); 1213 1214 dev->icounts = ngreadl(NGENE_INT_COUNTS); 1215 1216 dev->device_version = ngreadl(DEV_VER) & 0x0f; 1217 printk(KERN_INFO DEVICE_NAME ": Device version %d\n", 1218 dev->device_version); 1219 } 1220 1221 static int ngene_load_firm(struct ngene *dev) 1222 { 1223 u32 size; 1224 const struct firmware *fw = NULL; 1225 u8 *ngene_fw; 1226 char *fw_name; 1227 int err, version; 1228 1229 version = dev->card_info->fw_version; 1230 1231 switch (version) { 1232 default: 1233 case 15: 1234 version = 15; 1235 size = 23466; 1236 fw_name = "ngene_15.fw"; 1237 dev->cmd_timeout_workaround = true; 1238 break; 1239 case 16: 1240 size = 23498; 1241 fw_name = "ngene_16.fw"; 1242 dev->cmd_timeout_workaround = true; 1243 break; 1244 case 17: 1245 size = 24446; 1246 fw_name = "ngene_17.fw"; 1247 dev->cmd_timeout_workaround = true; 1248 break; 1249 case 18: 1250 size = 0; 1251 fw_name = "ngene_18.fw"; 1252 break; 1253 } 1254 1255 if (request_firmware(&fw, fw_name, &dev->pci_dev->dev) < 0) { 1256 printk(KERN_ERR DEVICE_NAME 1257 ": Could not load firmware file %s.\n", fw_name); 1258 printk(KERN_INFO DEVICE_NAME 1259 ": Copy %s to your hotplug directory!\n", fw_name); 1260 return -1; 1261 } 1262 if (size == 0) 1263 size = fw->size; 1264 if (size != fw->size) { 1265 printk(KERN_ERR DEVICE_NAME 1266 ": Firmware %s has invalid size!", fw_name); 1267 err = -1; 1268 } else { 1269 printk(KERN_INFO DEVICE_NAME 1270 ": Loading firmware file %s.\n", fw_name); 1271 ngene_fw = (u8 *) fw->data; 1272 err = ngene_command_load_firmware(dev, ngene_fw, size); 1273 } 1274 1275 release_firmware(fw); 1276 1277 return err; 1278 } 1279 1280 static void ngene_stop(struct ngene *dev) 1281 { 1282 mutex_destroy(&dev->cmd_mutex); 1283 i2c_del_adapter(&(dev->channel[0].i2c_adapter)); 1284 i2c_del_adapter(&(dev->channel[1].i2c_adapter)); 1285 ngwritel(0, NGENE_INT_ENABLE); 1286 ngwritel(0, NGENE_COMMAND); 1287 ngwritel(0, NGENE_COMMAND_HI); 1288 ngwritel(0, NGENE_STATUS); 1289 ngwritel(0, NGENE_STATUS_HI); 1290 ngwritel(0, NGENE_EVENT); 1291 ngwritel(0, NGENE_EVENT_HI); 1292 free_irq(dev->pci_dev->irq, dev); 1293 #ifdef CONFIG_PCI_MSI 1294 if (dev->msi_enabled) 1295 pci_disable_msi(dev->pci_dev); 1296 #endif 1297 } 1298 1299 static int ngene_buffer_config(struct ngene *dev) 1300 { 1301 int stat; 1302 1303 if (dev->card_info->fw_version >= 17) { 1304 u8 tsin12_config[6] = { 0x60, 0x60, 0x00, 0x00, 0x00, 0x00 }; 1305 u8 tsin1234_config[6] = { 0x30, 0x30, 0x00, 0x30, 0x30, 0x00 }; 1306 u8 tsio1235_config[6] = { 0x30, 0x30, 0x00, 0x28, 0x00, 0x38 }; 1307 u8 *bconf = tsin12_config; 1308 1309 if (dev->card_info->io_type[2]&NGENE_IO_TSIN && 1310 dev->card_info->io_type[3]&NGENE_IO_TSIN) { 1311 bconf = tsin1234_config; 1312 if (dev->card_info->io_type[4]&NGENE_IO_TSOUT && 1313 dev->ci.en) 1314 bconf = tsio1235_config; 1315 } 1316 stat = ngene_command_config_free_buf(dev, bconf); 1317 } else { 1318 int bconf = BUFFER_CONFIG_4422; 1319 1320 if (dev->card_info->io_type[3] == NGENE_IO_TSIN) 1321 bconf = BUFFER_CONFIG_3333; 1322 stat = ngene_command_config_buf(dev, bconf); 1323 } 1324 return stat; 1325 } 1326 1327 1328 static int ngene_start(struct ngene *dev) 1329 { 1330 int stat; 1331 int i; 1332 1333 pci_set_master(dev->pci_dev); 1334 ngene_init(dev); 1335 1336 stat = request_irq(dev->pci_dev->irq, irq_handler, 1337 IRQF_SHARED, "nGene", 1338 (void *)dev); 1339 if (stat < 0) 1340 return stat; 1341 1342 init_waitqueue_head(&dev->cmd_wq); 1343 init_waitqueue_head(&dev->tx_wq); 1344 init_waitqueue_head(&dev->rx_wq); 1345 mutex_init(&dev->cmd_mutex); 1346 mutex_init(&dev->stream_mutex); 1347 sema_init(&dev->pll_mutex, 1); 1348 mutex_init(&dev->i2c_switch_mutex); 1349 spin_lock_init(&dev->cmd_lock); 1350 for (i = 0; i < MAX_STREAM; i++) 1351 spin_lock_init(&dev->channel[i].state_lock); 1352 ngwritel(1, TIMESTAMPS); 1353 1354 ngwritel(1, NGENE_INT_ENABLE); 1355 1356 stat = ngene_load_firm(dev); 1357 if (stat < 0) 1358 goto fail; 1359 1360 #ifdef CONFIG_PCI_MSI 1361 /* enable MSI if kernel and card support it */ 1362 if (pci_msi_enabled() && dev->card_info->msi_supported) { 1363 unsigned long flags; 1364 1365 ngwritel(0, NGENE_INT_ENABLE); 1366 free_irq(dev->pci_dev->irq, dev); 1367 stat = pci_enable_msi(dev->pci_dev); 1368 if (stat) { 1369 printk(KERN_INFO DEVICE_NAME 1370 ": MSI not available\n"); 1371 flags = IRQF_SHARED; 1372 } else { 1373 flags = 0; 1374 dev->msi_enabled = true; 1375 } 1376 stat = request_irq(dev->pci_dev->irq, irq_handler, 1377 flags, "nGene", dev); 1378 if (stat < 0) 1379 goto fail2; 1380 ngwritel(1, NGENE_INT_ENABLE); 1381 } 1382 #endif 1383 1384 stat = ngene_i2c_init(dev, 0); 1385 if (stat < 0) 1386 goto fail; 1387 1388 stat = ngene_i2c_init(dev, 1); 1389 if (stat < 0) 1390 goto fail; 1391 1392 return 0; 1393 1394 fail: 1395 ngwritel(0, NGENE_INT_ENABLE); 1396 free_irq(dev->pci_dev->irq, dev); 1397 #ifdef CONFIG_PCI_MSI 1398 fail2: 1399 if (dev->msi_enabled) 1400 pci_disable_msi(dev->pci_dev); 1401 #endif 1402 return stat; 1403 } 1404 1405 /****************************************************************************/ 1406 /****************************************************************************/ 1407 /****************************************************************************/ 1408 1409 static void release_channel(struct ngene_channel *chan) 1410 { 1411 struct dvb_demux *dvbdemux = &chan->demux; 1412 struct ngene *dev = chan->dev; 1413 1414 if (chan->running) 1415 set_transfer(chan, 0); 1416 1417 tasklet_kill(&chan->demux_tasklet); 1418 1419 if (chan->ci_dev) { 1420 dvb_unregister_device(chan->ci_dev); 1421 chan->ci_dev = NULL; 1422 } 1423 1424 if (chan->fe2) 1425 dvb_unregister_frontend(chan->fe2); 1426 1427 if (chan->fe) { 1428 dvb_unregister_frontend(chan->fe); 1429 dvb_frontend_detach(chan->fe); 1430 chan->fe = NULL; 1431 } 1432 1433 if (chan->has_demux) { 1434 dvb_net_release(&chan->dvbnet); 1435 dvbdemux->dmx.close(&dvbdemux->dmx); 1436 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, 1437 &chan->hw_frontend); 1438 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, 1439 &chan->mem_frontend); 1440 dvb_dmxdev_release(&chan->dmxdev); 1441 dvb_dmx_release(&chan->demux); 1442 chan->has_demux = false; 1443 } 1444 1445 if (chan->has_adapter) { 1446 dvb_unregister_adapter(&dev->adapter[chan->number]); 1447 chan->has_adapter = false; 1448 } 1449 } 1450 1451 static int init_channel(struct ngene_channel *chan) 1452 { 1453 int ret = 0, nr = chan->number; 1454 struct dvb_adapter *adapter = NULL; 1455 struct dvb_demux *dvbdemux = &chan->demux; 1456 struct ngene *dev = chan->dev; 1457 struct ngene_info *ni = dev->card_info; 1458 int io = ni->io_type[nr]; 1459 1460 tasklet_init(&chan->demux_tasklet, demux_tasklet, (unsigned long)chan); 1461 chan->users = 0; 1462 chan->type = io; 1463 chan->mode = chan->type; /* for now only one mode */ 1464 1465 if (io & NGENE_IO_TSIN) { 1466 chan->fe = NULL; 1467 if (ni->demod_attach[nr]) { 1468 ret = ni->demod_attach[nr](chan); 1469 if (ret < 0) 1470 goto err; 1471 } 1472 if (chan->fe && ni->tuner_attach[nr]) { 1473 ret = ni->tuner_attach[nr](chan); 1474 if (ret < 0) 1475 goto err; 1476 } 1477 } 1478 1479 if (!dev->ci.en && (io & NGENE_IO_TSOUT)) 1480 return 0; 1481 1482 if (io & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) { 1483 if (nr >= STREAM_AUDIOIN1) 1484 chan->DataFormatFlags = DF_SWAP32; 1485 1486 if (nr == 0 || !one_adapter || dev->first_adapter == NULL) { 1487 adapter = &dev->adapter[nr]; 1488 ret = dvb_register_adapter(adapter, "nGene", 1489 THIS_MODULE, 1490 &chan->dev->pci_dev->dev, 1491 adapter_nr); 1492 if (ret < 0) 1493 goto err; 1494 if (dev->first_adapter == NULL) 1495 dev->first_adapter = adapter; 1496 chan->has_adapter = true; 1497 } else 1498 adapter = dev->first_adapter; 1499 } 1500 1501 if (dev->ci.en && (io & NGENE_IO_TSOUT)) { 1502 dvb_ca_en50221_init(adapter, dev->ci.en, 0, 1); 1503 set_transfer(chan, 1); 1504 chan->dev->channel[2].DataFormatFlags = DF_SWAP32; 1505 set_transfer(&chan->dev->channel[2], 1); 1506 dvb_register_device(adapter, &chan->ci_dev, 1507 &ngene_dvbdev_ci, (void *) chan, 1508 DVB_DEVICE_SEC, 0); 1509 if (!chan->ci_dev) 1510 goto err; 1511 } 1512 1513 if (chan->fe) { 1514 if (dvb_register_frontend(adapter, chan->fe) < 0) 1515 goto err; 1516 chan->has_demux = true; 1517 } 1518 if (chan->fe2) { 1519 if (dvb_register_frontend(adapter, chan->fe2) < 0) 1520 goto err; 1521 if (chan->fe) { 1522 chan->fe2->tuner_priv = chan->fe->tuner_priv; 1523 memcpy(&chan->fe2->ops.tuner_ops, 1524 &chan->fe->ops.tuner_ops, 1525 sizeof(struct dvb_tuner_ops)); 1526 } 1527 } 1528 1529 if (chan->has_demux) { 1530 ret = my_dvb_dmx_ts_card_init(dvbdemux, "SW demux", 1531 ngene_start_feed, 1532 ngene_stop_feed, chan); 1533 ret = my_dvb_dmxdev_ts_card_init(&chan->dmxdev, &chan->demux, 1534 &chan->hw_frontend, 1535 &chan->mem_frontend, adapter); 1536 ret = dvb_net_init(adapter, &chan->dvbnet, &chan->demux.dmx); 1537 } 1538 1539 return ret; 1540 1541 err: 1542 if (chan->fe) { 1543 dvb_frontend_detach(chan->fe); 1544 chan->fe = NULL; 1545 } 1546 release_channel(chan); 1547 return 0; 1548 } 1549 1550 static int init_channels(struct ngene *dev) 1551 { 1552 int i, j; 1553 1554 for (i = 0; i < MAX_STREAM; i++) { 1555 dev->channel[i].number = i; 1556 if (init_channel(&dev->channel[i]) < 0) { 1557 for (j = i - 1; j >= 0; j--) 1558 release_channel(&dev->channel[j]); 1559 return -1; 1560 } 1561 } 1562 return 0; 1563 } 1564 1565 static struct cxd2099_cfg cxd_cfg = { 1566 .bitrate = 62000, 1567 .adr = 0x40, 1568 .polarity = 0, 1569 .clock_mode = 0, 1570 }; 1571 1572 static void cxd_attach(struct ngene *dev) 1573 { 1574 struct ngene_ci *ci = &dev->ci; 1575 1576 ci->en = cxd2099_attach(&cxd_cfg, dev, &dev->channel[0].i2c_adapter); 1577 ci->dev = dev; 1578 return; 1579 } 1580 1581 static void cxd_detach(struct ngene *dev) 1582 { 1583 struct ngene_ci *ci = &dev->ci; 1584 1585 dvb_ca_en50221_release(ci->en); 1586 kfree(ci->en); 1587 ci->en = NULL; 1588 } 1589 1590 /***********************************/ 1591 /* workaround for shutdown failure */ 1592 /***********************************/ 1593 1594 static void ngene_unlink(struct ngene *dev) 1595 { 1596 struct ngene_command com; 1597 1598 com.cmd.hdr.Opcode = CMD_MEM_WRITE; 1599 com.cmd.hdr.Length = 3; 1600 com.cmd.MemoryWrite.address = 0x910c; 1601 com.cmd.MemoryWrite.data = 0xff; 1602 com.in_len = 3; 1603 com.out_len = 1; 1604 1605 mutex_lock(&dev->cmd_mutex); 1606 ngwritel(0, NGENE_INT_ENABLE); 1607 ngene_command_mutex(dev, &com); 1608 mutex_unlock(&dev->cmd_mutex); 1609 } 1610 1611 void ngene_shutdown(struct pci_dev *pdev) 1612 { 1613 struct ngene *dev = pci_get_drvdata(pdev); 1614 1615 if (!dev || !shutdown_workaround) 1616 return; 1617 1618 printk(KERN_INFO DEVICE_NAME ": shutdown workaround...\n"); 1619 ngene_unlink(dev); 1620 pci_disable_device(pdev); 1621 } 1622 1623 /****************************************************************************/ 1624 /* device probe/remove calls ************************************************/ 1625 /****************************************************************************/ 1626 1627 void ngene_remove(struct pci_dev *pdev) 1628 { 1629 struct ngene *dev = pci_get_drvdata(pdev); 1630 int i; 1631 1632 tasklet_kill(&dev->event_tasklet); 1633 for (i = MAX_STREAM - 1; i >= 0; i--) 1634 release_channel(&dev->channel[i]); 1635 if (dev->ci.en) 1636 cxd_detach(dev); 1637 ngene_stop(dev); 1638 ngene_release_buffers(dev); 1639 pci_disable_device(pdev); 1640 } 1641 1642 int ngene_probe(struct pci_dev *pci_dev, const struct pci_device_id *id) 1643 { 1644 struct ngene *dev; 1645 int stat = 0; 1646 1647 if (pci_enable_device(pci_dev) < 0) 1648 return -ENODEV; 1649 1650 dev = vzalloc(sizeof(struct ngene)); 1651 if (dev == NULL) { 1652 stat = -ENOMEM; 1653 goto fail0; 1654 } 1655 1656 dev->pci_dev = pci_dev; 1657 dev->card_info = (struct ngene_info *)id->driver_data; 1658 printk(KERN_INFO DEVICE_NAME ": Found %s\n", dev->card_info->name); 1659 1660 pci_set_drvdata(pci_dev, dev); 1661 1662 /* Alloc buffers and start nGene */ 1663 stat = ngene_get_buffers(dev); 1664 if (stat < 0) 1665 goto fail1; 1666 stat = ngene_start(dev); 1667 if (stat < 0) 1668 goto fail1; 1669 1670 cxd_attach(dev); 1671 1672 stat = ngene_buffer_config(dev); 1673 if (stat < 0) 1674 goto fail1; 1675 1676 1677 dev->i2c_current_bus = -1; 1678 1679 /* Register DVB adapters and devices for both channels */ 1680 stat = init_channels(dev); 1681 if (stat < 0) 1682 goto fail2; 1683 1684 return 0; 1685 1686 fail2: 1687 ngene_stop(dev); 1688 fail1: 1689 ngene_release_buffers(dev); 1690 fail0: 1691 pci_disable_device(pci_dev); 1692 return stat; 1693 } 1694