1 /* 2 * ngene.c: nGene PCIe bridge driver 3 * 4 * Copyright (C) 2005-2007 Micronas 5 * 6 * Copyright (C) 2008-2009 Ralph Metzler <rjkm@metzlerbros.de> 7 * Modifications for new nGene firmware, 8 * support for EEPROM-copying, 9 * support for new dual DVB-S2 card prototype 10 * 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License 14 * version 2 only, as published by the Free Software Foundation. 15 * 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * 23 * You should have received a copy of the GNU General Public License 24 * along with this program; if not, write to the Free Software 25 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 26 * 02110-1301, USA 27 * Or, point your browser to http://www.gnu.org/copyleft/gpl.html 28 */ 29 30 #include <linux/module.h> 31 #include <linux/init.h> 32 #include <linux/delay.h> 33 #include <linux/poll.h> 34 #include <linux/io.h> 35 #include <asm/div64.h> 36 #include <linux/pci.h> 37 #include <linux/timer.h> 38 #include <linux/byteorder/generic.h> 39 #include <linux/firmware.h> 40 #include <linux/vmalloc.h> 41 42 #include "ngene.h" 43 44 static int one_adapter; 45 module_param(one_adapter, int, 0444); 46 MODULE_PARM_DESC(one_adapter, "Use only one adapter."); 47 48 static int shutdown_workaround; 49 module_param(shutdown_workaround, int, 0644); 50 MODULE_PARM_DESC(shutdown_workaround, "Activate workaround for shutdown problem with some chipsets."); 51 52 static int debug; 53 module_param(debug, int, 0444); 54 MODULE_PARM_DESC(debug, "Print debugging information."); 55 56 DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr); 57 58 #define dprintk if (debug) printk 59 60 #define ngwriteb(dat, adr) writeb((dat), (char *)(dev->iomem + (adr))) 61 #define ngwritel(dat, adr) writel((dat), (char *)(dev->iomem + (adr))) 62 #define ngwriteb(dat, adr) writeb((dat), (char *)(dev->iomem + (adr))) 63 #define ngreadl(adr) readl(dev->iomem + (adr)) 64 #define ngreadb(adr) readb(dev->iomem + (adr)) 65 #define ngcpyto(adr, src, count) memcpy_toio((char *) \ 66 (dev->iomem + (adr)), (src), (count)) 67 #define ngcpyfrom(dst, adr, count) memcpy_fromio((dst), (char *) \ 68 (dev->iomem + (adr)), (count)) 69 70 /****************************************************************************/ 71 /* nGene interrupt handler **************************************************/ 72 /****************************************************************************/ 73 74 static void event_tasklet(unsigned long data) 75 { 76 struct ngene *dev = (struct ngene *)data; 77 78 while (dev->EventQueueReadIndex != dev->EventQueueWriteIndex) { 79 struct EVENT_BUFFER Event = 80 dev->EventQueue[dev->EventQueueReadIndex]; 81 dev->EventQueueReadIndex = 82 (dev->EventQueueReadIndex + 1) & (EVENT_QUEUE_SIZE - 1); 83 84 if ((Event.UARTStatus & 0x01) && (dev->TxEventNotify)) 85 dev->TxEventNotify(dev, Event.TimeStamp); 86 if ((Event.UARTStatus & 0x02) && (dev->RxEventNotify)) 87 dev->RxEventNotify(dev, Event.TimeStamp, 88 Event.RXCharacter); 89 } 90 } 91 92 static void demux_tasklet(unsigned long data) 93 { 94 struct ngene_channel *chan = (struct ngene_channel *)data; 95 struct SBufferHeader *Cur = chan->nextBuffer; 96 97 spin_lock_irq(&chan->state_lock); 98 99 while (Cur->ngeneBuffer.SR.Flags & 0x80) { 100 if (chan->mode & NGENE_IO_TSOUT) { 101 u32 Flags = chan->DataFormatFlags; 102 if (Cur->ngeneBuffer.SR.Flags & 0x20) 103 Flags |= BEF_OVERFLOW; 104 if (chan->pBufferExchange) { 105 if (!chan->pBufferExchange(chan, 106 Cur->Buffer1, 107 chan->Capture1Length, 108 Cur->ngeneBuffer.SR. 109 Clock, Flags)) { 110 /* 111 We didn't get data 112 Clear in service flag to make sure we 113 get called on next interrupt again. 114 leave fill/empty (0x80) flag alone 115 to avoid hardware running out of 116 buffers during startup, we hold only 117 in run state ( the source may be late 118 delivering data ) 119 */ 120 121 if (chan->HWState == HWSTATE_RUN) { 122 Cur->ngeneBuffer.SR.Flags &= 123 ~0x40; 124 break; 125 /* Stop processing stream */ 126 } 127 } else { 128 /* We got a valid buffer, 129 so switch to run state */ 130 chan->HWState = HWSTATE_RUN; 131 } 132 } else { 133 printk(KERN_ERR DEVICE_NAME ": OOPS\n"); 134 if (chan->HWState == HWSTATE_RUN) { 135 Cur->ngeneBuffer.SR.Flags &= ~0x40; 136 break; /* Stop processing stream */ 137 } 138 } 139 if (chan->AudioDTOUpdated) { 140 printk(KERN_INFO DEVICE_NAME 141 ": Update AudioDTO = %d\n", 142 chan->AudioDTOValue); 143 Cur->ngeneBuffer.SR.DTOUpdate = 144 chan->AudioDTOValue; 145 chan->AudioDTOUpdated = 0; 146 } 147 } else { 148 if (chan->HWState == HWSTATE_RUN) { 149 u32 Flags = chan->DataFormatFlags; 150 IBufferExchange *exch1 = chan->pBufferExchange; 151 IBufferExchange *exch2 = chan->pBufferExchange2; 152 if (Cur->ngeneBuffer.SR.Flags & 0x01) 153 Flags |= BEF_EVEN_FIELD; 154 if (Cur->ngeneBuffer.SR.Flags & 0x20) 155 Flags |= BEF_OVERFLOW; 156 spin_unlock_irq(&chan->state_lock); 157 if (exch1) 158 exch1(chan, Cur->Buffer1, 159 chan->Capture1Length, 160 Cur->ngeneBuffer.SR.Clock, 161 Flags); 162 if (exch2) 163 exch2(chan, Cur->Buffer2, 164 chan->Capture2Length, 165 Cur->ngeneBuffer.SR.Clock, 166 Flags); 167 spin_lock_irq(&chan->state_lock); 168 } else if (chan->HWState != HWSTATE_STOP) 169 chan->HWState = HWSTATE_RUN; 170 } 171 Cur->ngeneBuffer.SR.Flags = 0x00; 172 Cur = Cur->Next; 173 } 174 chan->nextBuffer = Cur; 175 176 spin_unlock_irq(&chan->state_lock); 177 } 178 179 static irqreturn_t irq_handler(int irq, void *dev_id) 180 { 181 struct ngene *dev = (struct ngene *)dev_id; 182 u32 icounts = 0; 183 irqreturn_t rc = IRQ_NONE; 184 u32 i = MAX_STREAM; 185 u8 *tmpCmdDoneByte; 186 187 if (dev->BootFirmware) { 188 icounts = ngreadl(NGENE_INT_COUNTS); 189 if (icounts != dev->icounts) { 190 ngwritel(0, FORCE_NMI); 191 dev->cmd_done = 1; 192 wake_up(&dev->cmd_wq); 193 dev->icounts = icounts; 194 rc = IRQ_HANDLED; 195 } 196 return rc; 197 } 198 199 ngwritel(0, FORCE_NMI); 200 201 spin_lock(&dev->cmd_lock); 202 tmpCmdDoneByte = dev->CmdDoneByte; 203 if (tmpCmdDoneByte && 204 (*tmpCmdDoneByte || 205 (dev->ngenetohost[0] == 1 && dev->ngenetohost[1] != 0))) { 206 dev->CmdDoneByte = NULL; 207 dev->cmd_done = 1; 208 wake_up(&dev->cmd_wq); 209 rc = IRQ_HANDLED; 210 } 211 spin_unlock(&dev->cmd_lock); 212 213 if (dev->EventBuffer->EventStatus & 0x80) { 214 u8 nextWriteIndex = 215 (dev->EventQueueWriteIndex + 1) & 216 (EVENT_QUEUE_SIZE - 1); 217 if (nextWriteIndex != dev->EventQueueReadIndex) { 218 dev->EventQueue[dev->EventQueueWriteIndex] = 219 *(dev->EventBuffer); 220 dev->EventQueueWriteIndex = nextWriteIndex; 221 } else { 222 printk(KERN_ERR DEVICE_NAME ": event overflow\n"); 223 dev->EventQueueOverflowCount += 1; 224 dev->EventQueueOverflowFlag = 1; 225 } 226 dev->EventBuffer->EventStatus &= ~0x80; 227 tasklet_schedule(&dev->event_tasklet); 228 rc = IRQ_HANDLED; 229 } 230 231 while (i > 0) { 232 i--; 233 spin_lock(&dev->channel[i].state_lock); 234 /* if (dev->channel[i].State>=KSSTATE_RUN) { */ 235 if (dev->channel[i].nextBuffer) { 236 if ((dev->channel[i].nextBuffer-> 237 ngeneBuffer.SR.Flags & 0xC0) == 0x80) { 238 dev->channel[i].nextBuffer-> 239 ngeneBuffer.SR.Flags |= 0x40; 240 tasklet_schedule( 241 &dev->channel[i].demux_tasklet); 242 rc = IRQ_HANDLED; 243 } 244 } 245 spin_unlock(&dev->channel[i].state_lock); 246 } 247 248 /* Request might have been processed by a previous call. */ 249 return IRQ_HANDLED; 250 } 251 252 /****************************************************************************/ 253 /* nGene command interface **************************************************/ 254 /****************************************************************************/ 255 256 static void dump_command_io(struct ngene *dev) 257 { 258 u8 buf[8], *b; 259 260 ngcpyfrom(buf, HOST_TO_NGENE, 8); 261 printk(KERN_ERR "host_to_ngene (%04x): %*ph\n", HOST_TO_NGENE, 8, buf); 262 263 ngcpyfrom(buf, NGENE_TO_HOST, 8); 264 printk(KERN_ERR "ngene_to_host (%04x): %*ph\n", NGENE_TO_HOST, 8, buf); 265 266 b = dev->hosttongene; 267 printk(KERN_ERR "dev->hosttongene (%p): %*ph\n", b, 8, b); 268 269 b = dev->ngenetohost; 270 printk(KERN_ERR "dev->ngenetohost (%p): %*ph\n", b, 8, b); 271 } 272 273 static int ngene_command_mutex(struct ngene *dev, struct ngene_command *com) 274 { 275 int ret; 276 u8 *tmpCmdDoneByte; 277 278 dev->cmd_done = 0; 279 280 if (com->cmd.hdr.Opcode == CMD_FWLOAD_PREPARE) { 281 dev->BootFirmware = 1; 282 dev->icounts = ngreadl(NGENE_INT_COUNTS); 283 ngwritel(0, NGENE_COMMAND); 284 ngwritel(0, NGENE_COMMAND_HI); 285 ngwritel(0, NGENE_STATUS); 286 ngwritel(0, NGENE_STATUS_HI); 287 ngwritel(0, NGENE_EVENT); 288 ngwritel(0, NGENE_EVENT_HI); 289 } else if (com->cmd.hdr.Opcode == CMD_FWLOAD_FINISH) { 290 u64 fwio = dev->PAFWInterfaceBuffer; 291 292 ngwritel(fwio & 0xffffffff, NGENE_COMMAND); 293 ngwritel(fwio >> 32, NGENE_COMMAND_HI); 294 ngwritel((fwio + 256) & 0xffffffff, NGENE_STATUS); 295 ngwritel((fwio + 256) >> 32, NGENE_STATUS_HI); 296 ngwritel((fwio + 512) & 0xffffffff, NGENE_EVENT); 297 ngwritel((fwio + 512) >> 32, NGENE_EVENT_HI); 298 } 299 300 memcpy(dev->FWInterfaceBuffer, com->cmd.raw8, com->in_len + 2); 301 302 if (dev->BootFirmware) 303 ngcpyto(HOST_TO_NGENE, com->cmd.raw8, com->in_len + 2); 304 305 spin_lock_irq(&dev->cmd_lock); 306 tmpCmdDoneByte = dev->ngenetohost + com->out_len; 307 if (!com->out_len) 308 tmpCmdDoneByte++; 309 *tmpCmdDoneByte = 0; 310 dev->ngenetohost[0] = 0; 311 dev->ngenetohost[1] = 0; 312 dev->CmdDoneByte = tmpCmdDoneByte; 313 spin_unlock_irq(&dev->cmd_lock); 314 315 /* Notify 8051. */ 316 ngwritel(1, FORCE_INT); 317 318 ret = wait_event_timeout(dev->cmd_wq, dev->cmd_done == 1, 2 * HZ); 319 if (!ret) { 320 /*ngwritel(0, FORCE_NMI);*/ 321 322 printk(KERN_ERR DEVICE_NAME 323 ": Command timeout cmd=%02x prev=%02x\n", 324 com->cmd.hdr.Opcode, dev->prev_cmd); 325 dump_command_io(dev); 326 return -1; 327 } 328 if (com->cmd.hdr.Opcode == CMD_FWLOAD_FINISH) 329 dev->BootFirmware = 0; 330 331 dev->prev_cmd = com->cmd.hdr.Opcode; 332 333 if (!com->out_len) 334 return 0; 335 336 memcpy(com->cmd.raw8, dev->ngenetohost, com->out_len); 337 338 return 0; 339 } 340 341 int ngene_command(struct ngene *dev, struct ngene_command *com) 342 { 343 int result; 344 345 down(&dev->cmd_mutex); 346 result = ngene_command_mutex(dev, com); 347 up(&dev->cmd_mutex); 348 return result; 349 } 350 351 352 static int ngene_command_load_firmware(struct ngene *dev, 353 u8 *ngene_fw, u32 size) 354 { 355 #define FIRSTCHUNK (1024) 356 u32 cleft; 357 struct ngene_command com; 358 359 com.cmd.hdr.Opcode = CMD_FWLOAD_PREPARE; 360 com.cmd.hdr.Length = 0; 361 com.in_len = 0; 362 com.out_len = 0; 363 364 ngene_command(dev, &com); 365 366 cleft = (size + 3) & ~3; 367 if (cleft > FIRSTCHUNK) { 368 ngcpyto(PROGRAM_SRAM + FIRSTCHUNK, ngene_fw + FIRSTCHUNK, 369 cleft - FIRSTCHUNK); 370 cleft = FIRSTCHUNK; 371 } 372 ngcpyto(DATA_FIFO_AREA, ngene_fw, cleft); 373 374 memset(&com, 0, sizeof(struct ngene_command)); 375 com.cmd.hdr.Opcode = CMD_FWLOAD_FINISH; 376 com.cmd.hdr.Length = 4; 377 com.cmd.FWLoadFinish.Address = DATA_FIFO_AREA; 378 com.cmd.FWLoadFinish.Length = (unsigned short)cleft; 379 com.in_len = 4; 380 com.out_len = 0; 381 382 return ngene_command(dev, &com); 383 } 384 385 386 static int ngene_command_config_buf(struct ngene *dev, u8 config) 387 { 388 struct ngene_command com; 389 390 com.cmd.hdr.Opcode = CMD_CONFIGURE_BUFFER; 391 com.cmd.hdr.Length = 1; 392 com.cmd.ConfigureBuffers.config = config; 393 com.in_len = 1; 394 com.out_len = 0; 395 396 if (ngene_command(dev, &com) < 0) 397 return -EIO; 398 return 0; 399 } 400 401 static int ngene_command_config_free_buf(struct ngene *dev, u8 *config) 402 { 403 struct ngene_command com; 404 405 com.cmd.hdr.Opcode = CMD_CONFIGURE_FREE_BUFFER; 406 com.cmd.hdr.Length = 6; 407 memcpy(&com.cmd.ConfigureBuffers.config, config, 6); 408 com.in_len = 6; 409 com.out_len = 0; 410 411 if (ngene_command(dev, &com) < 0) 412 return -EIO; 413 414 return 0; 415 } 416 417 int ngene_command_gpio_set(struct ngene *dev, u8 select, u8 level) 418 { 419 struct ngene_command com; 420 421 com.cmd.hdr.Opcode = CMD_SET_GPIO_PIN; 422 com.cmd.hdr.Length = 1; 423 com.cmd.SetGpioPin.select = select | (level << 7); 424 com.in_len = 1; 425 com.out_len = 0; 426 427 return ngene_command(dev, &com); 428 } 429 430 431 /* 432 02000640 is sample on rising edge. 433 02000740 is sample on falling edge. 434 02000040 is ignore "valid" signal 435 436 0: FD_CTL1 Bit 7,6 must be 0,1 437 7 disable(fw controlled) 438 6 0-AUX,1-TS 439 5 0-par,1-ser 440 4 0-lsb/1-msb 441 3,2 reserved 442 1,0 0-no sync, 1-use ext. start, 2-use 0x47, 3-both 443 1: FD_CTL2 has 3-valid must be hi, 2-use valid, 1-edge 444 2: FD_STA is read-only. 0-sync 445 3: FD_INSYNC is number of 47s to trigger "in sync". 446 4: FD_OUTSYNC is number of 47s to trigger "out of sync". 447 5: FD_MAXBYTE1 is low-order of bytes per packet. 448 6: FD_MAXBYTE2 is high-order of bytes per packet. 449 7: Top byte is unused. 450 */ 451 452 /****************************************************************************/ 453 454 static u8 TSFeatureDecoderSetup[8 * 5] = { 455 0x42, 0x00, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, 456 0x40, 0x06, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* DRXH */ 457 0x71, 0x07, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* DRXHser */ 458 0x72, 0x00, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* S2ser */ 459 0x40, 0x07, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* LGDT3303 */ 460 }; 461 462 /* Set NGENE I2S Config to 16 bit packed */ 463 static u8 I2SConfiguration[] = { 464 0x00, 0x10, 0x00, 0x00, 465 0x80, 0x10, 0x00, 0x00, 466 }; 467 468 static u8 SPDIFConfiguration[10] = { 469 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 470 }; 471 472 /* Set NGENE I2S Config to transport stream compatible mode */ 473 474 static u8 TS_I2SConfiguration[4] = { 0x3E, 0x18, 0x00, 0x00 }; 475 476 static u8 TS_I2SOutConfiguration[4] = { 0x80, 0x04, 0x00, 0x00 }; 477 478 static u8 ITUDecoderSetup[4][16] = { 479 {0x1c, 0x13, 0x01, 0x68, 0x3d, 0x90, 0x14, 0x20, /* SDTV */ 480 0x00, 0x00, 0x01, 0xb0, 0x9c, 0x00, 0x00, 0x00}, 481 {0x9c, 0x03, 0x23, 0xC0, 0x60, 0x0E, 0x13, 0x00, 482 0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00}, 483 {0x9f, 0x00, 0x23, 0xC0, 0x60, 0x0F, 0x13, 0x00, /* HDTV 1080i50 */ 484 0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00}, 485 {0x9c, 0x01, 0x23, 0xC0, 0x60, 0x0E, 0x13, 0x00, /* HDTV 1080i60 */ 486 0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00}, 487 }; 488 489 /* 490 * 50 48 60 gleich 491 * 27p50 9f 00 22 80 42 69 18 ... 492 * 27p60 93 00 22 80 82 69 1c ... 493 */ 494 495 /* Maxbyte to 1144 (for raw data) */ 496 static u8 ITUFeatureDecoderSetup[8] = { 497 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x04, 0x00 498 }; 499 500 void FillTSBuffer(void *Buffer, int Length, u32 Flags) 501 { 502 u32 *ptr = Buffer; 503 504 memset(Buffer, TS_FILLER, Length); 505 while (Length > 0) { 506 if (Flags & DF_SWAP32) 507 *ptr = 0x471FFF10; 508 else 509 *ptr = 0x10FF1F47; 510 ptr += (188 / 4); 511 Length -= 188; 512 } 513 } 514 515 516 static void flush_buffers(struct ngene_channel *chan) 517 { 518 u8 val; 519 520 do { 521 msleep(1); 522 spin_lock_irq(&chan->state_lock); 523 val = chan->nextBuffer->ngeneBuffer.SR.Flags & 0x80; 524 spin_unlock_irq(&chan->state_lock); 525 } while (val); 526 } 527 528 static void clear_buffers(struct ngene_channel *chan) 529 { 530 struct SBufferHeader *Cur = chan->nextBuffer; 531 532 do { 533 memset(&Cur->ngeneBuffer.SR, 0, sizeof(Cur->ngeneBuffer.SR)); 534 if (chan->mode & NGENE_IO_TSOUT) 535 FillTSBuffer(Cur->Buffer1, 536 chan->Capture1Length, 537 chan->DataFormatFlags); 538 Cur = Cur->Next; 539 } while (Cur != chan->nextBuffer); 540 541 if (chan->mode & NGENE_IO_TSOUT) { 542 chan->nextBuffer->ngeneBuffer.SR.DTOUpdate = 543 chan->AudioDTOValue; 544 chan->AudioDTOUpdated = 0; 545 546 Cur = chan->TSIdleBuffer.Head; 547 548 do { 549 memset(&Cur->ngeneBuffer.SR, 0, 550 sizeof(Cur->ngeneBuffer.SR)); 551 FillTSBuffer(Cur->Buffer1, 552 chan->Capture1Length, 553 chan->DataFormatFlags); 554 Cur = Cur->Next; 555 } while (Cur != chan->TSIdleBuffer.Head); 556 } 557 } 558 559 static int ngene_command_stream_control(struct ngene *dev, u8 stream, 560 u8 control, u8 mode, u8 flags) 561 { 562 struct ngene_channel *chan = &dev->channel[stream]; 563 struct ngene_command com; 564 u16 BsUVI = ((stream & 1) ? 0x9400 : 0x9300); 565 u16 BsSDI = ((stream & 1) ? 0x9600 : 0x9500); 566 u16 BsSPI = ((stream & 1) ? 0x9800 : 0x9700); 567 u16 BsSDO = 0x9B00; 568 569 down(&dev->stream_mutex); 570 memset(&com, 0, sizeof(com)); 571 com.cmd.hdr.Opcode = CMD_CONTROL; 572 com.cmd.hdr.Length = sizeof(struct FW_STREAM_CONTROL) - 2; 573 com.cmd.StreamControl.Stream = stream | (control ? 8 : 0); 574 if (chan->mode & NGENE_IO_TSOUT) 575 com.cmd.StreamControl.Stream |= 0x07; 576 com.cmd.StreamControl.Control = control | 577 (flags & SFLAG_ORDER_LUMA_CHROMA); 578 com.cmd.StreamControl.Mode = mode; 579 com.in_len = sizeof(struct FW_STREAM_CONTROL); 580 com.out_len = 0; 581 582 dprintk(KERN_INFO DEVICE_NAME 583 ": Stream=%02x, Control=%02x, Mode=%02x\n", 584 com.cmd.StreamControl.Stream, com.cmd.StreamControl.Control, 585 com.cmd.StreamControl.Mode); 586 587 chan->Mode = mode; 588 589 if (!(control & 0x80)) { 590 spin_lock_irq(&chan->state_lock); 591 if (chan->State == KSSTATE_RUN) { 592 chan->State = KSSTATE_ACQUIRE; 593 chan->HWState = HWSTATE_STOP; 594 spin_unlock_irq(&chan->state_lock); 595 if (ngene_command(dev, &com) < 0) { 596 up(&dev->stream_mutex); 597 return -1; 598 } 599 /* clear_buffers(chan); */ 600 flush_buffers(chan); 601 up(&dev->stream_mutex); 602 return 0; 603 } 604 spin_unlock_irq(&chan->state_lock); 605 up(&dev->stream_mutex); 606 return 0; 607 } 608 609 if (mode & SMODE_AUDIO_CAPTURE) { 610 com.cmd.StreamControl.CaptureBlockCount = 611 chan->Capture1Length / AUDIO_BLOCK_SIZE; 612 com.cmd.StreamControl.Buffer_Address = chan->RingBuffer.PAHead; 613 } else if (mode & SMODE_TRANSPORT_STREAM) { 614 com.cmd.StreamControl.CaptureBlockCount = 615 chan->Capture1Length / TS_BLOCK_SIZE; 616 com.cmd.StreamControl.MaxLinesPerField = 617 chan->Capture1Length / TS_BLOCK_SIZE; 618 com.cmd.StreamControl.Buffer_Address = 619 chan->TSRingBuffer.PAHead; 620 if (chan->mode & NGENE_IO_TSOUT) { 621 com.cmd.StreamControl.BytesPerVBILine = 622 chan->Capture1Length / TS_BLOCK_SIZE; 623 com.cmd.StreamControl.Stream |= 0x07; 624 } 625 } else { 626 com.cmd.StreamControl.BytesPerVideoLine = chan->nBytesPerLine; 627 com.cmd.StreamControl.MaxLinesPerField = chan->nLines; 628 com.cmd.StreamControl.MinLinesPerField = 100; 629 com.cmd.StreamControl.Buffer_Address = chan->RingBuffer.PAHead; 630 631 if (mode & SMODE_VBI_CAPTURE) { 632 com.cmd.StreamControl.MaxVBILinesPerField = 633 chan->nVBILines; 634 com.cmd.StreamControl.MinVBILinesPerField = 0; 635 com.cmd.StreamControl.BytesPerVBILine = 636 chan->nBytesPerVBILine; 637 } 638 if (flags & SFLAG_COLORBAR) 639 com.cmd.StreamControl.Stream |= 0x04; 640 } 641 642 spin_lock_irq(&chan->state_lock); 643 if (mode & SMODE_AUDIO_CAPTURE) { 644 chan->nextBuffer = chan->RingBuffer.Head; 645 if (mode & SMODE_AUDIO_SPDIF) { 646 com.cmd.StreamControl.SetupDataLen = 647 sizeof(SPDIFConfiguration); 648 com.cmd.StreamControl.SetupDataAddr = BsSPI; 649 memcpy(com.cmd.StreamControl.SetupData, 650 SPDIFConfiguration, sizeof(SPDIFConfiguration)); 651 } else { 652 com.cmd.StreamControl.SetupDataLen = 4; 653 com.cmd.StreamControl.SetupDataAddr = BsSDI; 654 memcpy(com.cmd.StreamControl.SetupData, 655 I2SConfiguration + 656 4 * dev->card_info->i2s[stream], 4); 657 } 658 } else if (mode & SMODE_TRANSPORT_STREAM) { 659 chan->nextBuffer = chan->TSRingBuffer.Head; 660 if (stream >= STREAM_AUDIOIN1) { 661 if (chan->mode & NGENE_IO_TSOUT) { 662 com.cmd.StreamControl.SetupDataLen = 663 sizeof(TS_I2SOutConfiguration); 664 com.cmd.StreamControl.SetupDataAddr = BsSDO; 665 memcpy(com.cmd.StreamControl.SetupData, 666 TS_I2SOutConfiguration, 667 sizeof(TS_I2SOutConfiguration)); 668 } else { 669 com.cmd.StreamControl.SetupDataLen = 670 sizeof(TS_I2SConfiguration); 671 com.cmd.StreamControl.SetupDataAddr = BsSDI; 672 memcpy(com.cmd.StreamControl.SetupData, 673 TS_I2SConfiguration, 674 sizeof(TS_I2SConfiguration)); 675 } 676 } else { 677 com.cmd.StreamControl.SetupDataLen = 8; 678 com.cmd.StreamControl.SetupDataAddr = BsUVI + 0x10; 679 memcpy(com.cmd.StreamControl.SetupData, 680 TSFeatureDecoderSetup + 681 8 * dev->card_info->tsf[stream], 8); 682 } 683 } else { 684 chan->nextBuffer = chan->RingBuffer.Head; 685 com.cmd.StreamControl.SetupDataLen = 686 16 + sizeof(ITUFeatureDecoderSetup); 687 com.cmd.StreamControl.SetupDataAddr = BsUVI; 688 memcpy(com.cmd.StreamControl.SetupData, 689 ITUDecoderSetup[chan->itumode], 16); 690 memcpy(com.cmd.StreamControl.SetupData + 16, 691 ITUFeatureDecoderSetup, sizeof(ITUFeatureDecoderSetup)); 692 } 693 clear_buffers(chan); 694 chan->State = KSSTATE_RUN; 695 if (mode & SMODE_TRANSPORT_STREAM) 696 chan->HWState = HWSTATE_RUN; 697 else 698 chan->HWState = HWSTATE_STARTUP; 699 spin_unlock_irq(&chan->state_lock); 700 701 if (ngene_command(dev, &com) < 0) { 702 up(&dev->stream_mutex); 703 return -1; 704 } 705 up(&dev->stream_mutex); 706 return 0; 707 } 708 709 void set_transfer(struct ngene_channel *chan, int state) 710 { 711 u8 control = 0, mode = 0, flags = 0; 712 struct ngene *dev = chan->dev; 713 int ret; 714 715 /* 716 printk(KERN_INFO DEVICE_NAME ": st %d\n", state); 717 msleep(100); 718 */ 719 720 if (state) { 721 if (chan->running) { 722 printk(KERN_INFO DEVICE_NAME ": already running\n"); 723 return; 724 } 725 } else { 726 if (!chan->running) { 727 printk(KERN_INFO DEVICE_NAME ": already stopped\n"); 728 return; 729 } 730 } 731 732 if (dev->card_info->switch_ctrl) 733 dev->card_info->switch_ctrl(chan, 1, state ^ 1); 734 735 if (state) { 736 spin_lock_irq(&chan->state_lock); 737 738 /* printk(KERN_INFO DEVICE_NAME ": lock=%08x\n", 739 ngreadl(0x9310)); */ 740 dvb_ringbuffer_flush(&dev->tsout_rbuf); 741 control = 0x80; 742 if (chan->mode & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) { 743 chan->Capture1Length = 512 * 188; 744 mode = SMODE_TRANSPORT_STREAM; 745 } 746 if (chan->mode & NGENE_IO_TSOUT) { 747 chan->pBufferExchange = tsout_exchange; 748 /* 0x66666666 = 50MHz *2^33 /250MHz */ 749 chan->AudioDTOValue = 0x80000000; 750 chan->AudioDTOUpdated = 1; 751 } 752 if (chan->mode & NGENE_IO_TSIN) 753 chan->pBufferExchange = tsin_exchange; 754 spin_unlock_irq(&chan->state_lock); 755 } 756 /* else printk(KERN_INFO DEVICE_NAME ": lock=%08x\n", 757 ngreadl(0x9310)); */ 758 759 ret = ngene_command_stream_control(dev, chan->number, 760 control, mode, flags); 761 if (!ret) 762 chan->running = state; 763 else 764 printk(KERN_ERR DEVICE_NAME ": set_transfer %d failed\n", 765 state); 766 if (!state) { 767 spin_lock_irq(&chan->state_lock); 768 chan->pBufferExchange = NULL; 769 dvb_ringbuffer_flush(&dev->tsout_rbuf); 770 spin_unlock_irq(&chan->state_lock); 771 } 772 } 773 774 775 /****************************************************************************/ 776 /* nGene hardware init and release functions ********************************/ 777 /****************************************************************************/ 778 779 static void free_ringbuffer(struct ngene *dev, struct SRingBufferDescriptor *rb) 780 { 781 struct SBufferHeader *Cur = rb->Head; 782 u32 j; 783 784 if (!Cur) 785 return; 786 787 for (j = 0; j < rb->NumBuffers; j++, Cur = Cur->Next) { 788 if (Cur->Buffer1) 789 pci_free_consistent(dev->pci_dev, 790 rb->Buffer1Length, 791 Cur->Buffer1, 792 Cur->scList1->Address); 793 794 if (Cur->Buffer2) 795 pci_free_consistent(dev->pci_dev, 796 rb->Buffer2Length, 797 Cur->Buffer2, 798 Cur->scList2->Address); 799 } 800 801 if (rb->SCListMem) 802 pci_free_consistent(dev->pci_dev, rb->SCListMemSize, 803 rb->SCListMem, rb->PASCListMem); 804 805 pci_free_consistent(dev->pci_dev, rb->MemSize, rb->Head, rb->PAHead); 806 } 807 808 static void free_idlebuffer(struct ngene *dev, 809 struct SRingBufferDescriptor *rb, 810 struct SRingBufferDescriptor *tb) 811 { 812 int j; 813 struct SBufferHeader *Cur = tb->Head; 814 815 if (!rb->Head) 816 return; 817 free_ringbuffer(dev, rb); 818 for (j = 0; j < tb->NumBuffers; j++, Cur = Cur->Next) { 819 Cur->Buffer2 = NULL; 820 Cur->scList2 = NULL; 821 Cur->ngeneBuffer.Address_of_first_entry_2 = 0; 822 Cur->ngeneBuffer.Number_of_entries_2 = 0; 823 } 824 } 825 826 static void free_common_buffers(struct ngene *dev) 827 { 828 u32 i; 829 struct ngene_channel *chan; 830 831 for (i = STREAM_VIDEOIN1; i < MAX_STREAM; i++) { 832 chan = &dev->channel[i]; 833 free_idlebuffer(dev, &chan->TSIdleBuffer, &chan->TSRingBuffer); 834 free_ringbuffer(dev, &chan->RingBuffer); 835 free_ringbuffer(dev, &chan->TSRingBuffer); 836 } 837 838 if (dev->OverflowBuffer) 839 pci_free_consistent(dev->pci_dev, 840 OVERFLOW_BUFFER_SIZE, 841 dev->OverflowBuffer, dev->PAOverflowBuffer); 842 843 if (dev->FWInterfaceBuffer) 844 pci_free_consistent(dev->pci_dev, 845 4096, 846 dev->FWInterfaceBuffer, 847 dev->PAFWInterfaceBuffer); 848 } 849 850 /****************************************************************************/ 851 /* Ring buffer handling *****************************************************/ 852 /****************************************************************************/ 853 854 static int create_ring_buffer(struct pci_dev *pci_dev, 855 struct SRingBufferDescriptor *descr, u32 NumBuffers) 856 { 857 dma_addr_t tmp; 858 struct SBufferHeader *Head; 859 u32 i; 860 u32 MemSize = SIZEOF_SBufferHeader * NumBuffers; 861 u64 PARingBufferHead; 862 u64 PARingBufferCur; 863 u64 PARingBufferNext; 864 struct SBufferHeader *Cur, *Next; 865 866 descr->Head = NULL; 867 descr->MemSize = 0; 868 descr->PAHead = 0; 869 descr->NumBuffers = 0; 870 871 if (MemSize < 4096) 872 MemSize = 4096; 873 874 Head = pci_alloc_consistent(pci_dev, MemSize, &tmp); 875 PARingBufferHead = tmp; 876 877 if (!Head) 878 return -ENOMEM; 879 880 memset(Head, 0, MemSize); 881 882 PARingBufferCur = PARingBufferHead; 883 Cur = Head; 884 885 for (i = 0; i < NumBuffers - 1; i++) { 886 Next = (struct SBufferHeader *) 887 (((u8 *) Cur) + SIZEOF_SBufferHeader); 888 PARingBufferNext = PARingBufferCur + SIZEOF_SBufferHeader; 889 Cur->Next = Next; 890 Cur->ngeneBuffer.Next = PARingBufferNext; 891 Cur = Next; 892 PARingBufferCur = PARingBufferNext; 893 } 894 /* Last Buffer points back to first one */ 895 Cur->Next = Head; 896 Cur->ngeneBuffer.Next = PARingBufferHead; 897 898 descr->Head = Head; 899 descr->MemSize = MemSize; 900 descr->PAHead = PARingBufferHead; 901 descr->NumBuffers = NumBuffers; 902 903 return 0; 904 } 905 906 static int AllocateRingBuffers(struct pci_dev *pci_dev, 907 dma_addr_t of, 908 struct SRingBufferDescriptor *pRingBuffer, 909 u32 Buffer1Length, u32 Buffer2Length) 910 { 911 dma_addr_t tmp; 912 u32 i, j; 913 int status = 0; 914 u32 SCListMemSize = pRingBuffer->NumBuffers 915 * ((Buffer2Length != 0) ? (NUM_SCATTER_GATHER_ENTRIES * 2) : 916 NUM_SCATTER_GATHER_ENTRIES) 917 * sizeof(struct HW_SCATTER_GATHER_ELEMENT); 918 919 u64 PASCListMem; 920 struct HW_SCATTER_GATHER_ELEMENT *SCListEntry; 921 u64 PASCListEntry; 922 struct SBufferHeader *Cur; 923 void *SCListMem; 924 925 if (SCListMemSize < 4096) 926 SCListMemSize = 4096; 927 928 SCListMem = pci_alloc_consistent(pci_dev, SCListMemSize, &tmp); 929 930 PASCListMem = tmp; 931 if (SCListMem == NULL) 932 return -ENOMEM; 933 934 memset(SCListMem, 0, SCListMemSize); 935 936 pRingBuffer->SCListMem = SCListMem; 937 pRingBuffer->PASCListMem = PASCListMem; 938 pRingBuffer->SCListMemSize = SCListMemSize; 939 pRingBuffer->Buffer1Length = Buffer1Length; 940 pRingBuffer->Buffer2Length = Buffer2Length; 941 942 SCListEntry = SCListMem; 943 PASCListEntry = PASCListMem; 944 Cur = pRingBuffer->Head; 945 946 for (i = 0; i < pRingBuffer->NumBuffers; i += 1, Cur = Cur->Next) { 947 u64 PABuffer; 948 949 void *Buffer = pci_alloc_consistent(pci_dev, Buffer1Length, 950 &tmp); 951 PABuffer = tmp; 952 953 if (Buffer == NULL) 954 return -ENOMEM; 955 956 Cur->Buffer1 = Buffer; 957 958 SCListEntry->Address = PABuffer; 959 SCListEntry->Length = Buffer1Length; 960 961 Cur->scList1 = SCListEntry; 962 Cur->ngeneBuffer.Address_of_first_entry_1 = PASCListEntry; 963 Cur->ngeneBuffer.Number_of_entries_1 = 964 NUM_SCATTER_GATHER_ENTRIES; 965 966 SCListEntry += 1; 967 PASCListEntry += sizeof(struct HW_SCATTER_GATHER_ELEMENT); 968 969 #if NUM_SCATTER_GATHER_ENTRIES > 1 970 for (j = 0; j < NUM_SCATTER_GATHER_ENTRIES - 1; j += 1) { 971 SCListEntry->Address = of; 972 SCListEntry->Length = OVERFLOW_BUFFER_SIZE; 973 SCListEntry += 1; 974 PASCListEntry += 975 sizeof(struct HW_SCATTER_GATHER_ELEMENT); 976 } 977 #endif 978 979 if (!Buffer2Length) 980 continue; 981 982 Buffer = pci_alloc_consistent(pci_dev, Buffer2Length, &tmp); 983 PABuffer = tmp; 984 985 if (Buffer == NULL) 986 return -ENOMEM; 987 988 Cur->Buffer2 = Buffer; 989 990 SCListEntry->Address = PABuffer; 991 SCListEntry->Length = Buffer2Length; 992 993 Cur->scList2 = SCListEntry; 994 Cur->ngeneBuffer.Address_of_first_entry_2 = PASCListEntry; 995 Cur->ngeneBuffer.Number_of_entries_2 = 996 NUM_SCATTER_GATHER_ENTRIES; 997 998 SCListEntry += 1; 999 PASCListEntry += sizeof(struct HW_SCATTER_GATHER_ELEMENT); 1000 1001 #if NUM_SCATTER_GATHER_ENTRIES > 1 1002 for (j = 0; j < NUM_SCATTER_GATHER_ENTRIES - 1; j++) { 1003 SCListEntry->Address = of; 1004 SCListEntry->Length = OVERFLOW_BUFFER_SIZE; 1005 SCListEntry += 1; 1006 PASCListEntry += 1007 sizeof(struct HW_SCATTER_GATHER_ELEMENT); 1008 } 1009 #endif 1010 1011 } 1012 1013 return status; 1014 } 1015 1016 static int FillTSIdleBuffer(struct SRingBufferDescriptor *pIdleBuffer, 1017 struct SRingBufferDescriptor *pRingBuffer) 1018 { 1019 int status = 0; 1020 1021 /* Copy pointer to scatter gather list in TSRingbuffer 1022 structure for buffer 2 1023 Load number of buffer 1024 */ 1025 u32 n = pRingBuffer->NumBuffers; 1026 1027 /* Point to first buffer entry */ 1028 struct SBufferHeader *Cur = pRingBuffer->Head; 1029 int i; 1030 /* Loop thru all buffer and set Buffer 2 pointers to TSIdlebuffer */ 1031 for (i = 0; i < n; i++) { 1032 Cur->Buffer2 = pIdleBuffer->Head->Buffer1; 1033 Cur->scList2 = pIdleBuffer->Head->scList1; 1034 Cur->ngeneBuffer.Address_of_first_entry_2 = 1035 pIdleBuffer->Head->ngeneBuffer. 1036 Address_of_first_entry_1; 1037 Cur->ngeneBuffer.Number_of_entries_2 = 1038 pIdleBuffer->Head->ngeneBuffer.Number_of_entries_1; 1039 Cur = Cur->Next; 1040 } 1041 return status; 1042 } 1043 1044 static u32 RingBufferSizes[MAX_STREAM] = { 1045 RING_SIZE_VIDEO, 1046 RING_SIZE_VIDEO, 1047 RING_SIZE_AUDIO, 1048 RING_SIZE_AUDIO, 1049 RING_SIZE_AUDIO, 1050 }; 1051 1052 static u32 Buffer1Sizes[MAX_STREAM] = { 1053 MAX_VIDEO_BUFFER_SIZE, 1054 MAX_VIDEO_BUFFER_SIZE, 1055 MAX_AUDIO_BUFFER_SIZE, 1056 MAX_AUDIO_BUFFER_SIZE, 1057 MAX_AUDIO_BUFFER_SIZE 1058 }; 1059 1060 static u32 Buffer2Sizes[MAX_STREAM] = { 1061 MAX_VBI_BUFFER_SIZE, 1062 MAX_VBI_BUFFER_SIZE, 1063 0, 1064 0, 1065 0 1066 }; 1067 1068 1069 static int AllocCommonBuffers(struct ngene *dev) 1070 { 1071 int status = 0, i; 1072 1073 dev->FWInterfaceBuffer = pci_alloc_consistent(dev->pci_dev, 4096, 1074 &dev->PAFWInterfaceBuffer); 1075 if (!dev->FWInterfaceBuffer) 1076 return -ENOMEM; 1077 dev->hosttongene = dev->FWInterfaceBuffer; 1078 dev->ngenetohost = dev->FWInterfaceBuffer + 256; 1079 dev->EventBuffer = dev->FWInterfaceBuffer + 512; 1080 1081 dev->OverflowBuffer = pci_alloc_consistent(dev->pci_dev, 1082 OVERFLOW_BUFFER_SIZE, 1083 &dev->PAOverflowBuffer); 1084 if (!dev->OverflowBuffer) 1085 return -ENOMEM; 1086 memset(dev->OverflowBuffer, 0, OVERFLOW_BUFFER_SIZE); 1087 1088 for (i = STREAM_VIDEOIN1; i < MAX_STREAM; i++) { 1089 int type = dev->card_info->io_type[i]; 1090 1091 dev->channel[i].State = KSSTATE_STOP; 1092 1093 if (type & (NGENE_IO_TV | NGENE_IO_HDTV | NGENE_IO_AIN)) { 1094 status = create_ring_buffer(dev->pci_dev, 1095 &dev->channel[i].RingBuffer, 1096 RingBufferSizes[i]); 1097 if (status < 0) 1098 break; 1099 1100 if (type & (NGENE_IO_TV | NGENE_IO_AIN)) { 1101 status = AllocateRingBuffers(dev->pci_dev, 1102 dev-> 1103 PAOverflowBuffer, 1104 &dev->channel[i]. 1105 RingBuffer, 1106 Buffer1Sizes[i], 1107 Buffer2Sizes[i]); 1108 if (status < 0) 1109 break; 1110 } else if (type & NGENE_IO_HDTV) { 1111 status = AllocateRingBuffers(dev->pci_dev, 1112 dev-> 1113 PAOverflowBuffer, 1114 &dev->channel[i]. 1115 RingBuffer, 1116 MAX_HDTV_BUFFER_SIZE, 1117 0); 1118 if (status < 0) 1119 break; 1120 } 1121 } 1122 1123 if (type & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) { 1124 1125 status = create_ring_buffer(dev->pci_dev, 1126 &dev->channel[i]. 1127 TSRingBuffer, RING_SIZE_TS); 1128 if (status < 0) 1129 break; 1130 1131 status = AllocateRingBuffers(dev->pci_dev, 1132 dev->PAOverflowBuffer, 1133 &dev->channel[i]. 1134 TSRingBuffer, 1135 MAX_TS_BUFFER_SIZE, 0); 1136 if (status) 1137 break; 1138 } 1139 1140 if (type & NGENE_IO_TSOUT) { 1141 status = create_ring_buffer(dev->pci_dev, 1142 &dev->channel[i]. 1143 TSIdleBuffer, 1); 1144 if (status < 0) 1145 break; 1146 status = AllocateRingBuffers(dev->pci_dev, 1147 dev->PAOverflowBuffer, 1148 &dev->channel[i]. 1149 TSIdleBuffer, 1150 MAX_TS_BUFFER_SIZE, 0); 1151 if (status) 1152 break; 1153 FillTSIdleBuffer(&dev->channel[i].TSIdleBuffer, 1154 &dev->channel[i].TSRingBuffer); 1155 } 1156 } 1157 return status; 1158 } 1159 1160 static void ngene_release_buffers(struct ngene *dev) 1161 { 1162 if (dev->iomem) 1163 iounmap(dev->iomem); 1164 free_common_buffers(dev); 1165 vfree(dev->tsout_buf); 1166 vfree(dev->tsin_buf); 1167 vfree(dev->ain_buf); 1168 vfree(dev->vin_buf); 1169 vfree(dev); 1170 } 1171 1172 static int ngene_get_buffers(struct ngene *dev) 1173 { 1174 if (AllocCommonBuffers(dev)) 1175 return -ENOMEM; 1176 if (dev->card_info->io_type[4] & NGENE_IO_TSOUT) { 1177 dev->tsout_buf = vmalloc(TSOUT_BUF_SIZE); 1178 if (!dev->tsout_buf) 1179 return -ENOMEM; 1180 dvb_ringbuffer_init(&dev->tsout_rbuf, 1181 dev->tsout_buf, TSOUT_BUF_SIZE); 1182 } 1183 if (dev->card_info->io_type[2]&NGENE_IO_TSIN) { 1184 dev->tsin_buf = vmalloc(TSIN_BUF_SIZE); 1185 if (!dev->tsin_buf) 1186 return -ENOMEM; 1187 dvb_ringbuffer_init(&dev->tsin_rbuf, 1188 dev->tsin_buf, TSIN_BUF_SIZE); 1189 } 1190 if (dev->card_info->io_type[2] & NGENE_IO_AIN) { 1191 dev->ain_buf = vmalloc(AIN_BUF_SIZE); 1192 if (!dev->ain_buf) 1193 return -ENOMEM; 1194 dvb_ringbuffer_init(&dev->ain_rbuf, dev->ain_buf, AIN_BUF_SIZE); 1195 } 1196 if (dev->card_info->io_type[0] & NGENE_IO_HDTV) { 1197 dev->vin_buf = vmalloc(VIN_BUF_SIZE); 1198 if (!dev->vin_buf) 1199 return -ENOMEM; 1200 dvb_ringbuffer_init(&dev->vin_rbuf, dev->vin_buf, VIN_BUF_SIZE); 1201 } 1202 dev->iomem = ioremap(pci_resource_start(dev->pci_dev, 0), 1203 pci_resource_len(dev->pci_dev, 0)); 1204 if (!dev->iomem) 1205 return -ENOMEM; 1206 1207 return 0; 1208 } 1209 1210 static void ngene_init(struct ngene *dev) 1211 { 1212 int i; 1213 1214 tasklet_init(&dev->event_tasklet, event_tasklet, (unsigned long)dev); 1215 1216 memset_io(dev->iomem + 0xc000, 0x00, 0x220); 1217 memset_io(dev->iomem + 0xc400, 0x00, 0x100); 1218 1219 for (i = 0; i < MAX_STREAM; i++) { 1220 dev->channel[i].dev = dev; 1221 dev->channel[i].number = i; 1222 } 1223 1224 dev->fw_interface_version = 0; 1225 1226 ngwritel(0, NGENE_INT_ENABLE); 1227 1228 dev->icounts = ngreadl(NGENE_INT_COUNTS); 1229 1230 dev->device_version = ngreadl(DEV_VER) & 0x0f; 1231 printk(KERN_INFO DEVICE_NAME ": Device version %d\n", 1232 dev->device_version); 1233 } 1234 1235 static int ngene_load_firm(struct ngene *dev) 1236 { 1237 u32 size; 1238 const struct firmware *fw = NULL; 1239 u8 *ngene_fw; 1240 char *fw_name; 1241 int err, version; 1242 1243 version = dev->card_info->fw_version; 1244 1245 switch (version) { 1246 default: 1247 case 15: 1248 version = 15; 1249 size = 23466; 1250 fw_name = "ngene_15.fw"; 1251 dev->cmd_timeout_workaround = true; 1252 break; 1253 case 16: 1254 size = 23498; 1255 fw_name = "ngene_16.fw"; 1256 dev->cmd_timeout_workaround = true; 1257 break; 1258 case 17: 1259 size = 24446; 1260 fw_name = "ngene_17.fw"; 1261 dev->cmd_timeout_workaround = true; 1262 break; 1263 case 18: 1264 size = 0; 1265 fw_name = "ngene_18.fw"; 1266 break; 1267 } 1268 1269 if (request_firmware(&fw, fw_name, &dev->pci_dev->dev) < 0) { 1270 printk(KERN_ERR DEVICE_NAME 1271 ": Could not load firmware file %s.\n", fw_name); 1272 printk(KERN_INFO DEVICE_NAME 1273 ": Copy %s to your hotplug directory!\n", fw_name); 1274 return -1; 1275 } 1276 if (size == 0) 1277 size = fw->size; 1278 if (size != fw->size) { 1279 printk(KERN_ERR DEVICE_NAME 1280 ": Firmware %s has invalid size!", fw_name); 1281 err = -1; 1282 } else { 1283 printk(KERN_INFO DEVICE_NAME 1284 ": Loading firmware file %s.\n", fw_name); 1285 ngene_fw = (u8 *) fw->data; 1286 err = ngene_command_load_firmware(dev, ngene_fw, size); 1287 } 1288 1289 release_firmware(fw); 1290 1291 return err; 1292 } 1293 1294 static void ngene_stop(struct ngene *dev) 1295 { 1296 down(&dev->cmd_mutex); 1297 i2c_del_adapter(&(dev->channel[0].i2c_adapter)); 1298 i2c_del_adapter(&(dev->channel[1].i2c_adapter)); 1299 ngwritel(0, NGENE_INT_ENABLE); 1300 ngwritel(0, NGENE_COMMAND); 1301 ngwritel(0, NGENE_COMMAND_HI); 1302 ngwritel(0, NGENE_STATUS); 1303 ngwritel(0, NGENE_STATUS_HI); 1304 ngwritel(0, NGENE_EVENT); 1305 ngwritel(0, NGENE_EVENT_HI); 1306 free_irq(dev->pci_dev->irq, dev); 1307 #ifdef CONFIG_PCI_MSI 1308 if (dev->msi_enabled) 1309 pci_disable_msi(dev->pci_dev); 1310 #endif 1311 } 1312 1313 static int ngene_buffer_config(struct ngene *dev) 1314 { 1315 int stat; 1316 1317 if (dev->card_info->fw_version >= 17) { 1318 u8 tsin12_config[6] = { 0x60, 0x60, 0x00, 0x00, 0x00, 0x00 }; 1319 u8 tsin1234_config[6] = { 0x30, 0x30, 0x00, 0x30, 0x30, 0x00 }; 1320 u8 tsio1235_config[6] = { 0x30, 0x30, 0x00, 0x28, 0x00, 0x38 }; 1321 u8 *bconf = tsin12_config; 1322 1323 if (dev->card_info->io_type[2]&NGENE_IO_TSIN && 1324 dev->card_info->io_type[3]&NGENE_IO_TSIN) { 1325 bconf = tsin1234_config; 1326 if (dev->card_info->io_type[4]&NGENE_IO_TSOUT && 1327 dev->ci.en) 1328 bconf = tsio1235_config; 1329 } 1330 stat = ngene_command_config_free_buf(dev, bconf); 1331 } else { 1332 int bconf = BUFFER_CONFIG_4422; 1333 1334 if (dev->card_info->io_type[3] == NGENE_IO_TSIN) 1335 bconf = BUFFER_CONFIG_3333; 1336 stat = ngene_command_config_buf(dev, bconf); 1337 } 1338 return stat; 1339 } 1340 1341 1342 static int ngene_start(struct ngene *dev) 1343 { 1344 int stat; 1345 int i; 1346 1347 pci_set_master(dev->pci_dev); 1348 ngene_init(dev); 1349 1350 stat = request_irq(dev->pci_dev->irq, irq_handler, 1351 IRQF_SHARED, "nGene", 1352 (void *)dev); 1353 if (stat < 0) 1354 return stat; 1355 1356 init_waitqueue_head(&dev->cmd_wq); 1357 init_waitqueue_head(&dev->tx_wq); 1358 init_waitqueue_head(&dev->rx_wq); 1359 sema_init(&dev->cmd_mutex, 1); 1360 sema_init(&dev->stream_mutex, 1); 1361 sema_init(&dev->pll_mutex, 1); 1362 sema_init(&dev->i2c_switch_mutex, 1); 1363 spin_lock_init(&dev->cmd_lock); 1364 for (i = 0; i < MAX_STREAM; i++) 1365 spin_lock_init(&dev->channel[i].state_lock); 1366 ngwritel(1, TIMESTAMPS); 1367 1368 ngwritel(1, NGENE_INT_ENABLE); 1369 1370 stat = ngene_load_firm(dev); 1371 if (stat < 0) 1372 goto fail; 1373 1374 #ifdef CONFIG_PCI_MSI 1375 /* enable MSI if kernel and card support it */ 1376 if (pci_msi_enabled() && dev->card_info->msi_supported) { 1377 unsigned long flags; 1378 1379 ngwritel(0, NGENE_INT_ENABLE); 1380 free_irq(dev->pci_dev->irq, dev); 1381 stat = pci_enable_msi(dev->pci_dev); 1382 if (stat) { 1383 printk(KERN_INFO DEVICE_NAME 1384 ": MSI not available\n"); 1385 flags = IRQF_SHARED; 1386 } else { 1387 flags = 0; 1388 dev->msi_enabled = true; 1389 } 1390 stat = request_irq(dev->pci_dev->irq, irq_handler, 1391 flags, "nGene", dev); 1392 if (stat < 0) 1393 goto fail2; 1394 ngwritel(1, NGENE_INT_ENABLE); 1395 } 1396 #endif 1397 1398 stat = ngene_i2c_init(dev, 0); 1399 if (stat < 0) 1400 goto fail; 1401 1402 stat = ngene_i2c_init(dev, 1); 1403 if (stat < 0) 1404 goto fail; 1405 1406 return 0; 1407 1408 fail: 1409 ngwritel(0, NGENE_INT_ENABLE); 1410 free_irq(dev->pci_dev->irq, dev); 1411 #ifdef CONFIG_PCI_MSI 1412 fail2: 1413 if (dev->msi_enabled) 1414 pci_disable_msi(dev->pci_dev); 1415 #endif 1416 return stat; 1417 } 1418 1419 /****************************************************************************/ 1420 /****************************************************************************/ 1421 /****************************************************************************/ 1422 1423 static void release_channel(struct ngene_channel *chan) 1424 { 1425 struct dvb_demux *dvbdemux = &chan->demux; 1426 struct ngene *dev = chan->dev; 1427 1428 if (chan->running) 1429 set_transfer(chan, 0); 1430 1431 tasklet_kill(&chan->demux_tasklet); 1432 1433 if (chan->ci_dev) { 1434 dvb_unregister_device(chan->ci_dev); 1435 chan->ci_dev = NULL; 1436 } 1437 1438 if (chan->fe2) 1439 dvb_unregister_frontend(chan->fe2); 1440 1441 if (chan->fe) { 1442 dvb_unregister_frontend(chan->fe); 1443 dvb_frontend_detach(chan->fe); 1444 chan->fe = NULL; 1445 } 1446 1447 if (chan->has_demux) { 1448 dvb_net_release(&chan->dvbnet); 1449 dvbdemux->dmx.close(&dvbdemux->dmx); 1450 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, 1451 &chan->hw_frontend); 1452 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, 1453 &chan->mem_frontend); 1454 dvb_dmxdev_release(&chan->dmxdev); 1455 dvb_dmx_release(&chan->demux); 1456 chan->has_demux = false; 1457 } 1458 1459 if (chan->has_adapter) { 1460 dvb_unregister_adapter(&dev->adapter[chan->number]); 1461 chan->has_adapter = false; 1462 } 1463 } 1464 1465 static int init_channel(struct ngene_channel *chan) 1466 { 1467 int ret = 0, nr = chan->number; 1468 struct dvb_adapter *adapter = NULL; 1469 struct dvb_demux *dvbdemux = &chan->demux; 1470 struct ngene *dev = chan->dev; 1471 struct ngene_info *ni = dev->card_info; 1472 int io = ni->io_type[nr]; 1473 1474 tasklet_init(&chan->demux_tasklet, demux_tasklet, (unsigned long)chan); 1475 chan->users = 0; 1476 chan->type = io; 1477 chan->mode = chan->type; /* for now only one mode */ 1478 1479 if (io & NGENE_IO_TSIN) { 1480 chan->fe = NULL; 1481 if (ni->demod_attach[nr]) { 1482 ret = ni->demod_attach[nr](chan); 1483 if (ret < 0) 1484 goto err; 1485 } 1486 if (chan->fe && ni->tuner_attach[nr]) { 1487 ret = ni->tuner_attach[nr](chan); 1488 if (ret < 0) 1489 goto err; 1490 } 1491 } 1492 1493 if (!dev->ci.en && (io & NGENE_IO_TSOUT)) 1494 return 0; 1495 1496 if (io & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) { 1497 if (nr >= STREAM_AUDIOIN1) 1498 chan->DataFormatFlags = DF_SWAP32; 1499 1500 if (nr == 0 || !one_adapter || dev->first_adapter == NULL) { 1501 adapter = &dev->adapter[nr]; 1502 ret = dvb_register_adapter(adapter, "nGene", 1503 THIS_MODULE, 1504 &chan->dev->pci_dev->dev, 1505 adapter_nr); 1506 if (ret < 0) 1507 goto err; 1508 if (dev->first_adapter == NULL) 1509 dev->first_adapter = adapter; 1510 chan->has_adapter = true; 1511 } else 1512 adapter = dev->first_adapter; 1513 } 1514 1515 if (dev->ci.en && (io & NGENE_IO_TSOUT)) { 1516 dvb_ca_en50221_init(adapter, dev->ci.en, 0, 1); 1517 set_transfer(chan, 1); 1518 chan->dev->channel[2].DataFormatFlags = DF_SWAP32; 1519 set_transfer(&chan->dev->channel[2], 1); 1520 dvb_register_device(adapter, &chan->ci_dev, 1521 &ngene_dvbdev_ci, (void *) chan, 1522 DVB_DEVICE_SEC); 1523 if (!chan->ci_dev) 1524 goto err; 1525 } 1526 1527 if (chan->fe) { 1528 if (dvb_register_frontend(adapter, chan->fe) < 0) 1529 goto err; 1530 chan->has_demux = true; 1531 } 1532 if (chan->fe2) { 1533 if (dvb_register_frontend(adapter, chan->fe2) < 0) 1534 goto err; 1535 chan->fe2->tuner_priv = chan->fe->tuner_priv; 1536 memcpy(&chan->fe2->ops.tuner_ops, 1537 &chan->fe->ops.tuner_ops, 1538 sizeof(struct dvb_tuner_ops)); 1539 } 1540 1541 if (chan->has_demux) { 1542 ret = my_dvb_dmx_ts_card_init(dvbdemux, "SW demux", 1543 ngene_start_feed, 1544 ngene_stop_feed, chan); 1545 ret = my_dvb_dmxdev_ts_card_init(&chan->dmxdev, &chan->demux, 1546 &chan->hw_frontend, 1547 &chan->mem_frontend, adapter); 1548 ret = dvb_net_init(adapter, &chan->dvbnet, &chan->demux.dmx); 1549 } 1550 1551 return ret; 1552 1553 err: 1554 if (chan->fe) { 1555 dvb_frontend_detach(chan->fe); 1556 chan->fe = NULL; 1557 } 1558 release_channel(chan); 1559 return 0; 1560 } 1561 1562 static int init_channels(struct ngene *dev) 1563 { 1564 int i, j; 1565 1566 for (i = 0; i < MAX_STREAM; i++) { 1567 dev->channel[i].number = i; 1568 if (init_channel(&dev->channel[i]) < 0) { 1569 for (j = i - 1; j >= 0; j--) 1570 release_channel(&dev->channel[j]); 1571 return -1; 1572 } 1573 } 1574 return 0; 1575 } 1576 1577 static struct cxd2099_cfg cxd_cfg = { 1578 .bitrate = 62000, 1579 .adr = 0x40, 1580 .polarity = 0, 1581 .clock_mode = 0, 1582 }; 1583 1584 static void cxd_attach(struct ngene *dev) 1585 { 1586 struct ngene_ci *ci = &dev->ci; 1587 1588 ci->en = cxd2099_attach(&cxd_cfg, dev, &dev->channel[0].i2c_adapter); 1589 ci->dev = dev; 1590 return; 1591 } 1592 1593 static void cxd_detach(struct ngene *dev) 1594 { 1595 struct ngene_ci *ci = &dev->ci; 1596 1597 dvb_ca_en50221_release(ci->en); 1598 kfree(ci->en); 1599 ci->en = 0; 1600 } 1601 1602 /***********************************/ 1603 /* workaround for shutdown failure */ 1604 /***********************************/ 1605 1606 static void ngene_unlink(struct ngene *dev) 1607 { 1608 struct ngene_command com; 1609 1610 com.cmd.hdr.Opcode = CMD_MEM_WRITE; 1611 com.cmd.hdr.Length = 3; 1612 com.cmd.MemoryWrite.address = 0x910c; 1613 com.cmd.MemoryWrite.data = 0xff; 1614 com.in_len = 3; 1615 com.out_len = 1; 1616 1617 down(&dev->cmd_mutex); 1618 ngwritel(0, NGENE_INT_ENABLE); 1619 ngene_command_mutex(dev, &com); 1620 up(&dev->cmd_mutex); 1621 } 1622 1623 void ngene_shutdown(struct pci_dev *pdev) 1624 { 1625 struct ngene *dev = pci_get_drvdata(pdev); 1626 1627 if (!dev || !shutdown_workaround) 1628 return; 1629 1630 printk(KERN_INFO DEVICE_NAME ": shutdown workaround...\n"); 1631 ngene_unlink(dev); 1632 pci_disable_device(pdev); 1633 } 1634 1635 /****************************************************************************/ 1636 /* device probe/remove calls ************************************************/ 1637 /****************************************************************************/ 1638 1639 void ngene_remove(struct pci_dev *pdev) 1640 { 1641 struct ngene *dev = pci_get_drvdata(pdev); 1642 int i; 1643 1644 tasklet_kill(&dev->event_tasklet); 1645 for (i = MAX_STREAM - 1; i >= 0; i--) 1646 release_channel(&dev->channel[i]); 1647 if (dev->ci.en) 1648 cxd_detach(dev); 1649 ngene_stop(dev); 1650 ngene_release_buffers(dev); 1651 pci_disable_device(pdev); 1652 } 1653 1654 int ngene_probe(struct pci_dev *pci_dev, const struct pci_device_id *id) 1655 { 1656 struct ngene *dev; 1657 int stat = 0; 1658 1659 if (pci_enable_device(pci_dev) < 0) 1660 return -ENODEV; 1661 1662 dev = vzalloc(sizeof(struct ngene)); 1663 if (dev == NULL) { 1664 stat = -ENOMEM; 1665 goto fail0; 1666 } 1667 1668 dev->pci_dev = pci_dev; 1669 dev->card_info = (struct ngene_info *)id->driver_data; 1670 printk(KERN_INFO DEVICE_NAME ": Found %s\n", dev->card_info->name); 1671 1672 pci_set_drvdata(pci_dev, dev); 1673 1674 /* Alloc buffers and start nGene */ 1675 stat = ngene_get_buffers(dev); 1676 if (stat < 0) 1677 goto fail1; 1678 stat = ngene_start(dev); 1679 if (stat < 0) 1680 goto fail1; 1681 1682 cxd_attach(dev); 1683 1684 stat = ngene_buffer_config(dev); 1685 if (stat < 0) 1686 goto fail1; 1687 1688 1689 dev->i2c_current_bus = -1; 1690 1691 /* Register DVB adapters and devices for both channels */ 1692 stat = init_channels(dev); 1693 if (stat < 0) 1694 goto fail2; 1695 1696 return 0; 1697 1698 fail2: 1699 ngene_stop(dev); 1700 fail1: 1701 ngene_release_buffers(dev); 1702 fail0: 1703 pci_disable_device(pci_dev); 1704 return stat; 1705 } 1706