1 /* 2 * netup_unidvb_i2c.c 3 * 4 * Internal I2C bus driver for NetUP Universal Dual DVB-CI 5 * 6 * Copyright (C) 2014 NetUP Inc. 7 * Copyright (C) 2014 Sergey Kozlov <serjk@netup.ru> 8 * Copyright (C) 2014 Abylay Ospan <aospan@netup.ru> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 */ 20 21 #include <linux/module.h> 22 #include <linux/moduleparam.h> 23 #include <linux/init.h> 24 #include <linux/delay.h> 25 #include "netup_unidvb.h" 26 27 #define NETUP_I2C_BUS0_ADDR 0x4800 28 #define NETUP_I2C_BUS1_ADDR 0x4840 29 #define NETUP_I2C_TIMEOUT 1000 30 31 /* twi_ctrl0_stat reg bits */ 32 #define TWI_IRQEN_COMPL 0x1 33 #define TWI_IRQEN_ANACK 0x2 34 #define TWI_IRQEN_DNACK 0x4 35 #define TWI_IRQ_COMPL (TWI_IRQEN_COMPL << 8) 36 #define TWI_IRQ_ANACK (TWI_IRQEN_ANACK << 8) 37 #define TWI_IRQ_DNACK (TWI_IRQEN_DNACK << 8) 38 #define TWI_IRQ_TX 0x800 39 #define TWI_IRQ_RX 0x1000 40 #define TWI_IRQEN (TWI_IRQEN_COMPL | TWI_IRQEN_ANACK | TWI_IRQEN_DNACK) 41 /* twi_addr_ctrl1 reg bits*/ 42 #define TWI_TRANSFER 0x100 43 #define TWI_NOSTOP 0x200 44 #define TWI_SOFT_RESET 0x2000 45 /* twi_clkdiv reg value */ 46 #define TWI_CLKDIV 156 47 /* fifo_stat_ctrl reg bits */ 48 #define FIFO_IRQEN 0x8000 49 #define FIFO_RESET 0x4000 50 /* FIFO size */ 51 #define FIFO_SIZE 16 52 53 struct netup_i2c_fifo_regs { 54 union { 55 __u8 data8; 56 __le16 data16; 57 __le32 data32; 58 }; 59 __u8 padding[4]; 60 __le16 stat_ctrl; 61 } __packed __aligned(1); 62 63 struct netup_i2c_regs { 64 __le16 clkdiv; 65 __le16 twi_ctrl0_stat; 66 __le16 twi_addr_ctrl1; 67 __le16 length; 68 __u8 padding1[8]; 69 struct netup_i2c_fifo_regs tx_fifo; 70 __u8 padding2[6]; 71 struct netup_i2c_fifo_regs rx_fifo; 72 } __packed __aligned(1); 73 74 irqreturn_t netup_i2c_interrupt(struct netup_i2c *i2c) 75 { 76 u16 reg, tmp; 77 unsigned long flags; 78 irqreturn_t iret = IRQ_HANDLED; 79 80 spin_lock_irqsave(&i2c->lock, flags); 81 reg = readw(&i2c->regs->twi_ctrl0_stat); 82 writew(reg & ~TWI_IRQEN, &i2c->regs->twi_ctrl0_stat); 83 dev_dbg(i2c->adap.dev.parent, 84 "%s(): twi_ctrl0_state 0x%x\n", __func__, reg); 85 if ((reg & TWI_IRQEN_COMPL) != 0 && (reg & TWI_IRQ_COMPL)) { 86 dev_dbg(i2c->adap.dev.parent, 87 "%s(): TWI_IRQEN_COMPL\n", __func__); 88 i2c->state = STATE_DONE; 89 goto irq_ok; 90 } 91 if ((reg & TWI_IRQEN_ANACK) != 0 && (reg & TWI_IRQ_ANACK)) { 92 dev_dbg(i2c->adap.dev.parent, 93 "%s(): TWI_IRQEN_ANACK\n", __func__); 94 i2c->state = STATE_ERROR; 95 goto irq_ok; 96 } 97 if ((reg & TWI_IRQEN_DNACK) != 0 && (reg & TWI_IRQ_DNACK)) { 98 dev_dbg(i2c->adap.dev.parent, 99 "%s(): TWI_IRQEN_DNACK\n", __func__); 100 i2c->state = STATE_ERROR; 101 goto irq_ok; 102 } 103 if ((reg & TWI_IRQ_RX) != 0) { 104 tmp = readw(&i2c->regs->rx_fifo.stat_ctrl); 105 writew(tmp & ~FIFO_IRQEN, &i2c->regs->rx_fifo.stat_ctrl); 106 i2c->state = STATE_WANT_READ; 107 dev_dbg(i2c->adap.dev.parent, 108 "%s(): want read\n", __func__); 109 goto irq_ok; 110 } 111 if ((reg & TWI_IRQ_TX) != 0) { 112 tmp = readw(&i2c->regs->tx_fifo.stat_ctrl); 113 writew(tmp & ~FIFO_IRQEN, &i2c->regs->tx_fifo.stat_ctrl); 114 i2c->state = STATE_WANT_WRITE; 115 dev_dbg(i2c->adap.dev.parent, 116 "%s(): want write\n", __func__); 117 goto irq_ok; 118 } 119 dev_warn(&i2c->adap.dev, "%s(): not mine interrupt\n", __func__); 120 iret = IRQ_NONE; 121 irq_ok: 122 spin_unlock_irqrestore(&i2c->lock, flags); 123 if (iret == IRQ_HANDLED) 124 wake_up(&i2c->wq); 125 return iret; 126 } 127 128 static void netup_i2c_reset(struct netup_i2c *i2c) 129 { 130 dev_dbg(i2c->adap.dev.parent, "%s()\n", __func__); 131 i2c->state = STATE_DONE; 132 writew(TWI_SOFT_RESET, &i2c->regs->twi_addr_ctrl1); 133 writew(TWI_CLKDIV, &i2c->regs->clkdiv); 134 writew(FIFO_RESET, &i2c->regs->tx_fifo.stat_ctrl); 135 writew(FIFO_RESET, &i2c->regs->rx_fifo.stat_ctrl); 136 writew(0x800, &i2c->regs->tx_fifo.stat_ctrl); 137 writew(0x800, &i2c->regs->rx_fifo.stat_ctrl); 138 } 139 140 static void netup_i2c_fifo_tx(struct netup_i2c *i2c) 141 { 142 u8 data; 143 u32 fifo_space = FIFO_SIZE - 144 (readw(&i2c->regs->tx_fifo.stat_ctrl) & 0x3f); 145 u32 msg_length = i2c->msg->len - i2c->xmit_size; 146 147 msg_length = (msg_length < fifo_space ? msg_length : fifo_space); 148 while (msg_length--) { 149 data = i2c->msg->buf[i2c->xmit_size++]; 150 writeb(data, &i2c->regs->tx_fifo.data8); 151 dev_dbg(i2c->adap.dev.parent, 152 "%s(): write 0x%02x\n", __func__, data); 153 } 154 if (i2c->xmit_size < i2c->msg->len) { 155 dev_dbg(i2c->adap.dev.parent, 156 "%s(): TX IRQ enabled\n", __func__); 157 writew(readw(&i2c->regs->tx_fifo.stat_ctrl) | FIFO_IRQEN, 158 &i2c->regs->tx_fifo.stat_ctrl); 159 } 160 } 161 162 static void netup_i2c_fifo_rx(struct netup_i2c *i2c) 163 { 164 u8 data; 165 u32 fifo_size = readw(&i2c->regs->rx_fifo.stat_ctrl) & 0x3f; 166 167 dev_dbg(i2c->adap.dev.parent, 168 "%s(): RX fifo size %d\n", __func__, fifo_size); 169 while (fifo_size--) { 170 data = readb(&i2c->regs->rx_fifo.data8); 171 if ((i2c->msg->flags & I2C_M_RD) != 0 && 172 i2c->xmit_size < i2c->msg->len) { 173 i2c->msg->buf[i2c->xmit_size++] = data; 174 dev_dbg(i2c->adap.dev.parent, 175 "%s(): read 0x%02x\n", __func__, data); 176 } 177 } 178 if (i2c->xmit_size < i2c->msg->len) { 179 dev_dbg(i2c->adap.dev.parent, 180 "%s(): RX IRQ enabled\n", __func__); 181 writew(readw(&i2c->regs->rx_fifo.stat_ctrl) | FIFO_IRQEN, 182 &i2c->regs->rx_fifo.stat_ctrl); 183 } 184 } 185 186 static void netup_i2c_start_xfer(struct netup_i2c *i2c) 187 { 188 u16 rdflag = ((i2c->msg->flags & I2C_M_RD) ? 1 : 0); 189 u16 reg = readw(&i2c->regs->twi_ctrl0_stat); 190 191 writew(TWI_IRQEN | reg, &i2c->regs->twi_ctrl0_stat); 192 writew(i2c->msg->len, &i2c->regs->length); 193 writew(TWI_TRANSFER | (i2c->msg->addr << 1) | rdflag, 194 &i2c->regs->twi_addr_ctrl1); 195 dev_dbg(i2c->adap.dev.parent, 196 "%s(): length %d twi_addr_ctrl1 0x%x twi_ctrl0_stat 0x%x\n", 197 __func__, readw(&i2c->regs->length), 198 readw(&i2c->regs->twi_addr_ctrl1), 199 readw(&i2c->regs->twi_ctrl0_stat)); 200 i2c->state = STATE_WAIT; 201 i2c->xmit_size = 0; 202 if (!rdflag) 203 netup_i2c_fifo_tx(i2c); 204 else 205 writew(FIFO_IRQEN | readw(&i2c->regs->rx_fifo.stat_ctrl), 206 &i2c->regs->rx_fifo.stat_ctrl); 207 } 208 209 static int netup_i2c_xfer(struct i2c_adapter *adap, 210 struct i2c_msg *msgs, int num) 211 { 212 unsigned long flags; 213 int i, trans_done, res = num; 214 struct netup_i2c *i2c = i2c_get_adapdata(adap); 215 u16 reg; 216 217 if (num <= 0) { 218 dev_dbg(i2c->adap.dev.parent, 219 "%s(): num == %d\n", __func__, num); 220 return -EINVAL; 221 } 222 spin_lock_irqsave(&i2c->lock, flags); 223 if (i2c->state != STATE_DONE) { 224 dev_dbg(i2c->adap.dev.parent, 225 "%s(): i2c->state == %d, resetting I2C\n", 226 __func__, i2c->state); 227 netup_i2c_reset(i2c); 228 } 229 dev_dbg(i2c->adap.dev.parent, "%s() num %d\n", __func__, num); 230 for (i = 0; i < num; i++) { 231 i2c->msg = &msgs[i]; 232 netup_i2c_start_xfer(i2c); 233 trans_done = 0; 234 while (!trans_done) { 235 spin_unlock_irqrestore(&i2c->lock, flags); 236 if (wait_event_timeout(i2c->wq, 237 i2c->state != STATE_WAIT, 238 msecs_to_jiffies(NETUP_I2C_TIMEOUT))) { 239 spin_lock_irqsave(&i2c->lock, flags); 240 switch (i2c->state) { 241 case STATE_WANT_READ: 242 netup_i2c_fifo_rx(i2c); 243 break; 244 case STATE_WANT_WRITE: 245 netup_i2c_fifo_tx(i2c); 246 break; 247 case STATE_DONE: 248 if ((i2c->msg->flags & I2C_M_RD) != 0 && 249 i2c->xmit_size != i2c->msg->len) 250 netup_i2c_fifo_rx(i2c); 251 dev_dbg(i2c->adap.dev.parent, 252 "%s(): msg %d OK\n", 253 __func__, i); 254 trans_done = 1; 255 break; 256 case STATE_ERROR: 257 res = -EIO; 258 dev_dbg(i2c->adap.dev.parent, 259 "%s(): error state\n", 260 __func__); 261 goto done; 262 default: 263 dev_dbg(i2c->adap.dev.parent, 264 "%s(): invalid state %d\n", 265 __func__, i2c->state); 266 res = -EINVAL; 267 goto done; 268 } 269 if (!trans_done) { 270 i2c->state = STATE_WAIT; 271 reg = readw( 272 &i2c->regs->twi_ctrl0_stat); 273 writew(TWI_IRQEN | reg, 274 &i2c->regs->twi_ctrl0_stat); 275 } 276 spin_unlock_irqrestore(&i2c->lock, flags); 277 } else { 278 spin_lock_irqsave(&i2c->lock, flags); 279 dev_dbg(i2c->adap.dev.parent, 280 "%s(): wait timeout\n", __func__); 281 res = -ETIMEDOUT; 282 goto done; 283 } 284 spin_lock_irqsave(&i2c->lock, flags); 285 } 286 } 287 done: 288 spin_unlock_irqrestore(&i2c->lock, flags); 289 dev_dbg(i2c->adap.dev.parent, "%s(): result %d\n", __func__, res); 290 return res; 291 } 292 293 static u32 netup_i2c_func(struct i2c_adapter *adap) 294 { 295 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 296 } 297 298 static const struct i2c_algorithm netup_i2c_algorithm = { 299 .master_xfer = netup_i2c_xfer, 300 .functionality = netup_i2c_func, 301 }; 302 303 static struct i2c_adapter netup_i2c_adapter = { 304 .owner = THIS_MODULE, 305 .name = NETUP_UNIDVB_NAME, 306 .class = I2C_CLASS_HWMON | I2C_CLASS_SPD, 307 .algo = &netup_i2c_algorithm, 308 }; 309 310 static int netup_i2c_init(struct netup_unidvb_dev *ndev, int bus_num) 311 { 312 int ret; 313 struct netup_i2c *i2c; 314 315 if (bus_num < 0 || bus_num > 1) { 316 dev_err(&ndev->pci_dev->dev, 317 "%s(): invalid bus_num %d\n", __func__, bus_num); 318 return -EINVAL; 319 } 320 i2c = &ndev->i2c[bus_num]; 321 spin_lock_init(&i2c->lock); 322 init_waitqueue_head(&i2c->wq); 323 i2c->regs = (struct netup_i2c_regs __iomem *)(ndev->bmmio0 + 324 (bus_num == 0 ? NETUP_I2C_BUS0_ADDR : NETUP_I2C_BUS1_ADDR)); 325 netup_i2c_reset(i2c); 326 i2c->adap = netup_i2c_adapter; 327 i2c->adap.dev.parent = &ndev->pci_dev->dev; 328 i2c_set_adapdata(&i2c->adap, i2c); 329 ret = i2c_add_adapter(&i2c->adap); 330 if (ret) { 331 dev_err(&ndev->pci_dev->dev, 332 "%s(): failed to add I2C adapter\n", __func__); 333 return ret; 334 } 335 dev_info(&ndev->pci_dev->dev, 336 "%s(): registered I2C bus %d at 0x%x\n", 337 __func__, 338 bus_num, (bus_num == 0 ? 339 NETUP_I2C_BUS0_ADDR : 340 NETUP_I2C_BUS1_ADDR)); 341 return 0; 342 } 343 344 static void netup_i2c_remove(struct netup_unidvb_dev *ndev, int bus_num) 345 { 346 struct netup_i2c *i2c; 347 348 if (bus_num < 0 || bus_num > 1) { 349 dev_err(&ndev->pci_dev->dev, 350 "%s(): invalid bus number %d\n", __func__, bus_num); 351 return; 352 } 353 i2c = &ndev->i2c[bus_num]; 354 netup_i2c_reset(i2c); 355 /* remove adapter */ 356 i2c_del_adapter(&i2c->adap); 357 dev_info(&ndev->pci_dev->dev, 358 "netup_i2c_remove: unregistered I2C bus %d\n", bus_num); 359 } 360 361 int netup_i2c_register(struct netup_unidvb_dev *ndev) 362 { 363 int ret; 364 365 ret = netup_i2c_init(ndev, 0); 366 if (ret) 367 return ret; 368 ret = netup_i2c_init(ndev, 1); 369 if (ret) { 370 netup_i2c_remove(ndev, 0); 371 return ret; 372 } 373 return 0; 374 } 375 376 void netup_i2c_unregister(struct netup_unidvb_dev *ndev) 377 { 378 netup_i2c_remove(ndev, 0); 379 netup_i2c_remove(ndev, 1); 380 } 381 382