1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (C) 2017 Intel Corporation */ 3 4 #ifndef __IPU3_CIO2_H 5 #define __IPU3_CIO2_H 6 7 #define CIO2_NAME "ipu3-cio2" 8 #define CIO2_DEVICE_NAME "Intel IPU3 CIO2" 9 #define CIO2_ENTITY_NAME "ipu3-csi2" 10 #define CIO2_PCI_ID 0x9d32 11 #define CIO2_PCI_BAR 0 12 #define CIO2_DMA_MASK DMA_BIT_MASK(39) 13 #define CIO2_IMAGE_MAX_WIDTH 4224 14 #define CIO2_IMAGE_MAX_LENGTH 3136 15 16 #define CIO2_IMAGE_MAX_WIDTH 4224 17 #define CIO2_IMAGE_MAX_LENGTH 3136 18 19 /* 32MB = 8xFBPT_entry */ 20 #define CIO2_MAX_LOPS 8 21 #define CIO2_MAX_BUFFERS (PAGE_SIZE / 16 / CIO2_MAX_LOPS) 22 23 #define CIO2_PAD_SINK 0 24 #define CIO2_PAD_SOURCE 1 25 #define CIO2_PADS 2 26 27 #define CIO2_NUM_DMA_CHAN 20 28 #define CIO2_NUM_PORTS 4 /* DPHYs */ 29 30 /* 1 for each sensor */ 31 #define CIO2_QUEUES CIO2_NUM_PORTS 32 33 /* Register and bit field definitions */ 34 #define CIO2_REG_PIPE_BASE(n) ((n) * 0x0400) /* n = 0..3 */ 35 #define CIO2_REG_CSIRX_BASE 0x000 36 #define CIO2_REG_MIPIBE_BASE 0x100 37 #define CIO2_REG_PIXELGEN_BAS 0x200 38 #define CIO2_REG_IRQCTRL_BASE 0x300 39 #define CIO2_REG_GPREG_BASE 0x1000 40 41 /* base register: CIO2_REG_PIPE_BASE(pipe) * CIO2_REG_CSIRX_BASE */ 42 #define CIO2_REG_CSIRX_ENABLE (CIO2_REG_CSIRX_BASE + 0x0) 43 #define CIO2_REG_CSIRX_NOF_ENABLED_LANES (CIO2_REG_CSIRX_BASE + 0x4) 44 #define CIO2_REG_CSIRX_SP_IF_CONFIG (CIO2_REG_CSIRX_BASE + 0x10) 45 #define CIO2_REG_CSIRX_LP_IF_CONFIG (CIO2_REG_CSIRX_BASE + 0x14) 46 #define CIO2_CSIRX_IF_CONFIG_FILTEROUT 0x00 47 #define CIO2_CSIRX_IF_CONFIG_FILTEROUT_VC_INACTIVE 0x01 48 #define CIO2_CSIRX_IF_CONFIG_PASS 0x02 49 #define CIO2_CSIRX_IF_CONFIG_FLAG_ERROR BIT(2) 50 #define CIO2_REG_CSIRX_STATUS (CIO2_REG_CSIRX_BASE + 0x18) 51 #define CIO2_REG_CSIRX_STATUS_DLANE_HS (CIO2_REG_CSIRX_BASE + 0x1c) 52 #define CIO2_CSIRX_STATUS_DLANE_HS_MASK 0xff 53 #define CIO2_REG_CSIRX_STATUS_DLANE_LP (CIO2_REG_CSIRX_BASE + 0x20) 54 #define CIO2_CSIRX_STATUS_DLANE_LP_MASK 0xffffff 55 /* Termination enable and settle in 0.0625ns units, lane=0..3 or -1 for clock */ 56 #define CIO2_REG_CSIRX_DLY_CNT_TERMEN(lane) \ 57 (CIO2_REG_CSIRX_BASE + 0x2c + 8 * (lane)) 58 #define CIO2_REG_CSIRX_DLY_CNT_SETTLE(lane) \ 59 (CIO2_REG_CSIRX_BASE + 0x30 + 8 * (lane)) 60 /* base register: CIO2_REG_PIPE_BASE(pipe) * CIO2_REG_MIPIBE_BASE */ 61 #define CIO2_REG_MIPIBE_ENABLE (CIO2_REG_MIPIBE_BASE + 0x0) 62 #define CIO2_REG_MIPIBE_STATUS (CIO2_REG_MIPIBE_BASE + 0x4) 63 #define CIO2_REG_MIPIBE_COMP_FORMAT(vc) \ 64 (CIO2_REG_MIPIBE_BASE + 0x8 + 0x4 * (vc)) 65 #define CIO2_REG_MIPIBE_FORCE_RAW8 (CIO2_REG_MIPIBE_BASE + 0x20) 66 #define CIO2_REG_MIPIBE_FORCE_RAW8_ENABLE BIT(0) 67 #define CIO2_REG_MIPIBE_FORCE_RAW8_USE_TYPEID BIT(1) 68 #define CIO2_REG_MIPIBE_FORCE_RAW8_TYPEID_SHIFT 2 69 70 #define CIO2_REG_MIPIBE_IRQ_STATUS (CIO2_REG_MIPIBE_BASE + 0x24) 71 #define CIO2_REG_MIPIBE_IRQ_CLEAR (CIO2_REG_MIPIBE_BASE + 0x28) 72 #define CIO2_REG_MIPIBE_GLOBAL_LUT_DISREGARD (CIO2_REG_MIPIBE_BASE + 0x68) 73 #define CIO2_MIPIBE_GLOBAL_LUT_DISREGARD 1 74 #define CIO2_REG_MIPIBE_PKT_STALL_STATUS (CIO2_REG_MIPIBE_BASE + 0x6c) 75 #define CIO2_REG_MIPIBE_PARSE_GSP_THROUGH_LP_LUT_REG_IDX \ 76 (CIO2_REG_MIPIBE_BASE + 0x70) 77 #define CIO2_REG_MIPIBE_SP_LUT_ENTRY(vc) \ 78 (CIO2_REG_MIPIBE_BASE + 0x74 + 4 * (vc)) 79 #define CIO2_REG_MIPIBE_LP_LUT_ENTRY(m) /* m = 0..15 */ \ 80 (CIO2_REG_MIPIBE_BASE + 0x84 + 4 * (m)) 81 #define CIO2_MIPIBE_LP_LUT_ENTRY_DISREGARD 1 82 #define CIO2_MIPIBE_LP_LUT_ENTRY_SID_SHIFT 1 83 #define CIO2_MIPIBE_LP_LUT_ENTRY_VC_SHIFT 5 84 #define CIO2_MIPIBE_LP_LUT_ENTRY_FORMAT_TYPE_SHIFT 7 85 86 /* base register: CIO2_REG_PIPE_BASE(pipe) * CIO2_REG_IRQCTRL_BASE */ 87 /* IRQ registers are 18-bit wide, see cio2_irq_error for bit definitions */ 88 #define CIO2_REG_IRQCTRL_EDGE (CIO2_REG_IRQCTRL_BASE + 0x00) 89 #define CIO2_REG_IRQCTRL_MASK (CIO2_REG_IRQCTRL_BASE + 0x04) 90 #define CIO2_REG_IRQCTRL_STATUS (CIO2_REG_IRQCTRL_BASE + 0x08) 91 #define CIO2_REG_IRQCTRL_CLEAR (CIO2_REG_IRQCTRL_BASE + 0x0c) 92 #define CIO2_REG_IRQCTRL_ENABLE (CIO2_REG_IRQCTRL_BASE + 0x10) 93 #define CIO2_REG_IRQCTRL_LEVEL_NOT_PULSE (CIO2_REG_IRQCTRL_BASE + 0x14) 94 95 #define CIO2_REG_GPREG_SRST (CIO2_REG_GPREG_BASE + 0x0) 96 #define CIO2_GPREG_SRST_ALL 0xffff /* Reset all */ 97 #define CIO2_REG_FB_HPLL_FREQ (CIO2_REG_GPREG_BASE + 0x08) 98 #define CIO2_REG_ISCLK_RATIO (CIO2_REG_GPREG_BASE + 0xc) 99 100 #define CIO2_REG_CGC 0x1400 101 #define CIO2_CGC_CSI2_TGE BIT(0) 102 #define CIO2_CGC_PRIM_TGE BIT(1) 103 #define CIO2_CGC_SIDE_TGE BIT(2) 104 #define CIO2_CGC_XOSC_TGE BIT(3) 105 #define CIO2_CGC_MPLL_SHUTDOWN_EN BIT(4) 106 #define CIO2_CGC_D3I3_TGE BIT(5) 107 #define CIO2_CGC_CSI2_INTERFRAME_TGE BIT(6) 108 #define CIO2_CGC_CSI2_PORT_DCGE BIT(8) 109 #define CIO2_CGC_CSI2_DCGE BIT(9) 110 #define CIO2_CGC_SIDE_DCGE BIT(10) 111 #define CIO2_CGC_PRIM_DCGE BIT(11) 112 #define CIO2_CGC_ROSC_DCGE BIT(12) 113 #define CIO2_CGC_XOSC_DCGE BIT(13) 114 #define CIO2_CGC_FLIS_DCGE BIT(14) 115 #define CIO2_CGC_CLKGATE_HOLDOFF_SHIFT 20 116 #define CIO2_CGC_CSI_CLKGATE_HOLDOFF_SHIFT 24 117 #define CIO2_REG_D0I3C 0x1408 118 #define CIO2_D0I3C_I3 BIT(2) /* Set D0I3 */ 119 #define CIO2_D0I3C_RR BIT(3) /* Restore? */ 120 #define CIO2_REG_SWRESET 0x140c 121 #define CIO2_SWRESET_SWRESET 1 122 #define CIO2_REG_SENSOR_ACTIVE 0x1410 123 #define CIO2_REG_INT_STS 0x1414 124 #define CIO2_REG_INT_STS_EXT_OE 0x1418 125 #define CIO2_INT_EXT_OE_DMAOE_SHIFT 0 126 #define CIO2_INT_EXT_OE_DMAOE_MASK 0x7ffff 127 #define CIO2_INT_EXT_OE_OES_SHIFT 24 128 #define CIO2_INT_EXT_OE_OES_MASK (0xf << CIO2_INT_EXT_OE_OES_SHIFT) 129 #define CIO2_REG_INT_EN 0x1420 130 #define CIO2_REG_INT_EN_IRQ (1 << 24) 131 #define CIO2_REG_INT_EN_IOS(dma) (1 << (((dma) >> 1) + 12)) 132 /* 133 * Interrupt on completion bit, Eg. DMA 0-3 maps to bit 0-3, 134 * DMA4 & DMA5 map to bit 4 ... DMA18 & DMA19 map to bit 11 Et cetera 135 */ 136 #define CIO2_INT_IOC(dma) (1 << ((dma) < 4 ? (dma) : ((dma) >> 1) + 2)) 137 #define CIO2_INT_IOC_SHIFT 0 138 #define CIO2_INT_IOC_MASK (0x7ff << CIO2_INT_IOC_SHIFT) 139 #define CIO2_INT_IOS_IOLN(dma) (1 << (((dma) >> 1) + 12)) 140 #define CIO2_INT_IOS_IOLN_SHIFT 12 141 #define CIO2_INT_IOS_IOLN_MASK (0x3ff << CIO2_INT_IOS_IOLN_SHIFT) 142 #define CIO2_INT_IOIE BIT(22) 143 #define CIO2_INT_IOOE BIT(23) 144 #define CIO2_INT_IOIRQ BIT(24) 145 #define CIO2_REG_INT_EN_EXT_OE 0x1424 146 #define CIO2_REG_DMA_DBG 0x1448 147 #define CIO2_REG_DMA_DBG_DMA_INDEX_SHIFT 0 148 #define CIO2_REG_PBM_ARB_CTRL 0x1460 149 #define CIO2_PBM_ARB_CTRL_LANES_DIV 0 /* 4-4-2-2 lanes */ 150 #define CIO2_PBM_ARB_CTRL_LANES_DIV_SHIFT 0 151 #define CIO2_PBM_ARB_CTRL_LE_EN BIT(7) 152 #define CIO2_PBM_ARB_CTRL_PLL_POST_SHTDN 2 153 #define CIO2_PBM_ARB_CTRL_PLL_POST_SHTDN_SHIFT 8 154 #define CIO2_PBM_ARB_CTRL_PLL_AHD_WK_UP 480 155 #define CIO2_PBM_ARB_CTRL_PLL_AHD_WK_UP_SHIFT 16 156 #define CIO2_REG_PBM_WMCTRL1 0x1464 157 #define CIO2_PBM_WMCTRL1_MIN_2CK_SHIFT 0 158 #define CIO2_PBM_WMCTRL1_MID1_2CK_SHIFT 8 159 #define CIO2_PBM_WMCTRL1_MID2_2CK_SHIFT 16 160 #define CIO2_PBM_WMCTRL1_TS_COUNT_DISABLE BIT(31) 161 #define CIO2_PBM_WMCTRL1_MIN_2CK (4 << CIO2_PBM_WMCTRL1_MIN_2CK_SHIFT) 162 #define CIO2_PBM_WMCTRL1_MID1_2CK (16 << CIO2_PBM_WMCTRL1_MID1_2CK_SHIFT) 163 #define CIO2_PBM_WMCTRL1_MID2_2CK (21 << CIO2_PBM_WMCTRL1_MID2_2CK_SHIFT) 164 #define CIO2_REG_PBM_WMCTRL2 0x1468 165 #define CIO2_PBM_WMCTRL2_HWM_2CK 40 166 #define CIO2_PBM_WMCTRL2_HWM_2CK_SHIFT 0 167 #define CIO2_PBM_WMCTRL2_LWM_2CK 22 168 #define CIO2_PBM_WMCTRL2_LWM_2CK_SHIFT 8 169 #define CIO2_PBM_WMCTRL2_OBFFWM_2CK 2 170 #define CIO2_PBM_WMCTRL2_OBFFWM_2CK_SHIFT 16 171 #define CIO2_PBM_WMCTRL2_TRANSDYN 1 172 #define CIO2_PBM_WMCTRL2_TRANSDYN_SHIFT 24 173 #define CIO2_PBM_WMCTRL2_DYNWMEN BIT(28) 174 #define CIO2_PBM_WMCTRL2_OBFF_MEM_EN BIT(29) 175 #define CIO2_PBM_WMCTRL2_OBFF_CPU_EN BIT(30) 176 #define CIO2_PBM_WMCTRL2_DRAINNOW BIT(31) 177 #define CIO2_REG_PBM_TS_COUNT 0x146c 178 #define CIO2_REG_PBM_FOPN_ABORT 0x1474 179 /* below n = 0..3 */ 180 #define CIO2_PBM_FOPN_ABORT(n) (0x1 << 8 * (n)) 181 #define CIO2_PBM_FOPN_FORCE_ABORT(n) (0x2 << 8 * (n)) 182 #define CIO2_PBM_FOPN_FRAMEOPEN(n) (0x8 << 8 * (n)) 183 #define CIO2_REG_LTRCTRL 0x1480 184 #define CIO2_LTRCTRL_LTRDYNEN BIT(16) 185 #define CIO2_LTRCTRL_LTRSTABLETIME_SHIFT 8 186 #define CIO2_LTRCTRL_LTRSTABLETIME_MASK 0xff 187 #define CIO2_LTRCTRL_LTRSEL1S3 BIT(7) 188 #define CIO2_LTRCTRL_LTRSEL1S2 BIT(6) 189 #define CIO2_LTRCTRL_LTRSEL1S1 BIT(5) 190 #define CIO2_LTRCTRL_LTRSEL1S0 BIT(4) 191 #define CIO2_LTRCTRL_LTRSEL2S3 BIT(3) 192 #define CIO2_LTRCTRL_LTRSEL2S2 BIT(2) 193 #define CIO2_LTRCTRL_LTRSEL2S1 BIT(1) 194 #define CIO2_LTRCTRL_LTRSEL2S0 BIT(0) 195 #define CIO2_REG_LTRVAL23 0x1484 196 #define CIO2_REG_LTRVAL01 0x1488 197 #define CIO2_LTRVAL02_VAL_SHIFT 0 198 #define CIO2_LTRVAL02_SCALE_SHIFT 10 199 #define CIO2_LTRVAL13_VAL_SHIFT 16 200 #define CIO2_LTRVAL13_SCALE_SHIFT 26 201 202 #define CIO2_LTRVAL0_VAL 175 203 /* Value times 1024 ns */ 204 #define CIO2_LTRVAL0_SCALE 2 205 #define CIO2_LTRVAL1_VAL 90 206 #define CIO2_LTRVAL1_SCALE 2 207 #define CIO2_LTRVAL2_VAL 90 208 #define CIO2_LTRVAL2_SCALE 2 209 #define CIO2_LTRVAL3_VAL 90 210 #define CIO2_LTRVAL3_SCALE 2 211 212 #define CIO2_REG_CDMABA(n) (0x1500 + 0x10 * (n)) /* n = 0..19 */ 213 #define CIO2_REG_CDMARI(n) (0x1504 + 0x10 * (n)) 214 #define CIO2_CDMARI_FBPT_RP_SHIFT 0 215 #define CIO2_CDMARI_FBPT_RP_MASK 0xff 216 #define CIO2_REG_CDMAC0(n) (0x1508 + 0x10 * (n)) 217 #define CIO2_CDMAC0_FBPT_LEN_SHIFT 0 218 #define CIO2_CDMAC0_FBPT_WIDTH_SHIFT 8 219 #define CIO2_CDMAC0_FBPT_NS BIT(25) 220 #define CIO2_CDMAC0_DMA_INTR_ON_FS BIT(26) 221 #define CIO2_CDMAC0_DMA_INTR_ON_FE BIT(27) 222 #define CIO2_CDMAC0_FBPT_UPDATE_FIFO_FULL BIT(28) 223 #define CIO2_CDMAC0_FBPT_FIFO_FULL_FIX_DIS BIT(29) 224 #define CIO2_CDMAC0_DMA_EN BIT(30) 225 #define CIO2_CDMAC0_DMA_HALTED BIT(31) 226 #define CIO2_REG_CDMAC1(n) (0x150c + 0x10 * (n)) 227 #define CIO2_CDMAC1_LINENUMINT_SHIFT 0 228 #define CIO2_CDMAC1_LINENUMUPDATE_SHIFT 16 229 /* n = 0..3 */ 230 #define CIO2_REG_PXM_PXF_FMT_CFG0(n) (0x1700 + 0x30 * (n)) 231 #define CIO2_PXM_PXF_FMT_CFG_SID0_SHIFT 0 232 #define CIO2_PXM_PXF_FMT_CFG_SID1_SHIFT 16 233 #define CIO2_PXM_PXF_FMT_CFG_PCK_64B (0 << 0) 234 #define CIO2_PXM_PXF_FMT_CFG_PCK_32B (1 << 0) 235 #define CIO2_PXM_PXF_FMT_CFG_BPP_08 (0 << 2) 236 #define CIO2_PXM_PXF_FMT_CFG_BPP_10 (1 << 2) 237 #define CIO2_PXM_PXF_FMT_CFG_BPP_12 (2 << 2) 238 #define CIO2_PXM_PXF_FMT_CFG_BPP_14 (3 << 2) 239 #define CIO2_PXM_PXF_FMT_CFG_SPEC_4PPC (0 << 4) 240 #define CIO2_PXM_PXF_FMT_CFG_SPEC_3PPC_RGBA (1 << 4) 241 #define CIO2_PXM_PXF_FMT_CFG_SPEC_3PPC_ARGB (2 << 4) 242 #define CIO2_PXM_PXF_FMT_CFG_SPEC_PLANAR2 (3 << 4) 243 #define CIO2_PXM_PXF_FMT_CFG_SPEC_PLANAR3 (4 << 4) 244 #define CIO2_PXM_PXF_FMT_CFG_SPEC_NV16 (5 << 4) 245 #define CIO2_PXM_PXF_FMT_CFG_PSWAP4_1ST_AB (1 << 7) 246 #define CIO2_PXM_PXF_FMT_CFG_PSWAP4_1ST_CD (1 << 8) 247 #define CIO2_PXM_PXF_FMT_CFG_PSWAP4_2ND_AC (1 << 9) 248 #define CIO2_PXM_PXF_FMT_CFG_PSWAP4_2ND_BD (1 << 10) 249 #define CIO2_REG_INT_STS_EXT_IE 0x17e4 250 #define CIO2_REG_INT_EN_EXT_IE 0x17e8 251 #define CIO2_INT_EXT_IE_ECC_RE(n) (0x01 << (8 * (n))) 252 #define CIO2_INT_EXT_IE_DPHY_NR(n) (0x02 << (8 * (n))) 253 #define CIO2_INT_EXT_IE_ECC_NR(n) (0x04 << (8 * (n))) 254 #define CIO2_INT_EXT_IE_CRCERR(n) (0x08 << (8 * (n))) 255 #define CIO2_INT_EXT_IE_INTERFRAMEDATA(n) (0x10 << (8 * (n))) 256 #define CIO2_INT_EXT_IE_PKT2SHORT(n) (0x20 << (8 * (n))) 257 #define CIO2_INT_EXT_IE_PKT2LONG(n) (0x40 << (8 * (n))) 258 #define CIO2_INT_EXT_IE_IRQ(n) (0x80 << (8 * (n))) 259 #define CIO2_REG_PXM_FRF_CFG(n) (0x1720 + 0x30 * (n)) 260 #define CIO2_PXM_FRF_CFG_FNSEL BIT(0) 261 #define CIO2_PXM_FRF_CFG_FN_RST BIT(1) 262 #define CIO2_PXM_FRF_CFG_ABORT BIT(2) 263 #define CIO2_PXM_FRF_CFG_CRC_TH_SHIFT 3 264 #define CIO2_PXM_FRF_CFG_MSK_ECC_DPHY_NR BIT(8) 265 #define CIO2_PXM_FRF_CFG_MSK_ECC_RE BIT(9) 266 #define CIO2_PXM_FRF_CFG_MSK_ECC_DPHY_NE BIT(10) 267 #define CIO2_PXM_FRF_CFG_EVEN_ODD_MODE_SHIFT 11 268 #define CIO2_PXM_FRF_CFG_MASK_CRC_THRES BIT(13) 269 #define CIO2_PXM_FRF_CFG_MASK_CSI_ACCEPT BIT(14) 270 #define CIO2_PXM_FRF_CFG_CIOHC_FS_MODE BIT(15) 271 #define CIO2_PXM_FRF_CFG_CIOHC_FRST_FRM_SHIFT 16 272 #define CIO2_REG_PXM_SID2BID0(n) (0x1724 + 0x30 * (n)) 273 #define CIO2_FB_HPLL_FREQ 0x2 274 #define CIO2_ISCLK_RATIO 0xc 275 276 #define CIO2_IRQCTRL_MASK 0x3ffff 277 278 #define CIO2_INT_EN_EXT_OE_MASK 0x8f0fffff 279 280 #define CIO2_CGC_CLKGATE_HOLDOFF 3 281 #define CIO2_CGC_CSI_CLKGATE_HOLDOFF 5 282 283 #define CIO2_PXM_FRF_CFG_CRC_TH 16 284 285 #define CIO2_INT_EN_EXT_IE_MASK 0xffffffff 286 287 #define CIO2_DMA_CHAN 0 288 289 #define CIO2_CSIRX_DLY_CNT_CLANE_IDX -1 290 291 #define CIO2_CSIRX_DLY_CNT_TERMEN_CLANE_A 0 292 #define CIO2_CSIRX_DLY_CNT_TERMEN_CLANE_B 0 293 #define CIO2_CSIRX_DLY_CNT_SETTLE_CLANE_A 95 294 #define CIO2_CSIRX_DLY_CNT_SETTLE_CLANE_B -8 295 296 #define CIO2_CSIRX_DLY_CNT_TERMEN_DLANE_A 0 297 #define CIO2_CSIRX_DLY_CNT_TERMEN_DLANE_B 0 298 #define CIO2_CSIRX_DLY_CNT_SETTLE_DLANE_A 85 299 #define CIO2_CSIRX_DLY_CNT_SETTLE_DLANE_B -2 300 301 #define CIO2_CSIRX_DLY_CNT_TERMEN_DEFAULT 0x4 302 #define CIO2_CSIRX_DLY_CNT_SETTLE_DEFAULT 0x570 303 304 #define CIO2_PMCSR_OFFSET 4 305 #define CIO2_PMCSR_D0D3_SHIFT 2 306 #define CIO2_PMCSR_D3 0x3 307 308 struct cio2_csi2_timing { 309 s32 clk_termen; 310 s32 clk_settle; 311 s32 dat_termen; 312 s32 dat_settle; 313 }; 314 315 struct cio2_buffer { 316 struct vb2_v4l2_buffer vbb; 317 u32 *lop[CIO2_MAX_LOPS]; 318 dma_addr_t lop_bus_addr[CIO2_MAX_LOPS]; 319 unsigned int offset; 320 }; 321 322 struct csi2_bus_info { 323 u32 port; 324 u32 lanes; 325 }; 326 327 struct cio2_queue { 328 /* mutex to be used by vb2_queue */ 329 struct mutex lock; 330 struct media_pipeline pipe; 331 struct csi2_bus_info csi2; 332 struct v4l2_subdev *sensor; 333 void __iomem *csi_rx_base; 334 335 /* Subdev, /dev/v4l-subdevX */ 336 struct v4l2_subdev subdev; 337 struct media_pad subdev_pads[CIO2_PADS]; 338 struct v4l2_mbus_framefmt subdev_fmt; 339 atomic_t frame_sequence; 340 341 /* Video device, /dev/videoX */ 342 struct video_device vdev; 343 struct media_pad vdev_pad; 344 struct v4l2_pix_format_mplane format; 345 struct vb2_queue vbq; 346 347 /* Buffer queue handling */ 348 struct cio2_fbpt_entry *fbpt; /* Frame buffer pointer table */ 349 dma_addr_t fbpt_bus_addr; 350 struct cio2_buffer *bufs[CIO2_MAX_BUFFERS]; 351 unsigned int bufs_first; /* Index of the first used entry */ 352 unsigned int bufs_next; /* Index of the first unused entry */ 353 atomic_t bufs_queued; 354 }; 355 356 struct cio2_device { 357 struct pci_dev *pci_dev; 358 void __iomem *base; 359 struct v4l2_device v4l2_dev; 360 struct cio2_queue queue[CIO2_QUEUES]; 361 struct cio2_queue *cur_queue; 362 /* mutex to be used by video_device */ 363 struct mutex lock; 364 365 bool streaming; 366 struct v4l2_async_notifier notifier; 367 struct media_device media_dev; 368 369 /* 370 * Safety net to catch DMA fetch ahead 371 * when reaching the end of LOP 372 */ 373 void *dummy_page; 374 /* DMA handle of dummy_page */ 375 dma_addr_t dummy_page_bus_addr; 376 /* single List of Pointers (LOP) page */ 377 u32 *dummy_lop; 378 /* DMA handle of dummy_lop */ 379 dma_addr_t dummy_lop_bus_addr; 380 }; 381 382 /**************** Virtual channel ****************/ 383 /* 384 * This should come from sensor driver. No 385 * driver interface nor requirement yet. 386 */ 387 #define SENSOR_VIR_CH_DFLT 0 388 389 /**************** FBPT operations ****************/ 390 #define CIO2_FBPT_SIZE (CIO2_MAX_BUFFERS * CIO2_MAX_LOPS * \ 391 sizeof(struct cio2_fbpt_entry)) 392 393 #define CIO2_FBPT_SUBENTRY_UNIT 4 394 #define CIO2_PAGE_SIZE 4096 395 396 /* cio2 fbpt first_entry ctrl status */ 397 #define CIO2_FBPT_CTRL_VALID BIT(0) 398 #define CIO2_FBPT_CTRL_IOC BIT(1) 399 #define CIO2_FBPT_CTRL_IOS BIT(2) 400 #define CIO2_FBPT_CTRL_SUCCXFAIL BIT(3) 401 #define CIO2_FBPT_CTRL_CMPLCODE_SHIFT 4 402 403 /* 404 * Frame Buffer Pointer Table(FBPT) entry 405 * each entry describe an output buffer and consists of 406 * several sub-entries 407 */ 408 struct __packed cio2_fbpt_entry { 409 union { 410 struct __packed { 411 u32 ctrl; /* status ctrl */ 412 u16 cur_line_num; /* current line # written to DDR */ 413 u16 frame_num; /* updated by DMA upon FE */ 414 u32 first_page_offset; /* offset for 1st page in LOP */ 415 } first_entry; 416 /* Second entry per buffer */ 417 struct __packed { 418 u32 timestamp; 419 u32 num_of_bytes; 420 /* the number of bytes for write on last page */ 421 u16 last_page_available_bytes; 422 /* the number of pages allocated for this buf */ 423 u16 num_of_pages; 424 } second_entry; 425 }; 426 u32 lop_page_addr; /* Points to list of pointers (LOP) table */ 427 }; 428 429 static inline struct cio2_queue *file_to_cio2_queue(struct file *file) 430 { 431 return container_of(video_devdata(file), struct cio2_queue, vdev); 432 } 433 434 static inline struct cio2_queue *vb2q_to_cio2_queue(struct vb2_queue *vq) 435 { 436 return container_of(vq, struct cio2_queue, vbq); 437 } 438 439 #endif 440