1 /*************************************************************************** 2 * Copyright (C) 2006-2010 by Marin Mitov * 3 * mitov@issp.bas.bg * 4 * * 5 * This program is free software; you can redistribute it and/or modify * 6 * it under the terms of the GNU General Public License as published by * 7 * the Free Software Foundation; either version 2 of the License, or * 8 * (at your option) any later version. * 9 * * 10 * This program is distributed in the hope that it will be useful, * 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of * 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * 13 * GNU General Public License for more details. * 14 * * 15 ***************************************************************************/ 16 17 /* DT3155 header file */ 18 #ifndef _DT3155_H_ 19 #define _DT3155_H_ 20 21 #include <linux/pci.h> 22 #include <linux/interrupt.h> 23 #include <media/v4l2-device.h> 24 #include <media/v4l2-dev.h> 25 #include <media/videobuf2-v4l2.h> 26 27 #define DT3155_NAME "dt3155" 28 #define DT3155_VER_MAJ 2 29 #define DT3155_VER_MIN 0 30 #define DT3155_VER_EXT 0 31 #define DT3155_VERSION __stringify(DT3155_VER_MAJ) "." \ 32 __stringify(DT3155_VER_MIN) "." \ 33 __stringify(DT3155_VER_EXT) 34 35 /* DT3155 Base Register offsets (memory mapped) */ 36 #define EVEN_DMA_START 0x00 37 #define ODD_DMA_START 0x0C 38 #define EVEN_DMA_STRIDE 0x18 39 #define ODD_DMA_STRIDE 0x24 40 #define EVEN_PIXEL_FMT 0x30 41 #define ODD_PIXEL_FMT 0x34 42 #define FIFO_TRIGER 0x38 43 #define XFER_MODE 0x3C 44 #define CSR1 0x40 45 #define RETRY_WAIT_CNT 0x44 46 #define INT_CSR 0x48 47 #define EVEN_FLD_MASK 0x4C 48 #define ODD_FLD_MASK 0x50 49 #define MASK_LENGTH 0x54 50 #define FIFO_FLAG_CNT 0x58 51 #define IIC_CLK_DUR 0x5C 52 #define IIC_CSR1 0x60 53 #define IIC_CSR2 0x64 54 55 /* DT3155 Internal Registers indexes (i2c/IIC mapped) */ 56 #define CSR2 0x10 57 #define EVEN_CSR 0x11 58 #define ODD_CSR 0x12 59 #define CONFIG 0x13 60 #define DT_ID 0x1F 61 #define X_CLIP_START 0x20 62 #define Y_CLIP_START 0x22 63 #define X_CLIP_END 0x24 64 #define Y_CLIP_END 0x26 65 #define AD_ADDR 0x30 66 #define AD_LUT 0x31 67 #define AD_CMD 0x32 68 #define DIG_OUT 0x40 69 #define PM_LUT_ADDR 0x50 70 #define PM_LUT_DATA 0x51 71 72 /* AD command register values */ 73 #define AD_CMD_REG 0x00 74 #define AD_POS_REF 0x01 75 #define AD_NEG_REF 0x02 76 77 /* CSR1 bit masks */ 78 #define RANGE_EN 0x00008000 79 #define CRPT_DIS 0x00004000 80 #define ADDR_ERR_ODD 0x00000800 81 #define ADDR_ERR_EVEN 0x00000400 82 #define FLD_CRPT_ODD 0x00000200 83 #define FLD_CRPT_EVEN 0x00000100 84 #define FIFO_EN 0x00000080 85 #define SRST 0x00000040 86 #define FLD_DN_ODD 0x00000020 87 #define FLD_DN_EVEN 0x00000010 88 /* These should not be used. 89 * Use CAP_CONT_ODD/EVEN instead 90 #define CAP_SNGL_ODD 0x00000008 91 #define CAP_SNGL_EVEN 0x00000004 92 */ 93 #define CAP_CONT_ODD 0x00000002 94 #define CAP_CONT_EVEN 0x00000001 95 96 /* INT_CSR bit masks */ 97 #define FLD_START_EN 0x00000400 98 #define FLD_END_ODD_EN 0x00000200 99 #define FLD_END_EVEN_EN 0x00000100 100 #define FLD_START 0x00000004 101 #define FLD_END_ODD 0x00000002 102 #define FLD_END_EVEN 0x00000001 103 104 /* IIC_CSR1 bit masks */ 105 #define DIRECT_ABORT 0x00000200 106 107 /* IIC_CSR2 bit masks */ 108 #define NEW_CYCLE 0x01000000 109 #define DIR_RD 0x00010000 110 #define IIC_READ 0x01010000 111 #define IIC_WRITE 0x01000000 112 113 /* CSR2 bit masks */ 114 #define DISP_PASS 0x40 115 #define BUSY_ODD 0x20 116 #define BUSY_EVEN 0x10 117 #define SYNC_PRESENT 0x08 118 #define VT_50HZ 0x04 119 #define SYNC_SNTL 0x02 120 #define CHROM_FILT 0x01 121 #define VT_60HZ 0x00 122 123 /* CSR_EVEN/ODD bit masks */ 124 #define CSR_ERROR 0x04 125 #define CSR_SNGL 0x02 126 #define CSR_DONE 0x01 127 128 /* CONFIG bit masks */ 129 #define PM_LUT_PGM 0x80 130 #define PM_LUT_SEL 0x40 131 #define CLIP_EN 0x20 132 #define HSCALE_EN 0x10 133 #define EXT_TRIG_UP 0x0C 134 #define EXT_TRIG_DOWN 0x04 135 #define ACQ_MODE_NEXT 0x02 136 #define ACQ_MODE_ODD 0x01 137 #define ACQ_MODE_EVEN 0x00 138 139 /* AD_CMD bit masks */ 140 #define VIDEO_CNL_1 0x00 141 #define VIDEO_CNL_2 0x40 142 #define VIDEO_CNL_3 0x80 143 #define VIDEO_CNL_4 0xC0 144 #define SYNC_CNL_1 0x00 145 #define SYNC_CNL_2 0x10 146 #define SYNC_CNL_3 0x20 147 #define SYNC_CNL_4 0x30 148 #define SYNC_LVL_1 0x00 149 #define SYNC_LVL_2 0x04 150 #define SYNC_LVL_3 0x08 151 #define SYNC_LVL_4 0x0C 152 153 /* DT3155 identificator */ 154 #define DT3155_ID 0x20 155 156 /* per board private data structure */ 157 /** 158 * struct dt3155_priv - private data structure 159 * 160 * @v4l2_dev: v4l2_device structure 161 * @vdev: video_device structure 162 * @pdev: pointer to pci_dev structure 163 * @vidq: vb2_queue structure 164 * @curr_buf: pointer to curren buffer 165 * @mux: mutex to protect the instance 166 * @dmaq: queue for dma buffers 167 * @lock: spinlock for dma queue 168 * @std: input standard 169 * @width: frame width 170 * @height: frame height 171 * @input: current input 172 * @sequence: frame counter 173 * @stats: statistics structure 174 * @regs: local copy of mmio base register 175 * @csr2: local copy of csr2 register 176 * @config: local copy of config register 177 */ 178 struct dt3155_priv { 179 struct v4l2_device v4l2_dev; 180 struct video_device vdev; 181 struct pci_dev *pdev; 182 struct vb2_queue vidq; 183 struct vb2_v4l2_buffer *curr_buf; 184 struct mutex mux; 185 struct list_head dmaq; 186 spinlock_t lock; 187 v4l2_std_id std; 188 unsigned width, height; 189 unsigned input; 190 unsigned int sequence; 191 void __iomem *regs; 192 u8 csr2, config; 193 }; 194 195 #endif /* _DT3155_H_ */ 196