1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /*************************************************************************** 3 * Copyright (C) 2006-2010 by Marin Mitov * 4 * mitov@issp.bas.bg * 5 * * 6 * * 7 ***************************************************************************/ 8 9 #include <linux/module.h> 10 #include <linux/stringify.h> 11 #include <linux/delay.h> 12 #include <linux/kthread.h> 13 #include <linux/slab.h> 14 #include <media/v4l2-dev.h> 15 #include <media/v4l2-ioctl.h> 16 #include <media/v4l2-common.h> 17 #include <media/videobuf2-dma-contig.h> 18 19 #include "dt3155.h" 20 21 #define DT3155_DEVICE_ID 0x1223 22 23 /** 24 * read_i2c_reg - reads an internal i2c register 25 * 26 * @addr: dt3155 mmio base address 27 * @index: index (internal address) of register to read 28 * @data: pointer to byte the read data will be placed in 29 * 30 * returns: zero on success or error code 31 * 32 * This function starts reading the specified (by index) register 33 * and busy waits for the process to finish. The result is placed 34 * in a byte pointed by data. 35 */ 36 static int read_i2c_reg(void __iomem *addr, u8 index, u8 *data) 37 { 38 u32 tmp = index; 39 40 iowrite32((tmp << 17) | IIC_READ, addr + IIC_CSR2); 41 udelay(45); /* wait at least 43 usec for NEW_CYCLE to clear */ 42 if (ioread32(addr + IIC_CSR2) & NEW_CYCLE) 43 return -EIO; /* error: NEW_CYCLE not cleared */ 44 tmp = ioread32(addr + IIC_CSR1); 45 if (tmp & DIRECT_ABORT) { 46 /* reset DIRECT_ABORT bit */ 47 iowrite32(DIRECT_ABORT, addr + IIC_CSR1); 48 return -EIO; /* error: DIRECT_ABORT set */ 49 } 50 *data = tmp >> 24; 51 return 0; 52 } 53 54 /** 55 * write_i2c_reg - writes to an internal i2c register 56 * 57 * @addr: dt3155 mmio base address 58 * @index: index (internal address) of register to read 59 * @data: data to be written 60 * 61 * returns: zero on success or error code 62 * 63 * This function starts writing the specified (by index) register 64 * and busy waits for the process to finish. 65 */ 66 static int write_i2c_reg(void __iomem *addr, u8 index, u8 data) 67 { 68 u32 tmp = index; 69 70 iowrite32((tmp << 17) | IIC_WRITE | data, addr + IIC_CSR2); 71 udelay(65); /* wait at least 63 usec for NEW_CYCLE to clear */ 72 if (ioread32(addr + IIC_CSR2) & NEW_CYCLE) 73 return -EIO; /* error: NEW_CYCLE not cleared */ 74 if (ioread32(addr + IIC_CSR1) & DIRECT_ABORT) { 75 /* reset DIRECT_ABORT bit */ 76 iowrite32(DIRECT_ABORT, addr + IIC_CSR1); 77 return -EIO; /* error: DIRECT_ABORT set */ 78 } 79 return 0; 80 } 81 82 /** 83 * write_i2c_reg_nowait - writes to an internal i2c register 84 * 85 * @addr: dt3155 mmio base address 86 * @index: index (internal address) of register to read 87 * @data: data to be written 88 * 89 * This function starts writing the specified (by index) register 90 * and then returns. 91 */ 92 static void write_i2c_reg_nowait(void __iomem *addr, u8 index, u8 data) 93 { 94 u32 tmp = index; 95 96 iowrite32((tmp << 17) | IIC_WRITE | data, addr + IIC_CSR2); 97 } 98 99 /** 100 * wait_i2c_reg - waits the read/write to finish 101 * 102 * @addr: dt3155 mmio base address 103 * 104 * returns: zero on success or error code 105 * 106 * This function waits reading/writing to finish. 107 */ 108 static int wait_i2c_reg(void __iomem *addr) 109 { 110 if (ioread32(addr + IIC_CSR2) & NEW_CYCLE) 111 udelay(65); /* wait at least 63 usec for NEW_CYCLE to clear */ 112 if (ioread32(addr + IIC_CSR2) & NEW_CYCLE) 113 return -EIO; /* error: NEW_CYCLE not cleared */ 114 if (ioread32(addr + IIC_CSR1) & DIRECT_ABORT) { 115 /* reset DIRECT_ABORT bit */ 116 iowrite32(DIRECT_ABORT, addr + IIC_CSR1); 117 return -EIO; /* error: DIRECT_ABORT set */ 118 } 119 return 0; 120 } 121 122 static int 123 dt3155_queue_setup(struct vb2_queue *vq, 124 unsigned int *nbuffers, unsigned int *num_planes, 125 unsigned int sizes[], struct device *alloc_devs[]) 126 127 { 128 struct dt3155_priv *pd = vb2_get_drv_priv(vq); 129 unsigned size = pd->width * pd->height; 130 131 if (vq->num_buffers + *nbuffers < 2) 132 *nbuffers = 2 - vq->num_buffers; 133 if (*num_planes) 134 return sizes[0] < size ? -EINVAL : 0; 135 *num_planes = 1; 136 sizes[0] = size; 137 return 0; 138 } 139 140 static int dt3155_buf_prepare(struct vb2_buffer *vb) 141 { 142 struct dt3155_priv *pd = vb2_get_drv_priv(vb->vb2_queue); 143 144 vb2_set_plane_payload(vb, 0, pd->width * pd->height); 145 return 0; 146 } 147 148 static int dt3155_start_streaming(struct vb2_queue *q, unsigned count) 149 { 150 struct dt3155_priv *pd = vb2_get_drv_priv(q); 151 struct vb2_buffer *vb = &pd->curr_buf->vb2_buf; 152 dma_addr_t dma_addr; 153 154 pd->sequence = 0; 155 dma_addr = vb2_dma_contig_plane_dma_addr(vb, 0); 156 iowrite32(dma_addr, pd->regs + EVEN_DMA_START); 157 iowrite32(dma_addr + pd->width, pd->regs + ODD_DMA_START); 158 iowrite32(pd->width, pd->regs + EVEN_DMA_STRIDE); 159 iowrite32(pd->width, pd->regs + ODD_DMA_STRIDE); 160 /* enable interrupts, clear all irq flags */ 161 iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START | 162 FLD_END_EVEN | FLD_END_ODD, pd->regs + INT_CSR); 163 iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN | 164 FLD_DN_ODD | FLD_DN_EVEN | CAP_CONT_EVEN | CAP_CONT_ODD, 165 pd->regs + CSR1); 166 wait_i2c_reg(pd->regs); 167 write_i2c_reg(pd->regs, CONFIG, pd->config); 168 write_i2c_reg(pd->regs, EVEN_CSR, CSR_ERROR | CSR_DONE); 169 write_i2c_reg(pd->regs, ODD_CSR, CSR_ERROR | CSR_DONE); 170 171 /* start the board */ 172 write_i2c_reg(pd->regs, CSR2, pd->csr2 | BUSY_EVEN | BUSY_ODD); 173 return 0; 174 } 175 176 static void dt3155_stop_streaming(struct vb2_queue *q) 177 { 178 struct dt3155_priv *pd = vb2_get_drv_priv(q); 179 struct vb2_buffer *vb; 180 181 spin_lock_irq(&pd->lock); 182 /* stop the board */ 183 write_i2c_reg_nowait(pd->regs, CSR2, pd->csr2); 184 iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN | 185 FLD_DN_ODD | FLD_DN_EVEN, pd->regs + CSR1); 186 /* disable interrupts, clear all irq flags */ 187 iowrite32(FLD_START | FLD_END_EVEN | FLD_END_ODD, pd->regs + INT_CSR); 188 spin_unlock_irq(&pd->lock); 189 190 /* 191 * It is not clear whether the DMA stops at once or whether it 192 * will finish the current frame or field first. To be on the 193 * safe side we wait a bit. 194 */ 195 msleep(45); 196 197 spin_lock_irq(&pd->lock); 198 if (pd->curr_buf) { 199 vb2_buffer_done(&pd->curr_buf->vb2_buf, VB2_BUF_STATE_ERROR); 200 pd->curr_buf = NULL; 201 } 202 203 while (!list_empty(&pd->dmaq)) { 204 vb = list_first_entry(&pd->dmaq, typeof(*vb), done_entry); 205 list_del(&vb->done_entry); 206 vb2_buffer_done(vb, VB2_BUF_STATE_ERROR); 207 } 208 spin_unlock_irq(&pd->lock); 209 } 210 211 static void dt3155_buf_queue(struct vb2_buffer *vb) 212 { 213 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); 214 struct dt3155_priv *pd = vb2_get_drv_priv(vb->vb2_queue); 215 216 /* pd->vidq.streaming = 1 when dt3155_buf_queue() is invoked */ 217 spin_lock_irq(&pd->lock); 218 if (pd->curr_buf) 219 list_add_tail(&vb->done_entry, &pd->dmaq); 220 else 221 pd->curr_buf = vbuf; 222 spin_unlock_irq(&pd->lock); 223 } 224 225 static const struct vb2_ops q_ops = { 226 .queue_setup = dt3155_queue_setup, 227 .wait_prepare = vb2_ops_wait_prepare, 228 .wait_finish = vb2_ops_wait_finish, 229 .buf_prepare = dt3155_buf_prepare, 230 .start_streaming = dt3155_start_streaming, 231 .stop_streaming = dt3155_stop_streaming, 232 .buf_queue = dt3155_buf_queue, 233 }; 234 235 static irqreturn_t dt3155_irq_handler_even(int irq, void *dev_id) 236 { 237 struct dt3155_priv *ipd = dev_id; 238 struct vb2_buffer *ivb; 239 dma_addr_t dma_addr; 240 u32 tmp; 241 242 tmp = ioread32(ipd->regs + INT_CSR) & (FLD_START | FLD_END_ODD); 243 if (!tmp) 244 return IRQ_NONE; /* not our irq */ 245 if ((tmp & FLD_START) && !(tmp & FLD_END_ODD)) { 246 iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START, 247 ipd->regs + INT_CSR); 248 return IRQ_HANDLED; /* start of field irq */ 249 } 250 tmp = ioread32(ipd->regs + CSR1) & (FLD_CRPT_EVEN | FLD_CRPT_ODD); 251 if (tmp) { 252 iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN | 253 FLD_DN_ODD | FLD_DN_EVEN | 254 CAP_CONT_EVEN | CAP_CONT_ODD, 255 ipd->regs + CSR1); 256 } 257 258 spin_lock(&ipd->lock); 259 if (ipd->curr_buf && !list_empty(&ipd->dmaq)) { 260 ipd->curr_buf->vb2_buf.timestamp = ktime_get_ns(); 261 ipd->curr_buf->sequence = ipd->sequence++; 262 ipd->curr_buf->field = V4L2_FIELD_NONE; 263 vb2_buffer_done(&ipd->curr_buf->vb2_buf, VB2_BUF_STATE_DONE); 264 265 ivb = list_first_entry(&ipd->dmaq, typeof(*ivb), done_entry); 266 list_del(&ivb->done_entry); 267 ipd->curr_buf = to_vb2_v4l2_buffer(ivb); 268 dma_addr = vb2_dma_contig_plane_dma_addr(ivb, 0); 269 iowrite32(dma_addr, ipd->regs + EVEN_DMA_START); 270 iowrite32(dma_addr + ipd->width, ipd->regs + ODD_DMA_START); 271 iowrite32(ipd->width, ipd->regs + EVEN_DMA_STRIDE); 272 iowrite32(ipd->width, ipd->regs + ODD_DMA_STRIDE); 273 } 274 275 /* enable interrupts, clear all irq flags */ 276 iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START | 277 FLD_END_EVEN | FLD_END_ODD, ipd->regs + INT_CSR); 278 spin_unlock(&ipd->lock); 279 return IRQ_HANDLED; 280 } 281 282 static const struct v4l2_file_operations dt3155_fops = { 283 .owner = THIS_MODULE, 284 .open = v4l2_fh_open, 285 .release = vb2_fop_release, 286 .unlocked_ioctl = video_ioctl2, 287 .read = vb2_fop_read, 288 .mmap = vb2_fop_mmap, 289 .poll = vb2_fop_poll 290 }; 291 292 static int dt3155_querycap(struct file *filp, void *p, 293 struct v4l2_capability *cap) 294 { 295 struct dt3155_priv *pd = video_drvdata(filp); 296 297 strscpy(cap->driver, DT3155_NAME, sizeof(cap->driver)); 298 strscpy(cap->card, DT3155_NAME " frame grabber", sizeof(cap->card)); 299 sprintf(cap->bus_info, "PCI:%s", pci_name(pd->pdev)); 300 return 0; 301 } 302 303 static int dt3155_enum_fmt_vid_cap(struct file *filp, 304 void *p, struct v4l2_fmtdesc *f) 305 { 306 if (f->index) 307 return -EINVAL; 308 f->pixelformat = V4L2_PIX_FMT_GREY; 309 strscpy(f->description, "8-bit Greyscale", sizeof(f->description)); 310 return 0; 311 } 312 313 static int dt3155_fmt_vid_cap(struct file *filp, void *p, struct v4l2_format *f) 314 { 315 struct dt3155_priv *pd = video_drvdata(filp); 316 317 f->fmt.pix.width = pd->width; 318 f->fmt.pix.height = pd->height; 319 f->fmt.pix.pixelformat = V4L2_PIX_FMT_GREY; 320 f->fmt.pix.field = V4L2_FIELD_NONE; 321 f->fmt.pix.bytesperline = f->fmt.pix.width; 322 f->fmt.pix.sizeimage = f->fmt.pix.width * f->fmt.pix.height; 323 f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M; 324 return 0; 325 } 326 327 static int dt3155_g_std(struct file *filp, void *p, v4l2_std_id *norm) 328 { 329 struct dt3155_priv *pd = video_drvdata(filp); 330 331 *norm = pd->std; 332 return 0; 333 } 334 335 static int dt3155_s_std(struct file *filp, void *p, v4l2_std_id norm) 336 { 337 struct dt3155_priv *pd = video_drvdata(filp); 338 339 if (pd->std == norm) 340 return 0; 341 if (vb2_is_busy(&pd->vidq)) 342 return -EBUSY; 343 pd->std = norm; 344 if (pd->std & V4L2_STD_525_60) { 345 pd->csr2 = VT_60HZ; 346 pd->width = 640; 347 pd->height = 480; 348 } else { 349 pd->csr2 = VT_50HZ; 350 pd->width = 768; 351 pd->height = 576; 352 } 353 return 0; 354 } 355 356 static int dt3155_enum_input(struct file *filp, void *p, 357 struct v4l2_input *input) 358 { 359 if (input->index > 3) 360 return -EINVAL; 361 if (input->index) 362 snprintf(input->name, sizeof(input->name), "VID%d", 363 input->index); 364 else 365 strscpy(input->name, "J2/VID0", sizeof(input->name)); 366 input->type = V4L2_INPUT_TYPE_CAMERA; 367 input->std = V4L2_STD_ALL; 368 input->status = 0; 369 return 0; 370 } 371 372 static int dt3155_g_input(struct file *filp, void *p, unsigned int *i) 373 { 374 struct dt3155_priv *pd = video_drvdata(filp); 375 376 *i = pd->input; 377 return 0; 378 } 379 380 static int dt3155_s_input(struct file *filp, void *p, unsigned int i) 381 { 382 struct dt3155_priv *pd = video_drvdata(filp); 383 384 if (i > 3) 385 return -EINVAL; 386 pd->input = i; 387 write_i2c_reg(pd->regs, AD_ADDR, AD_CMD_REG); 388 write_i2c_reg(pd->regs, AD_CMD, (i << 6) | (i << 4) | SYNC_LVL_3); 389 return 0; 390 } 391 392 static const struct v4l2_ioctl_ops dt3155_ioctl_ops = { 393 .vidioc_querycap = dt3155_querycap, 394 .vidioc_enum_fmt_vid_cap = dt3155_enum_fmt_vid_cap, 395 .vidioc_try_fmt_vid_cap = dt3155_fmt_vid_cap, 396 .vidioc_g_fmt_vid_cap = dt3155_fmt_vid_cap, 397 .vidioc_s_fmt_vid_cap = dt3155_fmt_vid_cap, 398 .vidioc_reqbufs = vb2_ioctl_reqbufs, 399 .vidioc_create_bufs = vb2_ioctl_create_bufs, 400 .vidioc_querybuf = vb2_ioctl_querybuf, 401 .vidioc_expbuf = vb2_ioctl_expbuf, 402 .vidioc_qbuf = vb2_ioctl_qbuf, 403 .vidioc_dqbuf = vb2_ioctl_dqbuf, 404 .vidioc_streamon = vb2_ioctl_streamon, 405 .vidioc_streamoff = vb2_ioctl_streamoff, 406 .vidioc_g_std = dt3155_g_std, 407 .vidioc_s_std = dt3155_s_std, 408 .vidioc_enum_input = dt3155_enum_input, 409 .vidioc_g_input = dt3155_g_input, 410 .vidioc_s_input = dt3155_s_input, 411 }; 412 413 static int dt3155_init_board(struct dt3155_priv *pd) 414 { 415 struct pci_dev *pdev = pd->pdev; 416 int i; 417 u8 tmp = 0; 418 419 pci_set_master(pdev); /* dt3155 needs it */ 420 421 /* resetting the adapter */ 422 iowrite32(ADDR_ERR_ODD | ADDR_ERR_EVEN | FLD_CRPT_ODD | FLD_CRPT_EVEN | 423 FLD_DN_ODD | FLD_DN_EVEN, pd->regs + CSR1); 424 msleep(20); 425 426 /* initializing adapter registers */ 427 iowrite32(FIFO_EN | SRST, pd->regs + CSR1); 428 iowrite32(0xEEEEEE01, pd->regs + EVEN_PIXEL_FMT); 429 iowrite32(0xEEEEEE01, pd->regs + ODD_PIXEL_FMT); 430 iowrite32(0x00000020, pd->regs + FIFO_TRIGER); 431 iowrite32(0x00000103, pd->regs + XFER_MODE); 432 iowrite32(0, pd->regs + RETRY_WAIT_CNT); 433 iowrite32(0, pd->regs + INT_CSR); 434 iowrite32(1, pd->regs + EVEN_FLD_MASK); 435 iowrite32(1, pd->regs + ODD_FLD_MASK); 436 iowrite32(0, pd->regs + MASK_LENGTH); 437 iowrite32(0x0005007C, pd->regs + FIFO_FLAG_CNT); 438 iowrite32(0x01010101, pd->regs + IIC_CLK_DUR); 439 440 /* verifying that we have a DT3155 board (not just a SAA7116 chip) */ 441 read_i2c_reg(pd->regs, DT_ID, &tmp); 442 if (tmp != DT3155_ID) 443 return -ENODEV; 444 445 /* initialize AD LUT */ 446 write_i2c_reg(pd->regs, AD_ADDR, 0); 447 for (i = 0; i < 256; i++) 448 write_i2c_reg(pd->regs, AD_LUT, i); 449 450 /* initialize ADC references */ 451 /* FIXME: pos_ref & neg_ref depend on VT_50HZ */ 452 write_i2c_reg(pd->regs, AD_ADDR, AD_CMD_REG); 453 write_i2c_reg(pd->regs, AD_CMD, VIDEO_CNL_1 | SYNC_CNL_1 | SYNC_LVL_3); 454 write_i2c_reg(pd->regs, AD_ADDR, AD_POS_REF); 455 write_i2c_reg(pd->regs, AD_CMD, 34); 456 write_i2c_reg(pd->regs, AD_ADDR, AD_NEG_REF); 457 write_i2c_reg(pd->regs, AD_CMD, 0); 458 459 /* initialize PM LUT */ 460 write_i2c_reg(pd->regs, CONFIG, pd->config | PM_LUT_PGM); 461 for (i = 0; i < 256; i++) { 462 write_i2c_reg(pd->regs, PM_LUT_ADDR, i); 463 write_i2c_reg(pd->regs, PM_LUT_DATA, i); 464 } 465 write_i2c_reg(pd->regs, CONFIG, pd->config | PM_LUT_PGM | PM_LUT_SEL); 466 for (i = 0; i < 256; i++) { 467 write_i2c_reg(pd->regs, PM_LUT_ADDR, i); 468 write_i2c_reg(pd->regs, PM_LUT_DATA, i); 469 } 470 write_i2c_reg(pd->regs, CONFIG, pd->config); /* ACQ_MODE_EVEN */ 471 472 /* select channel 1 for input and set sync level */ 473 write_i2c_reg(pd->regs, AD_ADDR, AD_CMD_REG); 474 write_i2c_reg(pd->regs, AD_CMD, VIDEO_CNL_1 | SYNC_CNL_1 | SYNC_LVL_3); 475 476 /* disable all irqs, clear all irq flags */ 477 iowrite32(FLD_START | FLD_END_EVEN | FLD_END_ODD, 478 pd->regs + INT_CSR); 479 480 return 0; 481 } 482 483 static const struct video_device dt3155_vdev = { 484 .name = DT3155_NAME, 485 .fops = &dt3155_fops, 486 .ioctl_ops = &dt3155_ioctl_ops, 487 .minor = -1, 488 .release = video_device_release_empty, 489 .tvnorms = V4L2_STD_ALL, 490 .device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING | 491 V4L2_CAP_READWRITE, 492 }; 493 494 static int dt3155_probe(struct pci_dev *pdev, const struct pci_device_id *id) 495 { 496 int err; 497 struct dt3155_priv *pd; 498 499 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 500 if (err) 501 return -ENODEV; 502 pd = devm_kzalloc(&pdev->dev, sizeof(*pd), GFP_KERNEL); 503 if (!pd) 504 return -ENOMEM; 505 506 err = v4l2_device_register(&pdev->dev, &pd->v4l2_dev); 507 if (err) 508 return err; 509 pd->vdev = dt3155_vdev; 510 pd->vdev.v4l2_dev = &pd->v4l2_dev; 511 video_set_drvdata(&pd->vdev, pd); /* for use in video_fops */ 512 pd->pdev = pdev; 513 pd->std = V4L2_STD_625_50; 514 pd->csr2 = VT_50HZ; 515 pd->width = 768; 516 pd->height = 576; 517 INIT_LIST_HEAD(&pd->dmaq); 518 mutex_init(&pd->mux); 519 pd->vdev.lock = &pd->mux; /* for locking v4l2_file_operations */ 520 pd->vidq.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; 521 pd->vidq.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; 522 pd->vidq.io_modes = VB2_MMAP | VB2_DMABUF | VB2_READ; 523 pd->vidq.ops = &q_ops; 524 pd->vidq.mem_ops = &vb2_dma_contig_memops; 525 pd->vidq.drv_priv = pd; 526 pd->vidq.min_buffers_needed = 2; 527 pd->vidq.gfp_flags = GFP_DMA32; 528 pd->vidq.lock = &pd->mux; /* for locking v4l2_file_operations */ 529 pd->vidq.dev = &pdev->dev; 530 pd->vdev.queue = &pd->vidq; 531 err = vb2_queue_init(&pd->vidq); 532 if (err < 0) 533 goto err_v4l2_dev_unreg; 534 spin_lock_init(&pd->lock); 535 pd->config = ACQ_MODE_EVEN; 536 err = pci_enable_device(pdev); 537 if (err) 538 goto err_v4l2_dev_unreg; 539 err = pci_request_region(pdev, 0, pci_name(pdev)); 540 if (err) 541 goto err_pci_disable; 542 pd->regs = pci_iomap(pdev, 0, pci_resource_len(pd->pdev, 0)); 543 if (!pd->regs) { 544 err = -ENOMEM; 545 goto err_free_reg; 546 } 547 err = dt3155_init_board(pd); 548 if (err) 549 goto err_iounmap; 550 err = request_irq(pd->pdev->irq, dt3155_irq_handler_even, 551 IRQF_SHARED, DT3155_NAME, pd); 552 if (err) 553 goto err_iounmap; 554 err = video_register_device(&pd->vdev, VFL_TYPE_GRABBER, -1); 555 if (err) 556 goto err_free_irq; 557 dev_info(&pdev->dev, "/dev/video%i is ready\n", pd->vdev.minor); 558 return 0; /* success */ 559 560 err_free_irq: 561 free_irq(pd->pdev->irq, pd); 562 err_iounmap: 563 pci_iounmap(pdev, pd->regs); 564 err_free_reg: 565 pci_release_region(pdev, 0); 566 err_pci_disable: 567 pci_disable_device(pdev); 568 err_v4l2_dev_unreg: 569 v4l2_device_unregister(&pd->v4l2_dev); 570 return err; 571 } 572 573 static void dt3155_remove(struct pci_dev *pdev) 574 { 575 struct v4l2_device *v4l2_dev = pci_get_drvdata(pdev); 576 struct dt3155_priv *pd = container_of(v4l2_dev, struct dt3155_priv, 577 v4l2_dev); 578 579 video_unregister_device(&pd->vdev); 580 free_irq(pd->pdev->irq, pd); 581 vb2_queue_release(&pd->vidq); 582 v4l2_device_unregister(&pd->v4l2_dev); 583 pci_iounmap(pdev, pd->regs); 584 pci_release_region(pdev, 0); 585 pci_disable_device(pdev); 586 } 587 588 static const struct pci_device_id pci_ids[] = { 589 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, DT3155_DEVICE_ID) }, 590 { 0, /* zero marks the end */ }, 591 }; 592 MODULE_DEVICE_TABLE(pci, pci_ids); 593 594 static struct pci_driver pci_driver = { 595 .name = DT3155_NAME, 596 .id_table = pci_ids, 597 .probe = dt3155_probe, 598 .remove = dt3155_remove, 599 }; 600 601 module_pci_driver(pci_driver); 602 603 MODULE_DESCRIPTION("video4linux pci-driver for dt3155 frame grabber"); 604 MODULE_AUTHOR("Marin Mitov <mitov@issp.bas.bg>"); 605 MODULE_VERSION(DT3155_VERSION); 606 MODULE_LICENSE("GPL"); 607