1 /*
2  * ddbridge-regs.h: Digital Devices PCIe bridge driver
3  *
4  * Copyright (C) 2010-2017 Digital Devices GmbH
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License
8  * version 2 only, as published by the Free Software Foundation.
9  *
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  * To obtain the license, point your browser to
17  * http://www.gnu.org/copyleft/gpl.html
18  */
19 
20 #ifndef __DDBRIDGE_REGS_H__
21 #define __DDBRIDGE_REGS_H__
22 
23 /* ------------------------------------------------------------------------- */
24 /* SPI Controller */
25 
26 #define SPI_CONTROL     0x10
27 #define SPI_DATA        0x14
28 
29 /* ------------------------------------------------------------------------- */
30 /* GPIO */
31 
32 #define GPIO_OUTPUT      0x20
33 #define GPIO_INPUT       0x24
34 #define GPIO_DIRECTION   0x28
35 
36 /* ------------------------------------------------------------------------- */
37 /* MDIO */
38 
39 #define MDIO_CTRL        0x20
40 #define MDIO_ADR         0x24
41 #define MDIO_REG         0x28
42 #define MDIO_VAL         0x2C
43 
44 /* ------------------------------------------------------------------------- */
45 
46 #define BOARD_CONTROL    0x30
47 
48 /* ------------------------------------------------------------------------- */
49 
50 /* Interrupt controller
51  * How many MSI's are available depends on HW (Min 2 max 8)
52  * How many are usable also depends on Host platform
53  */
54 
55 #define INTERRUPT_BASE   (0x40)
56 
57 #define INTERRUPT_ENABLE (INTERRUPT_BASE + 0x00)
58 #define MSI1_ENABLE      (INTERRUPT_BASE + 0x04)
59 #define MSI2_ENABLE      (INTERRUPT_BASE + 0x08)
60 #define MSI3_ENABLE      (INTERRUPT_BASE + 0x0C)
61 #define MSI4_ENABLE      (INTERRUPT_BASE + 0x10)
62 #define MSI5_ENABLE      (INTERRUPT_BASE + 0x14)
63 #define MSI6_ENABLE      (INTERRUPT_BASE + 0x18)
64 #define MSI7_ENABLE      (INTERRUPT_BASE + 0x1C)
65 
66 #define INTERRUPT_STATUS (INTERRUPT_BASE + 0x20)
67 #define INTERRUPT_ACK    (INTERRUPT_BASE + 0x20)
68 
69 /* Temperature Monitor ( 2x LM75A @ 0x90,0x92 I2c ) */
70 #define TEMPMON_BASE			(0x1c0)
71 #define TEMPMON_CONTROL			(TEMPMON_BASE + 0x00)
72 
73 #define TEMPMON_CONTROL_AUTOSCAN	(0x00000002)
74 #define TEMPMON_CONTROL_INTENABLE	(0x00000004)
75 #define TEMPMON_CONTROL_OVERTEMP	(0x00008000)
76 
77 /* SHORT Temperature in Celsius x 256 */
78 #define TEMPMON_SENSOR0			(TEMPMON_BASE + 0x04)
79 #define TEMPMON_SENSOR1			(TEMPMON_BASE + 0x08)
80 
81 #define TEMPMON_FANCONTROL		(TEMPMON_BASE + 0x10)
82 
83 /* ------------------------------------------------------------------------- */
84 /* I2C Master Controller */
85 
86 #define I2C_COMMAND     (0x00)
87 #define I2C_TIMING      (0x04)
88 #define I2C_TASKLENGTH  (0x08)     /* High read, low write */
89 #define I2C_TASKADDRESS (0x0C)     /* High read, low write */
90 #define I2C_MONITOR     (0x1C)
91 
92 #define I2C_SPEED_400   (0x04030404)
93 #define I2C_SPEED_100   (0x13121313)
94 
95 /* ------------------------------------------------------------------------- */
96 /* DMA  Controller */
97 
98 #define DMA_BASE_WRITE        (0x100)
99 #define DMA_BASE_READ         (0x140)
100 
101 #define TS_CONTROL(_io)         ((_io)->regs + 0x00)
102 #define TS_CONTROL2(_io)        ((_io)->regs + 0x04)
103 
104 /* ------------------------------------------------------------------------- */
105 /* DMA  Buffer */
106 
107 #define DMA_BUFFER_CONTROL(_dma)       ((_dma)->regs + 0x00)
108 #define DMA_BUFFER_ACK(_dma)           ((_dma)->regs + 0x04)
109 #define DMA_BUFFER_CURRENT(_dma)       ((_dma)->regs + 0x08)
110 #define DMA_BUFFER_SIZE(_dma)          ((_dma)->regs + 0x0c)
111 
112 /* ------------------------------------------------------------------------- */
113 /* CI Interface (only CI-Bridge) */
114 
115 #define CI_BASE                         (0x400)
116 #define CI_CONTROL(i)                   (CI_BASE + (i) * 32 + 0x00)
117 
118 #define CI_DO_ATTRIBUTE_RW(i)           (CI_BASE + (i) * 32 + 0x04)
119 #define CI_DO_IO_RW(i)                  (CI_BASE + (i) * 32 + 0x08)
120 #define CI_READDATA(i)                  (CI_BASE + (i) * 32 + 0x0c)
121 #define CI_DO_READ_ATTRIBUTES(i)        (CI_BASE + (i) * 32 + 0x10)
122 
123 #define CI_RESET_CAM                    (0x00000001)
124 #define CI_POWER_ON                     (0x00000002)
125 #define CI_ENABLE                       (0x00000004)
126 #define CI_BYPASS_DISABLE               (0x00000010)
127 
128 #define CI_CAM_READY                    (0x00010000)
129 #define CI_CAM_DETECT                   (0x00020000)
130 #define CI_READY                        (0x80000000)
131 
132 #define CI_READ_CMD                     (0x40000000)
133 #define CI_WRITE_CMD                    (0x80000000)
134 
135 #define CI_BUFFER_BASE                  (0x3000)
136 #define CI_BUFFER_SIZE                  (0x0800)
137 
138 #define CI_BUFFER(i)                    (CI_BUFFER_BASE + (i) * CI_BUFFER_SIZE)
139 
140 /* ------------------------------------------------------------------------- */
141 /* LNB commands (mxl5xx / Max S8) */
142 
143 #define LNB_BASE			(0x400)
144 #define LNB_CONTROL(i)			(LNB_BASE + (i) * 0x20 + 0x00)
145 
146 #define LNB_CMD				(7ULL << 0)
147 #define LNB_CMD_NOP			0
148 #define LNB_CMD_INIT			1
149 #define LNB_CMD_LOW			3
150 #define LNB_CMD_HIGH			4
151 #define LNB_CMD_OFF			5
152 #define LNB_CMD_DISEQC			6
153 
154 #define LNB_BUSY			BIT_ULL(4)
155 #define LNB_TONE			BIT_ULL(15)
156 
157 #define LNB_BUF_LEVEL(i)		(LNB_BASE + (i) * 0x20 + 0x10)
158 #define LNB_BUF_WRITE(i)		(LNB_BASE + (i) * 0x20 + 0x14)
159 
160 #endif /* __DDBRIDGE_REGS_H__ */
161