1 /* 2 * ddbridge.c: Digital Devices PCIe bridge driver 3 * 4 * Copyright (C) 2010-2011 Digital Devices GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * version 2 only, as published by the Free Software Foundation. 9 * 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * To obtain the license, point your browser to 17 * http://www.gnu.org/copyleft/gpl.html 18 */ 19 20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 21 22 #include <linux/module.h> 23 #include <linux/init.h> 24 #include <linux/interrupt.h> 25 #include <linux/delay.h> 26 #include <linux/slab.h> 27 #include <linux/poll.h> 28 #include <linux/io.h> 29 #include <linux/pci.h> 30 #include <linux/pci_ids.h> 31 #include <linux/timer.h> 32 #include <linux/i2c.h> 33 #include <linux/swab.h> 34 #include <linux/vmalloc.h> 35 #include "ddbridge.h" 36 37 #include "ddbridge-regs.h" 38 39 #include "tda18271c2dd.h" 40 #include "stv6110x.h" 41 #include "stv090x.h" 42 #include "lnbh24.h" 43 #include "drxk.h" 44 #include "stv0367.h" 45 #include "stv0367_priv.h" 46 #include "cxd2841er.h" 47 #include "tda18212.h" 48 49 static int xo2_speed = 2; 50 module_param(xo2_speed, int, 0444); 51 MODULE_PARM_DESC(xo2_speed, "default transfer speed for xo2 based duoflex, 0=55,1=75,2=90,3=104 MBit/s, default=2, use attribute to change for individual cards"); 52 53 DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr); 54 55 /* MSI had problems with lost interrupts, fixed but needs testing */ 56 #undef CONFIG_PCI_MSI 57 58 /******************************************************************************/ 59 60 static int i2c_io(struct i2c_adapter *adapter, u8 adr, 61 u8 *wbuf, u32 wlen, u8 *rbuf, u32 rlen) 62 { 63 struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0, 64 .buf = wbuf, .len = wlen }, 65 {.addr = adr, .flags = I2C_M_RD, 66 .buf = rbuf, .len = rlen } }; 67 return (i2c_transfer(adapter, msgs, 2) == 2) ? 0 : -1; 68 } 69 70 static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len) 71 { 72 struct i2c_msg msg = {.addr = adr, .flags = 0, 73 .buf = data, .len = len}; 74 75 return (i2c_transfer(adap, &msg, 1) == 1) ? 0 : -1; 76 } 77 78 static int i2c_read(struct i2c_adapter *adapter, u8 adr, u8 *val) 79 { 80 struct i2c_msg msgs[1] = {{.addr = adr, .flags = I2C_M_RD, 81 .buf = val, .len = 1 } }; 82 return (i2c_transfer(adapter, msgs, 1) == 1) ? 0 : -1; 83 } 84 85 static int i2c_read_regs(struct i2c_adapter *adapter, 86 u8 adr, u8 reg, u8 *val, u8 len) 87 { 88 struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0, 89 .buf = ®, .len = 1 }, 90 {.addr = adr, .flags = I2C_M_RD, 91 .buf = val, .len = len } }; 92 return (i2c_transfer(adapter, msgs, 2) == 2) ? 0 : -1; 93 } 94 95 static int i2c_read_reg(struct i2c_adapter *adapter, u8 adr, u8 reg, u8 *val) 96 { 97 return i2c_read_regs(adapter, adr, reg, val, 1); 98 } 99 100 static int i2c_read_reg16(struct i2c_adapter *adapter, u8 adr, 101 u16 reg, u8 *val) 102 { 103 u8 msg[2] = {reg>>8, reg&0xff}; 104 struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0, 105 .buf = msg, .len = 2}, 106 {.addr = adr, .flags = I2C_M_RD, 107 .buf = val, .len = 1} }; 108 return (i2c_transfer(adapter, msgs, 2) == 2) ? 0 : -1; 109 } 110 111 static int i2c_write_reg(struct i2c_adapter *adap, u8 adr, 112 u8 reg, u8 val) 113 { 114 u8 msg[2] = {reg, val}; 115 116 return i2c_write(adap, adr, msg, 2); 117 } 118 119 static inline u32 safe_ddbreadl(struct ddb *dev, u32 adr) 120 { 121 u32 val = ddbreadl(adr); 122 123 /* (ddb)readl returns (uint)-1 (all bits set) on failure, catch that */ 124 if (val == ~0) { 125 printk(KERN_ERR "ddbreadl failure, adr=%08x\n", adr); 126 return 0; 127 } 128 129 return val; 130 } 131 132 static int ddb_i2c_cmd(struct ddb_i2c *i2c, u32 adr, u32 cmd) 133 { 134 struct ddb *dev = i2c->dev; 135 long stat; 136 u32 val; 137 138 i2c->done = 0; 139 ddbwritel((adr << 9) | cmd, i2c->regs + I2C_COMMAND); 140 stat = wait_event_timeout(i2c->wq, i2c->done == 1, HZ); 141 if (stat == 0) { 142 dev_err(&dev->pdev->dev, "I2C timeout\n"); 143 { /* MSI debugging*/ 144 u32 istat = ddbreadl(INTERRUPT_STATUS); 145 dev_err(&dev->pdev->dev, "IRS %08x\n", istat); 146 ddbwritel(istat, INTERRUPT_ACK); 147 } 148 return -EIO; 149 } 150 val = ddbreadl(i2c->regs+I2C_COMMAND); 151 if (val & 0x70000) 152 return -EIO; 153 return 0; 154 } 155 156 static int ddb_i2c_master_xfer(struct i2c_adapter *adapter, 157 struct i2c_msg msg[], int num) 158 { 159 struct ddb_i2c *i2c = (struct ddb_i2c *)i2c_get_adapdata(adapter); 160 struct ddb *dev = i2c->dev; 161 u8 addr = 0; 162 163 if (num) 164 addr = msg[0].addr; 165 166 if (num == 2 && msg[1].flags & I2C_M_RD && 167 !(msg[0].flags & I2C_M_RD)) { 168 memcpy_toio(dev->regs + I2C_TASKMEM_BASE + i2c->wbuf, 169 msg[0].buf, msg[0].len); 170 ddbwritel(msg[0].len|(msg[1].len << 16), 171 i2c->regs+I2C_TASKLENGTH); 172 if (!ddb_i2c_cmd(i2c, addr, 1)) { 173 memcpy_fromio(msg[1].buf, 174 dev->regs + I2C_TASKMEM_BASE + i2c->rbuf, 175 msg[1].len); 176 return num; 177 } 178 } 179 180 if (num == 1 && !(msg[0].flags & I2C_M_RD)) { 181 ddbcpyto(I2C_TASKMEM_BASE + i2c->wbuf, msg[0].buf, msg[0].len); 182 ddbwritel(msg[0].len, i2c->regs + I2C_TASKLENGTH); 183 if (!ddb_i2c_cmd(i2c, addr, 2)) 184 return num; 185 } 186 if (num == 1 && (msg[0].flags & I2C_M_RD)) { 187 ddbwritel(msg[0].len << 16, i2c->regs + I2C_TASKLENGTH); 188 if (!ddb_i2c_cmd(i2c, addr, 3)) { 189 ddbcpyfrom(msg[0].buf, 190 I2C_TASKMEM_BASE + i2c->rbuf, msg[0].len); 191 return num; 192 } 193 } 194 return -EIO; 195 } 196 197 198 static u32 ddb_i2c_functionality(struct i2c_adapter *adap) 199 { 200 return I2C_FUNC_SMBUS_EMUL; 201 } 202 203 static struct i2c_algorithm ddb_i2c_algo = { 204 .master_xfer = ddb_i2c_master_xfer, 205 .functionality = ddb_i2c_functionality, 206 }; 207 208 static void ddb_i2c_release(struct ddb *dev) 209 { 210 int i; 211 struct ddb_i2c *i2c; 212 struct i2c_adapter *adap; 213 214 for (i = 0; i < dev->info->port_num; i++) { 215 i2c = &dev->i2c[i]; 216 adap = &i2c->adap; 217 i2c_del_adapter(adap); 218 } 219 } 220 221 static int ddb_i2c_init(struct ddb *dev) 222 { 223 int i, j, stat = 0; 224 struct ddb_i2c *i2c; 225 struct i2c_adapter *adap; 226 227 for (i = 0; i < dev->info->port_num; i++) { 228 i2c = &dev->i2c[i]; 229 i2c->dev = dev; 230 i2c->nr = i; 231 i2c->wbuf = i * (I2C_TASKMEM_SIZE / 4); 232 i2c->rbuf = i2c->wbuf + (I2C_TASKMEM_SIZE / 8); 233 i2c->regs = 0x80 + i * 0x20; 234 ddbwritel(I2C_SPEED_100, i2c->regs + I2C_TIMING); 235 ddbwritel((i2c->rbuf << 16) | i2c->wbuf, 236 i2c->regs + I2C_TASKADDRESS); 237 init_waitqueue_head(&i2c->wq); 238 239 adap = &i2c->adap; 240 i2c_set_adapdata(adap, i2c); 241 #ifdef I2C_ADAP_CLASS_TV_DIGITAL 242 adap->class = I2C_ADAP_CLASS_TV_DIGITAL|I2C_CLASS_TV_ANALOG; 243 #else 244 #ifdef I2C_CLASS_TV_ANALOG 245 adap->class = I2C_CLASS_TV_ANALOG; 246 #endif 247 #endif 248 strcpy(adap->name, "ddbridge"); 249 adap->algo = &ddb_i2c_algo; 250 adap->algo_data = (void *)i2c; 251 adap->dev.parent = &dev->pdev->dev; 252 stat = i2c_add_adapter(adap); 253 if (stat) 254 break; 255 } 256 if (stat) 257 for (j = 0; j < i; j++) { 258 i2c = &dev->i2c[j]; 259 adap = &i2c->adap; 260 i2c_del_adapter(adap); 261 } 262 return stat; 263 } 264 265 266 /******************************************************************************/ 267 /******************************************************************************/ 268 /******************************************************************************/ 269 270 #if 0 271 static void set_table(struct ddb *dev, u32 off, 272 dma_addr_t *pbuf, u32 num) 273 { 274 u32 i, base; 275 u64 mem; 276 277 base = DMA_BASE_ADDRESS_TABLE + off; 278 for (i = 0; i < num; i++) { 279 mem = pbuf[i]; 280 ddbwritel(mem & 0xffffffff, base + i * 8); 281 ddbwritel(mem >> 32, base + i * 8 + 4); 282 } 283 } 284 #endif 285 286 static void ddb_address_table(struct ddb *dev) 287 { 288 u32 i, j, base; 289 u64 mem; 290 dma_addr_t *pbuf; 291 292 for (i = 0; i < dev->info->port_num * 2; i++) { 293 base = DMA_BASE_ADDRESS_TABLE + i * 0x100; 294 pbuf = dev->input[i].pbuf; 295 for (j = 0; j < dev->input[i].dma_buf_num; j++) { 296 mem = pbuf[j]; 297 ddbwritel(mem & 0xffffffff, base + j * 8); 298 ddbwritel(mem >> 32, base + j * 8 + 4); 299 } 300 } 301 for (i = 0; i < dev->info->port_num; i++) { 302 base = DMA_BASE_ADDRESS_TABLE + 0x800 + i * 0x100; 303 pbuf = dev->output[i].pbuf; 304 for (j = 0; j < dev->output[i].dma_buf_num; j++) { 305 mem = pbuf[j]; 306 ddbwritel(mem & 0xffffffff, base + j * 8); 307 ddbwritel(mem >> 32, base + j * 8 + 4); 308 } 309 } 310 } 311 312 static void io_free(struct pci_dev *pdev, u8 **vbuf, 313 dma_addr_t *pbuf, u32 size, int num) 314 { 315 int i; 316 317 for (i = 0; i < num; i++) { 318 if (vbuf[i]) { 319 pci_free_consistent(pdev, size, vbuf[i], pbuf[i]); 320 vbuf[i] = NULL; 321 } 322 } 323 } 324 325 static int io_alloc(struct pci_dev *pdev, u8 **vbuf, 326 dma_addr_t *pbuf, u32 size, int num) 327 { 328 int i; 329 330 for (i = 0; i < num; i++) { 331 vbuf[i] = pci_alloc_consistent(pdev, size, &pbuf[i]); 332 if (!vbuf[i]) 333 return -ENOMEM; 334 } 335 return 0; 336 } 337 338 static int ddb_buffers_alloc(struct ddb *dev) 339 { 340 int i; 341 struct ddb_port *port; 342 343 for (i = 0; i < dev->info->port_num; i++) { 344 port = &dev->port[i]; 345 switch (port->class) { 346 case DDB_PORT_TUNER: 347 if (io_alloc(dev->pdev, port->input[0]->vbuf, 348 port->input[0]->pbuf, 349 port->input[0]->dma_buf_size, 350 port->input[0]->dma_buf_num) < 0) 351 return -1; 352 if (io_alloc(dev->pdev, port->input[1]->vbuf, 353 port->input[1]->pbuf, 354 port->input[1]->dma_buf_size, 355 port->input[1]->dma_buf_num) < 0) 356 return -1; 357 break; 358 case DDB_PORT_CI: 359 if (io_alloc(dev->pdev, port->input[0]->vbuf, 360 port->input[0]->pbuf, 361 port->input[0]->dma_buf_size, 362 port->input[0]->dma_buf_num) < 0) 363 return -1; 364 if (io_alloc(dev->pdev, port->output->vbuf, 365 port->output->pbuf, 366 port->output->dma_buf_size, 367 port->output->dma_buf_num) < 0) 368 return -1; 369 break; 370 default: 371 break; 372 } 373 } 374 ddb_address_table(dev); 375 return 0; 376 } 377 378 static void ddb_buffers_free(struct ddb *dev) 379 { 380 int i; 381 struct ddb_port *port; 382 383 for (i = 0; i < dev->info->port_num; i++) { 384 port = &dev->port[i]; 385 io_free(dev->pdev, port->input[0]->vbuf, 386 port->input[0]->pbuf, 387 port->input[0]->dma_buf_size, 388 port->input[0]->dma_buf_num); 389 io_free(dev->pdev, port->input[1]->vbuf, 390 port->input[1]->pbuf, 391 port->input[1]->dma_buf_size, 392 port->input[1]->dma_buf_num); 393 io_free(dev->pdev, port->output->vbuf, 394 port->output->pbuf, 395 port->output->dma_buf_size, 396 port->output->dma_buf_num); 397 } 398 } 399 400 static void ddb_input_start(struct ddb_input *input) 401 { 402 struct ddb *dev = input->port->dev; 403 404 spin_lock_irq(&input->lock); 405 input->cbuf = 0; 406 input->coff = 0; 407 408 /* reset */ 409 ddbwritel(0, TS_INPUT_CONTROL(input->nr)); 410 ddbwritel(2, TS_INPUT_CONTROL(input->nr)); 411 ddbwritel(0, TS_INPUT_CONTROL(input->nr)); 412 413 ddbwritel((1 << 16) | 414 (input->dma_buf_num << 11) | 415 (input->dma_buf_size >> 7), 416 DMA_BUFFER_SIZE(input->nr)); 417 ddbwritel(0, DMA_BUFFER_ACK(input->nr)); 418 419 ddbwritel(1, DMA_BASE_WRITE); 420 ddbwritel(3, DMA_BUFFER_CONTROL(input->nr)); 421 ddbwritel(9, TS_INPUT_CONTROL(input->nr)); 422 input->running = 1; 423 spin_unlock_irq(&input->lock); 424 } 425 426 static void ddb_input_stop(struct ddb_input *input) 427 { 428 struct ddb *dev = input->port->dev; 429 430 spin_lock_irq(&input->lock); 431 ddbwritel(0, TS_INPUT_CONTROL(input->nr)); 432 ddbwritel(0, DMA_BUFFER_CONTROL(input->nr)); 433 input->running = 0; 434 spin_unlock_irq(&input->lock); 435 } 436 437 static void ddb_output_start(struct ddb_output *output) 438 { 439 struct ddb *dev = output->port->dev; 440 441 spin_lock_irq(&output->lock); 442 output->cbuf = 0; 443 output->coff = 0; 444 ddbwritel(0, TS_OUTPUT_CONTROL(output->nr)); 445 ddbwritel(2, TS_OUTPUT_CONTROL(output->nr)); 446 ddbwritel(0, TS_OUTPUT_CONTROL(output->nr)); 447 ddbwritel(0x3c, TS_OUTPUT_CONTROL(output->nr)); 448 ddbwritel((1 << 16) | 449 (output->dma_buf_num << 11) | 450 (output->dma_buf_size >> 7), 451 DMA_BUFFER_SIZE(output->nr + 8)); 452 ddbwritel(0, DMA_BUFFER_ACK(output->nr + 8)); 453 454 ddbwritel(1, DMA_BASE_READ); 455 ddbwritel(3, DMA_BUFFER_CONTROL(output->nr + 8)); 456 /* ddbwritel(0xbd, TS_OUTPUT_CONTROL(output->nr)); */ 457 ddbwritel(0x1d, TS_OUTPUT_CONTROL(output->nr)); 458 output->running = 1; 459 spin_unlock_irq(&output->lock); 460 } 461 462 static void ddb_output_stop(struct ddb_output *output) 463 { 464 struct ddb *dev = output->port->dev; 465 466 spin_lock_irq(&output->lock); 467 ddbwritel(0, TS_OUTPUT_CONTROL(output->nr)); 468 ddbwritel(0, DMA_BUFFER_CONTROL(output->nr + 8)); 469 output->running = 0; 470 spin_unlock_irq(&output->lock); 471 } 472 473 static u32 ddb_output_free(struct ddb_output *output) 474 { 475 u32 idx, off, stat = output->stat; 476 s32 diff; 477 478 idx = (stat >> 11) & 0x1f; 479 off = (stat & 0x7ff) << 7; 480 481 if (output->cbuf != idx) { 482 if ((((output->cbuf + 1) % output->dma_buf_num) == idx) && 483 (output->dma_buf_size - output->coff <= 188)) 484 return 0; 485 return 188; 486 } 487 diff = off - output->coff; 488 if (diff <= 0 || diff > 188) 489 return 188; 490 return 0; 491 } 492 493 static ssize_t ddb_output_write(struct ddb_output *output, 494 const __user u8 *buf, size_t count) 495 { 496 struct ddb *dev = output->port->dev; 497 u32 idx, off, stat = output->stat; 498 u32 left = count, len; 499 500 idx = (stat >> 11) & 0x1f; 501 off = (stat & 0x7ff) << 7; 502 503 while (left) { 504 len = output->dma_buf_size - output->coff; 505 if ((((output->cbuf + 1) % output->dma_buf_num) == idx) && 506 (off == 0)) { 507 if (len <= 188) 508 break; 509 len -= 188; 510 } 511 if (output->cbuf == idx) { 512 if (off > output->coff) { 513 #if 1 514 len = off - output->coff; 515 len -= (len % 188); 516 if (len <= 188) 517 518 #endif 519 break; 520 len -= 188; 521 } 522 } 523 if (len > left) 524 len = left; 525 if (copy_from_user(output->vbuf[output->cbuf] + output->coff, 526 buf, len)) 527 return -EIO; 528 left -= len; 529 buf += len; 530 output->coff += len; 531 if (output->coff == output->dma_buf_size) { 532 output->coff = 0; 533 output->cbuf = ((output->cbuf + 1) % output->dma_buf_num); 534 } 535 ddbwritel((output->cbuf << 11) | (output->coff >> 7), 536 DMA_BUFFER_ACK(output->nr + 8)); 537 } 538 return count - left; 539 } 540 541 static u32 ddb_input_avail(struct ddb_input *input) 542 { 543 struct ddb *dev = input->port->dev; 544 u32 idx, off, stat = input->stat; 545 u32 ctrl = ddbreadl(DMA_BUFFER_CONTROL(input->nr)); 546 547 idx = (stat >> 11) & 0x1f; 548 off = (stat & 0x7ff) << 7; 549 550 if (ctrl & 4) { 551 dev_err(&dev->pdev->dev, "IA %d %d %08x\n", idx, off, ctrl); 552 ddbwritel(input->stat, DMA_BUFFER_ACK(input->nr)); 553 return 0; 554 } 555 if (input->cbuf != idx) 556 return 188; 557 return 0; 558 } 559 560 static ssize_t ddb_input_read(struct ddb_input *input, __user u8 *buf, size_t count) 561 { 562 struct ddb *dev = input->port->dev; 563 u32 left = count; 564 u32 idx, free, stat = input->stat; 565 int ret; 566 567 idx = (stat >> 11) & 0x1f; 568 569 while (left) { 570 if (input->cbuf == idx) 571 return count - left; 572 free = input->dma_buf_size - input->coff; 573 if (free > left) 574 free = left; 575 ret = copy_to_user(buf, input->vbuf[input->cbuf] + 576 input->coff, free); 577 if (ret) 578 return -EFAULT; 579 input->coff += free; 580 if (input->coff == input->dma_buf_size) { 581 input->coff = 0; 582 input->cbuf = (input->cbuf+1) % input->dma_buf_num; 583 } 584 left -= free; 585 ddbwritel((input->cbuf << 11) | (input->coff >> 7), 586 DMA_BUFFER_ACK(input->nr)); 587 } 588 return count; 589 } 590 591 /******************************************************************************/ 592 /******************************************************************************/ 593 /******************************************************************************/ 594 595 #if 0 596 static struct ddb_input *fe2input(struct ddb *dev, struct dvb_frontend *fe) 597 { 598 int i; 599 600 for (i = 0; i < dev->info->port_num * 2; i++) { 601 if (dev->input[i].fe == fe) 602 return &dev->input[i]; 603 } 604 return NULL; 605 } 606 #endif 607 608 static int drxk_gate_ctrl(struct dvb_frontend *fe, int enable) 609 { 610 struct ddb_input *input = fe->sec_priv; 611 struct ddb_port *port = input->port; 612 int status; 613 614 if (enable) { 615 mutex_lock(&port->i2c_gate_lock); 616 status = input->gate_ctrl(fe, 1); 617 } else { 618 status = input->gate_ctrl(fe, 0); 619 mutex_unlock(&port->i2c_gate_lock); 620 } 621 return status; 622 } 623 624 static int demod_attach_drxk(struct ddb_input *input) 625 { 626 struct i2c_adapter *i2c = &input->port->i2c->adap; 627 struct dvb_frontend *fe; 628 struct drxk_config config; 629 struct device *dev = &input->port->dev->pdev->dev; 630 631 memset(&config, 0, sizeof(config)); 632 config.microcode_name = "drxk_a3.mc"; 633 config.qam_demod_parameter_count = 4; 634 config.adr = 0x29 + (input->nr & 1); 635 636 fe = input->fe = dvb_attach(drxk_attach, &config, i2c); 637 if (!input->fe) { 638 dev_err(dev, "No DRXK found!\n"); 639 return -ENODEV; 640 } 641 fe->sec_priv = input; 642 input->gate_ctrl = fe->ops.i2c_gate_ctrl; 643 fe->ops.i2c_gate_ctrl = drxk_gate_ctrl; 644 return 0; 645 } 646 647 static int tuner_attach_tda18271(struct ddb_input *input) 648 { 649 struct i2c_adapter *i2c = &input->port->i2c->adap; 650 struct dvb_frontend *fe; 651 struct device *dev = &input->port->dev->pdev->dev; 652 653 if (input->fe->ops.i2c_gate_ctrl) 654 input->fe->ops.i2c_gate_ctrl(input->fe, 1); 655 fe = dvb_attach(tda18271c2dd_attach, input->fe, i2c, 0x60); 656 if (!fe) { 657 dev_err(dev, "No TDA18271 found!\n"); 658 return -ENODEV; 659 } 660 if (input->fe->ops.i2c_gate_ctrl) 661 input->fe->ops.i2c_gate_ctrl(input->fe, 0); 662 return 0; 663 } 664 665 /******************************************************************************/ 666 /******************************************************************************/ 667 /******************************************************************************/ 668 669 static struct stv0367_config ddb_stv0367_config[] = { 670 { 671 .demod_address = 0x1f, 672 .xtal = 27000000, 673 .if_khz = 0, 674 .if_iq_mode = FE_TER_NORMAL_IF_TUNER, 675 .ts_mode = STV0367_SERIAL_PUNCT_CLOCK, 676 .clk_pol = STV0367_CLOCKPOLARITY_DEFAULT, 677 }, { 678 .demod_address = 0x1e, 679 .xtal = 27000000, 680 .if_khz = 0, 681 .if_iq_mode = FE_TER_NORMAL_IF_TUNER, 682 .ts_mode = STV0367_SERIAL_PUNCT_CLOCK, 683 .clk_pol = STV0367_CLOCKPOLARITY_DEFAULT, 684 }, 685 }; 686 687 static int demod_attach_stv0367(struct ddb_input *input) 688 { 689 struct i2c_adapter *i2c = &input->port->i2c->adap; 690 struct device *dev = &input->port->dev->pdev->dev; 691 692 /* attach frontend */ 693 input->fe = dvb_attach(stv0367ddb_attach, 694 &ddb_stv0367_config[(input->nr & 1)], i2c); 695 696 if (!input->fe) { 697 dev_err(dev, "stv0367ddb_attach failed (not found?)\n"); 698 return -ENODEV; 699 } 700 701 input->fe->sec_priv = input; 702 input->gate_ctrl = input->fe->ops.i2c_gate_ctrl; 703 input->fe->ops.i2c_gate_ctrl = drxk_gate_ctrl; 704 705 return 0; 706 } 707 708 static int tuner_tda18212_ping(struct ddb_input *input, unsigned short adr) 709 { 710 struct i2c_adapter *adapter = &input->port->i2c->adap; 711 struct device *dev = &input->port->dev->pdev->dev; 712 713 u8 tda_id[2]; 714 u8 subaddr = 0x00; 715 716 dev_dbg(dev, "stv0367-tda18212 tuner ping\n"); 717 if (input->fe->ops.i2c_gate_ctrl) 718 input->fe->ops.i2c_gate_ctrl(input->fe, 1); 719 720 if (i2c_read_regs(adapter, adr, subaddr, tda_id, sizeof(tda_id)) < 0) 721 dev_dbg(dev, "tda18212 ping 1 fail\n"); 722 if (i2c_read_regs(adapter, adr, subaddr, tda_id, sizeof(tda_id)) < 0) 723 dev_warn(dev, "tda18212 ping failed, expect problems\n"); 724 725 if (input->fe->ops.i2c_gate_ctrl) 726 input->fe->ops.i2c_gate_ctrl(input->fe, 0); 727 728 return 0; 729 } 730 731 static int demod_attach_cxd28xx(struct ddb_input *input, int par, int osc24) 732 { 733 struct i2c_adapter *i2c = &input->port->i2c->adap; 734 struct device *dev = &input->port->dev->pdev->dev; 735 struct cxd2841er_config cfg; 736 737 /* the cxd2841er driver expects 8bit/shifted I2C addresses */ 738 cfg.i2c_addr = ((input->nr & 1) ? 0x6d : 0x6c) << 1; 739 740 cfg.xtal = osc24 ? SONY_XTAL_24000 : SONY_XTAL_20500; 741 cfg.flags = CXD2841ER_AUTO_IFHZ | CXD2841ER_EARLY_TUNE | 742 CXD2841ER_NO_WAIT_LOCK | CXD2841ER_NO_AGCNEG | 743 CXD2841ER_TSBITS; 744 745 if (!par) 746 cfg.flags |= CXD2841ER_TS_SERIAL; 747 748 /* attach frontend */ 749 input->fe = dvb_attach(cxd2841er_attach_t_c, &cfg, i2c); 750 751 if (!input->fe) { 752 dev_err(dev, "No Sony CXD28xx found!\n"); 753 return -ENODEV; 754 } 755 756 input->fe->sec_priv = input; 757 input->gate_ctrl = input->fe->ops.i2c_gate_ctrl; 758 input->fe->ops.i2c_gate_ctrl = drxk_gate_ctrl; 759 760 return 0; 761 } 762 763 static int tuner_attach_tda18212(struct ddb_input *input, u32 porttype) 764 { 765 struct i2c_adapter *adapter = &input->port->i2c->adap; 766 struct device *dev = &input->port->dev->pdev->dev; 767 struct i2c_client *client; 768 struct tda18212_config config = { 769 .fe = input->fe, 770 .if_dvbt_6 = 3550, 771 .if_dvbt_7 = 3700, 772 .if_dvbt_8 = 4150, 773 .if_dvbt2_6 = 3250, 774 .if_dvbt2_7 = 4000, 775 .if_dvbt2_8 = 4000, 776 .if_dvbc = 5000, 777 }; 778 struct i2c_board_info board_info = { 779 .type = "tda18212", 780 .platform_data = &config, 781 }; 782 783 if (input->nr & 1) 784 board_info.addr = 0x63; 785 else 786 board_info.addr = 0x60; 787 788 /* due to a hardware quirk with the I2C gate on the stv0367+tda18212 789 * combo, the tda18212 must be probed by reading it's id _twice_ when 790 * cold started, or it very likely will fail. 791 */ 792 if (porttype == DDB_TUNER_DVBCT_ST) 793 tuner_tda18212_ping(input, board_info.addr); 794 795 request_module(board_info.type); 796 797 /* perform tuner init/attach */ 798 client = i2c_new_device(adapter, &board_info); 799 if (client == NULL || client->dev.driver == NULL) 800 goto err; 801 802 if (!try_module_get(client->dev.driver->owner)) { 803 i2c_unregister_device(client); 804 goto err; 805 } 806 807 input->i2c_client[0] = client; 808 809 return 0; 810 err: 811 dev_warn(dev, "TDA18212 tuner not found. Device is not fully operational.\n"); 812 return -ENODEV; 813 } 814 815 /******************************************************************************/ 816 /******************************************************************************/ 817 /******************************************************************************/ 818 819 static struct stv090x_config stv0900 = { 820 .device = STV0900, 821 .demod_mode = STV090x_DUAL, 822 .clk_mode = STV090x_CLK_EXT, 823 824 .xtal = 27000000, 825 .address = 0x69, 826 827 .ts1_mode = STV090x_TSMODE_SERIAL_PUNCTURED, 828 .ts2_mode = STV090x_TSMODE_SERIAL_PUNCTURED, 829 830 .repeater_level = STV090x_RPTLEVEL_16, 831 832 .adc1_range = STV090x_ADC_1Vpp, 833 .adc2_range = STV090x_ADC_1Vpp, 834 835 .diseqc_envelope_mode = true, 836 }; 837 838 static struct stv090x_config stv0900_aa = { 839 .device = STV0900, 840 .demod_mode = STV090x_DUAL, 841 .clk_mode = STV090x_CLK_EXT, 842 843 .xtal = 27000000, 844 .address = 0x68, 845 846 .ts1_mode = STV090x_TSMODE_SERIAL_PUNCTURED, 847 .ts2_mode = STV090x_TSMODE_SERIAL_PUNCTURED, 848 849 .repeater_level = STV090x_RPTLEVEL_16, 850 851 .adc1_range = STV090x_ADC_1Vpp, 852 .adc2_range = STV090x_ADC_1Vpp, 853 854 .diseqc_envelope_mode = true, 855 }; 856 857 static struct stv6110x_config stv6110a = { 858 .addr = 0x60, 859 .refclk = 27000000, 860 .clk_div = 1, 861 }; 862 863 static struct stv6110x_config stv6110b = { 864 .addr = 0x63, 865 .refclk = 27000000, 866 .clk_div = 1, 867 }; 868 869 static int demod_attach_stv0900(struct ddb_input *input, int type) 870 { 871 struct i2c_adapter *i2c = &input->port->i2c->adap; 872 struct device *dev = &input->port->dev->pdev->dev; 873 struct stv090x_config *feconf = type ? &stv0900_aa : &stv0900; 874 875 input->fe = dvb_attach(stv090x_attach, feconf, i2c, 876 (input->nr & 1) ? STV090x_DEMODULATOR_1 877 : STV090x_DEMODULATOR_0); 878 if (!input->fe) { 879 dev_err(dev, "No STV0900 found!\n"); 880 return -ENODEV; 881 } 882 if (!dvb_attach(lnbh24_attach, input->fe, i2c, 0, 883 0, (input->nr & 1) ? 884 (0x09 - type) : (0x0b - type))) { 885 dev_err(dev, "No LNBH24 found!\n"); 886 return -ENODEV; 887 } 888 return 0; 889 } 890 891 static int tuner_attach_stv6110(struct ddb_input *input, int type) 892 { 893 struct i2c_adapter *i2c = &input->port->i2c->adap; 894 struct device *dev = &input->port->dev->pdev->dev; 895 struct stv090x_config *feconf = type ? &stv0900_aa : &stv0900; 896 struct stv6110x_config *tunerconf = (input->nr & 1) ? 897 &stv6110b : &stv6110a; 898 const struct stv6110x_devctl *ctl; 899 900 ctl = dvb_attach(stv6110x_attach, input->fe, tunerconf, i2c); 901 if (!ctl) { 902 dev_err(dev, "No STV6110X found!\n"); 903 return -ENODEV; 904 } 905 dev_info(dev, "attach tuner input %d adr %02x\n", 906 input->nr, tunerconf->addr); 907 908 feconf->tuner_init = ctl->tuner_init; 909 feconf->tuner_sleep = ctl->tuner_sleep; 910 feconf->tuner_set_mode = ctl->tuner_set_mode; 911 feconf->tuner_set_frequency = ctl->tuner_set_frequency; 912 feconf->tuner_get_frequency = ctl->tuner_get_frequency; 913 feconf->tuner_set_bandwidth = ctl->tuner_set_bandwidth; 914 feconf->tuner_get_bandwidth = ctl->tuner_get_bandwidth; 915 feconf->tuner_set_bbgain = ctl->tuner_set_bbgain; 916 feconf->tuner_get_bbgain = ctl->tuner_get_bbgain; 917 feconf->tuner_set_refclk = ctl->tuner_set_refclk; 918 feconf->tuner_get_status = ctl->tuner_get_status; 919 920 return 0; 921 } 922 923 static int my_dvb_dmx_ts_card_init(struct dvb_demux *dvbdemux, char *id, 924 int (*start_feed)(struct dvb_demux_feed *), 925 int (*stop_feed)(struct dvb_demux_feed *), 926 void *priv) 927 { 928 dvbdemux->priv = priv; 929 930 dvbdemux->filternum = 256; 931 dvbdemux->feednum = 256; 932 dvbdemux->start_feed = start_feed; 933 dvbdemux->stop_feed = stop_feed; 934 dvbdemux->write_to_decoder = NULL; 935 dvbdemux->dmx.capabilities = (DMX_TS_FILTERING | 936 DMX_SECTION_FILTERING | 937 DMX_MEMORY_BASED_FILTERING); 938 return dvb_dmx_init(dvbdemux); 939 } 940 941 static int my_dvb_dmxdev_ts_card_init(struct dmxdev *dmxdev, 942 struct dvb_demux *dvbdemux, 943 struct dmx_frontend *hw_frontend, 944 struct dmx_frontend *mem_frontend, 945 struct dvb_adapter *dvb_adapter) 946 { 947 int ret; 948 949 dmxdev->filternum = 256; 950 dmxdev->demux = &dvbdemux->dmx; 951 dmxdev->capabilities = 0; 952 ret = dvb_dmxdev_init(dmxdev, dvb_adapter); 953 if (ret < 0) 954 return ret; 955 956 hw_frontend->source = DMX_FRONTEND_0; 957 dvbdemux->dmx.add_frontend(&dvbdemux->dmx, hw_frontend); 958 mem_frontend->source = DMX_MEMORY_FE; 959 dvbdemux->dmx.add_frontend(&dvbdemux->dmx, mem_frontend); 960 return dvbdemux->dmx.connect_frontend(&dvbdemux->dmx, hw_frontend); 961 } 962 963 static int start_feed(struct dvb_demux_feed *dvbdmxfeed) 964 { 965 struct dvb_demux *dvbdmx = dvbdmxfeed->demux; 966 struct ddb_input *input = dvbdmx->priv; 967 968 if (!input->users) 969 ddb_input_start(input); 970 971 return ++input->users; 972 } 973 974 static int stop_feed(struct dvb_demux_feed *dvbdmxfeed) 975 { 976 struct dvb_demux *dvbdmx = dvbdmxfeed->demux; 977 struct ddb_input *input = dvbdmx->priv; 978 979 if (--input->users) 980 return input->users; 981 982 ddb_input_stop(input); 983 return 0; 984 } 985 986 987 static void dvb_input_detach(struct ddb_input *input) 988 { 989 struct dvb_adapter *adap = &input->adap; 990 struct dvb_demux *dvbdemux = &input->demux; 991 struct i2c_client *client; 992 993 switch (input->attached) { 994 case 5: 995 client = input->i2c_client[0]; 996 if (client) { 997 module_put(client->dev.driver->owner); 998 i2c_unregister_device(client); 999 } 1000 if (input->fe2) { 1001 dvb_unregister_frontend(input->fe2); 1002 input->fe2 = NULL; 1003 } 1004 if (input->fe) { 1005 dvb_unregister_frontend(input->fe); 1006 dvb_frontend_detach(input->fe); 1007 input->fe = NULL; 1008 } 1009 /* fall-through */ 1010 case 4: 1011 dvb_net_release(&input->dvbnet); 1012 /* fall-through */ 1013 case 3: 1014 dvbdemux->dmx.close(&dvbdemux->dmx); 1015 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, 1016 &input->hw_frontend); 1017 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, 1018 &input->mem_frontend); 1019 dvb_dmxdev_release(&input->dmxdev); 1020 /* fall-through */ 1021 case 2: 1022 dvb_dmx_release(&input->demux); 1023 /* fall-through */ 1024 case 1: 1025 dvb_unregister_adapter(adap); 1026 } 1027 input->attached = 0; 1028 } 1029 1030 static int dvb_input_attach(struct ddb_input *input) 1031 { 1032 int ret; 1033 struct ddb_port *port = input->port; 1034 struct dvb_adapter *adap = &input->adap; 1035 struct dvb_demux *dvbdemux = &input->demux; 1036 struct device *dev = &input->port->dev->pdev->dev; 1037 int sony_osc24 = 0, sony_tspar = 0; 1038 1039 ret = dvb_register_adapter(adap, "DDBridge", THIS_MODULE, 1040 &input->port->dev->pdev->dev, 1041 adapter_nr); 1042 if (ret < 0) { 1043 dev_err(dev, "Could not register adapter. Check if you enabled enough adapters in dvb-core!\n"); 1044 return ret; 1045 } 1046 input->attached = 1; 1047 1048 ret = my_dvb_dmx_ts_card_init(dvbdemux, "SW demux", 1049 start_feed, 1050 stop_feed, input); 1051 if (ret < 0) 1052 return ret; 1053 input->attached = 2; 1054 1055 ret = my_dvb_dmxdev_ts_card_init(&input->dmxdev, &input->demux, 1056 &input->hw_frontend, 1057 &input->mem_frontend, adap); 1058 if (ret < 0) 1059 return ret; 1060 input->attached = 3; 1061 1062 ret = dvb_net_init(adap, &input->dvbnet, input->dmxdev.demux); 1063 if (ret < 0) 1064 return ret; 1065 input->attached = 4; 1066 1067 input->fe = NULL; 1068 switch (port->type) { 1069 case DDB_TUNER_DVBS_ST: 1070 if (demod_attach_stv0900(input, 0) < 0) 1071 return -ENODEV; 1072 if (tuner_attach_stv6110(input, 0) < 0) 1073 return -ENODEV; 1074 if (input->fe) { 1075 if (dvb_register_frontend(adap, input->fe) < 0) 1076 return -ENODEV; 1077 } 1078 break; 1079 case DDB_TUNER_DVBS_ST_AA: 1080 if (demod_attach_stv0900(input, 1) < 0) 1081 return -ENODEV; 1082 if (tuner_attach_stv6110(input, 1) < 0) 1083 return -ENODEV; 1084 if (input->fe) { 1085 if (dvb_register_frontend(adap, input->fe) < 0) 1086 return -ENODEV; 1087 } 1088 break; 1089 case DDB_TUNER_DVBCT_TR: 1090 if (demod_attach_drxk(input) < 0) 1091 return -ENODEV; 1092 if (tuner_attach_tda18271(input) < 0) 1093 return -ENODEV; 1094 if (dvb_register_frontend(adap, input->fe) < 0) 1095 return -ENODEV; 1096 if (input->fe2) { 1097 if (dvb_register_frontend(adap, input->fe2) < 0) 1098 return -ENODEV; 1099 input->fe2->tuner_priv = input->fe->tuner_priv; 1100 memcpy(&input->fe2->ops.tuner_ops, 1101 &input->fe->ops.tuner_ops, 1102 sizeof(struct dvb_tuner_ops)); 1103 } 1104 break; 1105 case DDB_TUNER_DVBCT_ST: 1106 if (demod_attach_stv0367(input) < 0) 1107 return -ENODEV; 1108 if (tuner_attach_tda18212(input, port->type) < 0) 1109 return -ENODEV; 1110 if (input->fe) { 1111 if (dvb_register_frontend(adap, input->fe) < 0) 1112 return -ENODEV; 1113 } 1114 break; 1115 case DDB_TUNER_DVBC2T2I_SONY_P: 1116 case DDB_TUNER_DVBCT2_SONY_P: 1117 case DDB_TUNER_DVBC2T2_SONY_P: 1118 case DDB_TUNER_ISDBT_SONY_P: 1119 if (port->type == DDB_TUNER_DVBC2T2I_SONY_P) 1120 sony_osc24 = 1; 1121 if (input->port->dev->info->ts_quirks & TS_QUIRK_ALT_OSC) 1122 sony_osc24 = 0; 1123 if (input->port->dev->info->ts_quirks & TS_QUIRK_SERIAL) 1124 sony_tspar = 0; 1125 else 1126 sony_tspar = 1; 1127 1128 if (demod_attach_cxd28xx(input, sony_tspar, sony_osc24) < 0) 1129 return -ENODEV; 1130 if (tuner_attach_tda18212(input, port->type) < 0) 1131 return -ENODEV; 1132 if (input->fe) { 1133 if (dvb_register_frontend(adap, input->fe) < 0) 1134 return -ENODEV; 1135 } 1136 break; 1137 case DDB_TUNER_XO2_DVBC2T2I_SONY: 1138 case DDB_TUNER_XO2_DVBCT2_SONY: 1139 case DDB_TUNER_XO2_DVBC2T2_SONY: 1140 case DDB_TUNER_XO2_ISDBT_SONY: 1141 if (port->type == DDB_TUNER_XO2_DVBC2T2I_SONY) 1142 sony_osc24 = 1; 1143 1144 if (demod_attach_cxd28xx(input, 0, sony_osc24) < 0) 1145 return -ENODEV; 1146 if (tuner_attach_tda18212(input, port->type) < 0) 1147 return -ENODEV; 1148 if (input->fe) { 1149 if (dvb_register_frontend(adap, input->fe) < 0) 1150 return -ENODEV; 1151 } 1152 break; 1153 } 1154 1155 input->attached = 5; 1156 return 0; 1157 } 1158 1159 /****************************************************************************/ 1160 /****************************************************************************/ 1161 1162 static ssize_t ts_write(struct file *file, const __user char *buf, 1163 size_t count, loff_t *ppos) 1164 { 1165 struct dvb_device *dvbdev = file->private_data; 1166 struct ddb_output *output = dvbdev->priv; 1167 size_t left = count; 1168 int stat; 1169 1170 while (left) { 1171 if (ddb_output_free(output) < 188) { 1172 if (file->f_flags & O_NONBLOCK) 1173 break; 1174 if (wait_event_interruptible( 1175 output->wq, ddb_output_free(output) >= 188) < 0) 1176 break; 1177 } 1178 stat = ddb_output_write(output, buf, left); 1179 if (stat < 0) 1180 break; 1181 buf += stat; 1182 left -= stat; 1183 } 1184 return (left == count) ? -EAGAIN : (count - left); 1185 } 1186 1187 static ssize_t ts_read(struct file *file, __user char *buf, 1188 size_t count, loff_t *ppos) 1189 { 1190 struct dvb_device *dvbdev = file->private_data; 1191 struct ddb_output *output = dvbdev->priv; 1192 struct ddb_input *input = output->port->input[0]; 1193 int left, read; 1194 1195 count -= count % 188; 1196 left = count; 1197 while (left) { 1198 if (ddb_input_avail(input) < 188) { 1199 if (file->f_flags & O_NONBLOCK) 1200 break; 1201 if (wait_event_interruptible( 1202 input->wq, ddb_input_avail(input) >= 188) < 0) 1203 break; 1204 } 1205 read = ddb_input_read(input, buf, left); 1206 if (read < 0) 1207 return read; 1208 left -= read; 1209 buf += read; 1210 } 1211 return (left == count) ? -EAGAIN : (count - left); 1212 } 1213 1214 static unsigned int ts_poll(struct file *file, poll_table *wait) 1215 { 1216 /* 1217 struct dvb_device *dvbdev = file->private_data; 1218 struct ddb_output *output = dvbdev->priv; 1219 struct ddb_input *input = output->port->input[0]; 1220 */ 1221 unsigned int mask = 0; 1222 1223 #if 0 1224 if (data_avail_to_read) 1225 mask |= POLLIN | POLLRDNORM; 1226 if (data_avail_to_write) 1227 mask |= POLLOUT | POLLWRNORM; 1228 1229 poll_wait(file, &read_queue, wait); 1230 poll_wait(file, &write_queue, wait); 1231 #endif 1232 return mask; 1233 } 1234 1235 static const struct file_operations ci_fops = { 1236 .owner = THIS_MODULE, 1237 .read = ts_read, 1238 .write = ts_write, 1239 .open = dvb_generic_open, 1240 .release = dvb_generic_release, 1241 .poll = ts_poll, 1242 }; 1243 1244 static struct dvb_device dvbdev_ci = { 1245 .readers = -1, 1246 .writers = -1, 1247 .users = -1, 1248 .fops = &ci_fops, 1249 }; 1250 1251 /****************************************************************************/ 1252 /****************************************************************************/ 1253 /****************************************************************************/ 1254 1255 static void input_tasklet(unsigned long data) 1256 { 1257 struct ddb_input *input = (struct ddb_input *) data; 1258 struct ddb *dev = input->port->dev; 1259 1260 spin_lock(&input->lock); 1261 if (!input->running) { 1262 spin_unlock(&input->lock); 1263 return; 1264 } 1265 input->stat = ddbreadl(DMA_BUFFER_CURRENT(input->nr)); 1266 1267 if (input->port->class == DDB_PORT_TUNER) { 1268 if (4&ddbreadl(DMA_BUFFER_CONTROL(input->nr))) 1269 dev_err(&dev->pdev->dev, "Overflow input %d\n", input->nr); 1270 while (input->cbuf != ((input->stat >> 11) & 0x1f) 1271 || (4 & safe_ddbreadl(dev, DMA_BUFFER_CONTROL(input->nr)))) { 1272 dvb_dmx_swfilter_packets(&input->demux, 1273 input->vbuf[input->cbuf], 1274 input->dma_buf_size / 188); 1275 1276 input->cbuf = (input->cbuf + 1) % input->dma_buf_num; 1277 ddbwritel((input->cbuf << 11), 1278 DMA_BUFFER_ACK(input->nr)); 1279 input->stat = ddbreadl(DMA_BUFFER_CURRENT(input->nr)); 1280 } 1281 } 1282 if (input->port->class == DDB_PORT_CI) 1283 wake_up(&input->wq); 1284 spin_unlock(&input->lock); 1285 } 1286 1287 static void output_tasklet(unsigned long data) 1288 { 1289 struct ddb_output *output = (struct ddb_output *) data; 1290 struct ddb *dev = output->port->dev; 1291 1292 spin_lock(&output->lock); 1293 if (!output->running) { 1294 spin_unlock(&output->lock); 1295 return; 1296 } 1297 output->stat = ddbreadl(DMA_BUFFER_CURRENT(output->nr + 8)); 1298 wake_up(&output->wq); 1299 spin_unlock(&output->lock); 1300 } 1301 1302 1303 static struct cxd2099_cfg cxd_cfg = { 1304 .bitrate = 62000, 1305 .adr = 0x40, 1306 .polarity = 1, 1307 .clock_mode = 1, 1308 }; 1309 1310 static int ddb_ci_attach(struct ddb_port *port) 1311 { 1312 int ret; 1313 1314 ret = dvb_register_adapter(&port->output->adap, 1315 "DDBridge", 1316 THIS_MODULE, 1317 &port->dev->pdev->dev, 1318 adapter_nr); 1319 if (ret < 0) 1320 return ret; 1321 port->en = cxd2099_attach(&cxd_cfg, port, &port->i2c->adap); 1322 if (!port->en) { 1323 dvb_unregister_adapter(&port->output->adap); 1324 return -ENODEV; 1325 } 1326 ddb_input_start(port->input[0]); 1327 ddb_output_start(port->output); 1328 dvb_ca_en50221_init(&port->output->adap, 1329 port->en, 0, 1); 1330 ret = dvb_register_device(&port->output->adap, &port->output->dev, 1331 &dvbdev_ci, (void *) port->output, 1332 DVB_DEVICE_SEC, 0); 1333 return ret; 1334 } 1335 1336 static int ddb_port_attach(struct ddb_port *port) 1337 { 1338 struct device *dev = &port->dev->pdev->dev; 1339 int ret = 0; 1340 1341 switch (port->class) { 1342 case DDB_PORT_TUNER: 1343 ret = dvb_input_attach(port->input[0]); 1344 if (ret < 0) 1345 break; 1346 ret = dvb_input_attach(port->input[1]); 1347 break; 1348 case DDB_PORT_CI: 1349 ret = ddb_ci_attach(port); 1350 break; 1351 default: 1352 break; 1353 } 1354 if (ret < 0) 1355 dev_err(dev, "port_attach on port %d failed\n", port->nr); 1356 return ret; 1357 } 1358 1359 static int ddb_ports_attach(struct ddb *dev) 1360 { 1361 int i, ret = 0; 1362 struct ddb_port *port; 1363 1364 for (i = 0; i < dev->info->port_num; i++) { 1365 port = &dev->port[i]; 1366 ret = ddb_port_attach(port); 1367 if (ret < 0) 1368 break; 1369 } 1370 return ret; 1371 } 1372 1373 static void ddb_ports_detach(struct ddb *dev) 1374 { 1375 int i; 1376 struct ddb_port *port; 1377 1378 for (i = 0; i < dev->info->port_num; i++) { 1379 port = &dev->port[i]; 1380 switch (port->class) { 1381 case DDB_PORT_TUNER: 1382 dvb_input_detach(port->input[0]); 1383 dvb_input_detach(port->input[1]); 1384 break; 1385 case DDB_PORT_CI: 1386 dvb_unregister_device(port->output->dev); 1387 if (port->en) { 1388 ddb_input_stop(port->input[0]); 1389 ddb_output_stop(port->output); 1390 dvb_ca_en50221_release(port->en); 1391 kfree(port->en); 1392 port->en = NULL; 1393 dvb_unregister_adapter(&port->output->adap); 1394 } 1395 break; 1396 } 1397 } 1398 } 1399 1400 /****************************************************************************/ 1401 /****************************************************************************/ 1402 1403 static int init_xo2(struct ddb_port *port) 1404 { 1405 struct i2c_adapter *i2c = &port->i2c->adap; 1406 struct device *dev = &port->dev->pdev->dev; 1407 u8 val, data[2]; 1408 int res; 1409 1410 res = i2c_read_regs(i2c, 0x10, 0x04, data, 2); 1411 if (res < 0) 1412 return res; 1413 1414 if (data[0] != 0x01) { 1415 dev_info(dev, "Port %d: invalid XO2\n", port->nr); 1416 return -1; 1417 } 1418 1419 i2c_read_reg(i2c, 0x10, 0x08, &val); 1420 if (val != 0) { 1421 i2c_write_reg(i2c, 0x10, 0x08, 0x00); 1422 msleep(100); 1423 } 1424 /* Enable tuner power, disable pll, reset demods */ 1425 i2c_write_reg(i2c, 0x10, 0x08, 0x04); 1426 usleep_range(2000, 3000); 1427 /* Release demod resets */ 1428 i2c_write_reg(i2c, 0x10, 0x08, 0x07); 1429 1430 /* speed: 0=55,1=75,2=90,3=104 MBit/s */ 1431 i2c_write_reg(i2c, 0x10, 0x09, 1432 ((xo2_speed >= 0 && xo2_speed <= 3) ? xo2_speed : 2)); 1433 1434 i2c_write_reg(i2c, 0x10, 0x0a, 0x01); 1435 i2c_write_reg(i2c, 0x10, 0x0b, 0x01); 1436 1437 usleep_range(2000, 3000); 1438 /* Start XO2 PLL */ 1439 i2c_write_reg(i2c, 0x10, 0x08, 0x87); 1440 1441 return 0; 1442 } 1443 1444 static int port_has_xo2(struct ddb_port *port, u8 *type, u8 *id) 1445 { 1446 u8 probe[1] = { 0x00 }, data[4]; 1447 1448 *type = DDB_XO2_TYPE_NONE; 1449 1450 if (i2c_io(&port->i2c->adap, 0x10, probe, 1, data, 4)) 1451 return 0; 1452 if (data[0] == 'D' && data[1] == 'F') { 1453 *id = data[2]; 1454 *type = DDB_XO2_TYPE_DUOFLEX; 1455 return 1; 1456 } 1457 if (data[0] == 'C' && data[1] == 'I') { 1458 *id = data[2]; 1459 *type = DDB_XO2_TYPE_CI; 1460 return 1; 1461 } 1462 return 0; 1463 } 1464 1465 /****************************************************************************/ 1466 /****************************************************************************/ 1467 1468 static int port_has_ci(struct ddb_port *port) 1469 { 1470 u8 val; 1471 return i2c_read_reg(&port->i2c->adap, 0x40, 0, &val) ? 0 : 1; 1472 } 1473 1474 static int port_has_stv0900(struct ddb_port *port) 1475 { 1476 u8 val; 1477 if (i2c_read_reg16(&port->i2c->adap, 0x69, 0xf100, &val) < 0) 1478 return 0; 1479 return 1; 1480 } 1481 1482 static int port_has_stv0900_aa(struct ddb_port *port) 1483 { 1484 u8 val; 1485 if (i2c_read_reg16(&port->i2c->adap, 0x68, 0xf100, &val) < 0) 1486 return 0; 1487 return 1; 1488 } 1489 1490 static int port_has_drxks(struct ddb_port *port) 1491 { 1492 u8 val; 1493 if (i2c_read(&port->i2c->adap, 0x29, &val) < 0) 1494 return 0; 1495 if (i2c_read(&port->i2c->adap, 0x2a, &val) < 0) 1496 return 0; 1497 return 1; 1498 } 1499 1500 static int port_has_stv0367(struct ddb_port *port) 1501 { 1502 u8 val; 1503 if (i2c_read_reg16(&port->i2c->adap, 0x1e, 0xf000, &val) < 0) 1504 return 0; 1505 if (val != 0x60) 1506 return 0; 1507 if (i2c_read_reg16(&port->i2c->adap, 0x1f, 0xf000, &val) < 0) 1508 return 0; 1509 if (val != 0x60) 1510 return 0; 1511 return 1; 1512 } 1513 1514 static int port_has_cxd28xx(struct ddb_port *port, u8 *id) 1515 { 1516 struct i2c_adapter *i2c = &port->i2c->adap; 1517 int status; 1518 1519 status = i2c_write_reg(&port->i2c->adap, 0x6e, 0, 0); 1520 if (status) 1521 return 0; 1522 status = i2c_read_reg(i2c, 0x6e, 0xfd, id); 1523 if (status) 1524 return 0; 1525 return 1; 1526 } 1527 1528 static void ddb_port_probe(struct ddb_port *port) 1529 { 1530 struct ddb *dev = port->dev; 1531 char *modname = "NO MODULE"; 1532 u8 xo2_type, xo2_id, cxd_id; 1533 1534 port->class = DDB_PORT_NONE; 1535 1536 if (port_has_ci(port)) { 1537 modname = "CI"; 1538 port->class = DDB_PORT_CI; 1539 ddbwritel(I2C_SPEED_400, port->i2c->regs + I2C_TIMING); 1540 } else if (port_has_xo2(port, &xo2_type, &xo2_id)) { 1541 dev_dbg(&dev->pdev->dev, "Port %d (TAB %d): XO2 type: %d, id: %d\n", 1542 port->nr, port->nr+1, xo2_type, xo2_id); 1543 1544 ddbwritel(I2C_SPEED_400, port->i2c->regs + I2C_TIMING); 1545 1546 switch (xo2_type) { 1547 case DDB_XO2_TYPE_DUOFLEX: 1548 init_xo2(port); 1549 switch (xo2_id >> 2) { 1550 case 0: 1551 modname = "DUAL DVB-S2 (unsupported)"; 1552 port->class = DDB_PORT_NONE; 1553 port->type = DDB_TUNER_XO2_DVBS_STV0910; 1554 break; 1555 case 1: 1556 modname = "DUAL DVB-C/T/T2"; 1557 port->class = DDB_PORT_TUNER; 1558 port->type = DDB_TUNER_XO2_DVBCT2_SONY; 1559 break; 1560 case 2: 1561 modname = "DUAL DVB-ISDBT"; 1562 port->class = DDB_PORT_TUNER; 1563 port->type = DDB_TUNER_XO2_ISDBT_SONY; 1564 break; 1565 case 3: 1566 modname = "DUAL DVB-C/C2/T/T2"; 1567 port->class = DDB_PORT_TUNER; 1568 port->type = DDB_TUNER_XO2_DVBC2T2_SONY; 1569 break; 1570 case 4: 1571 modname = "DUAL ATSC (unsupported)"; 1572 port->class = DDB_PORT_NONE; 1573 port->type = DDB_TUNER_XO2_ATSC_ST; 1574 break; 1575 case 5: 1576 modname = "DUAL DVB-C/C2/T/T2/ISDBT"; 1577 port->class = DDB_PORT_TUNER; 1578 port->type = DDB_TUNER_XO2_DVBC2T2I_SONY; 1579 break; 1580 default: 1581 modname = "Unknown XO2 DuoFlex module\n"; 1582 break; 1583 } 1584 break; 1585 case DDB_XO2_TYPE_CI: 1586 dev_info(&dev->pdev->dev, "DuoFlex CI modules not supported\n"); 1587 break; 1588 default: 1589 dev_info(&dev->pdev->dev, "Unknown XO2 DuoFlex module\n"); 1590 break; 1591 } 1592 } else if (port_has_cxd28xx(port, &cxd_id)) { 1593 switch (cxd_id) { 1594 case 0xa4: 1595 modname = "DUAL DVB-C2T2 CXD2843"; 1596 port->class = DDB_PORT_TUNER; 1597 port->type = DDB_TUNER_DVBC2T2_SONY_P; 1598 break; 1599 case 0xb1: 1600 modname = "DUAL DVB-CT2 CXD2837"; 1601 port->class = DDB_PORT_TUNER; 1602 port->type = DDB_TUNER_DVBCT2_SONY_P; 1603 break; 1604 case 0xb0: 1605 modname = "DUAL ISDB-T CXD2838"; 1606 port->class = DDB_PORT_TUNER; 1607 port->type = DDB_TUNER_ISDBT_SONY_P; 1608 break; 1609 case 0xc1: 1610 modname = "DUAL DVB-C2T2 ISDB-T CXD2854"; 1611 port->class = DDB_PORT_TUNER; 1612 port->type = DDB_TUNER_DVBC2T2I_SONY_P; 1613 break; 1614 default: 1615 modname = "Unknown CXD28xx tuner"; 1616 break; 1617 } 1618 ddbwritel(I2C_SPEED_400, port->i2c->regs + I2C_TIMING); 1619 } else if (port_has_stv0900(port)) { 1620 modname = "DUAL DVB-S2"; 1621 port->class = DDB_PORT_TUNER; 1622 port->type = DDB_TUNER_DVBS_ST; 1623 ddbwritel(I2C_SPEED_100, port->i2c->regs + I2C_TIMING); 1624 } else if (port_has_stv0900_aa(port)) { 1625 modname = "DUAL DVB-S2"; 1626 port->class = DDB_PORT_TUNER; 1627 port->type = DDB_TUNER_DVBS_ST_AA; 1628 ddbwritel(I2C_SPEED_100, port->i2c->regs + I2C_TIMING); 1629 } else if (port_has_drxks(port)) { 1630 modname = "DUAL DVB-C/T"; 1631 port->class = DDB_PORT_TUNER; 1632 port->type = DDB_TUNER_DVBCT_TR; 1633 ddbwritel(I2C_SPEED_400, port->i2c->regs + I2C_TIMING); 1634 } else if (port_has_stv0367(port)) { 1635 modname = "DUAL DVB-C/T"; 1636 port->class = DDB_PORT_TUNER; 1637 port->type = DDB_TUNER_DVBCT_ST; 1638 ddbwritel(I2C_SPEED_100, port->i2c->regs + I2C_TIMING); 1639 } 1640 1641 dev_info(&dev->pdev->dev, "Port %d (TAB %d): %s\n", 1642 port->nr, port->nr+1, modname); 1643 } 1644 1645 static void ddb_input_init(struct ddb_port *port, int nr) 1646 { 1647 struct ddb *dev = port->dev; 1648 struct ddb_input *input = &dev->input[nr]; 1649 1650 input->nr = nr; 1651 input->port = port; 1652 input->dma_buf_num = INPUT_DMA_BUFS; 1653 input->dma_buf_size = INPUT_DMA_SIZE; 1654 ddbwritel(0, TS_INPUT_CONTROL(nr)); 1655 ddbwritel(2, TS_INPUT_CONTROL(nr)); 1656 ddbwritel(0, TS_INPUT_CONTROL(nr)); 1657 ddbwritel(0, DMA_BUFFER_ACK(nr)); 1658 tasklet_init(&input->tasklet, input_tasklet, (unsigned long) input); 1659 spin_lock_init(&input->lock); 1660 init_waitqueue_head(&input->wq); 1661 } 1662 1663 static void ddb_output_init(struct ddb_port *port, int nr) 1664 { 1665 struct ddb *dev = port->dev; 1666 struct ddb_output *output = &dev->output[nr]; 1667 output->nr = nr; 1668 output->port = port; 1669 output->dma_buf_num = OUTPUT_DMA_BUFS; 1670 output->dma_buf_size = OUTPUT_DMA_SIZE; 1671 1672 ddbwritel(0, TS_OUTPUT_CONTROL(nr)); 1673 ddbwritel(2, TS_OUTPUT_CONTROL(nr)); 1674 ddbwritel(0, TS_OUTPUT_CONTROL(nr)); 1675 tasklet_init(&output->tasklet, output_tasklet, (unsigned long) output); 1676 init_waitqueue_head(&output->wq); 1677 } 1678 1679 static void ddb_ports_init(struct ddb *dev) 1680 { 1681 int i; 1682 struct ddb_port *port; 1683 1684 for (i = 0; i < dev->info->port_num; i++) { 1685 port = &dev->port[i]; 1686 port->dev = dev; 1687 port->nr = i; 1688 port->i2c = &dev->i2c[i]; 1689 port->input[0] = &dev->input[2 * i]; 1690 port->input[1] = &dev->input[2 * i + 1]; 1691 port->output = &dev->output[i]; 1692 1693 mutex_init(&port->i2c_gate_lock); 1694 ddb_port_probe(port); 1695 ddb_input_init(port, 2 * i); 1696 ddb_input_init(port, 2 * i + 1); 1697 ddb_output_init(port, i); 1698 } 1699 } 1700 1701 static void ddb_ports_release(struct ddb *dev) 1702 { 1703 int i; 1704 struct ddb_port *port; 1705 1706 for (i = 0; i < dev->info->port_num; i++) { 1707 port = &dev->port[i]; 1708 port->dev = dev; 1709 tasklet_kill(&port->input[0]->tasklet); 1710 tasklet_kill(&port->input[1]->tasklet); 1711 tasklet_kill(&port->output->tasklet); 1712 } 1713 } 1714 1715 /****************************************************************************/ 1716 /****************************************************************************/ 1717 /****************************************************************************/ 1718 1719 static void irq_handle_i2c(struct ddb *dev, int n) 1720 { 1721 struct ddb_i2c *i2c = &dev->i2c[n]; 1722 1723 i2c->done = 1; 1724 wake_up(&i2c->wq); 1725 } 1726 1727 static irqreturn_t irq_handler(int irq, void *dev_id) 1728 { 1729 struct ddb *dev = (struct ddb *) dev_id; 1730 u32 s = ddbreadl(INTERRUPT_STATUS); 1731 1732 if (!s) 1733 return IRQ_NONE; 1734 1735 do { 1736 ddbwritel(s, INTERRUPT_ACK); 1737 1738 if (s & 0x00000001) 1739 irq_handle_i2c(dev, 0); 1740 if (s & 0x00000002) 1741 irq_handle_i2c(dev, 1); 1742 if (s & 0x00000004) 1743 irq_handle_i2c(dev, 2); 1744 if (s & 0x00000008) 1745 irq_handle_i2c(dev, 3); 1746 1747 if (s & 0x00000100) 1748 tasklet_schedule(&dev->input[0].tasklet); 1749 if (s & 0x00000200) 1750 tasklet_schedule(&dev->input[1].tasklet); 1751 if (s & 0x00000400) 1752 tasklet_schedule(&dev->input[2].tasklet); 1753 if (s & 0x00000800) 1754 tasklet_schedule(&dev->input[3].tasklet); 1755 if (s & 0x00001000) 1756 tasklet_schedule(&dev->input[4].tasklet); 1757 if (s & 0x00002000) 1758 tasklet_schedule(&dev->input[5].tasklet); 1759 if (s & 0x00004000) 1760 tasklet_schedule(&dev->input[6].tasklet); 1761 if (s & 0x00008000) 1762 tasklet_schedule(&dev->input[7].tasklet); 1763 1764 if (s & 0x00010000) 1765 tasklet_schedule(&dev->output[0].tasklet); 1766 if (s & 0x00020000) 1767 tasklet_schedule(&dev->output[1].tasklet); 1768 if (s & 0x00040000) 1769 tasklet_schedule(&dev->output[2].tasklet); 1770 if (s & 0x00080000) 1771 tasklet_schedule(&dev->output[3].tasklet); 1772 1773 /* if (s & 0x000f0000) printk(KERN_DEBUG "%08x\n", istat); */ 1774 } while ((s = ddbreadl(INTERRUPT_STATUS))); 1775 1776 return IRQ_HANDLED; 1777 } 1778 1779 /******************************************************************************/ 1780 /******************************************************************************/ 1781 /******************************************************************************/ 1782 1783 static int flashio(struct ddb *dev, u8 *wbuf, u32 wlen, u8 *rbuf, u32 rlen) 1784 { 1785 u32 data, shift; 1786 1787 if (wlen > 4) 1788 ddbwritel(1, SPI_CONTROL); 1789 while (wlen > 4) { 1790 /* FIXME: check for big-endian */ 1791 data = swab32(*(u32 *)wbuf); 1792 wbuf += 4; 1793 wlen -= 4; 1794 ddbwritel(data, SPI_DATA); 1795 while (safe_ddbreadl(dev, SPI_CONTROL) & 0x0004) 1796 ; 1797 } 1798 1799 if (rlen) 1800 ddbwritel(0x0001 | ((wlen << (8 + 3)) & 0x1f00), SPI_CONTROL); 1801 else 1802 ddbwritel(0x0003 | ((wlen << (8 + 3)) & 0x1f00), SPI_CONTROL); 1803 1804 data = 0; 1805 shift = ((4 - wlen) * 8); 1806 while (wlen) { 1807 data <<= 8; 1808 data |= *wbuf; 1809 wlen--; 1810 wbuf++; 1811 } 1812 if (shift) 1813 data <<= shift; 1814 ddbwritel(data, SPI_DATA); 1815 while (safe_ddbreadl(dev, SPI_CONTROL) & 0x0004) 1816 ; 1817 1818 if (!rlen) { 1819 ddbwritel(0, SPI_CONTROL); 1820 return 0; 1821 } 1822 if (rlen > 4) 1823 ddbwritel(1, SPI_CONTROL); 1824 1825 while (rlen > 4) { 1826 ddbwritel(0xffffffff, SPI_DATA); 1827 while (safe_ddbreadl(dev, SPI_CONTROL) & 0x0004) 1828 ; 1829 data = ddbreadl(SPI_DATA); 1830 *(u32 *) rbuf = swab32(data); 1831 rbuf += 4; 1832 rlen -= 4; 1833 } 1834 ddbwritel(0x0003 | ((rlen << (8 + 3)) & 0x1F00), SPI_CONTROL); 1835 ddbwritel(0xffffffff, SPI_DATA); 1836 while (safe_ddbreadl(dev, SPI_CONTROL) & 0x0004) 1837 ; 1838 1839 data = ddbreadl(SPI_DATA); 1840 ddbwritel(0, SPI_CONTROL); 1841 1842 if (rlen < 4) 1843 data <<= ((4 - rlen) * 8); 1844 1845 while (rlen > 0) { 1846 *rbuf = ((data >> 24) & 0xff); 1847 data <<= 8; 1848 rbuf++; 1849 rlen--; 1850 } 1851 return 0; 1852 } 1853 1854 #define DDB_MAGIC 'd' 1855 1856 struct ddb_flashio { 1857 __user __u8 *write_buf; 1858 __u32 write_len; 1859 __user __u8 *read_buf; 1860 __u32 read_len; 1861 }; 1862 1863 #define IOCTL_DDB_FLASHIO _IOWR(DDB_MAGIC, 0x00, struct ddb_flashio) 1864 1865 #define DDB_NAME "ddbridge" 1866 1867 static u32 ddb_num; 1868 static struct ddb *ddbs[32]; 1869 static struct class *ddb_class; 1870 static int ddb_major; 1871 1872 static int ddb_open(struct inode *inode, struct file *file) 1873 { 1874 struct ddb *dev = ddbs[iminor(inode)]; 1875 1876 file->private_data = dev; 1877 return 0; 1878 } 1879 1880 static long ddb_ioctl(struct file *file, unsigned int cmd, unsigned long arg) 1881 { 1882 struct ddb *dev = file->private_data; 1883 __user void *parg = (__user void *)arg; 1884 int res; 1885 1886 switch (cmd) { 1887 case IOCTL_DDB_FLASHIO: 1888 { 1889 struct ddb_flashio fio; 1890 u8 *rbuf, *wbuf; 1891 1892 if (copy_from_user(&fio, parg, sizeof(fio))) 1893 return -EFAULT; 1894 1895 if (fio.write_len > 1028 || fio.read_len > 1028) 1896 return -EINVAL; 1897 if (fio.write_len + fio.read_len > 1028) 1898 return -EINVAL; 1899 1900 wbuf = &dev->iobuf[0]; 1901 rbuf = wbuf + fio.write_len; 1902 1903 if (copy_from_user(wbuf, fio.write_buf, fio.write_len)) 1904 return -EFAULT; 1905 res = flashio(dev, wbuf, fio.write_len, rbuf, fio.read_len); 1906 if (res) 1907 return res; 1908 if (copy_to_user(fio.read_buf, rbuf, fio.read_len)) 1909 return -EFAULT; 1910 break; 1911 } 1912 default: 1913 return -ENOTTY; 1914 } 1915 return 0; 1916 } 1917 1918 static const struct file_operations ddb_fops = { 1919 .unlocked_ioctl = ddb_ioctl, 1920 .open = ddb_open, 1921 }; 1922 1923 static char *ddb_devnode(struct device *device, umode_t *mode) 1924 { 1925 struct ddb *dev = dev_get_drvdata(device); 1926 1927 return kasprintf(GFP_KERNEL, "ddbridge/card%d", dev->nr); 1928 } 1929 1930 static int ddb_class_create(void) 1931 { 1932 ddb_major = register_chrdev(0, DDB_NAME, &ddb_fops); 1933 if (ddb_major < 0) 1934 return ddb_major; 1935 1936 ddb_class = class_create(THIS_MODULE, DDB_NAME); 1937 if (IS_ERR(ddb_class)) { 1938 unregister_chrdev(ddb_major, DDB_NAME); 1939 return PTR_ERR(ddb_class); 1940 } 1941 ddb_class->devnode = ddb_devnode; 1942 return 0; 1943 } 1944 1945 static void ddb_class_destroy(void) 1946 { 1947 class_destroy(ddb_class); 1948 unregister_chrdev(ddb_major, DDB_NAME); 1949 } 1950 1951 static int ddb_device_create(struct ddb *dev) 1952 { 1953 dev->nr = ddb_num++; 1954 dev->ddb_dev = device_create(ddb_class, NULL, 1955 MKDEV(ddb_major, dev->nr), 1956 dev, "ddbridge%d", dev->nr); 1957 ddbs[dev->nr] = dev; 1958 if (IS_ERR(dev->ddb_dev)) 1959 return -1; 1960 return 0; 1961 } 1962 1963 static void ddb_device_destroy(struct ddb *dev) 1964 { 1965 ddb_num--; 1966 if (IS_ERR(dev->ddb_dev)) 1967 return; 1968 device_destroy(ddb_class, MKDEV(ddb_major, 0)); 1969 } 1970 1971 1972 /****************************************************************************/ 1973 /****************************************************************************/ 1974 /****************************************************************************/ 1975 1976 static void ddb_unmap(struct ddb *dev) 1977 { 1978 if (dev->regs) 1979 iounmap(dev->regs); 1980 vfree(dev); 1981 } 1982 1983 1984 static void ddb_remove(struct pci_dev *pdev) 1985 { 1986 struct ddb *dev = pci_get_drvdata(pdev); 1987 1988 ddb_ports_detach(dev); 1989 ddb_i2c_release(dev); 1990 1991 ddbwritel(0, INTERRUPT_ENABLE); 1992 free_irq(dev->pdev->irq, dev); 1993 #ifdef CONFIG_PCI_MSI 1994 if (dev->msi) 1995 pci_disable_msi(dev->pdev); 1996 #endif 1997 ddb_ports_release(dev); 1998 ddb_buffers_free(dev); 1999 ddb_device_destroy(dev); 2000 2001 ddb_unmap(dev); 2002 pci_set_drvdata(pdev, NULL); 2003 pci_disable_device(pdev); 2004 } 2005 2006 2007 static int ddb_probe(struct pci_dev *pdev, const struct pci_device_id *id) 2008 { 2009 struct ddb *dev; 2010 int stat = 0; 2011 int irq_flag = IRQF_SHARED; 2012 2013 if (pci_enable_device(pdev) < 0) 2014 return -ENODEV; 2015 2016 dev = vzalloc(sizeof(struct ddb)); 2017 if (dev == NULL) 2018 return -ENOMEM; 2019 2020 dev->pdev = pdev; 2021 pci_set_drvdata(pdev, dev); 2022 dev->info = (struct ddb_info *) id->driver_data; 2023 dev_info(&pdev->dev, "Detected %s\n", dev->info->name); 2024 2025 dev->regs = ioremap(pci_resource_start(dev->pdev, 0), 2026 pci_resource_len(dev->pdev, 0)); 2027 if (!dev->regs) { 2028 stat = -ENOMEM; 2029 goto fail; 2030 } 2031 dev_info(&pdev->dev, "HW %08x FW %08x\n", ddbreadl(0), ddbreadl(4)); 2032 2033 #ifdef CONFIG_PCI_MSI 2034 if (pci_msi_enabled()) 2035 stat = pci_enable_msi(dev->pdev); 2036 if (stat) { 2037 dev_info(&pdev->dev, "MSI not available.\n"); 2038 } else { 2039 irq_flag = 0; 2040 dev->msi = 1; 2041 } 2042 #endif 2043 stat = request_irq(dev->pdev->irq, irq_handler, 2044 irq_flag, "DDBridge", (void *) dev); 2045 if (stat < 0) 2046 goto fail1; 2047 ddbwritel(0, DMA_BASE_WRITE); 2048 ddbwritel(0, DMA_BASE_READ); 2049 ddbwritel(0xffffffff, INTERRUPT_ACK); 2050 ddbwritel(0xfff0f, INTERRUPT_ENABLE); 2051 ddbwritel(0, MSI1_ENABLE); 2052 2053 /* board control */ 2054 if (dev->info->board_control) { 2055 ddbwritel(0, DDB_LINK_TAG(0) | BOARD_CONTROL); 2056 msleep(100); 2057 ddbwritel(dev->info->board_control_2, 2058 DDB_LINK_TAG(0) | BOARD_CONTROL); 2059 usleep_range(2000, 3000); 2060 ddbwritel(dev->info->board_control_2 2061 | dev->info->board_control, 2062 DDB_LINK_TAG(0) | BOARD_CONTROL); 2063 usleep_range(2000, 3000); 2064 } 2065 2066 if (ddb_i2c_init(dev) < 0) 2067 goto fail1; 2068 ddb_ports_init(dev); 2069 if (ddb_buffers_alloc(dev) < 0) { 2070 dev_err(&pdev->dev, "Could not allocate buffer memory\n"); 2071 goto fail2; 2072 } 2073 if (ddb_ports_attach(dev) < 0) 2074 goto fail3; 2075 ddb_device_create(dev); 2076 return 0; 2077 2078 fail3: 2079 ddb_ports_detach(dev); 2080 dev_err(&pdev->dev, "fail3\n"); 2081 ddb_ports_release(dev); 2082 fail2: 2083 dev_err(&pdev->dev, "fail2\n"); 2084 ddb_buffers_free(dev); 2085 fail1: 2086 dev_err(&pdev->dev, "fail1\n"); 2087 if (dev->msi) 2088 pci_disable_msi(dev->pdev); 2089 if (stat == 0) 2090 free_irq(dev->pdev->irq, dev); 2091 fail: 2092 dev_err(&pdev->dev, "fail\n"); 2093 ddb_unmap(dev); 2094 pci_set_drvdata(pdev, NULL); 2095 pci_disable_device(pdev); 2096 return -1; 2097 } 2098 2099 /******************************************************************************/ 2100 /******************************************************************************/ 2101 /******************************************************************************/ 2102 2103 static const struct ddb_info ddb_none = { 2104 .type = DDB_NONE, 2105 .name = "Digital Devices PCIe bridge", 2106 }; 2107 2108 static const struct ddb_info ddb_octopus = { 2109 .type = DDB_OCTOPUS, 2110 .name = "Digital Devices Octopus DVB adapter", 2111 .port_num = 4, 2112 }; 2113 2114 static const struct ddb_info ddb_octopus_le = { 2115 .type = DDB_OCTOPUS, 2116 .name = "Digital Devices Octopus LE DVB adapter", 2117 .port_num = 2, 2118 }; 2119 2120 static const struct ddb_info ddb_octopus_oem = { 2121 .type = DDB_OCTOPUS, 2122 .name = "Digital Devices Octopus OEM", 2123 .port_num = 4, 2124 }; 2125 2126 static const struct ddb_info ddb_octopus_mini = { 2127 .type = DDB_OCTOPUS, 2128 .name = "Digital Devices Octopus Mini", 2129 .port_num = 4, 2130 }; 2131 2132 static const struct ddb_info ddb_v6 = { 2133 .type = DDB_OCTOPUS, 2134 .name = "Digital Devices Cine S2 V6 DVB adapter", 2135 .port_num = 3, 2136 }; 2137 static const struct ddb_info ddb_v6_5 = { 2138 .type = DDB_OCTOPUS, 2139 .name = "Digital Devices Cine S2 V6.5 DVB adapter", 2140 .port_num = 4, 2141 }; 2142 2143 static const struct ddb_info ddb_dvbct = { 2144 .type = DDB_OCTOPUS, 2145 .name = "Digital Devices DVBCT V6.1 DVB adapter", 2146 .port_num = 3, 2147 }; 2148 2149 static const struct ddb_info ddb_ctv7 = { 2150 .type = DDB_OCTOPUS, 2151 .name = "Digital Devices Cine CT V7 DVB adapter", 2152 .port_num = 4, 2153 .board_control = 3, 2154 .board_control_2 = 4, 2155 }; 2156 2157 static const struct ddb_info ddb_satixS2v3 = { 2158 .type = DDB_OCTOPUS, 2159 .name = "Mystique SaTiX-S2 V3 DVB adapter", 2160 .port_num = 3, 2161 }; 2162 2163 static const struct ddb_info ddb_octopusv3 = { 2164 .type = DDB_OCTOPUS, 2165 .name = "Digital Devices Octopus V3 DVB adapter", 2166 .port_num = 4, 2167 }; 2168 2169 /*** MaxA8 adapters ***********************************************************/ 2170 2171 static struct ddb_info ddb_ct2_8 = { 2172 .type = DDB_OCTOPUS_MAX_CT, 2173 .name = "Digital Devices MAX A8 CT2", 2174 .port_num = 4, 2175 .board_control = 0x0ff, 2176 .board_control_2 = 0xf00, 2177 .ts_quirks = TS_QUIRK_SERIAL, 2178 }; 2179 2180 static struct ddb_info ddb_c2t2_8 = { 2181 .type = DDB_OCTOPUS_MAX_CT, 2182 .name = "Digital Devices MAX A8 C2T2", 2183 .port_num = 4, 2184 .board_control = 0x0ff, 2185 .board_control_2 = 0xf00, 2186 .ts_quirks = TS_QUIRK_SERIAL, 2187 }; 2188 2189 static struct ddb_info ddb_isdbt_8 = { 2190 .type = DDB_OCTOPUS_MAX_CT, 2191 .name = "Digital Devices MAX A8 ISDBT", 2192 .port_num = 4, 2193 .board_control = 0x0ff, 2194 .board_control_2 = 0xf00, 2195 .ts_quirks = TS_QUIRK_SERIAL, 2196 }; 2197 2198 static struct ddb_info ddb_c2t2i_v0_8 = { 2199 .type = DDB_OCTOPUS_MAX_CT, 2200 .name = "Digital Devices MAX A8 C2T2I V0", 2201 .port_num = 4, 2202 .board_control = 0x0ff, 2203 .board_control_2 = 0xf00, 2204 .ts_quirks = TS_QUIRK_SERIAL | TS_QUIRK_ALT_OSC, 2205 }; 2206 2207 static struct ddb_info ddb_c2t2i_8 = { 2208 .type = DDB_OCTOPUS_MAX_CT, 2209 .name = "Digital Devices MAX A8 C2T2I", 2210 .port_num = 4, 2211 .board_control = 0x0ff, 2212 .board_control_2 = 0xf00, 2213 .ts_quirks = TS_QUIRK_SERIAL, 2214 }; 2215 2216 /******************************************************************************/ 2217 2218 #define DDVID 0xdd01 /* Digital Devices Vendor ID */ 2219 2220 #define DDB_ID(_vend, _dev, _subvend, _subdev, _driverdata) { \ 2221 .vendor = _vend, .device = _dev, \ 2222 .subvendor = _subvend, .subdevice = _subdev, \ 2223 .driver_data = (unsigned long)&_driverdata } 2224 2225 static const struct pci_device_id ddb_id_tbl[] = { 2226 DDB_ID(DDVID, 0x0002, DDVID, 0x0001, ddb_octopus), 2227 DDB_ID(DDVID, 0x0003, DDVID, 0x0001, ddb_octopus), 2228 DDB_ID(DDVID, 0x0005, DDVID, 0x0004, ddb_octopusv3), 2229 DDB_ID(DDVID, 0x0003, DDVID, 0x0002, ddb_octopus_le), 2230 DDB_ID(DDVID, 0x0003, DDVID, 0x0003, ddb_octopus_oem), 2231 DDB_ID(DDVID, 0x0003, DDVID, 0x0010, ddb_octopus_mini), 2232 DDB_ID(DDVID, 0x0005, DDVID, 0x0011, ddb_octopus_mini), 2233 DDB_ID(DDVID, 0x0003, DDVID, 0x0020, ddb_v6), 2234 DDB_ID(DDVID, 0x0003, DDVID, 0x0021, ddb_v6_5), 2235 DDB_ID(DDVID, 0x0003, DDVID, 0x0030, ddb_dvbct), 2236 DDB_ID(DDVID, 0x0003, DDVID, 0xdb03, ddb_satixS2v3), 2237 DDB_ID(DDVID, 0x0006, DDVID, 0x0031, ddb_ctv7), 2238 DDB_ID(DDVID, 0x0006, DDVID, 0x0032, ddb_ctv7), 2239 DDB_ID(DDVID, 0x0006, DDVID, 0x0033, ddb_ctv7), 2240 DDB_ID(DDVID, 0x0008, DDVID, 0x0034, ddb_ct2_8), 2241 DDB_ID(DDVID, 0x0008, DDVID, 0x0035, ddb_c2t2_8), 2242 DDB_ID(DDVID, 0x0008, DDVID, 0x0036, ddb_isdbt_8), 2243 DDB_ID(DDVID, 0x0008, DDVID, 0x0037, ddb_c2t2i_v0_8), 2244 DDB_ID(DDVID, 0x0008, DDVID, 0x0038, ddb_c2t2i_8), 2245 DDB_ID(DDVID, 0x0006, DDVID, 0x0039, ddb_ctv7), 2246 /* in case sub-ids got deleted in flash */ 2247 DDB_ID(DDVID, 0x0003, PCI_ANY_ID, PCI_ANY_ID, ddb_none), 2248 DDB_ID(DDVID, 0x0005, PCI_ANY_ID, PCI_ANY_ID, ddb_none), 2249 DDB_ID(DDVID, 0x0006, PCI_ANY_ID, PCI_ANY_ID, ddb_none), 2250 DDB_ID(DDVID, 0x0007, PCI_ANY_ID, PCI_ANY_ID, ddb_none), 2251 DDB_ID(DDVID, 0x0008, PCI_ANY_ID, PCI_ANY_ID, ddb_none), 2252 DDB_ID(DDVID, 0x0011, PCI_ANY_ID, PCI_ANY_ID, ddb_none), 2253 DDB_ID(DDVID, 0x0013, PCI_ANY_ID, PCI_ANY_ID, ddb_none), 2254 DDB_ID(DDVID, 0x0201, PCI_ANY_ID, PCI_ANY_ID, ddb_none), 2255 DDB_ID(DDVID, 0x0320, PCI_ANY_ID, PCI_ANY_ID, ddb_none), 2256 {0} 2257 }; 2258 MODULE_DEVICE_TABLE(pci, ddb_id_tbl); 2259 2260 2261 static struct pci_driver ddb_pci_driver = { 2262 .name = "DDBridge", 2263 .id_table = ddb_id_tbl, 2264 .probe = ddb_probe, 2265 .remove = ddb_remove, 2266 }; 2267 2268 static __init int module_init_ddbridge(void) 2269 { 2270 int ret; 2271 2272 pr_info("Digital Devices PCIE bridge driver, Copyright (C) 2010-11 Digital Devices GmbH\n"); 2273 2274 ret = ddb_class_create(); 2275 if (ret < 0) 2276 return ret; 2277 ret = pci_register_driver(&ddb_pci_driver); 2278 if (ret < 0) 2279 ddb_class_destroy(); 2280 return ret; 2281 } 2282 2283 static __exit void module_exit_ddbridge(void) 2284 { 2285 pci_unregister_driver(&ddb_pci_driver); 2286 ddb_class_destroy(); 2287 } 2288 2289 module_init(module_init_ddbridge); 2290 module_exit(module_exit_ddbridge); 2291 2292 MODULE_DESCRIPTION("Digital Devices PCIe Bridge"); 2293 MODULE_AUTHOR("Ralph Metzler"); 2294 MODULE_LICENSE("GPL"); 2295 MODULE_VERSION("0.5"); 2296