1 /* 2 * ddbridge.c: Digital Devices PCIe bridge driver 3 * 4 * Copyright (C) 2010-2011 Digital Devices GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * version 2 only, as published by the Free Software Foundation. 9 * 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * To obtain the license, point your browser to 17 * http://www.gnu.org/copyleft/gpl.html 18 */ 19 20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 21 22 #include <linux/module.h> 23 #include <linux/init.h> 24 #include <linux/interrupt.h> 25 #include <linux/delay.h> 26 #include <linux/slab.h> 27 #include <linux/poll.h> 28 #include <linux/io.h> 29 #include <linux/pci.h> 30 #include <linux/pci_ids.h> 31 #include <linux/timer.h> 32 #include <linux/i2c.h> 33 #include <linux/swab.h> 34 #include <linux/vmalloc.h> 35 #include "ddbridge.h" 36 37 #include "ddbridge-regs.h" 38 39 #include "tda18271c2dd.h" 40 #include "stv6110x.h" 41 #include "stv090x.h" 42 #include "lnbh24.h" 43 #include "drxk.h" 44 #include "stv0367.h" 45 #include "stv0367_priv.h" 46 #include "cxd2841er.h" 47 #include "tda18212.h" 48 49 static int xo2_speed = 2; 50 module_param(xo2_speed, int, 0444); 51 MODULE_PARM_DESC(xo2_speed, "default transfer speed for xo2 based duoflex, 0=55,1=75,2=90,3=104 MBit/s, default=2, use attribute to change for individual cards"); 52 53 DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr); 54 55 /* MSI had problems with lost interrupts, fixed but needs testing */ 56 #undef CONFIG_PCI_MSI 57 58 /******************************************************************************/ 59 60 static int i2c_io(struct i2c_adapter *adapter, u8 adr, 61 u8 *wbuf, u32 wlen, u8 *rbuf, u32 rlen) 62 { 63 struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0, 64 .buf = wbuf, .len = wlen }, 65 {.addr = adr, .flags = I2C_M_RD, 66 .buf = rbuf, .len = rlen } }; 67 return (i2c_transfer(adapter, msgs, 2) == 2) ? 0 : -1; 68 } 69 70 static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len) 71 { 72 struct i2c_msg msg = {.addr = adr, .flags = 0, 73 .buf = data, .len = len}; 74 75 return (i2c_transfer(adap, &msg, 1) == 1) ? 0 : -1; 76 } 77 78 static int i2c_read(struct i2c_adapter *adapter, u8 adr, u8 *val) 79 { 80 struct i2c_msg msgs[1] = {{.addr = adr, .flags = I2C_M_RD, 81 .buf = val, .len = 1 } }; 82 return (i2c_transfer(adapter, msgs, 1) == 1) ? 0 : -1; 83 } 84 85 static int i2c_read_regs(struct i2c_adapter *adapter, 86 u8 adr, u8 reg, u8 *val, u8 len) 87 { 88 struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0, 89 .buf = ®, .len = 1 }, 90 {.addr = adr, .flags = I2C_M_RD, 91 .buf = val, .len = len } }; 92 return (i2c_transfer(adapter, msgs, 2) == 2) ? 0 : -1; 93 } 94 95 static int i2c_read_reg(struct i2c_adapter *adapter, u8 adr, u8 reg, u8 *val) 96 { 97 return i2c_read_regs(adapter, adr, reg, val, 1); 98 } 99 100 static int i2c_read_reg16(struct i2c_adapter *adapter, u8 adr, 101 u16 reg, u8 *val) 102 { 103 u8 msg[2] = {reg>>8, reg&0xff}; 104 struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0, 105 .buf = msg, .len = 2}, 106 {.addr = adr, .flags = I2C_M_RD, 107 .buf = val, .len = 1} }; 108 return (i2c_transfer(adapter, msgs, 2) == 2) ? 0 : -1; 109 } 110 111 static int i2c_write_reg(struct i2c_adapter *adap, u8 adr, 112 u8 reg, u8 val) 113 { 114 u8 msg[2] = {reg, val}; 115 116 return i2c_write(adap, adr, msg, 2); 117 } 118 119 static inline u32 safe_ddbreadl(struct ddb *dev, u32 adr) 120 { 121 u32 val = ddbreadl(adr); 122 123 /* (ddb)readl returns (uint)-1 (all bits set) on failure, catch that */ 124 if (val == ~0) { 125 dev_err(&dev->pdev->dev, "ddbreadl failure, adr=%08x\n", adr); 126 return 0; 127 } 128 129 return val; 130 } 131 132 static int ddb_i2c_cmd(struct ddb_i2c *i2c, u32 adr, u32 cmd) 133 { 134 struct ddb *dev = i2c->dev; 135 long stat; 136 u32 val; 137 138 i2c->done = 0; 139 ddbwritel((adr << 9) | cmd, i2c->regs + I2C_COMMAND); 140 stat = wait_event_timeout(i2c->wq, i2c->done == 1, HZ); 141 if (stat == 0) { 142 dev_err(&dev->pdev->dev, "I2C timeout\n"); 143 { /* MSI debugging*/ 144 u32 istat = ddbreadl(INTERRUPT_STATUS); 145 dev_err(&dev->pdev->dev, "IRS %08x\n", istat); 146 ddbwritel(istat, INTERRUPT_ACK); 147 } 148 return -EIO; 149 } 150 val = ddbreadl(i2c->regs+I2C_COMMAND); 151 if (val & 0x70000) 152 return -EIO; 153 return 0; 154 } 155 156 static int ddb_i2c_master_xfer(struct i2c_adapter *adapter, 157 struct i2c_msg msg[], int num) 158 { 159 struct ddb_i2c *i2c = (struct ddb_i2c *)i2c_get_adapdata(adapter); 160 struct ddb *dev = i2c->dev; 161 u8 addr = 0; 162 163 if (num) 164 addr = msg[0].addr; 165 166 if (num == 2 && msg[1].flags & I2C_M_RD && 167 !(msg[0].flags & I2C_M_RD)) { 168 memcpy_toio(dev->regs + I2C_TASKMEM_BASE + i2c->wbuf, 169 msg[0].buf, msg[0].len); 170 ddbwritel(msg[0].len|(msg[1].len << 16), 171 i2c->regs+I2C_TASKLENGTH); 172 if (!ddb_i2c_cmd(i2c, addr, 1)) { 173 memcpy_fromio(msg[1].buf, 174 dev->regs + I2C_TASKMEM_BASE + i2c->rbuf, 175 msg[1].len); 176 return num; 177 } 178 } 179 180 if (num == 1 && !(msg[0].flags & I2C_M_RD)) { 181 ddbcpyto(I2C_TASKMEM_BASE + i2c->wbuf, msg[0].buf, msg[0].len); 182 ddbwritel(msg[0].len, i2c->regs + I2C_TASKLENGTH); 183 if (!ddb_i2c_cmd(i2c, addr, 2)) 184 return num; 185 } 186 if (num == 1 && (msg[0].flags & I2C_M_RD)) { 187 ddbwritel(msg[0].len << 16, i2c->regs + I2C_TASKLENGTH); 188 if (!ddb_i2c_cmd(i2c, addr, 3)) { 189 ddbcpyfrom(msg[0].buf, 190 I2C_TASKMEM_BASE + i2c->rbuf, msg[0].len); 191 return num; 192 } 193 } 194 return -EIO; 195 } 196 197 198 static u32 ddb_i2c_functionality(struct i2c_adapter *adap) 199 { 200 return I2C_FUNC_SMBUS_EMUL; 201 } 202 203 static struct i2c_algorithm ddb_i2c_algo = { 204 .master_xfer = ddb_i2c_master_xfer, 205 .functionality = ddb_i2c_functionality, 206 }; 207 208 static void ddb_i2c_release(struct ddb *dev) 209 { 210 int i; 211 struct ddb_i2c *i2c; 212 struct i2c_adapter *adap; 213 214 for (i = 0; i < dev->info->port_num; i++) { 215 i2c = &dev->i2c[i]; 216 adap = &i2c->adap; 217 i2c_del_adapter(adap); 218 } 219 } 220 221 static int ddb_i2c_init(struct ddb *dev) 222 { 223 int i, j, stat = 0; 224 struct ddb_i2c *i2c; 225 struct i2c_adapter *adap; 226 227 for (i = 0; i < dev->info->port_num; i++) { 228 i2c = &dev->i2c[i]; 229 i2c->dev = dev; 230 i2c->nr = i; 231 i2c->wbuf = i * (I2C_TASKMEM_SIZE / 4); 232 i2c->rbuf = i2c->wbuf + (I2C_TASKMEM_SIZE / 8); 233 i2c->regs = 0x80 + i * 0x20; 234 ddbwritel(I2C_SPEED_100, i2c->regs + I2C_TIMING); 235 ddbwritel((i2c->rbuf << 16) | i2c->wbuf, 236 i2c->regs + I2C_TASKADDRESS); 237 init_waitqueue_head(&i2c->wq); 238 239 adap = &i2c->adap; 240 i2c_set_adapdata(adap, i2c); 241 #ifdef I2C_ADAP_CLASS_TV_DIGITAL 242 adap->class = I2C_ADAP_CLASS_TV_DIGITAL|I2C_CLASS_TV_ANALOG; 243 #else 244 #ifdef I2C_CLASS_TV_ANALOG 245 adap->class = I2C_CLASS_TV_ANALOG; 246 #endif 247 #endif 248 strcpy(adap->name, "ddbridge"); 249 adap->algo = &ddb_i2c_algo; 250 adap->algo_data = (void *)i2c; 251 adap->dev.parent = &dev->pdev->dev; 252 stat = i2c_add_adapter(adap); 253 if (stat) 254 break; 255 } 256 if (stat) 257 for (j = 0; j < i; j++) { 258 i2c = &dev->i2c[j]; 259 adap = &i2c->adap; 260 i2c_del_adapter(adap); 261 } 262 return stat; 263 } 264 265 266 /******************************************************************************/ 267 /******************************************************************************/ 268 /******************************************************************************/ 269 270 #if 0 271 static void set_table(struct ddb *dev, u32 off, 272 dma_addr_t *pbuf, u32 num) 273 { 274 u32 i, base; 275 u64 mem; 276 277 base = DMA_BASE_ADDRESS_TABLE + off; 278 for (i = 0; i < num; i++) { 279 mem = pbuf[i]; 280 ddbwritel(mem & 0xffffffff, base + i * 8); 281 ddbwritel(mem >> 32, base + i * 8 + 4); 282 } 283 } 284 #endif 285 286 static void ddb_address_table(struct ddb *dev) 287 { 288 u32 i, j, base; 289 u64 mem; 290 dma_addr_t *pbuf; 291 292 for (i = 0; i < dev->info->port_num * 2; i++) { 293 base = DMA_BASE_ADDRESS_TABLE + i * 0x100; 294 pbuf = dev->input[i].pbuf; 295 for (j = 0; j < dev->input[i].dma_buf_num; j++) { 296 mem = pbuf[j]; 297 ddbwritel(mem & 0xffffffff, base + j * 8); 298 ddbwritel(mem >> 32, base + j * 8 + 4); 299 } 300 } 301 for (i = 0; i < dev->info->port_num; i++) { 302 base = DMA_BASE_ADDRESS_TABLE + 0x800 + i * 0x100; 303 pbuf = dev->output[i].pbuf; 304 for (j = 0; j < dev->output[i].dma_buf_num; j++) { 305 mem = pbuf[j]; 306 ddbwritel(mem & 0xffffffff, base + j * 8); 307 ddbwritel(mem >> 32, base + j * 8 + 4); 308 } 309 } 310 } 311 312 static void io_free(struct pci_dev *pdev, u8 **vbuf, 313 dma_addr_t *pbuf, u32 size, int num) 314 { 315 int i; 316 317 for (i = 0; i < num; i++) { 318 if (vbuf[i]) { 319 pci_free_consistent(pdev, size, vbuf[i], pbuf[i]); 320 vbuf[i] = NULL; 321 } 322 } 323 } 324 325 static int io_alloc(struct pci_dev *pdev, u8 **vbuf, 326 dma_addr_t *pbuf, u32 size, int num) 327 { 328 int i; 329 330 for (i = 0; i < num; i++) { 331 vbuf[i] = pci_alloc_consistent(pdev, size, &pbuf[i]); 332 if (!vbuf[i]) 333 return -ENOMEM; 334 } 335 return 0; 336 } 337 338 static int ddb_buffers_alloc(struct ddb *dev) 339 { 340 int i; 341 struct ddb_port *port; 342 343 for (i = 0; i < dev->info->port_num; i++) { 344 port = &dev->port[i]; 345 switch (port->class) { 346 case DDB_PORT_TUNER: 347 if (io_alloc(dev->pdev, port->input[0]->vbuf, 348 port->input[0]->pbuf, 349 port->input[0]->dma_buf_size, 350 port->input[0]->dma_buf_num) < 0) 351 return -1; 352 if (io_alloc(dev->pdev, port->input[1]->vbuf, 353 port->input[1]->pbuf, 354 port->input[1]->dma_buf_size, 355 port->input[1]->dma_buf_num) < 0) 356 return -1; 357 break; 358 case DDB_PORT_CI: 359 if (io_alloc(dev->pdev, port->input[0]->vbuf, 360 port->input[0]->pbuf, 361 port->input[0]->dma_buf_size, 362 port->input[0]->dma_buf_num) < 0) 363 return -1; 364 if (io_alloc(dev->pdev, port->output->vbuf, 365 port->output->pbuf, 366 port->output->dma_buf_size, 367 port->output->dma_buf_num) < 0) 368 return -1; 369 break; 370 default: 371 break; 372 } 373 } 374 ddb_address_table(dev); 375 return 0; 376 } 377 378 static void ddb_buffers_free(struct ddb *dev) 379 { 380 int i; 381 struct ddb_port *port; 382 383 for (i = 0; i < dev->info->port_num; i++) { 384 port = &dev->port[i]; 385 io_free(dev->pdev, port->input[0]->vbuf, 386 port->input[0]->pbuf, 387 port->input[0]->dma_buf_size, 388 port->input[0]->dma_buf_num); 389 io_free(dev->pdev, port->input[1]->vbuf, 390 port->input[1]->pbuf, 391 port->input[1]->dma_buf_size, 392 port->input[1]->dma_buf_num); 393 io_free(dev->pdev, port->output->vbuf, 394 port->output->pbuf, 395 port->output->dma_buf_size, 396 port->output->dma_buf_num); 397 } 398 } 399 400 static void ddb_input_start(struct ddb_input *input) 401 { 402 struct ddb *dev = input->port->dev; 403 404 spin_lock_irq(&input->lock); 405 input->cbuf = 0; 406 input->coff = 0; 407 408 /* reset */ 409 ddbwritel(0, TS_INPUT_CONTROL(input->nr)); 410 ddbwritel(2, TS_INPUT_CONTROL(input->nr)); 411 ddbwritel(0, TS_INPUT_CONTROL(input->nr)); 412 413 ddbwritel((1 << 16) | 414 (input->dma_buf_num << 11) | 415 (input->dma_buf_size >> 7), 416 DMA_BUFFER_SIZE(input->nr)); 417 ddbwritel(0, DMA_BUFFER_ACK(input->nr)); 418 419 ddbwritel(1, DMA_BASE_WRITE); 420 ddbwritel(3, DMA_BUFFER_CONTROL(input->nr)); 421 ddbwritel(9, TS_INPUT_CONTROL(input->nr)); 422 input->running = 1; 423 spin_unlock_irq(&input->lock); 424 } 425 426 static void ddb_input_stop(struct ddb_input *input) 427 { 428 struct ddb *dev = input->port->dev; 429 430 spin_lock_irq(&input->lock); 431 ddbwritel(0, TS_INPUT_CONTROL(input->nr)); 432 ddbwritel(0, DMA_BUFFER_CONTROL(input->nr)); 433 input->running = 0; 434 spin_unlock_irq(&input->lock); 435 } 436 437 static void ddb_output_start(struct ddb_output *output) 438 { 439 struct ddb *dev = output->port->dev; 440 441 spin_lock_irq(&output->lock); 442 output->cbuf = 0; 443 output->coff = 0; 444 ddbwritel(0, TS_OUTPUT_CONTROL(output->nr)); 445 ddbwritel(2, TS_OUTPUT_CONTROL(output->nr)); 446 ddbwritel(0, TS_OUTPUT_CONTROL(output->nr)); 447 ddbwritel(0x3c, TS_OUTPUT_CONTROL(output->nr)); 448 ddbwritel((1 << 16) | 449 (output->dma_buf_num << 11) | 450 (output->dma_buf_size >> 7), 451 DMA_BUFFER_SIZE(output->nr + 8)); 452 ddbwritel(0, DMA_BUFFER_ACK(output->nr + 8)); 453 454 ddbwritel(1, DMA_BASE_READ); 455 ddbwritel(3, DMA_BUFFER_CONTROL(output->nr + 8)); 456 /* ddbwritel(0xbd, TS_OUTPUT_CONTROL(output->nr)); */ 457 ddbwritel(0x1d, TS_OUTPUT_CONTROL(output->nr)); 458 output->running = 1; 459 spin_unlock_irq(&output->lock); 460 } 461 462 static void ddb_output_stop(struct ddb_output *output) 463 { 464 struct ddb *dev = output->port->dev; 465 466 spin_lock_irq(&output->lock); 467 ddbwritel(0, TS_OUTPUT_CONTROL(output->nr)); 468 ddbwritel(0, DMA_BUFFER_CONTROL(output->nr + 8)); 469 output->running = 0; 470 spin_unlock_irq(&output->lock); 471 } 472 473 static u32 ddb_output_free(struct ddb_output *output) 474 { 475 u32 idx, off, stat = output->stat; 476 s32 diff; 477 478 idx = (stat >> 11) & 0x1f; 479 off = (stat & 0x7ff) << 7; 480 481 if (output->cbuf != idx) { 482 if ((((output->cbuf + 1) % output->dma_buf_num) == idx) && 483 (output->dma_buf_size - output->coff <= 188)) 484 return 0; 485 return 188; 486 } 487 diff = off - output->coff; 488 if (diff <= 0 || diff > 188) 489 return 188; 490 return 0; 491 } 492 493 static ssize_t ddb_output_write(struct ddb_output *output, 494 const __user u8 *buf, size_t count) 495 { 496 struct ddb *dev = output->port->dev; 497 u32 idx, off, stat = output->stat; 498 u32 left = count, len; 499 500 idx = (stat >> 11) & 0x1f; 501 off = (stat & 0x7ff) << 7; 502 503 while (left) { 504 len = output->dma_buf_size - output->coff; 505 if ((((output->cbuf + 1) % output->dma_buf_num) == idx) && 506 (off == 0)) { 507 if (len <= 188) 508 break; 509 len -= 188; 510 } 511 if (output->cbuf == idx) { 512 if (off > output->coff) { 513 #if 1 514 len = off - output->coff; 515 len -= (len % 188); 516 if (len <= 188) 517 518 #endif 519 break; 520 len -= 188; 521 } 522 } 523 if (len > left) 524 len = left; 525 if (copy_from_user(output->vbuf[output->cbuf] + output->coff, 526 buf, len)) 527 return -EIO; 528 left -= len; 529 buf += len; 530 output->coff += len; 531 if (output->coff == output->dma_buf_size) { 532 output->coff = 0; 533 output->cbuf = ((output->cbuf + 1) % output->dma_buf_num); 534 } 535 ddbwritel((output->cbuf << 11) | (output->coff >> 7), 536 DMA_BUFFER_ACK(output->nr + 8)); 537 } 538 return count - left; 539 } 540 541 static u32 ddb_input_avail(struct ddb_input *input) 542 { 543 struct ddb *dev = input->port->dev; 544 u32 idx, off, stat = input->stat; 545 u32 ctrl = ddbreadl(DMA_BUFFER_CONTROL(input->nr)); 546 547 idx = (stat >> 11) & 0x1f; 548 off = (stat & 0x7ff) << 7; 549 550 if (ctrl & 4) { 551 dev_err(&dev->pdev->dev, "IA %d %d %08x\n", idx, off, ctrl); 552 ddbwritel(input->stat, DMA_BUFFER_ACK(input->nr)); 553 return 0; 554 } 555 if (input->cbuf != idx) 556 return 188; 557 return 0; 558 } 559 560 static ssize_t ddb_input_read(struct ddb_input *input, __user u8 *buf, size_t count) 561 { 562 struct ddb *dev = input->port->dev; 563 u32 left = count; 564 u32 idx, free, stat = input->stat; 565 int ret; 566 567 idx = (stat >> 11) & 0x1f; 568 569 while (left) { 570 if (input->cbuf == idx) 571 return count - left; 572 free = input->dma_buf_size - input->coff; 573 if (free > left) 574 free = left; 575 ret = copy_to_user(buf, input->vbuf[input->cbuf] + 576 input->coff, free); 577 if (ret) 578 return -EFAULT; 579 input->coff += free; 580 if (input->coff == input->dma_buf_size) { 581 input->coff = 0; 582 input->cbuf = (input->cbuf+1) % input->dma_buf_num; 583 } 584 left -= free; 585 ddbwritel((input->cbuf << 11) | (input->coff >> 7), 586 DMA_BUFFER_ACK(input->nr)); 587 } 588 return count; 589 } 590 591 /******************************************************************************/ 592 /******************************************************************************/ 593 /******************************************************************************/ 594 595 #if 0 596 static struct ddb_input *fe2input(struct ddb *dev, struct dvb_frontend *fe) 597 { 598 int i; 599 600 for (i = 0; i < dev->info->port_num * 2; i++) { 601 if (dev->input[i].fe == fe) 602 return &dev->input[i]; 603 } 604 return NULL; 605 } 606 #endif 607 608 static int drxk_gate_ctrl(struct dvb_frontend *fe, int enable) 609 { 610 struct ddb_input *input = fe->sec_priv; 611 struct ddb_port *port = input->port; 612 int status; 613 614 if (enable) { 615 mutex_lock(&port->i2c_gate_lock); 616 status = input->gate_ctrl(fe, 1); 617 } else { 618 status = input->gate_ctrl(fe, 0); 619 mutex_unlock(&port->i2c_gate_lock); 620 } 621 return status; 622 } 623 624 static int demod_attach_drxk(struct ddb_input *input) 625 { 626 struct i2c_adapter *i2c = &input->port->i2c->adap; 627 struct dvb_frontend *fe; 628 struct drxk_config config; 629 struct device *dev = &input->port->dev->pdev->dev; 630 631 memset(&config, 0, sizeof(config)); 632 config.microcode_name = "drxk_a3.mc"; 633 config.qam_demod_parameter_count = 4; 634 config.adr = 0x29 + (input->nr & 1); 635 636 fe = input->fe = dvb_attach(drxk_attach, &config, i2c); 637 if (!input->fe) { 638 dev_err(dev, "No DRXK found!\n"); 639 return -ENODEV; 640 } 641 fe->sec_priv = input; 642 input->gate_ctrl = fe->ops.i2c_gate_ctrl; 643 fe->ops.i2c_gate_ctrl = drxk_gate_ctrl; 644 return 0; 645 } 646 647 static int tuner_attach_tda18271(struct ddb_input *input) 648 { 649 struct i2c_adapter *i2c = &input->port->i2c->adap; 650 struct dvb_frontend *fe; 651 struct device *dev = &input->port->dev->pdev->dev; 652 653 if (input->fe->ops.i2c_gate_ctrl) 654 input->fe->ops.i2c_gate_ctrl(input->fe, 1); 655 fe = dvb_attach(tda18271c2dd_attach, input->fe, i2c, 0x60); 656 if (!fe) { 657 dev_err(dev, "No TDA18271 found!\n"); 658 return -ENODEV; 659 } 660 if (input->fe->ops.i2c_gate_ctrl) 661 input->fe->ops.i2c_gate_ctrl(input->fe, 0); 662 return 0; 663 } 664 665 /******************************************************************************/ 666 /******************************************************************************/ 667 /******************************************************************************/ 668 669 static struct stv0367_config ddb_stv0367_config[] = { 670 { 671 .demod_address = 0x1f, 672 .xtal = 27000000, 673 .if_khz = 0, 674 .if_iq_mode = FE_TER_NORMAL_IF_TUNER, 675 .ts_mode = STV0367_SERIAL_PUNCT_CLOCK, 676 .clk_pol = STV0367_CLOCKPOLARITY_DEFAULT, 677 }, { 678 .demod_address = 0x1e, 679 .xtal = 27000000, 680 .if_khz = 0, 681 .if_iq_mode = FE_TER_NORMAL_IF_TUNER, 682 .ts_mode = STV0367_SERIAL_PUNCT_CLOCK, 683 .clk_pol = STV0367_CLOCKPOLARITY_DEFAULT, 684 }, 685 }; 686 687 static int demod_attach_stv0367(struct ddb_input *input) 688 { 689 struct i2c_adapter *i2c = &input->port->i2c->adap; 690 struct device *dev = &input->port->dev->pdev->dev; 691 692 /* attach frontend */ 693 input->fe = dvb_attach(stv0367ddb_attach, 694 &ddb_stv0367_config[(input->nr & 1)], i2c); 695 696 if (!input->fe) { 697 dev_err(dev, "stv0367ddb_attach failed (not found?)\n"); 698 return -ENODEV; 699 } 700 701 input->fe->sec_priv = input; 702 input->gate_ctrl = input->fe->ops.i2c_gate_ctrl; 703 input->fe->ops.i2c_gate_ctrl = drxk_gate_ctrl; 704 705 return 0; 706 } 707 708 static int tuner_tda18212_ping(struct ddb_input *input, unsigned short adr) 709 { 710 struct i2c_adapter *adapter = &input->port->i2c->adap; 711 struct device *dev = &input->port->dev->pdev->dev; 712 713 u8 tda_id[2]; 714 u8 subaddr = 0x00; 715 716 dev_dbg(dev, "stv0367-tda18212 tuner ping\n"); 717 if (input->fe->ops.i2c_gate_ctrl) 718 input->fe->ops.i2c_gate_ctrl(input->fe, 1); 719 720 if (i2c_read_regs(adapter, adr, subaddr, tda_id, sizeof(tda_id)) < 0) 721 dev_dbg(dev, "tda18212 ping 1 fail\n"); 722 if (i2c_read_regs(adapter, adr, subaddr, tda_id, sizeof(tda_id)) < 0) 723 dev_warn(dev, "tda18212 ping failed, expect problems\n"); 724 725 if (input->fe->ops.i2c_gate_ctrl) 726 input->fe->ops.i2c_gate_ctrl(input->fe, 0); 727 728 return 0; 729 } 730 731 static int demod_attach_cxd28xx(struct ddb_input *input, int par, int osc24) 732 { 733 struct i2c_adapter *i2c = &input->port->i2c->adap; 734 struct device *dev = &input->port->dev->pdev->dev; 735 struct cxd2841er_config cfg; 736 737 /* the cxd2841er driver expects 8bit/shifted I2C addresses */ 738 cfg.i2c_addr = ((input->nr & 1) ? 0x6d : 0x6c) << 1; 739 740 cfg.xtal = osc24 ? SONY_XTAL_24000 : SONY_XTAL_20500; 741 cfg.flags = CXD2841ER_AUTO_IFHZ | CXD2841ER_EARLY_TUNE | 742 CXD2841ER_NO_WAIT_LOCK | CXD2841ER_NO_AGCNEG | 743 CXD2841ER_TSBITS; 744 745 if (!par) 746 cfg.flags |= CXD2841ER_TS_SERIAL; 747 748 /* attach frontend */ 749 input->fe = dvb_attach(cxd2841er_attach_t_c, &cfg, i2c); 750 751 if (!input->fe) { 752 dev_err(dev, "No Sony CXD28xx found!\n"); 753 return -ENODEV; 754 } 755 756 input->fe->sec_priv = input; 757 input->gate_ctrl = input->fe->ops.i2c_gate_ctrl; 758 input->fe->ops.i2c_gate_ctrl = drxk_gate_ctrl; 759 760 return 0; 761 } 762 763 static int tuner_attach_tda18212(struct ddb_input *input, u32 porttype) 764 { 765 struct i2c_adapter *adapter = &input->port->i2c->adap; 766 struct device *dev = &input->port->dev->pdev->dev; 767 struct i2c_client *client; 768 struct tda18212_config config = { 769 .fe = input->fe, 770 .if_dvbt_6 = 3550, 771 .if_dvbt_7 = 3700, 772 .if_dvbt_8 = 4150, 773 .if_dvbt2_6 = 3250, 774 .if_dvbt2_7 = 4000, 775 .if_dvbt2_8 = 4000, 776 .if_dvbc = 5000, 777 }; 778 struct i2c_board_info board_info = { 779 .type = "tda18212", 780 .platform_data = &config, 781 }; 782 783 if (input->nr & 1) 784 board_info.addr = 0x63; 785 else 786 board_info.addr = 0x60; 787 788 /* due to a hardware quirk with the I2C gate on the stv0367+tda18212 789 * combo, the tda18212 must be probed by reading it's id _twice_ when 790 * cold started, or it very likely will fail. 791 */ 792 if (porttype == DDB_TUNER_DVBCT_ST) 793 tuner_tda18212_ping(input, board_info.addr); 794 795 request_module(board_info.type); 796 797 /* perform tuner init/attach */ 798 client = i2c_new_device(adapter, &board_info); 799 if (client == NULL || client->dev.driver == NULL) 800 goto err; 801 802 if (!try_module_get(client->dev.driver->owner)) { 803 i2c_unregister_device(client); 804 goto err; 805 } 806 807 input->i2c_client[0] = client; 808 809 return 0; 810 err: 811 dev_warn(dev, "TDA18212 tuner not found. Device is not fully operational.\n"); 812 return -ENODEV; 813 } 814 815 /******************************************************************************/ 816 /******************************************************************************/ 817 /******************************************************************************/ 818 819 static struct stv090x_config stv0900 = { 820 .device = STV0900, 821 .demod_mode = STV090x_DUAL, 822 .clk_mode = STV090x_CLK_EXT, 823 824 .xtal = 27000000, 825 .address = 0x69, 826 827 .ts1_mode = STV090x_TSMODE_SERIAL_PUNCTURED, 828 .ts2_mode = STV090x_TSMODE_SERIAL_PUNCTURED, 829 830 .repeater_level = STV090x_RPTLEVEL_16, 831 832 .adc1_range = STV090x_ADC_1Vpp, 833 .adc2_range = STV090x_ADC_1Vpp, 834 835 .diseqc_envelope_mode = true, 836 }; 837 838 static struct stv090x_config stv0900_aa = { 839 .device = STV0900, 840 .demod_mode = STV090x_DUAL, 841 .clk_mode = STV090x_CLK_EXT, 842 843 .xtal = 27000000, 844 .address = 0x68, 845 846 .ts1_mode = STV090x_TSMODE_SERIAL_PUNCTURED, 847 .ts2_mode = STV090x_TSMODE_SERIAL_PUNCTURED, 848 849 .repeater_level = STV090x_RPTLEVEL_16, 850 851 .adc1_range = STV090x_ADC_1Vpp, 852 .adc2_range = STV090x_ADC_1Vpp, 853 854 .diseqc_envelope_mode = true, 855 }; 856 857 static struct stv6110x_config stv6110a = { 858 .addr = 0x60, 859 .refclk = 27000000, 860 .clk_div = 1, 861 }; 862 863 static struct stv6110x_config stv6110b = { 864 .addr = 0x63, 865 .refclk = 27000000, 866 .clk_div = 1, 867 }; 868 869 static int demod_attach_stv0900(struct ddb_input *input, int type) 870 { 871 struct i2c_adapter *i2c = &input->port->i2c->adap; 872 struct device *dev = &input->port->dev->pdev->dev; 873 struct stv090x_config *feconf = type ? &stv0900_aa : &stv0900; 874 875 input->fe = dvb_attach(stv090x_attach, feconf, i2c, 876 (input->nr & 1) ? STV090x_DEMODULATOR_1 877 : STV090x_DEMODULATOR_0); 878 if (!input->fe) { 879 dev_err(dev, "No STV0900 found!\n"); 880 return -ENODEV; 881 } 882 if (!dvb_attach(lnbh24_attach, input->fe, i2c, 0, 883 0, (input->nr & 1) ? 884 (0x09 - type) : (0x0b - type))) { 885 dev_err(dev, "No LNBH24 found!\n"); 886 return -ENODEV; 887 } 888 return 0; 889 } 890 891 static int tuner_attach_stv6110(struct ddb_input *input, int type) 892 { 893 struct i2c_adapter *i2c = &input->port->i2c->adap; 894 struct device *dev = &input->port->dev->pdev->dev; 895 struct stv090x_config *feconf = type ? &stv0900_aa : &stv0900; 896 struct stv6110x_config *tunerconf = (input->nr & 1) ? 897 &stv6110b : &stv6110a; 898 const struct stv6110x_devctl *ctl; 899 900 ctl = dvb_attach(stv6110x_attach, input->fe, tunerconf, i2c); 901 if (!ctl) { 902 dev_err(dev, "No STV6110X found!\n"); 903 return -ENODEV; 904 } 905 dev_info(dev, "attach tuner input %d adr %02x\n", 906 input->nr, tunerconf->addr); 907 908 feconf->tuner_init = ctl->tuner_init; 909 feconf->tuner_sleep = ctl->tuner_sleep; 910 feconf->tuner_set_mode = ctl->tuner_set_mode; 911 feconf->tuner_set_frequency = ctl->tuner_set_frequency; 912 feconf->tuner_get_frequency = ctl->tuner_get_frequency; 913 feconf->tuner_set_bandwidth = ctl->tuner_set_bandwidth; 914 feconf->tuner_get_bandwidth = ctl->tuner_get_bandwidth; 915 feconf->tuner_set_bbgain = ctl->tuner_set_bbgain; 916 feconf->tuner_get_bbgain = ctl->tuner_get_bbgain; 917 feconf->tuner_set_refclk = ctl->tuner_set_refclk; 918 feconf->tuner_get_status = ctl->tuner_get_status; 919 920 return 0; 921 } 922 923 static int my_dvb_dmx_ts_card_init(struct dvb_demux *dvbdemux, char *id, 924 int (*start_feed)(struct dvb_demux_feed *), 925 int (*stop_feed)(struct dvb_demux_feed *), 926 void *priv) 927 { 928 dvbdemux->priv = priv; 929 930 dvbdemux->filternum = 256; 931 dvbdemux->feednum = 256; 932 dvbdemux->start_feed = start_feed; 933 dvbdemux->stop_feed = stop_feed; 934 dvbdemux->write_to_decoder = NULL; 935 dvbdemux->dmx.capabilities = (DMX_TS_FILTERING | 936 DMX_SECTION_FILTERING | 937 DMX_MEMORY_BASED_FILTERING); 938 return dvb_dmx_init(dvbdemux); 939 } 940 941 static int my_dvb_dmxdev_ts_card_init(struct dmxdev *dmxdev, 942 struct dvb_demux *dvbdemux, 943 struct dmx_frontend *hw_frontend, 944 struct dmx_frontend *mem_frontend, 945 struct dvb_adapter *dvb_adapter) 946 { 947 int ret; 948 949 dmxdev->filternum = 256; 950 dmxdev->demux = &dvbdemux->dmx; 951 dmxdev->capabilities = 0; 952 ret = dvb_dmxdev_init(dmxdev, dvb_adapter); 953 if (ret < 0) 954 return ret; 955 956 hw_frontend->source = DMX_FRONTEND_0; 957 dvbdemux->dmx.add_frontend(&dvbdemux->dmx, hw_frontend); 958 mem_frontend->source = DMX_MEMORY_FE; 959 dvbdemux->dmx.add_frontend(&dvbdemux->dmx, mem_frontend); 960 return dvbdemux->dmx.connect_frontend(&dvbdemux->dmx, hw_frontend); 961 } 962 963 static int start_feed(struct dvb_demux_feed *dvbdmxfeed) 964 { 965 struct dvb_demux *dvbdmx = dvbdmxfeed->demux; 966 struct ddb_input *input = dvbdmx->priv; 967 968 if (!input->users) 969 ddb_input_start(input); 970 971 return ++input->users; 972 } 973 974 static int stop_feed(struct dvb_demux_feed *dvbdmxfeed) 975 { 976 struct dvb_demux *dvbdmx = dvbdmxfeed->demux; 977 struct ddb_input *input = dvbdmx->priv; 978 979 if (--input->users) 980 return input->users; 981 982 ddb_input_stop(input); 983 return 0; 984 } 985 986 987 static void dvb_input_detach(struct ddb_input *input) 988 { 989 struct dvb_adapter *adap = &input->adap; 990 struct dvb_demux *dvbdemux = &input->demux; 991 struct i2c_client *client; 992 993 switch (input->attached) { 994 case 5: 995 client = input->i2c_client[0]; 996 if (client) { 997 module_put(client->dev.driver->owner); 998 i2c_unregister_device(client); 999 } 1000 if (input->fe2) { 1001 dvb_unregister_frontend(input->fe2); 1002 input->fe2 = NULL; 1003 } 1004 if (input->fe) { 1005 dvb_unregister_frontend(input->fe); 1006 dvb_frontend_detach(input->fe); 1007 input->fe = NULL; 1008 } 1009 /* fall-through */ 1010 case 4: 1011 dvb_net_release(&input->dvbnet); 1012 /* fall-through */ 1013 case 3: 1014 dvbdemux->dmx.close(&dvbdemux->dmx); 1015 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, 1016 &input->hw_frontend); 1017 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, 1018 &input->mem_frontend); 1019 dvb_dmxdev_release(&input->dmxdev); 1020 /* fall-through */ 1021 case 2: 1022 dvb_dmx_release(&input->demux); 1023 /* fall-through */ 1024 case 1: 1025 dvb_unregister_adapter(adap); 1026 } 1027 input->attached = 0; 1028 } 1029 1030 static int dvb_input_attach(struct ddb_input *input) 1031 { 1032 int ret; 1033 struct ddb_port *port = input->port; 1034 struct dvb_adapter *adap = &input->adap; 1035 struct dvb_demux *dvbdemux = &input->demux; 1036 struct device *dev = &input->port->dev->pdev->dev; 1037 int sony_osc24 = 0, sony_tspar = 0; 1038 1039 ret = dvb_register_adapter(adap, "DDBridge", THIS_MODULE, 1040 &input->port->dev->pdev->dev, 1041 adapter_nr); 1042 if (ret < 0) { 1043 dev_err(dev, "Could not register adapter. Check if you enabled enough adapters in dvb-core!\n"); 1044 return ret; 1045 } 1046 input->attached = 1; 1047 1048 ret = my_dvb_dmx_ts_card_init(dvbdemux, "SW demux", 1049 start_feed, 1050 stop_feed, input); 1051 if (ret < 0) 1052 return ret; 1053 input->attached = 2; 1054 1055 ret = my_dvb_dmxdev_ts_card_init(&input->dmxdev, &input->demux, 1056 &input->hw_frontend, 1057 &input->mem_frontend, adap); 1058 if (ret < 0) 1059 return ret; 1060 input->attached = 3; 1061 1062 ret = dvb_net_init(adap, &input->dvbnet, input->dmxdev.demux); 1063 if (ret < 0) 1064 return ret; 1065 input->attached = 4; 1066 1067 input->fe = NULL; 1068 switch (port->type) { 1069 case DDB_TUNER_DVBS_ST: 1070 if (demod_attach_stv0900(input, 0) < 0) 1071 return -ENODEV; 1072 if (tuner_attach_stv6110(input, 0) < 0) 1073 return -ENODEV; 1074 if (input->fe) { 1075 if (dvb_register_frontend(adap, input->fe) < 0) 1076 return -ENODEV; 1077 } 1078 break; 1079 case DDB_TUNER_DVBS_ST_AA: 1080 if (demod_attach_stv0900(input, 1) < 0) 1081 return -ENODEV; 1082 if (tuner_attach_stv6110(input, 1) < 0) 1083 return -ENODEV; 1084 if (input->fe) { 1085 if (dvb_register_frontend(adap, input->fe) < 0) 1086 return -ENODEV; 1087 } 1088 break; 1089 case DDB_TUNER_DVBCT_TR: 1090 if (demod_attach_drxk(input) < 0) 1091 return -ENODEV; 1092 if (tuner_attach_tda18271(input) < 0) 1093 return -ENODEV; 1094 if (dvb_register_frontend(adap, input->fe) < 0) 1095 return -ENODEV; 1096 if (input->fe2) { 1097 if (dvb_register_frontend(adap, input->fe2) < 0) 1098 return -ENODEV; 1099 input->fe2->tuner_priv = input->fe->tuner_priv; 1100 memcpy(&input->fe2->ops.tuner_ops, 1101 &input->fe->ops.tuner_ops, 1102 sizeof(struct dvb_tuner_ops)); 1103 } 1104 break; 1105 case DDB_TUNER_DVBCT_ST: 1106 if (demod_attach_stv0367(input) < 0) 1107 return -ENODEV; 1108 if (tuner_attach_tda18212(input, port->type) < 0) 1109 return -ENODEV; 1110 if (input->fe) { 1111 if (dvb_register_frontend(adap, input->fe) < 0) 1112 return -ENODEV; 1113 } 1114 break; 1115 case DDB_TUNER_DVBC2T2I_SONY_P: 1116 case DDB_TUNER_DVBCT2_SONY_P: 1117 case DDB_TUNER_DVBC2T2_SONY_P: 1118 case DDB_TUNER_ISDBT_SONY_P: 1119 if (port->type == DDB_TUNER_DVBC2T2I_SONY_P) 1120 sony_osc24 = 1; 1121 if (input->port->dev->info->ts_quirks & TS_QUIRK_ALT_OSC) 1122 sony_osc24 = 0; 1123 if (input->port->dev->info->ts_quirks & TS_QUIRK_SERIAL) 1124 sony_tspar = 0; 1125 else 1126 sony_tspar = 1; 1127 1128 if (demod_attach_cxd28xx(input, sony_tspar, sony_osc24) < 0) 1129 return -ENODEV; 1130 if (tuner_attach_tda18212(input, port->type) < 0) 1131 return -ENODEV; 1132 if (input->fe) { 1133 if (dvb_register_frontend(adap, input->fe) < 0) 1134 return -ENODEV; 1135 } 1136 break; 1137 case DDB_TUNER_XO2_DVBC2T2I_SONY: 1138 case DDB_TUNER_XO2_DVBCT2_SONY: 1139 case DDB_TUNER_XO2_DVBC2T2_SONY: 1140 case DDB_TUNER_XO2_ISDBT_SONY: 1141 if (port->type == DDB_TUNER_XO2_DVBC2T2I_SONY) 1142 sony_osc24 = 1; 1143 1144 if (demod_attach_cxd28xx(input, 0, sony_osc24) < 0) 1145 return -ENODEV; 1146 if (tuner_attach_tda18212(input, port->type) < 0) 1147 return -ENODEV; 1148 if (input->fe) { 1149 if (dvb_register_frontend(adap, input->fe) < 0) 1150 return -ENODEV; 1151 } 1152 break; 1153 } 1154 1155 input->attached = 5; 1156 return 0; 1157 } 1158 1159 /****************************************************************************/ 1160 /****************************************************************************/ 1161 1162 static ssize_t ts_write(struct file *file, const __user char *buf, 1163 size_t count, loff_t *ppos) 1164 { 1165 struct dvb_device *dvbdev = file->private_data; 1166 struct ddb_output *output = dvbdev->priv; 1167 size_t left = count; 1168 int stat; 1169 1170 while (left) { 1171 if (ddb_output_free(output) < 188) { 1172 if (file->f_flags & O_NONBLOCK) 1173 break; 1174 if (wait_event_interruptible( 1175 output->wq, ddb_output_free(output) >= 188) < 0) 1176 break; 1177 } 1178 stat = ddb_output_write(output, buf, left); 1179 if (stat < 0) 1180 break; 1181 buf += stat; 1182 left -= stat; 1183 } 1184 return (left == count) ? -EAGAIN : (count - left); 1185 } 1186 1187 static ssize_t ts_read(struct file *file, __user char *buf, 1188 size_t count, loff_t *ppos) 1189 { 1190 struct dvb_device *dvbdev = file->private_data; 1191 struct ddb_output *output = dvbdev->priv; 1192 struct ddb_input *input = output->port->input[0]; 1193 int left, read; 1194 1195 count -= count % 188; 1196 left = count; 1197 while (left) { 1198 if (ddb_input_avail(input) < 188) { 1199 if (file->f_flags & O_NONBLOCK) 1200 break; 1201 if (wait_event_interruptible( 1202 input->wq, ddb_input_avail(input) >= 188) < 0) 1203 break; 1204 } 1205 read = ddb_input_read(input, buf, left); 1206 if (read < 0) 1207 return read; 1208 left -= read; 1209 buf += read; 1210 } 1211 return (left == count) ? -EAGAIN : (count - left); 1212 } 1213 1214 static unsigned int ts_poll(struct file *file, poll_table *wait) 1215 { 1216 /* 1217 struct dvb_device *dvbdev = file->private_data; 1218 struct ddb_output *output = dvbdev->priv; 1219 struct ddb_input *input = output->port->input[0]; 1220 */ 1221 unsigned int mask = 0; 1222 1223 #if 0 1224 if (data_avail_to_read) 1225 mask |= POLLIN | POLLRDNORM; 1226 if (data_avail_to_write) 1227 mask |= POLLOUT | POLLWRNORM; 1228 1229 poll_wait(file, &read_queue, wait); 1230 poll_wait(file, &write_queue, wait); 1231 #endif 1232 return mask; 1233 } 1234 1235 static const struct file_operations ci_fops = { 1236 .owner = THIS_MODULE, 1237 .read = ts_read, 1238 .write = ts_write, 1239 .open = dvb_generic_open, 1240 .release = dvb_generic_release, 1241 .poll = ts_poll, 1242 }; 1243 1244 static struct dvb_device dvbdev_ci = { 1245 .readers = -1, 1246 .writers = -1, 1247 .users = -1, 1248 .fops = &ci_fops, 1249 }; 1250 1251 /****************************************************************************/ 1252 /****************************************************************************/ 1253 /****************************************************************************/ 1254 1255 static void input_tasklet(unsigned long data) 1256 { 1257 struct ddb_input *input = (struct ddb_input *) data; 1258 struct ddb *dev = input->port->dev; 1259 1260 spin_lock(&input->lock); 1261 if (!input->running) { 1262 spin_unlock(&input->lock); 1263 return; 1264 } 1265 input->stat = ddbreadl(DMA_BUFFER_CURRENT(input->nr)); 1266 1267 if (input->port->class == DDB_PORT_TUNER) { 1268 if (4&ddbreadl(DMA_BUFFER_CONTROL(input->nr))) 1269 dev_err(&dev->pdev->dev, "Overflow input %d\n", input->nr); 1270 while (input->cbuf != ((input->stat >> 11) & 0x1f) 1271 || (4 & safe_ddbreadl(dev, DMA_BUFFER_CONTROL(input->nr)))) { 1272 dvb_dmx_swfilter_packets(&input->demux, 1273 input->vbuf[input->cbuf], 1274 input->dma_buf_size / 188); 1275 1276 input->cbuf = (input->cbuf + 1) % input->dma_buf_num; 1277 ddbwritel((input->cbuf << 11), 1278 DMA_BUFFER_ACK(input->nr)); 1279 input->stat = ddbreadl(DMA_BUFFER_CURRENT(input->nr)); 1280 } 1281 } 1282 if (input->port->class == DDB_PORT_CI) 1283 wake_up(&input->wq); 1284 spin_unlock(&input->lock); 1285 } 1286 1287 static void output_tasklet(unsigned long data) 1288 { 1289 struct ddb_output *output = (struct ddb_output *) data; 1290 struct ddb *dev = output->port->dev; 1291 1292 spin_lock(&output->lock); 1293 if (!output->running) { 1294 spin_unlock(&output->lock); 1295 return; 1296 } 1297 output->stat = ddbreadl(DMA_BUFFER_CURRENT(output->nr + 8)); 1298 wake_up(&output->wq); 1299 spin_unlock(&output->lock); 1300 } 1301 1302 1303 static struct cxd2099_cfg cxd_cfg = { 1304 .bitrate = 62000, 1305 .adr = 0x40, 1306 .polarity = 1, 1307 .clock_mode = 1, 1308 .max_i2c = 512, 1309 }; 1310 1311 static int ddb_ci_attach(struct ddb_port *port) 1312 { 1313 int ret; 1314 1315 ret = dvb_register_adapter(&port->output->adap, 1316 "DDBridge", 1317 THIS_MODULE, 1318 &port->dev->pdev->dev, 1319 adapter_nr); 1320 if (ret < 0) 1321 return ret; 1322 port->en = cxd2099_attach(&cxd_cfg, port, &port->i2c->adap); 1323 if (!port->en) { 1324 dvb_unregister_adapter(&port->output->adap); 1325 return -ENODEV; 1326 } 1327 ddb_input_start(port->input[0]); 1328 ddb_output_start(port->output); 1329 dvb_ca_en50221_init(&port->output->adap, 1330 port->en, 0, 1); 1331 ret = dvb_register_device(&port->output->adap, &port->output->dev, 1332 &dvbdev_ci, (void *) port->output, 1333 DVB_DEVICE_SEC, 0); 1334 return ret; 1335 } 1336 1337 static int ddb_port_attach(struct ddb_port *port) 1338 { 1339 struct device *dev = &port->dev->pdev->dev; 1340 int ret = 0; 1341 1342 switch (port->class) { 1343 case DDB_PORT_TUNER: 1344 ret = dvb_input_attach(port->input[0]); 1345 if (ret < 0) 1346 break; 1347 ret = dvb_input_attach(port->input[1]); 1348 break; 1349 case DDB_PORT_CI: 1350 ret = ddb_ci_attach(port); 1351 break; 1352 default: 1353 break; 1354 } 1355 if (ret < 0) 1356 dev_err(dev, "port_attach on port %d failed\n", port->nr); 1357 return ret; 1358 } 1359 1360 static int ddb_ports_attach(struct ddb *dev) 1361 { 1362 int i, ret = 0; 1363 struct ddb_port *port; 1364 1365 for (i = 0; i < dev->info->port_num; i++) { 1366 port = &dev->port[i]; 1367 ret = ddb_port_attach(port); 1368 if (ret < 0) 1369 break; 1370 } 1371 return ret; 1372 } 1373 1374 static void ddb_ports_detach(struct ddb *dev) 1375 { 1376 int i; 1377 struct ddb_port *port; 1378 1379 for (i = 0; i < dev->info->port_num; i++) { 1380 port = &dev->port[i]; 1381 switch (port->class) { 1382 case DDB_PORT_TUNER: 1383 dvb_input_detach(port->input[0]); 1384 dvb_input_detach(port->input[1]); 1385 break; 1386 case DDB_PORT_CI: 1387 dvb_unregister_device(port->output->dev); 1388 if (port->en) { 1389 ddb_input_stop(port->input[0]); 1390 ddb_output_stop(port->output); 1391 dvb_ca_en50221_release(port->en); 1392 kfree(port->en); 1393 port->en = NULL; 1394 dvb_unregister_adapter(&port->output->adap); 1395 } 1396 break; 1397 } 1398 } 1399 } 1400 1401 /****************************************************************************/ 1402 /****************************************************************************/ 1403 1404 static int init_xo2(struct ddb_port *port) 1405 { 1406 struct i2c_adapter *i2c = &port->i2c->adap; 1407 struct device *dev = &port->dev->pdev->dev; 1408 u8 val, data[2]; 1409 int res; 1410 1411 res = i2c_read_regs(i2c, 0x10, 0x04, data, 2); 1412 if (res < 0) 1413 return res; 1414 1415 if (data[0] != 0x01) { 1416 dev_info(dev, "Port %d: invalid XO2\n", port->nr); 1417 return -1; 1418 } 1419 1420 i2c_read_reg(i2c, 0x10, 0x08, &val); 1421 if (val != 0) { 1422 i2c_write_reg(i2c, 0x10, 0x08, 0x00); 1423 msleep(100); 1424 } 1425 /* Enable tuner power, disable pll, reset demods */ 1426 i2c_write_reg(i2c, 0x10, 0x08, 0x04); 1427 usleep_range(2000, 3000); 1428 /* Release demod resets */ 1429 i2c_write_reg(i2c, 0x10, 0x08, 0x07); 1430 1431 /* speed: 0=55,1=75,2=90,3=104 MBit/s */ 1432 i2c_write_reg(i2c, 0x10, 0x09, 1433 ((xo2_speed >= 0 && xo2_speed <= 3) ? xo2_speed : 2)); 1434 1435 i2c_write_reg(i2c, 0x10, 0x0a, 0x01); 1436 i2c_write_reg(i2c, 0x10, 0x0b, 0x01); 1437 1438 usleep_range(2000, 3000); 1439 /* Start XO2 PLL */ 1440 i2c_write_reg(i2c, 0x10, 0x08, 0x87); 1441 1442 return 0; 1443 } 1444 1445 static int port_has_xo2(struct ddb_port *port, u8 *type, u8 *id) 1446 { 1447 u8 probe[1] = { 0x00 }, data[4]; 1448 1449 *type = DDB_XO2_TYPE_NONE; 1450 1451 if (i2c_io(&port->i2c->adap, 0x10, probe, 1, data, 4)) 1452 return 0; 1453 if (data[0] == 'D' && data[1] == 'F') { 1454 *id = data[2]; 1455 *type = DDB_XO2_TYPE_DUOFLEX; 1456 return 1; 1457 } 1458 if (data[0] == 'C' && data[1] == 'I') { 1459 *id = data[2]; 1460 *type = DDB_XO2_TYPE_CI; 1461 return 1; 1462 } 1463 return 0; 1464 } 1465 1466 /****************************************************************************/ 1467 /****************************************************************************/ 1468 1469 static int port_has_ci(struct ddb_port *port) 1470 { 1471 u8 val; 1472 return i2c_read_reg(&port->i2c->adap, 0x40, 0, &val) ? 0 : 1; 1473 } 1474 1475 static int port_has_stv0900(struct ddb_port *port) 1476 { 1477 u8 val; 1478 if (i2c_read_reg16(&port->i2c->adap, 0x69, 0xf100, &val) < 0) 1479 return 0; 1480 return 1; 1481 } 1482 1483 static int port_has_stv0900_aa(struct ddb_port *port) 1484 { 1485 u8 val; 1486 if (i2c_read_reg16(&port->i2c->adap, 0x68, 0xf100, &val) < 0) 1487 return 0; 1488 return 1; 1489 } 1490 1491 static int port_has_drxks(struct ddb_port *port) 1492 { 1493 u8 val; 1494 if (i2c_read(&port->i2c->adap, 0x29, &val) < 0) 1495 return 0; 1496 if (i2c_read(&port->i2c->adap, 0x2a, &val) < 0) 1497 return 0; 1498 return 1; 1499 } 1500 1501 static int port_has_stv0367(struct ddb_port *port) 1502 { 1503 u8 val; 1504 if (i2c_read_reg16(&port->i2c->adap, 0x1e, 0xf000, &val) < 0) 1505 return 0; 1506 if (val != 0x60) 1507 return 0; 1508 if (i2c_read_reg16(&port->i2c->adap, 0x1f, 0xf000, &val) < 0) 1509 return 0; 1510 if (val != 0x60) 1511 return 0; 1512 return 1; 1513 } 1514 1515 static int port_has_cxd28xx(struct ddb_port *port, u8 *id) 1516 { 1517 struct i2c_adapter *i2c = &port->i2c->adap; 1518 int status; 1519 1520 status = i2c_write_reg(&port->i2c->adap, 0x6e, 0, 0); 1521 if (status) 1522 return 0; 1523 status = i2c_read_reg(i2c, 0x6e, 0xfd, id); 1524 if (status) 1525 return 0; 1526 return 1; 1527 } 1528 1529 static void ddb_port_probe(struct ddb_port *port) 1530 { 1531 struct ddb *dev = port->dev; 1532 char *modname = "NO MODULE"; 1533 u8 xo2_type, xo2_id, cxd_id; 1534 1535 port->class = DDB_PORT_NONE; 1536 1537 if (port_has_ci(port)) { 1538 modname = "CI"; 1539 port->class = DDB_PORT_CI; 1540 ddbwritel(I2C_SPEED_400, port->i2c->regs + I2C_TIMING); 1541 } else if (port_has_xo2(port, &xo2_type, &xo2_id)) { 1542 dev_dbg(&dev->pdev->dev, "Port %d (TAB %d): XO2 type: %d, id: %d\n", 1543 port->nr, port->nr+1, xo2_type, xo2_id); 1544 1545 ddbwritel(I2C_SPEED_400, port->i2c->regs + I2C_TIMING); 1546 1547 switch (xo2_type) { 1548 case DDB_XO2_TYPE_DUOFLEX: 1549 init_xo2(port); 1550 switch (xo2_id >> 2) { 1551 case 0: 1552 modname = "DUAL DVB-S2 (unsupported)"; 1553 port->class = DDB_PORT_NONE; 1554 port->type = DDB_TUNER_XO2_DVBS_STV0910; 1555 break; 1556 case 1: 1557 modname = "DUAL DVB-C/T/T2"; 1558 port->class = DDB_PORT_TUNER; 1559 port->type = DDB_TUNER_XO2_DVBCT2_SONY; 1560 break; 1561 case 2: 1562 modname = "DUAL DVB-ISDBT"; 1563 port->class = DDB_PORT_TUNER; 1564 port->type = DDB_TUNER_XO2_ISDBT_SONY; 1565 break; 1566 case 3: 1567 modname = "DUAL DVB-C/C2/T/T2"; 1568 port->class = DDB_PORT_TUNER; 1569 port->type = DDB_TUNER_XO2_DVBC2T2_SONY; 1570 break; 1571 case 4: 1572 modname = "DUAL ATSC (unsupported)"; 1573 port->class = DDB_PORT_NONE; 1574 port->type = DDB_TUNER_XO2_ATSC_ST; 1575 break; 1576 case 5: 1577 modname = "DUAL DVB-C/C2/T/T2/ISDBT"; 1578 port->class = DDB_PORT_TUNER; 1579 port->type = DDB_TUNER_XO2_DVBC2T2I_SONY; 1580 break; 1581 default: 1582 modname = "Unknown XO2 DuoFlex module\n"; 1583 break; 1584 } 1585 break; 1586 case DDB_XO2_TYPE_CI: 1587 dev_info(&dev->pdev->dev, "DuoFlex CI modules not supported\n"); 1588 break; 1589 default: 1590 dev_info(&dev->pdev->dev, "Unknown XO2 DuoFlex module\n"); 1591 break; 1592 } 1593 } else if (port_has_cxd28xx(port, &cxd_id)) { 1594 switch (cxd_id) { 1595 case 0xa4: 1596 modname = "DUAL DVB-C2T2 CXD2843"; 1597 port->class = DDB_PORT_TUNER; 1598 port->type = DDB_TUNER_DVBC2T2_SONY_P; 1599 break; 1600 case 0xb1: 1601 modname = "DUAL DVB-CT2 CXD2837"; 1602 port->class = DDB_PORT_TUNER; 1603 port->type = DDB_TUNER_DVBCT2_SONY_P; 1604 break; 1605 case 0xb0: 1606 modname = "DUAL ISDB-T CXD2838"; 1607 port->class = DDB_PORT_TUNER; 1608 port->type = DDB_TUNER_ISDBT_SONY_P; 1609 break; 1610 case 0xc1: 1611 modname = "DUAL DVB-C2T2 ISDB-T CXD2854"; 1612 port->class = DDB_PORT_TUNER; 1613 port->type = DDB_TUNER_DVBC2T2I_SONY_P; 1614 break; 1615 default: 1616 modname = "Unknown CXD28xx tuner"; 1617 break; 1618 } 1619 ddbwritel(I2C_SPEED_400, port->i2c->regs + I2C_TIMING); 1620 } else if (port_has_stv0900(port)) { 1621 modname = "DUAL DVB-S2"; 1622 port->class = DDB_PORT_TUNER; 1623 port->type = DDB_TUNER_DVBS_ST; 1624 ddbwritel(I2C_SPEED_100, port->i2c->regs + I2C_TIMING); 1625 } else if (port_has_stv0900_aa(port)) { 1626 modname = "DUAL DVB-S2"; 1627 port->class = DDB_PORT_TUNER; 1628 port->type = DDB_TUNER_DVBS_ST_AA; 1629 ddbwritel(I2C_SPEED_100, port->i2c->regs + I2C_TIMING); 1630 } else if (port_has_drxks(port)) { 1631 modname = "DUAL DVB-C/T"; 1632 port->class = DDB_PORT_TUNER; 1633 port->type = DDB_TUNER_DVBCT_TR; 1634 ddbwritel(I2C_SPEED_400, port->i2c->regs + I2C_TIMING); 1635 } else if (port_has_stv0367(port)) { 1636 modname = "DUAL DVB-C/T"; 1637 port->class = DDB_PORT_TUNER; 1638 port->type = DDB_TUNER_DVBCT_ST; 1639 ddbwritel(I2C_SPEED_100, port->i2c->regs + I2C_TIMING); 1640 } 1641 1642 dev_info(&dev->pdev->dev, "Port %d (TAB %d): %s\n", 1643 port->nr, port->nr+1, modname); 1644 } 1645 1646 static void ddb_input_init(struct ddb_port *port, int nr) 1647 { 1648 struct ddb *dev = port->dev; 1649 struct ddb_input *input = &dev->input[nr]; 1650 1651 input->nr = nr; 1652 input->port = port; 1653 input->dma_buf_num = INPUT_DMA_BUFS; 1654 input->dma_buf_size = INPUT_DMA_SIZE; 1655 ddbwritel(0, TS_INPUT_CONTROL(nr)); 1656 ddbwritel(2, TS_INPUT_CONTROL(nr)); 1657 ddbwritel(0, TS_INPUT_CONTROL(nr)); 1658 ddbwritel(0, DMA_BUFFER_ACK(nr)); 1659 tasklet_init(&input->tasklet, input_tasklet, (unsigned long) input); 1660 spin_lock_init(&input->lock); 1661 init_waitqueue_head(&input->wq); 1662 } 1663 1664 static void ddb_output_init(struct ddb_port *port, int nr) 1665 { 1666 struct ddb *dev = port->dev; 1667 struct ddb_output *output = &dev->output[nr]; 1668 output->nr = nr; 1669 output->port = port; 1670 output->dma_buf_num = OUTPUT_DMA_BUFS; 1671 output->dma_buf_size = OUTPUT_DMA_SIZE; 1672 1673 ddbwritel(0, TS_OUTPUT_CONTROL(nr)); 1674 ddbwritel(2, TS_OUTPUT_CONTROL(nr)); 1675 ddbwritel(0, TS_OUTPUT_CONTROL(nr)); 1676 tasklet_init(&output->tasklet, output_tasklet, (unsigned long) output); 1677 init_waitqueue_head(&output->wq); 1678 } 1679 1680 static void ddb_ports_init(struct ddb *dev) 1681 { 1682 int i; 1683 struct ddb_port *port; 1684 1685 for (i = 0; i < dev->info->port_num; i++) { 1686 port = &dev->port[i]; 1687 port->dev = dev; 1688 port->nr = i; 1689 port->i2c = &dev->i2c[i]; 1690 port->input[0] = &dev->input[2 * i]; 1691 port->input[1] = &dev->input[2 * i + 1]; 1692 port->output = &dev->output[i]; 1693 1694 mutex_init(&port->i2c_gate_lock); 1695 ddb_port_probe(port); 1696 ddb_input_init(port, 2 * i); 1697 ddb_input_init(port, 2 * i + 1); 1698 ddb_output_init(port, i); 1699 } 1700 } 1701 1702 static void ddb_ports_release(struct ddb *dev) 1703 { 1704 int i; 1705 struct ddb_port *port; 1706 1707 for (i = 0; i < dev->info->port_num; i++) { 1708 port = &dev->port[i]; 1709 port->dev = dev; 1710 tasklet_kill(&port->input[0]->tasklet); 1711 tasklet_kill(&port->input[1]->tasklet); 1712 tasklet_kill(&port->output->tasklet); 1713 } 1714 } 1715 1716 /****************************************************************************/ 1717 /****************************************************************************/ 1718 /****************************************************************************/ 1719 1720 static void irq_handle_i2c(struct ddb *dev, int n) 1721 { 1722 struct ddb_i2c *i2c = &dev->i2c[n]; 1723 1724 i2c->done = 1; 1725 wake_up(&i2c->wq); 1726 } 1727 1728 static irqreturn_t irq_handler(int irq, void *dev_id) 1729 { 1730 struct ddb *dev = (struct ddb *) dev_id; 1731 u32 s = ddbreadl(INTERRUPT_STATUS); 1732 1733 if (!s) 1734 return IRQ_NONE; 1735 1736 do { 1737 ddbwritel(s, INTERRUPT_ACK); 1738 1739 if (s & 0x00000001) 1740 irq_handle_i2c(dev, 0); 1741 if (s & 0x00000002) 1742 irq_handle_i2c(dev, 1); 1743 if (s & 0x00000004) 1744 irq_handle_i2c(dev, 2); 1745 if (s & 0x00000008) 1746 irq_handle_i2c(dev, 3); 1747 1748 if (s & 0x00000100) 1749 tasklet_schedule(&dev->input[0].tasklet); 1750 if (s & 0x00000200) 1751 tasklet_schedule(&dev->input[1].tasklet); 1752 if (s & 0x00000400) 1753 tasklet_schedule(&dev->input[2].tasklet); 1754 if (s & 0x00000800) 1755 tasklet_schedule(&dev->input[3].tasklet); 1756 if (s & 0x00001000) 1757 tasklet_schedule(&dev->input[4].tasklet); 1758 if (s & 0x00002000) 1759 tasklet_schedule(&dev->input[5].tasklet); 1760 if (s & 0x00004000) 1761 tasklet_schedule(&dev->input[6].tasklet); 1762 if (s & 0x00008000) 1763 tasklet_schedule(&dev->input[7].tasklet); 1764 1765 if (s & 0x00010000) 1766 tasklet_schedule(&dev->output[0].tasklet); 1767 if (s & 0x00020000) 1768 tasklet_schedule(&dev->output[1].tasklet); 1769 if (s & 0x00040000) 1770 tasklet_schedule(&dev->output[2].tasklet); 1771 if (s & 0x00080000) 1772 tasklet_schedule(&dev->output[3].tasklet); 1773 1774 /* if (s & 0x000f0000) printk(KERN_DEBUG "%08x\n", istat); */ 1775 } while ((s = ddbreadl(INTERRUPT_STATUS))); 1776 1777 return IRQ_HANDLED; 1778 } 1779 1780 /******************************************************************************/ 1781 /******************************************************************************/ 1782 /******************************************************************************/ 1783 1784 static int flashio(struct ddb *dev, u8 *wbuf, u32 wlen, u8 *rbuf, u32 rlen) 1785 { 1786 u32 data, shift; 1787 1788 if (wlen > 4) 1789 ddbwritel(1, SPI_CONTROL); 1790 while (wlen > 4) { 1791 /* FIXME: check for big-endian */ 1792 data = swab32(*(u32 *)wbuf); 1793 wbuf += 4; 1794 wlen -= 4; 1795 ddbwritel(data, SPI_DATA); 1796 while (safe_ddbreadl(dev, SPI_CONTROL) & 0x0004) 1797 ; 1798 } 1799 1800 if (rlen) 1801 ddbwritel(0x0001 | ((wlen << (8 + 3)) & 0x1f00), SPI_CONTROL); 1802 else 1803 ddbwritel(0x0003 | ((wlen << (8 + 3)) & 0x1f00), SPI_CONTROL); 1804 1805 data = 0; 1806 shift = ((4 - wlen) * 8); 1807 while (wlen) { 1808 data <<= 8; 1809 data |= *wbuf; 1810 wlen--; 1811 wbuf++; 1812 } 1813 if (shift) 1814 data <<= shift; 1815 ddbwritel(data, SPI_DATA); 1816 while (safe_ddbreadl(dev, SPI_CONTROL) & 0x0004) 1817 ; 1818 1819 if (!rlen) { 1820 ddbwritel(0, SPI_CONTROL); 1821 return 0; 1822 } 1823 if (rlen > 4) 1824 ddbwritel(1, SPI_CONTROL); 1825 1826 while (rlen > 4) { 1827 ddbwritel(0xffffffff, SPI_DATA); 1828 while (safe_ddbreadl(dev, SPI_CONTROL) & 0x0004) 1829 ; 1830 data = ddbreadl(SPI_DATA); 1831 *(u32 *) rbuf = swab32(data); 1832 rbuf += 4; 1833 rlen -= 4; 1834 } 1835 ddbwritel(0x0003 | ((rlen << (8 + 3)) & 0x1F00), SPI_CONTROL); 1836 ddbwritel(0xffffffff, SPI_DATA); 1837 while (safe_ddbreadl(dev, SPI_CONTROL) & 0x0004) 1838 ; 1839 1840 data = ddbreadl(SPI_DATA); 1841 ddbwritel(0, SPI_CONTROL); 1842 1843 if (rlen < 4) 1844 data <<= ((4 - rlen) * 8); 1845 1846 while (rlen > 0) { 1847 *rbuf = ((data >> 24) & 0xff); 1848 data <<= 8; 1849 rbuf++; 1850 rlen--; 1851 } 1852 return 0; 1853 } 1854 1855 #define DDB_MAGIC 'd' 1856 1857 struct ddb_flashio { 1858 __user __u8 *write_buf; 1859 __u32 write_len; 1860 __user __u8 *read_buf; 1861 __u32 read_len; 1862 }; 1863 1864 #define IOCTL_DDB_FLASHIO _IOWR(DDB_MAGIC, 0x00, struct ddb_flashio) 1865 1866 #define DDB_NAME "ddbridge" 1867 1868 static u32 ddb_num; 1869 static struct ddb *ddbs[32]; 1870 static struct class *ddb_class; 1871 static int ddb_major; 1872 1873 static int ddb_open(struct inode *inode, struct file *file) 1874 { 1875 struct ddb *dev = ddbs[iminor(inode)]; 1876 1877 file->private_data = dev; 1878 return 0; 1879 } 1880 1881 static long ddb_ioctl(struct file *file, unsigned int cmd, unsigned long arg) 1882 { 1883 struct ddb *dev = file->private_data; 1884 __user void *parg = (__user void *)arg; 1885 int res; 1886 1887 switch (cmd) { 1888 case IOCTL_DDB_FLASHIO: 1889 { 1890 struct ddb_flashio fio; 1891 u8 *rbuf, *wbuf; 1892 1893 if (copy_from_user(&fio, parg, sizeof(fio))) 1894 return -EFAULT; 1895 1896 if (fio.write_len > 1028 || fio.read_len > 1028) 1897 return -EINVAL; 1898 if (fio.write_len + fio.read_len > 1028) 1899 return -EINVAL; 1900 1901 wbuf = &dev->iobuf[0]; 1902 rbuf = wbuf + fio.write_len; 1903 1904 if (copy_from_user(wbuf, fio.write_buf, fio.write_len)) 1905 return -EFAULT; 1906 res = flashio(dev, wbuf, fio.write_len, rbuf, fio.read_len); 1907 if (res) 1908 return res; 1909 if (copy_to_user(fio.read_buf, rbuf, fio.read_len)) 1910 return -EFAULT; 1911 break; 1912 } 1913 default: 1914 return -ENOTTY; 1915 } 1916 return 0; 1917 } 1918 1919 static const struct file_operations ddb_fops = { 1920 .unlocked_ioctl = ddb_ioctl, 1921 .open = ddb_open, 1922 }; 1923 1924 static char *ddb_devnode(struct device *device, umode_t *mode) 1925 { 1926 struct ddb *dev = dev_get_drvdata(device); 1927 1928 return kasprintf(GFP_KERNEL, "ddbridge/card%d", dev->nr); 1929 } 1930 1931 static int ddb_class_create(void) 1932 { 1933 ddb_major = register_chrdev(0, DDB_NAME, &ddb_fops); 1934 if (ddb_major < 0) 1935 return ddb_major; 1936 1937 ddb_class = class_create(THIS_MODULE, DDB_NAME); 1938 if (IS_ERR(ddb_class)) { 1939 unregister_chrdev(ddb_major, DDB_NAME); 1940 return PTR_ERR(ddb_class); 1941 } 1942 ddb_class->devnode = ddb_devnode; 1943 return 0; 1944 } 1945 1946 static void ddb_class_destroy(void) 1947 { 1948 class_destroy(ddb_class); 1949 unregister_chrdev(ddb_major, DDB_NAME); 1950 } 1951 1952 static int ddb_device_create(struct ddb *dev) 1953 { 1954 dev->nr = ddb_num++; 1955 dev->ddb_dev = device_create(ddb_class, NULL, 1956 MKDEV(ddb_major, dev->nr), 1957 dev, "ddbridge%d", dev->nr); 1958 ddbs[dev->nr] = dev; 1959 if (IS_ERR(dev->ddb_dev)) 1960 return -1; 1961 return 0; 1962 } 1963 1964 static void ddb_device_destroy(struct ddb *dev) 1965 { 1966 ddb_num--; 1967 if (IS_ERR(dev->ddb_dev)) 1968 return; 1969 device_destroy(ddb_class, MKDEV(ddb_major, 0)); 1970 } 1971 1972 1973 /****************************************************************************/ 1974 /****************************************************************************/ 1975 /****************************************************************************/ 1976 1977 static void ddb_unmap(struct ddb *dev) 1978 { 1979 if (dev->regs) 1980 iounmap(dev->regs); 1981 vfree(dev); 1982 } 1983 1984 1985 static void ddb_remove(struct pci_dev *pdev) 1986 { 1987 struct ddb *dev = pci_get_drvdata(pdev); 1988 1989 ddb_ports_detach(dev); 1990 ddb_i2c_release(dev); 1991 1992 ddbwritel(0, INTERRUPT_ENABLE); 1993 free_irq(dev->pdev->irq, dev); 1994 #ifdef CONFIG_PCI_MSI 1995 if (dev->msi) 1996 pci_disable_msi(dev->pdev); 1997 #endif 1998 ddb_ports_release(dev); 1999 ddb_buffers_free(dev); 2000 ddb_device_destroy(dev); 2001 2002 ddb_unmap(dev); 2003 pci_set_drvdata(pdev, NULL); 2004 pci_disable_device(pdev); 2005 } 2006 2007 2008 static int ddb_probe(struct pci_dev *pdev, const struct pci_device_id *id) 2009 { 2010 struct ddb *dev; 2011 int stat = 0; 2012 int irq_flag = IRQF_SHARED; 2013 2014 if (pci_enable_device(pdev) < 0) 2015 return -ENODEV; 2016 2017 dev = vzalloc(sizeof(struct ddb)); 2018 if (dev == NULL) 2019 return -ENOMEM; 2020 2021 dev->pdev = pdev; 2022 pci_set_drvdata(pdev, dev); 2023 dev->info = (struct ddb_info *) id->driver_data; 2024 dev_info(&pdev->dev, "Detected %s\n", dev->info->name); 2025 2026 dev->regs = ioremap(pci_resource_start(dev->pdev, 0), 2027 pci_resource_len(dev->pdev, 0)); 2028 if (!dev->regs) { 2029 stat = -ENOMEM; 2030 goto fail; 2031 } 2032 dev_info(&pdev->dev, "HW %08x FW %08x\n", ddbreadl(0), ddbreadl(4)); 2033 2034 #ifdef CONFIG_PCI_MSI 2035 if (pci_msi_enabled()) 2036 stat = pci_enable_msi(dev->pdev); 2037 if (stat) { 2038 dev_info(&pdev->dev, "MSI not available.\n"); 2039 } else { 2040 irq_flag = 0; 2041 dev->msi = 1; 2042 } 2043 #endif 2044 stat = request_irq(dev->pdev->irq, irq_handler, 2045 irq_flag, "DDBridge", (void *) dev); 2046 if (stat < 0) 2047 goto fail1; 2048 ddbwritel(0, DMA_BASE_WRITE); 2049 ddbwritel(0, DMA_BASE_READ); 2050 ddbwritel(0xffffffff, INTERRUPT_ACK); 2051 ddbwritel(0xfff0f, INTERRUPT_ENABLE); 2052 ddbwritel(0, MSI1_ENABLE); 2053 2054 /* board control */ 2055 if (dev->info->board_control) { 2056 ddbwritel(0, DDB_LINK_TAG(0) | BOARD_CONTROL); 2057 msleep(100); 2058 ddbwritel(dev->info->board_control_2, 2059 DDB_LINK_TAG(0) | BOARD_CONTROL); 2060 usleep_range(2000, 3000); 2061 ddbwritel(dev->info->board_control_2 2062 | dev->info->board_control, 2063 DDB_LINK_TAG(0) | BOARD_CONTROL); 2064 usleep_range(2000, 3000); 2065 } 2066 2067 if (ddb_i2c_init(dev) < 0) 2068 goto fail1; 2069 ddb_ports_init(dev); 2070 if (ddb_buffers_alloc(dev) < 0) { 2071 dev_err(&pdev->dev, "Could not allocate buffer memory\n"); 2072 goto fail2; 2073 } 2074 if (ddb_ports_attach(dev) < 0) 2075 goto fail3; 2076 ddb_device_create(dev); 2077 return 0; 2078 2079 fail3: 2080 ddb_ports_detach(dev); 2081 dev_err(&pdev->dev, "fail3\n"); 2082 ddb_ports_release(dev); 2083 fail2: 2084 dev_err(&pdev->dev, "fail2\n"); 2085 ddb_buffers_free(dev); 2086 fail1: 2087 dev_err(&pdev->dev, "fail1\n"); 2088 if (dev->msi) 2089 pci_disable_msi(dev->pdev); 2090 if (stat == 0) 2091 free_irq(dev->pdev->irq, dev); 2092 fail: 2093 dev_err(&pdev->dev, "fail\n"); 2094 ddb_unmap(dev); 2095 pci_set_drvdata(pdev, NULL); 2096 pci_disable_device(pdev); 2097 return -1; 2098 } 2099 2100 /******************************************************************************/ 2101 /******************************************************************************/ 2102 /******************************************************************************/ 2103 2104 static const struct ddb_info ddb_none = { 2105 .type = DDB_NONE, 2106 .name = "Digital Devices PCIe bridge", 2107 }; 2108 2109 static const struct ddb_info ddb_octopus = { 2110 .type = DDB_OCTOPUS, 2111 .name = "Digital Devices Octopus DVB adapter", 2112 .port_num = 4, 2113 }; 2114 2115 static const struct ddb_info ddb_octopus_le = { 2116 .type = DDB_OCTOPUS, 2117 .name = "Digital Devices Octopus LE DVB adapter", 2118 .port_num = 2, 2119 }; 2120 2121 static const struct ddb_info ddb_octopus_oem = { 2122 .type = DDB_OCTOPUS, 2123 .name = "Digital Devices Octopus OEM", 2124 .port_num = 4, 2125 }; 2126 2127 static const struct ddb_info ddb_octopus_mini = { 2128 .type = DDB_OCTOPUS, 2129 .name = "Digital Devices Octopus Mini", 2130 .port_num = 4, 2131 }; 2132 2133 static const struct ddb_info ddb_v6 = { 2134 .type = DDB_OCTOPUS, 2135 .name = "Digital Devices Cine S2 V6 DVB adapter", 2136 .port_num = 3, 2137 }; 2138 static const struct ddb_info ddb_v6_5 = { 2139 .type = DDB_OCTOPUS, 2140 .name = "Digital Devices Cine S2 V6.5 DVB adapter", 2141 .port_num = 4, 2142 }; 2143 2144 static const struct ddb_info ddb_dvbct = { 2145 .type = DDB_OCTOPUS, 2146 .name = "Digital Devices DVBCT V6.1 DVB adapter", 2147 .port_num = 3, 2148 }; 2149 2150 static const struct ddb_info ddb_ctv7 = { 2151 .type = DDB_OCTOPUS, 2152 .name = "Digital Devices Cine CT V7 DVB adapter", 2153 .port_num = 4, 2154 .board_control = 3, 2155 .board_control_2 = 4, 2156 }; 2157 2158 static const struct ddb_info ddb_satixS2v3 = { 2159 .type = DDB_OCTOPUS, 2160 .name = "Mystique SaTiX-S2 V3 DVB adapter", 2161 .port_num = 3, 2162 }; 2163 2164 static const struct ddb_info ddb_octopusv3 = { 2165 .type = DDB_OCTOPUS, 2166 .name = "Digital Devices Octopus V3 DVB adapter", 2167 .port_num = 4, 2168 }; 2169 2170 /*** MaxA8 adapters ***********************************************************/ 2171 2172 static struct ddb_info ddb_ct2_8 = { 2173 .type = DDB_OCTOPUS_MAX_CT, 2174 .name = "Digital Devices MAX A8 CT2", 2175 .port_num = 4, 2176 .board_control = 0x0ff, 2177 .board_control_2 = 0xf00, 2178 .ts_quirks = TS_QUIRK_SERIAL, 2179 }; 2180 2181 static struct ddb_info ddb_c2t2_8 = { 2182 .type = DDB_OCTOPUS_MAX_CT, 2183 .name = "Digital Devices MAX A8 C2T2", 2184 .port_num = 4, 2185 .board_control = 0x0ff, 2186 .board_control_2 = 0xf00, 2187 .ts_quirks = TS_QUIRK_SERIAL, 2188 }; 2189 2190 static struct ddb_info ddb_isdbt_8 = { 2191 .type = DDB_OCTOPUS_MAX_CT, 2192 .name = "Digital Devices MAX A8 ISDBT", 2193 .port_num = 4, 2194 .board_control = 0x0ff, 2195 .board_control_2 = 0xf00, 2196 .ts_quirks = TS_QUIRK_SERIAL, 2197 }; 2198 2199 static struct ddb_info ddb_c2t2i_v0_8 = { 2200 .type = DDB_OCTOPUS_MAX_CT, 2201 .name = "Digital Devices MAX A8 C2T2I V0", 2202 .port_num = 4, 2203 .board_control = 0x0ff, 2204 .board_control_2 = 0xf00, 2205 .ts_quirks = TS_QUIRK_SERIAL | TS_QUIRK_ALT_OSC, 2206 }; 2207 2208 static struct ddb_info ddb_c2t2i_8 = { 2209 .type = DDB_OCTOPUS_MAX_CT, 2210 .name = "Digital Devices MAX A8 C2T2I", 2211 .port_num = 4, 2212 .board_control = 0x0ff, 2213 .board_control_2 = 0xf00, 2214 .ts_quirks = TS_QUIRK_SERIAL, 2215 }; 2216 2217 /******************************************************************************/ 2218 2219 #define DDVID 0xdd01 /* Digital Devices Vendor ID */ 2220 2221 #define DDB_ID(_vend, _dev, _subvend, _subdev, _driverdata) { \ 2222 .vendor = _vend, .device = _dev, \ 2223 .subvendor = _subvend, .subdevice = _subdev, \ 2224 .driver_data = (unsigned long)&_driverdata } 2225 2226 static const struct pci_device_id ddb_id_tbl[] = { 2227 DDB_ID(DDVID, 0x0002, DDVID, 0x0001, ddb_octopus), 2228 DDB_ID(DDVID, 0x0003, DDVID, 0x0001, ddb_octopus), 2229 DDB_ID(DDVID, 0x0005, DDVID, 0x0004, ddb_octopusv3), 2230 DDB_ID(DDVID, 0x0003, DDVID, 0x0002, ddb_octopus_le), 2231 DDB_ID(DDVID, 0x0003, DDVID, 0x0003, ddb_octopus_oem), 2232 DDB_ID(DDVID, 0x0003, DDVID, 0x0010, ddb_octopus_mini), 2233 DDB_ID(DDVID, 0x0005, DDVID, 0x0011, ddb_octopus_mini), 2234 DDB_ID(DDVID, 0x0003, DDVID, 0x0020, ddb_v6), 2235 DDB_ID(DDVID, 0x0003, DDVID, 0x0021, ddb_v6_5), 2236 DDB_ID(DDVID, 0x0003, DDVID, 0x0030, ddb_dvbct), 2237 DDB_ID(DDVID, 0x0003, DDVID, 0xdb03, ddb_satixS2v3), 2238 DDB_ID(DDVID, 0x0006, DDVID, 0x0031, ddb_ctv7), 2239 DDB_ID(DDVID, 0x0006, DDVID, 0x0032, ddb_ctv7), 2240 DDB_ID(DDVID, 0x0006, DDVID, 0x0033, ddb_ctv7), 2241 DDB_ID(DDVID, 0x0008, DDVID, 0x0034, ddb_ct2_8), 2242 DDB_ID(DDVID, 0x0008, DDVID, 0x0035, ddb_c2t2_8), 2243 DDB_ID(DDVID, 0x0008, DDVID, 0x0036, ddb_isdbt_8), 2244 DDB_ID(DDVID, 0x0008, DDVID, 0x0037, ddb_c2t2i_v0_8), 2245 DDB_ID(DDVID, 0x0008, DDVID, 0x0038, ddb_c2t2i_8), 2246 DDB_ID(DDVID, 0x0006, DDVID, 0x0039, ddb_ctv7), 2247 /* in case sub-ids got deleted in flash */ 2248 DDB_ID(DDVID, 0x0003, PCI_ANY_ID, PCI_ANY_ID, ddb_none), 2249 DDB_ID(DDVID, 0x0005, PCI_ANY_ID, PCI_ANY_ID, ddb_none), 2250 DDB_ID(DDVID, 0x0006, PCI_ANY_ID, PCI_ANY_ID, ddb_none), 2251 DDB_ID(DDVID, 0x0007, PCI_ANY_ID, PCI_ANY_ID, ddb_none), 2252 DDB_ID(DDVID, 0x0008, PCI_ANY_ID, PCI_ANY_ID, ddb_none), 2253 DDB_ID(DDVID, 0x0011, PCI_ANY_ID, PCI_ANY_ID, ddb_none), 2254 DDB_ID(DDVID, 0x0013, PCI_ANY_ID, PCI_ANY_ID, ddb_none), 2255 DDB_ID(DDVID, 0x0201, PCI_ANY_ID, PCI_ANY_ID, ddb_none), 2256 DDB_ID(DDVID, 0x0320, PCI_ANY_ID, PCI_ANY_ID, ddb_none), 2257 {0} 2258 }; 2259 MODULE_DEVICE_TABLE(pci, ddb_id_tbl); 2260 2261 2262 static struct pci_driver ddb_pci_driver = { 2263 .name = "DDBridge", 2264 .id_table = ddb_id_tbl, 2265 .probe = ddb_probe, 2266 .remove = ddb_remove, 2267 }; 2268 2269 static __init int module_init_ddbridge(void) 2270 { 2271 int ret; 2272 2273 pr_info("Digital Devices PCIE bridge driver, Copyright (C) 2010-11 Digital Devices GmbH\n"); 2274 2275 ret = ddb_class_create(); 2276 if (ret < 0) 2277 return ret; 2278 ret = pci_register_driver(&ddb_pci_driver); 2279 if (ret < 0) 2280 ddb_class_destroy(); 2281 return ret; 2282 } 2283 2284 static __exit void module_exit_ddbridge(void) 2285 { 2286 pci_unregister_driver(&ddb_pci_driver); 2287 ddb_class_destroy(); 2288 } 2289 2290 module_init(module_init_ddbridge); 2291 module_exit(module_exit_ddbridge); 2292 2293 MODULE_DESCRIPTION("Digital Devices PCIe Bridge"); 2294 MODULE_AUTHOR("Ralph Metzler"); 2295 MODULE_LICENSE("GPL"); 2296 MODULE_VERSION("0.5"); 2297