1 /* 2 * 3 * device driver for Conexant 2388x based TV cards 4 * video4linux video interface 5 * 6 * (c) 2003-04 Gerd Knorr <kraxel@bytesex.org> [SuSE Labs] 7 * 8 * (c) 2005-2006 Mauro Carvalho Chehab <mchehab@infradead.org> 9 * - Multituner support 10 * - video_ioctl2 conversion 11 * - PAL/M fixes 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of the GNU General Public License as published by 15 * the Free Software Foundation; either version 2 of the License, or 16 * (at your option) any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License 24 * along with this program; if not, write to the Free Software 25 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 26 */ 27 28 #include <linux/init.h> 29 #include <linux/list.h> 30 #include <linux/module.h> 31 #include <linux/kmod.h> 32 #include <linux/kernel.h> 33 #include <linux/slab.h> 34 #include <linux/interrupt.h> 35 #include <linux/dma-mapping.h> 36 #include <linux/delay.h> 37 #include <linux/kthread.h> 38 #include <asm/div64.h> 39 40 #include "cx88.h" 41 #include <media/v4l2-common.h> 42 #include <media/v4l2-ioctl.h> 43 #include <media/v4l2-event.h> 44 #include <media/wm8775.h> 45 46 MODULE_DESCRIPTION("v4l2 driver module for cx2388x based TV cards"); 47 MODULE_AUTHOR("Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]"); 48 MODULE_LICENSE("GPL"); 49 MODULE_VERSION(CX88_VERSION); 50 51 /* ------------------------------------------------------------------ */ 52 53 static unsigned int video_nr[] = {[0 ... (CX88_MAXBOARDS - 1)] = UNSET }; 54 static unsigned int vbi_nr[] = {[0 ... (CX88_MAXBOARDS - 1)] = UNSET }; 55 static unsigned int radio_nr[] = {[0 ... (CX88_MAXBOARDS - 1)] = UNSET }; 56 57 module_param_array(video_nr, int, NULL, 0444); 58 module_param_array(vbi_nr, int, NULL, 0444); 59 module_param_array(radio_nr, int, NULL, 0444); 60 61 MODULE_PARM_DESC(video_nr,"video device numbers"); 62 MODULE_PARM_DESC(vbi_nr,"vbi device numbers"); 63 MODULE_PARM_DESC(radio_nr,"radio device numbers"); 64 65 static unsigned int video_debug; 66 module_param(video_debug,int,0644); 67 MODULE_PARM_DESC(video_debug,"enable debug messages [video]"); 68 69 static unsigned int irq_debug; 70 module_param(irq_debug,int,0644); 71 MODULE_PARM_DESC(irq_debug,"enable debug messages [IRQ handler]"); 72 73 #define dprintk(level,fmt, arg...) if (video_debug >= level) \ 74 printk(KERN_DEBUG "%s/0: " fmt, core->name , ## arg) 75 76 /* ------------------------------------------------------------------- */ 77 /* static data */ 78 79 static const struct cx8800_fmt formats[] = { 80 { 81 .name = "8 bpp, gray", 82 .fourcc = V4L2_PIX_FMT_GREY, 83 .cxformat = ColorFormatY8, 84 .depth = 8, 85 .flags = FORMAT_FLAGS_PACKED, 86 },{ 87 .name = "15 bpp RGB, le", 88 .fourcc = V4L2_PIX_FMT_RGB555, 89 .cxformat = ColorFormatRGB15, 90 .depth = 16, 91 .flags = FORMAT_FLAGS_PACKED, 92 },{ 93 .name = "15 bpp RGB, be", 94 .fourcc = V4L2_PIX_FMT_RGB555X, 95 .cxformat = ColorFormatRGB15 | ColorFormatBSWAP, 96 .depth = 16, 97 .flags = FORMAT_FLAGS_PACKED, 98 },{ 99 .name = "16 bpp RGB, le", 100 .fourcc = V4L2_PIX_FMT_RGB565, 101 .cxformat = ColorFormatRGB16, 102 .depth = 16, 103 .flags = FORMAT_FLAGS_PACKED, 104 },{ 105 .name = "16 bpp RGB, be", 106 .fourcc = V4L2_PIX_FMT_RGB565X, 107 .cxformat = ColorFormatRGB16 | ColorFormatBSWAP, 108 .depth = 16, 109 .flags = FORMAT_FLAGS_PACKED, 110 },{ 111 .name = "24 bpp RGB, le", 112 .fourcc = V4L2_PIX_FMT_BGR24, 113 .cxformat = ColorFormatRGB24, 114 .depth = 24, 115 .flags = FORMAT_FLAGS_PACKED, 116 },{ 117 .name = "32 bpp RGB, le", 118 .fourcc = V4L2_PIX_FMT_BGR32, 119 .cxformat = ColorFormatRGB32, 120 .depth = 32, 121 .flags = FORMAT_FLAGS_PACKED, 122 },{ 123 .name = "32 bpp RGB, be", 124 .fourcc = V4L2_PIX_FMT_RGB32, 125 .cxformat = ColorFormatRGB32 | ColorFormatBSWAP | ColorFormatWSWAP, 126 .depth = 32, 127 .flags = FORMAT_FLAGS_PACKED, 128 },{ 129 .name = "4:2:2, packed, YUYV", 130 .fourcc = V4L2_PIX_FMT_YUYV, 131 .cxformat = ColorFormatYUY2, 132 .depth = 16, 133 .flags = FORMAT_FLAGS_PACKED, 134 },{ 135 .name = "4:2:2, packed, UYVY", 136 .fourcc = V4L2_PIX_FMT_UYVY, 137 .cxformat = ColorFormatYUY2 | ColorFormatBSWAP, 138 .depth = 16, 139 .flags = FORMAT_FLAGS_PACKED, 140 }, 141 }; 142 143 static const struct cx8800_fmt* format_by_fourcc(unsigned int fourcc) 144 { 145 unsigned int i; 146 147 for (i = 0; i < ARRAY_SIZE(formats); i++) 148 if (formats[i].fourcc == fourcc) 149 return formats+i; 150 return NULL; 151 } 152 153 /* ------------------------------------------------------------------- */ 154 155 struct cx88_ctrl { 156 /* control information */ 157 u32 id; 158 s32 minimum; 159 s32 maximum; 160 u32 step; 161 s32 default_value; 162 163 /* control register information */ 164 u32 off; 165 u32 reg; 166 u32 sreg; 167 u32 mask; 168 u32 shift; 169 }; 170 171 static const struct cx88_ctrl cx8800_vid_ctls[] = { 172 /* --- video --- */ 173 { 174 .id = V4L2_CID_BRIGHTNESS, 175 .minimum = 0x00, 176 .maximum = 0xff, 177 .step = 1, 178 .default_value = 0x7f, 179 .off = 128, 180 .reg = MO_CONTR_BRIGHT, 181 .mask = 0x00ff, 182 .shift = 0, 183 },{ 184 .id = V4L2_CID_CONTRAST, 185 .minimum = 0, 186 .maximum = 0xff, 187 .step = 1, 188 .default_value = 0x3f, 189 .off = 0, 190 .reg = MO_CONTR_BRIGHT, 191 .mask = 0xff00, 192 .shift = 8, 193 },{ 194 .id = V4L2_CID_HUE, 195 .minimum = 0, 196 .maximum = 0xff, 197 .step = 1, 198 .default_value = 0x7f, 199 .off = 128, 200 .reg = MO_HUE, 201 .mask = 0x00ff, 202 .shift = 0, 203 },{ 204 /* strictly, this only describes only U saturation. 205 * V saturation is handled specially through code. 206 */ 207 .id = V4L2_CID_SATURATION, 208 .minimum = 0, 209 .maximum = 0xff, 210 .step = 1, 211 .default_value = 0x7f, 212 .off = 0, 213 .reg = MO_UV_SATURATION, 214 .mask = 0x00ff, 215 .shift = 0, 216 }, { 217 .id = V4L2_CID_SHARPNESS, 218 .minimum = 0, 219 .maximum = 4, 220 .step = 1, 221 .default_value = 0x0, 222 .off = 0, 223 /* NOTE: the value is converted and written to both even 224 and odd registers in the code */ 225 .reg = MO_FILTER_ODD, 226 .mask = 7 << 7, 227 .shift = 7, 228 }, { 229 .id = V4L2_CID_CHROMA_AGC, 230 .minimum = 0, 231 .maximum = 1, 232 .default_value = 0x1, 233 .reg = MO_INPUT_FORMAT, 234 .mask = 1 << 10, 235 .shift = 10, 236 }, { 237 .id = V4L2_CID_COLOR_KILLER, 238 .minimum = 0, 239 .maximum = 1, 240 .default_value = 0x1, 241 .reg = MO_INPUT_FORMAT, 242 .mask = 1 << 9, 243 .shift = 9, 244 }, { 245 .id = V4L2_CID_BAND_STOP_FILTER, 246 .minimum = 0, 247 .maximum = 1, 248 .step = 1, 249 .default_value = 0x0, 250 .off = 0, 251 .reg = MO_HTOTAL, 252 .mask = 3 << 11, 253 .shift = 11, 254 } 255 }; 256 257 static const struct cx88_ctrl cx8800_aud_ctls[] = { 258 { 259 /* --- audio --- */ 260 .id = V4L2_CID_AUDIO_MUTE, 261 .minimum = 0, 262 .maximum = 1, 263 .default_value = 1, 264 .reg = AUD_VOL_CTL, 265 .sreg = SHADOW_AUD_VOL_CTL, 266 .mask = (1 << 6), 267 .shift = 6, 268 },{ 269 .id = V4L2_CID_AUDIO_VOLUME, 270 .minimum = 0, 271 .maximum = 0x3f, 272 .step = 1, 273 .default_value = 0x3f, 274 .reg = AUD_VOL_CTL, 275 .sreg = SHADOW_AUD_VOL_CTL, 276 .mask = 0x3f, 277 .shift = 0, 278 },{ 279 .id = V4L2_CID_AUDIO_BALANCE, 280 .minimum = 0, 281 .maximum = 0x7f, 282 .step = 1, 283 .default_value = 0x40, 284 .reg = AUD_BAL_CTL, 285 .sreg = SHADOW_AUD_BAL_CTL, 286 .mask = 0x7f, 287 .shift = 0, 288 } 289 }; 290 291 enum { 292 CX8800_VID_CTLS = ARRAY_SIZE(cx8800_vid_ctls), 293 CX8800_AUD_CTLS = ARRAY_SIZE(cx8800_aud_ctls), 294 }; 295 296 /* ------------------------------------------------------------------ */ 297 298 int cx88_video_mux(struct cx88_core *core, unsigned int input) 299 { 300 /* struct cx88_core *core = dev->core; */ 301 302 dprintk(1,"video_mux: %d [vmux=%d,gpio=0x%x,0x%x,0x%x,0x%x]\n", 303 input, INPUT(input).vmux, 304 INPUT(input).gpio0,INPUT(input).gpio1, 305 INPUT(input).gpio2,INPUT(input).gpio3); 306 core->input = input; 307 cx_andor(MO_INPUT_FORMAT, 0x03 << 14, INPUT(input).vmux << 14); 308 cx_write(MO_GP3_IO, INPUT(input).gpio3); 309 cx_write(MO_GP0_IO, INPUT(input).gpio0); 310 cx_write(MO_GP1_IO, INPUT(input).gpio1); 311 cx_write(MO_GP2_IO, INPUT(input).gpio2); 312 313 switch (INPUT(input).type) { 314 case CX88_VMUX_SVIDEO: 315 cx_set(MO_AFECFG_IO, 0x00000001); 316 cx_set(MO_INPUT_FORMAT, 0x00010010); 317 cx_set(MO_FILTER_EVEN, 0x00002020); 318 cx_set(MO_FILTER_ODD, 0x00002020); 319 break; 320 default: 321 cx_clear(MO_AFECFG_IO, 0x00000001); 322 cx_clear(MO_INPUT_FORMAT, 0x00010010); 323 cx_clear(MO_FILTER_EVEN, 0x00002020); 324 cx_clear(MO_FILTER_ODD, 0x00002020); 325 break; 326 } 327 328 /* if there are audioroutes defined, we have an external 329 ADC to deal with audio */ 330 if (INPUT(input).audioroute) { 331 /* The wm8775 module has the "2" route hardwired into 332 the initialization. Some boards may use different 333 routes for different inputs. HVR-1300 surely does */ 334 if (core->sd_wm8775) { 335 call_all(core, audio, s_routing, 336 INPUT(input).audioroute, 0, 0); 337 } 338 /* cx2388's C-ADC is connected to the tuner only. 339 When used with S-Video, that ADC is busy dealing with 340 chroma, so an external must be used for baseband audio */ 341 if (INPUT(input).type != CX88_VMUX_TELEVISION && 342 INPUT(input).type != CX88_VMUX_CABLE) { 343 /* "I2S ADC mode" */ 344 core->tvaudio = WW_I2SADC; 345 cx88_set_tvaudio(core); 346 } else { 347 /* Normal mode */ 348 cx_write(AUD_I2SCNTL, 0x0); 349 cx_clear(AUD_CTL, EN_I2SIN_ENABLE); 350 } 351 } 352 353 return 0; 354 } 355 EXPORT_SYMBOL(cx88_video_mux); 356 357 /* ------------------------------------------------------------------ */ 358 359 static int start_video_dma(struct cx8800_dev *dev, 360 struct cx88_dmaqueue *q, 361 struct cx88_buffer *buf) 362 { 363 struct cx88_core *core = dev->core; 364 365 /* setup fifo + format */ 366 cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH21], 367 buf->bpl, buf->risc.dma); 368 cx88_set_scale(core, core->width, core->height, core->field); 369 cx_write(MO_COLOR_CTRL, dev->fmt->cxformat | ColorFormatGamma); 370 371 /* reset counter */ 372 cx_write(MO_VIDY_GPCNTRL,GP_COUNT_CONTROL_RESET); 373 q->count = 0; 374 375 /* enable irqs */ 376 cx_set(MO_PCI_INTMSK, core->pci_irqmask | PCI_INT_VIDINT); 377 378 /* Enables corresponding bits at PCI_INT_STAT: 379 bits 0 to 4: video, audio, transport stream, VIP, Host 380 bit 7: timer 381 bits 8 and 9: DMA complete for: SRC, DST 382 bits 10 and 11: BERR signal asserted for RISC: RD, WR 383 bits 12 to 15: BERR signal asserted for: BRDG, SRC, DST, IPB 384 */ 385 cx_set(MO_VID_INTMSK, 0x0f0011); 386 387 /* enable capture */ 388 cx_set(VID_CAPTURE_CONTROL,0x06); 389 390 /* start dma */ 391 cx_set(MO_DEV_CNTRL2, (1<<5)); 392 cx_set(MO_VID_DMACNTRL, 0x11); /* Planar Y and packed FIFO and RISC enable */ 393 394 return 0; 395 } 396 397 #ifdef CONFIG_PM 398 static int stop_video_dma(struct cx8800_dev *dev) 399 { 400 struct cx88_core *core = dev->core; 401 402 /* stop dma */ 403 cx_clear(MO_VID_DMACNTRL, 0x11); 404 405 /* disable capture */ 406 cx_clear(VID_CAPTURE_CONTROL,0x06); 407 408 /* disable irqs */ 409 cx_clear(MO_PCI_INTMSK, PCI_INT_VIDINT); 410 cx_clear(MO_VID_INTMSK, 0x0f0011); 411 return 0; 412 } 413 414 static int restart_video_queue(struct cx8800_dev *dev, 415 struct cx88_dmaqueue *q) 416 { 417 struct cx88_core *core = dev->core; 418 struct cx88_buffer *buf; 419 420 if (!list_empty(&q->active)) { 421 buf = list_entry(q->active.next, struct cx88_buffer, list); 422 dprintk(2,"restart_queue [%p/%d]: restart dma\n", 423 buf, buf->vb.v4l2_buf.index); 424 start_video_dma(dev, q, buf); 425 } 426 return 0; 427 } 428 #endif 429 430 /* ------------------------------------------------------------------ */ 431 432 static int queue_setup(struct vb2_queue *q, const struct v4l2_format *fmt, 433 unsigned int *num_buffers, unsigned int *num_planes, 434 unsigned int sizes[], void *alloc_ctxs[]) 435 { 436 struct cx8800_dev *dev = q->drv_priv; 437 struct cx88_core *core = dev->core; 438 439 *num_planes = 1; 440 sizes[0] = (dev->fmt->depth * core->width * core->height) >> 3; 441 alloc_ctxs[0] = dev->alloc_ctx; 442 return 0; 443 } 444 445 static int buffer_prepare(struct vb2_buffer *vb) 446 { 447 struct cx8800_dev *dev = vb->vb2_queue->drv_priv; 448 struct cx88_core *core = dev->core; 449 struct cx88_buffer *buf = container_of(vb, struct cx88_buffer, vb); 450 struct sg_table *sgt = vb2_dma_sg_plane_desc(vb, 0); 451 452 buf->bpl = core->width * dev->fmt->depth >> 3; 453 454 if (vb2_plane_size(vb, 0) < core->height * buf->bpl) 455 return -EINVAL; 456 vb2_set_plane_payload(vb, 0, core->height * buf->bpl); 457 458 switch (core->field) { 459 case V4L2_FIELD_TOP: 460 cx88_risc_buffer(dev->pci, &buf->risc, 461 sgt->sgl, 0, UNSET, 462 buf->bpl, 0, core->height); 463 break; 464 case V4L2_FIELD_BOTTOM: 465 cx88_risc_buffer(dev->pci, &buf->risc, 466 sgt->sgl, UNSET, 0, 467 buf->bpl, 0, core->height); 468 break; 469 case V4L2_FIELD_SEQ_TB: 470 cx88_risc_buffer(dev->pci, &buf->risc, 471 sgt->sgl, 472 0, buf->bpl * (core->height >> 1), 473 buf->bpl, 0, 474 core->height >> 1); 475 break; 476 case V4L2_FIELD_SEQ_BT: 477 cx88_risc_buffer(dev->pci, &buf->risc, 478 sgt->sgl, 479 buf->bpl * (core->height >> 1), 0, 480 buf->bpl, 0, 481 core->height >> 1); 482 break; 483 case V4L2_FIELD_INTERLACED: 484 default: 485 cx88_risc_buffer(dev->pci, &buf->risc, 486 sgt->sgl, 0, buf->bpl, 487 buf->bpl, buf->bpl, 488 core->height >> 1); 489 break; 490 } 491 dprintk(2,"[%p/%d] buffer_prepare - %dx%d %dbpp \"%s\" - dma=0x%08lx\n", 492 buf, buf->vb.v4l2_buf.index, 493 core->width, core->height, dev->fmt->depth, dev->fmt->name, 494 (unsigned long)buf->risc.dma); 495 return 0; 496 } 497 498 static void buffer_finish(struct vb2_buffer *vb) 499 { 500 struct cx8800_dev *dev = vb->vb2_queue->drv_priv; 501 struct cx88_buffer *buf = container_of(vb, struct cx88_buffer, vb); 502 struct cx88_riscmem *risc = &buf->risc; 503 504 if (risc->cpu) 505 pci_free_consistent(dev->pci, risc->size, risc->cpu, risc->dma); 506 memset(risc, 0, sizeof(*risc)); 507 } 508 509 static void buffer_queue(struct vb2_buffer *vb) 510 { 511 struct cx8800_dev *dev = vb->vb2_queue->drv_priv; 512 struct cx88_buffer *buf = container_of(vb, struct cx88_buffer, vb); 513 struct cx88_buffer *prev; 514 struct cx88_core *core = dev->core; 515 struct cx88_dmaqueue *q = &dev->vidq; 516 517 /* add jump to start */ 518 buf->risc.cpu[1] = cpu_to_le32(buf->risc.dma + 8); 519 buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_CNT_INC); 520 buf->risc.jmp[1] = cpu_to_le32(buf->risc.dma + 8); 521 522 if (list_empty(&q->active)) { 523 list_add_tail(&buf->list, &q->active); 524 dprintk(2,"[%p/%d] buffer_queue - first active\n", 525 buf, buf->vb.v4l2_buf.index); 526 527 } else { 528 buf->risc.cpu[0] |= cpu_to_le32(RISC_IRQ1); 529 prev = list_entry(q->active.prev, struct cx88_buffer, list); 530 list_add_tail(&buf->list, &q->active); 531 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma); 532 dprintk(2, "[%p/%d] buffer_queue - append to active\n", 533 buf, buf->vb.v4l2_buf.index); 534 } 535 } 536 537 static int start_streaming(struct vb2_queue *q, unsigned int count) 538 { 539 struct cx8800_dev *dev = q->drv_priv; 540 struct cx88_dmaqueue *dmaq = &dev->vidq; 541 struct cx88_buffer *buf = list_entry(dmaq->active.next, 542 struct cx88_buffer, list); 543 544 start_video_dma(dev, dmaq, buf); 545 return 0; 546 } 547 548 static void stop_streaming(struct vb2_queue *q) 549 { 550 struct cx8800_dev *dev = q->drv_priv; 551 struct cx88_core *core = dev->core; 552 struct cx88_dmaqueue *dmaq = &dev->vidq; 553 unsigned long flags; 554 555 cx_clear(MO_VID_DMACNTRL, 0x11); 556 cx_clear(VID_CAPTURE_CONTROL, 0x06); 557 spin_lock_irqsave(&dev->slock, flags); 558 while (!list_empty(&dmaq->active)) { 559 struct cx88_buffer *buf = list_entry(dmaq->active.next, 560 struct cx88_buffer, list); 561 562 list_del(&buf->list); 563 vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR); 564 } 565 spin_unlock_irqrestore(&dev->slock, flags); 566 } 567 568 static struct vb2_ops cx8800_video_qops = { 569 .queue_setup = queue_setup, 570 .buf_prepare = buffer_prepare, 571 .buf_finish = buffer_finish, 572 .buf_queue = buffer_queue, 573 .wait_prepare = vb2_ops_wait_prepare, 574 .wait_finish = vb2_ops_wait_finish, 575 .start_streaming = start_streaming, 576 .stop_streaming = stop_streaming, 577 }; 578 579 /* ------------------------------------------------------------------ */ 580 581 static int radio_open(struct file *file) 582 { 583 struct cx8800_dev *dev = video_drvdata(file); 584 struct cx88_core *core = dev->core; 585 int ret = v4l2_fh_open(file); 586 587 if (ret) 588 return ret; 589 590 cx_write(MO_GP3_IO, core->board.radio.gpio3); 591 cx_write(MO_GP0_IO, core->board.radio.gpio0); 592 cx_write(MO_GP1_IO, core->board.radio.gpio1); 593 cx_write(MO_GP2_IO, core->board.radio.gpio2); 594 if (core->board.radio.audioroute) { 595 if (core->sd_wm8775) { 596 call_all(core, audio, s_routing, 597 core->board.radio.audioroute, 0, 0); 598 } 599 /* "I2S ADC mode" */ 600 core->tvaudio = WW_I2SADC; 601 cx88_set_tvaudio(core); 602 } else { 603 /* FM Mode */ 604 core->tvaudio = WW_FM; 605 cx88_set_tvaudio(core); 606 cx88_set_stereo(core, V4L2_TUNER_MODE_STEREO, 1); 607 } 608 call_all(core, tuner, s_radio); 609 return 0; 610 } 611 612 /* ------------------------------------------------------------------ */ 613 /* VIDEO CTRL IOCTLS */ 614 615 static int cx8800_s_vid_ctrl(struct v4l2_ctrl *ctrl) 616 { 617 struct cx88_core *core = 618 container_of(ctrl->handler, struct cx88_core, video_hdl); 619 const struct cx88_ctrl *cc = ctrl->priv; 620 u32 value, mask; 621 622 mask = cc->mask; 623 switch (ctrl->id) { 624 case V4L2_CID_SATURATION: 625 /* special v_sat handling */ 626 627 value = ((ctrl->val - cc->off) << cc->shift) & cc->mask; 628 629 if (core->tvnorm & V4L2_STD_SECAM) { 630 /* For SECAM, both U and V sat should be equal */ 631 value = value << 8 | value; 632 } else { 633 /* Keeps U Saturation proportional to V Sat */ 634 value = (value * 0x5a) / 0x7f << 8 | value; 635 } 636 mask = 0xffff; 637 break; 638 case V4L2_CID_SHARPNESS: 639 /* 0b000, 0b100, 0b101, 0b110, or 0b111 */ 640 value = (ctrl->val < 1 ? 0 : ((ctrl->val + 3) << 7)); 641 /* needs to be set for both fields */ 642 cx_andor(MO_FILTER_EVEN, mask, value); 643 break; 644 case V4L2_CID_CHROMA_AGC: 645 value = ((ctrl->val - cc->off) << cc->shift) & cc->mask; 646 break; 647 default: 648 value = ((ctrl->val - cc->off) << cc->shift) & cc->mask; 649 break; 650 } 651 dprintk(1, "set_control id=0x%X(%s) ctrl=0x%02x, reg=0x%02x val=0x%02x (mask 0x%02x)%s\n", 652 ctrl->id, ctrl->name, ctrl->val, cc->reg, value, 653 mask, cc->sreg ? " [shadowed]" : ""); 654 if (cc->sreg) 655 cx_sandor(cc->sreg, cc->reg, mask, value); 656 else 657 cx_andor(cc->reg, mask, value); 658 return 0; 659 } 660 661 static int cx8800_s_aud_ctrl(struct v4l2_ctrl *ctrl) 662 { 663 struct cx88_core *core = 664 container_of(ctrl->handler, struct cx88_core, audio_hdl); 665 const struct cx88_ctrl *cc = ctrl->priv; 666 u32 value,mask; 667 668 /* Pass changes onto any WM8775 */ 669 if (core->sd_wm8775) { 670 switch (ctrl->id) { 671 case V4L2_CID_AUDIO_MUTE: 672 wm8775_s_ctrl(core, ctrl->id, ctrl->val); 673 break; 674 case V4L2_CID_AUDIO_VOLUME: 675 wm8775_s_ctrl(core, ctrl->id, (ctrl->val) ? 676 (0x90 + ctrl->val) << 8 : 0); 677 break; 678 case V4L2_CID_AUDIO_BALANCE: 679 wm8775_s_ctrl(core, ctrl->id, ctrl->val << 9); 680 break; 681 default: 682 break; 683 } 684 } 685 686 mask = cc->mask; 687 switch (ctrl->id) { 688 case V4L2_CID_AUDIO_BALANCE: 689 value = (ctrl->val < 0x40) ? (0x7f - ctrl->val) : (ctrl->val - 0x40); 690 break; 691 case V4L2_CID_AUDIO_VOLUME: 692 value = 0x3f - (ctrl->val & 0x3f); 693 break; 694 default: 695 value = ((ctrl->val - cc->off) << cc->shift) & cc->mask; 696 break; 697 } 698 dprintk(1,"set_control id=0x%X(%s) ctrl=0x%02x, reg=0x%02x val=0x%02x (mask 0x%02x)%s\n", 699 ctrl->id, ctrl->name, ctrl->val, cc->reg, value, 700 mask, cc->sreg ? " [shadowed]" : ""); 701 if (cc->sreg) 702 cx_sandor(cc->sreg, cc->reg, mask, value); 703 else 704 cx_andor(cc->reg, mask, value); 705 return 0; 706 } 707 708 /* ------------------------------------------------------------------ */ 709 /* VIDEO IOCTLS */ 710 711 static int vidioc_g_fmt_vid_cap(struct file *file, void *priv, 712 struct v4l2_format *f) 713 { 714 struct cx8800_dev *dev = video_drvdata(file); 715 struct cx88_core *core = dev->core; 716 717 f->fmt.pix.width = core->width; 718 f->fmt.pix.height = core->height; 719 f->fmt.pix.field = core->field; 720 f->fmt.pix.pixelformat = dev->fmt->fourcc; 721 f->fmt.pix.bytesperline = 722 (f->fmt.pix.width * dev->fmt->depth) >> 3; 723 f->fmt.pix.sizeimage = 724 f->fmt.pix.height * f->fmt.pix.bytesperline; 725 f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M; 726 return 0; 727 } 728 729 static int vidioc_try_fmt_vid_cap(struct file *file, void *priv, 730 struct v4l2_format *f) 731 { 732 struct cx8800_dev *dev = video_drvdata(file); 733 struct cx88_core *core = dev->core; 734 const struct cx8800_fmt *fmt; 735 enum v4l2_field field; 736 unsigned int maxw, maxh; 737 738 fmt = format_by_fourcc(f->fmt.pix.pixelformat); 739 if (NULL == fmt) 740 return -EINVAL; 741 742 maxw = norm_maxw(core->tvnorm); 743 maxh = norm_maxh(core->tvnorm); 744 745 field = f->fmt.pix.field; 746 747 switch (field) { 748 case V4L2_FIELD_TOP: 749 case V4L2_FIELD_BOTTOM: 750 case V4L2_FIELD_INTERLACED: 751 case V4L2_FIELD_SEQ_BT: 752 case V4L2_FIELD_SEQ_TB: 753 break; 754 default: 755 field = (f->fmt.pix.height > maxh / 2) 756 ? V4L2_FIELD_INTERLACED 757 : V4L2_FIELD_BOTTOM; 758 break; 759 } 760 if (V4L2_FIELD_HAS_T_OR_B(field)) 761 maxh /= 2; 762 763 v4l_bound_align_image(&f->fmt.pix.width, 48, maxw, 2, 764 &f->fmt.pix.height, 32, maxh, 0, 0); 765 f->fmt.pix.field = field; 766 f->fmt.pix.bytesperline = 767 (f->fmt.pix.width * fmt->depth) >> 3; 768 f->fmt.pix.sizeimage = 769 f->fmt.pix.height * f->fmt.pix.bytesperline; 770 f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M; 771 772 return 0; 773 } 774 775 static int vidioc_s_fmt_vid_cap(struct file *file, void *priv, 776 struct v4l2_format *f) 777 { 778 struct cx8800_dev *dev = video_drvdata(file); 779 struct cx88_core *core = dev->core; 780 int err = vidioc_try_fmt_vid_cap (file,priv,f); 781 782 if (0 != err) 783 return err; 784 if (vb2_is_busy(&dev->vb2_vidq) || vb2_is_busy(&dev->vb2_vbiq)) 785 return -EBUSY; 786 if (core->dvbdev && vb2_is_busy(&core->dvbdev->vb2_mpegq)) 787 return -EBUSY; 788 dev->fmt = format_by_fourcc(f->fmt.pix.pixelformat); 789 core->width = f->fmt.pix.width; 790 core->height = f->fmt.pix.height; 791 core->field = f->fmt.pix.field; 792 return 0; 793 } 794 795 void cx88_querycap(struct file *file, struct cx88_core *core, 796 struct v4l2_capability *cap) 797 { 798 struct video_device *vdev = video_devdata(file); 799 800 strlcpy(cap->card, core->board.name, sizeof(cap->card)); 801 cap->device_caps = V4L2_CAP_READWRITE | V4L2_CAP_STREAMING; 802 if (UNSET != core->board.tuner_type) 803 cap->device_caps |= V4L2_CAP_TUNER; 804 switch (vdev->vfl_type) { 805 case VFL_TYPE_RADIO: 806 cap->device_caps = V4L2_CAP_RADIO | V4L2_CAP_TUNER; 807 break; 808 case VFL_TYPE_GRABBER: 809 cap->device_caps |= V4L2_CAP_VIDEO_CAPTURE; 810 break; 811 case VFL_TYPE_VBI: 812 cap->device_caps |= V4L2_CAP_VBI_CAPTURE; 813 break; 814 } 815 cap->capabilities = cap->device_caps | V4L2_CAP_VIDEO_CAPTURE | 816 V4L2_CAP_VBI_CAPTURE | V4L2_CAP_DEVICE_CAPS; 817 if (core->board.radio.type == CX88_RADIO) 818 cap->capabilities |= V4L2_CAP_RADIO; 819 } 820 EXPORT_SYMBOL(cx88_querycap); 821 822 static int vidioc_querycap(struct file *file, void *priv, 823 struct v4l2_capability *cap) 824 { 825 struct cx8800_dev *dev = video_drvdata(file); 826 struct cx88_core *core = dev->core; 827 828 strcpy(cap->driver, "cx8800"); 829 sprintf(cap->bus_info, "PCI:%s", pci_name(dev->pci)); 830 cx88_querycap(file, core, cap); 831 return 0; 832 } 833 834 static int vidioc_enum_fmt_vid_cap (struct file *file, void *priv, 835 struct v4l2_fmtdesc *f) 836 { 837 if (unlikely(f->index >= ARRAY_SIZE(formats))) 838 return -EINVAL; 839 840 strlcpy(f->description,formats[f->index].name,sizeof(f->description)); 841 f->pixelformat = formats[f->index].fourcc; 842 843 return 0; 844 } 845 846 static int vidioc_g_std(struct file *file, void *priv, v4l2_std_id *tvnorm) 847 { 848 struct cx8800_dev *dev = video_drvdata(file); 849 struct cx88_core *core = dev->core; 850 851 *tvnorm = core->tvnorm; 852 return 0; 853 } 854 855 static int vidioc_s_std(struct file *file, void *priv, v4l2_std_id tvnorms) 856 { 857 struct cx8800_dev *dev = video_drvdata(file); 858 struct cx88_core *core = dev->core; 859 860 return cx88_set_tvnorm(core, tvnorms); 861 } 862 863 /* only one input in this sample driver */ 864 int cx88_enum_input (struct cx88_core *core,struct v4l2_input *i) 865 { 866 static const char * const iname[] = { 867 [ CX88_VMUX_COMPOSITE1 ] = "Composite1", 868 [ CX88_VMUX_COMPOSITE2 ] = "Composite2", 869 [ CX88_VMUX_COMPOSITE3 ] = "Composite3", 870 [ CX88_VMUX_COMPOSITE4 ] = "Composite4", 871 [ CX88_VMUX_SVIDEO ] = "S-Video", 872 [ CX88_VMUX_TELEVISION ] = "Television", 873 [ CX88_VMUX_CABLE ] = "Cable TV", 874 [ CX88_VMUX_DVB ] = "DVB", 875 [ CX88_VMUX_DEBUG ] = "for debug only", 876 }; 877 unsigned int n = i->index; 878 879 if (n >= 4) 880 return -EINVAL; 881 if (0 == INPUT(n).type) 882 return -EINVAL; 883 i->type = V4L2_INPUT_TYPE_CAMERA; 884 strcpy(i->name,iname[INPUT(n).type]); 885 if ((CX88_VMUX_TELEVISION == INPUT(n).type) || 886 (CX88_VMUX_CABLE == INPUT(n).type)) { 887 i->type = V4L2_INPUT_TYPE_TUNER; 888 } 889 i->std = CX88_NORMS; 890 return 0; 891 } 892 EXPORT_SYMBOL(cx88_enum_input); 893 894 static int vidioc_enum_input (struct file *file, void *priv, 895 struct v4l2_input *i) 896 { 897 struct cx8800_dev *dev = video_drvdata(file); 898 struct cx88_core *core = dev->core; 899 return cx88_enum_input (core,i); 900 } 901 902 static int vidioc_g_input (struct file *file, void *priv, unsigned int *i) 903 { 904 struct cx8800_dev *dev = video_drvdata(file); 905 struct cx88_core *core = dev->core; 906 907 *i = core->input; 908 return 0; 909 } 910 911 static int vidioc_s_input (struct file *file, void *priv, unsigned int i) 912 { 913 struct cx8800_dev *dev = video_drvdata(file); 914 struct cx88_core *core = dev->core; 915 916 if (i >= 4) 917 return -EINVAL; 918 if (0 == INPUT(i).type) 919 return -EINVAL; 920 921 cx88_newstation(core); 922 cx88_video_mux(core,i); 923 return 0; 924 } 925 926 static int vidioc_g_tuner (struct file *file, void *priv, 927 struct v4l2_tuner *t) 928 { 929 struct cx8800_dev *dev = video_drvdata(file); 930 struct cx88_core *core = dev->core; 931 u32 reg; 932 933 if (unlikely(UNSET == core->board.tuner_type)) 934 return -EINVAL; 935 if (0 != t->index) 936 return -EINVAL; 937 938 strcpy(t->name, "Television"); 939 t->capability = V4L2_TUNER_CAP_NORM; 940 t->rangehigh = 0xffffffffUL; 941 call_all(core, tuner, g_tuner, t); 942 943 cx88_get_stereo(core ,t); 944 reg = cx_read(MO_DEVICE_STATUS); 945 t->signal = (reg & (1<<5)) ? 0xffff : 0x0000; 946 return 0; 947 } 948 949 static int vidioc_s_tuner (struct file *file, void *priv, 950 const struct v4l2_tuner *t) 951 { 952 struct cx8800_dev *dev = video_drvdata(file); 953 struct cx88_core *core = dev->core; 954 955 if (UNSET == core->board.tuner_type) 956 return -EINVAL; 957 if (0 != t->index) 958 return -EINVAL; 959 960 cx88_set_stereo(core, t->audmode, 1); 961 return 0; 962 } 963 964 static int vidioc_g_frequency (struct file *file, void *priv, 965 struct v4l2_frequency *f) 966 { 967 struct cx8800_dev *dev = video_drvdata(file); 968 struct cx88_core *core = dev->core; 969 970 if (unlikely(UNSET == core->board.tuner_type)) 971 return -EINVAL; 972 if (f->tuner) 973 return -EINVAL; 974 975 f->frequency = core->freq; 976 977 call_all(core, tuner, g_frequency, f); 978 979 return 0; 980 } 981 982 int cx88_set_freq (struct cx88_core *core, 983 const struct v4l2_frequency *f) 984 { 985 struct v4l2_frequency new_freq = *f; 986 987 if (unlikely(UNSET == core->board.tuner_type)) 988 return -EINVAL; 989 if (unlikely(f->tuner != 0)) 990 return -EINVAL; 991 992 cx88_newstation(core); 993 call_all(core, tuner, s_frequency, f); 994 call_all(core, tuner, g_frequency, &new_freq); 995 core->freq = new_freq.frequency; 996 997 /* When changing channels it is required to reset TVAUDIO */ 998 msleep (10); 999 cx88_set_tvaudio(core); 1000 1001 return 0; 1002 } 1003 EXPORT_SYMBOL(cx88_set_freq); 1004 1005 static int vidioc_s_frequency (struct file *file, void *priv, 1006 const struct v4l2_frequency *f) 1007 { 1008 struct cx8800_dev *dev = video_drvdata(file); 1009 struct cx88_core *core = dev->core; 1010 1011 return cx88_set_freq(core, f); 1012 } 1013 1014 #ifdef CONFIG_VIDEO_ADV_DEBUG 1015 static int vidioc_g_register (struct file *file, void *fh, 1016 struct v4l2_dbg_register *reg) 1017 { 1018 struct cx8800_dev *dev = video_drvdata(file); 1019 struct cx88_core *core = dev->core; 1020 1021 /* cx2388x has a 24-bit register space */ 1022 reg->val = cx_read(reg->reg & 0xfffffc); 1023 reg->size = 4; 1024 return 0; 1025 } 1026 1027 static int vidioc_s_register (struct file *file, void *fh, 1028 const struct v4l2_dbg_register *reg) 1029 { 1030 struct cx8800_dev *dev = video_drvdata(file); 1031 struct cx88_core *core = dev->core; 1032 1033 cx_write(reg->reg & 0xfffffc, reg->val); 1034 return 0; 1035 } 1036 #endif 1037 1038 /* ----------------------------------------------------------- */ 1039 /* RADIO ESPECIFIC IOCTLS */ 1040 /* ----------------------------------------------------------- */ 1041 1042 static int radio_g_tuner (struct file *file, void *priv, 1043 struct v4l2_tuner *t) 1044 { 1045 struct cx8800_dev *dev = video_drvdata(file); 1046 struct cx88_core *core = dev->core; 1047 1048 if (unlikely(t->index > 0)) 1049 return -EINVAL; 1050 1051 strcpy(t->name, "Radio"); 1052 1053 call_all(core, tuner, g_tuner, t); 1054 return 0; 1055 } 1056 1057 static int radio_s_tuner (struct file *file, void *priv, 1058 const struct v4l2_tuner *t) 1059 { 1060 struct cx8800_dev *dev = video_drvdata(file); 1061 struct cx88_core *core = dev->core; 1062 1063 if (0 != t->index) 1064 return -EINVAL; 1065 1066 call_all(core, tuner, s_tuner, t); 1067 return 0; 1068 } 1069 1070 /* ----------------------------------------------------------- */ 1071 1072 static const char *cx88_vid_irqs[32] = { 1073 "y_risci1", "u_risci1", "v_risci1", "vbi_risc1", 1074 "y_risci2", "u_risci2", "v_risci2", "vbi_risc2", 1075 "y_oflow", "u_oflow", "v_oflow", "vbi_oflow", 1076 "y_sync", "u_sync", "v_sync", "vbi_sync", 1077 "opc_err", "par_err", "rip_err", "pci_abort", 1078 }; 1079 1080 static void cx8800_vid_irq(struct cx8800_dev *dev) 1081 { 1082 struct cx88_core *core = dev->core; 1083 u32 status, mask, count; 1084 1085 status = cx_read(MO_VID_INTSTAT); 1086 mask = cx_read(MO_VID_INTMSK); 1087 if (0 == (status & mask)) 1088 return; 1089 cx_write(MO_VID_INTSTAT, status); 1090 if (irq_debug || (status & mask & ~0xff)) 1091 cx88_print_irqbits(core->name, "irq vid", 1092 cx88_vid_irqs, ARRAY_SIZE(cx88_vid_irqs), 1093 status, mask); 1094 1095 /* risc op code error */ 1096 if (status & (1 << 16)) { 1097 printk(KERN_WARNING "%s/0: video risc op code error\n",core->name); 1098 cx_clear(MO_VID_DMACNTRL, 0x11); 1099 cx_clear(VID_CAPTURE_CONTROL, 0x06); 1100 cx88_sram_channel_dump(core, &cx88_sram_channels[SRAM_CH21]); 1101 } 1102 1103 /* risc1 y */ 1104 if (status & 0x01) { 1105 spin_lock(&dev->slock); 1106 count = cx_read(MO_VIDY_GPCNT); 1107 cx88_wakeup(core, &dev->vidq, count); 1108 spin_unlock(&dev->slock); 1109 } 1110 1111 /* risc1 vbi */ 1112 if (status & 0x08) { 1113 spin_lock(&dev->slock); 1114 count = cx_read(MO_VBI_GPCNT); 1115 cx88_wakeup(core, &dev->vbiq, count); 1116 spin_unlock(&dev->slock); 1117 } 1118 } 1119 1120 static irqreturn_t cx8800_irq(int irq, void *dev_id) 1121 { 1122 struct cx8800_dev *dev = dev_id; 1123 struct cx88_core *core = dev->core; 1124 u32 status; 1125 int loop, handled = 0; 1126 1127 for (loop = 0; loop < 10; loop++) { 1128 status = cx_read(MO_PCI_INTSTAT) & 1129 (core->pci_irqmask | PCI_INT_VIDINT); 1130 if (0 == status) 1131 goto out; 1132 cx_write(MO_PCI_INTSTAT, status); 1133 handled = 1; 1134 1135 if (status & core->pci_irqmask) 1136 cx88_core_irq(core,status); 1137 if (status & PCI_INT_VIDINT) 1138 cx8800_vid_irq(dev); 1139 } 1140 if (10 == loop) { 1141 printk(KERN_WARNING "%s/0: irq loop -- clearing mask\n", 1142 core->name); 1143 cx_write(MO_PCI_INTMSK,0); 1144 } 1145 1146 out: 1147 return IRQ_RETVAL(handled); 1148 } 1149 1150 /* ----------------------------------------------------------- */ 1151 /* exported stuff */ 1152 1153 static const struct v4l2_file_operations video_fops = 1154 { 1155 .owner = THIS_MODULE, 1156 .open = v4l2_fh_open, 1157 .release = vb2_fop_release, 1158 .read = vb2_fop_read, 1159 .poll = vb2_fop_poll, 1160 .mmap = vb2_fop_mmap, 1161 .unlocked_ioctl = video_ioctl2, 1162 }; 1163 1164 static const struct v4l2_ioctl_ops video_ioctl_ops = { 1165 .vidioc_querycap = vidioc_querycap, 1166 .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap, 1167 .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap, 1168 .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap, 1169 .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap, 1170 .vidioc_reqbufs = vb2_ioctl_reqbufs, 1171 .vidioc_querybuf = vb2_ioctl_querybuf, 1172 .vidioc_qbuf = vb2_ioctl_qbuf, 1173 .vidioc_dqbuf = vb2_ioctl_dqbuf, 1174 .vidioc_g_std = vidioc_g_std, 1175 .vidioc_s_std = vidioc_s_std, 1176 .vidioc_enum_input = vidioc_enum_input, 1177 .vidioc_g_input = vidioc_g_input, 1178 .vidioc_s_input = vidioc_s_input, 1179 .vidioc_streamon = vb2_ioctl_streamon, 1180 .vidioc_streamoff = vb2_ioctl_streamoff, 1181 .vidioc_g_tuner = vidioc_g_tuner, 1182 .vidioc_s_tuner = vidioc_s_tuner, 1183 .vidioc_g_frequency = vidioc_g_frequency, 1184 .vidioc_s_frequency = vidioc_s_frequency, 1185 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, 1186 .vidioc_unsubscribe_event = v4l2_event_unsubscribe, 1187 #ifdef CONFIG_VIDEO_ADV_DEBUG 1188 .vidioc_g_register = vidioc_g_register, 1189 .vidioc_s_register = vidioc_s_register, 1190 #endif 1191 }; 1192 1193 static const struct video_device cx8800_video_template = { 1194 .name = "cx8800-video", 1195 .fops = &video_fops, 1196 .ioctl_ops = &video_ioctl_ops, 1197 .tvnorms = CX88_NORMS, 1198 }; 1199 1200 static const struct v4l2_ioctl_ops vbi_ioctl_ops = { 1201 .vidioc_querycap = vidioc_querycap, 1202 .vidioc_g_fmt_vbi_cap = cx8800_vbi_fmt, 1203 .vidioc_try_fmt_vbi_cap = cx8800_vbi_fmt, 1204 .vidioc_s_fmt_vbi_cap = cx8800_vbi_fmt, 1205 .vidioc_reqbufs = vb2_ioctl_reqbufs, 1206 .vidioc_querybuf = vb2_ioctl_querybuf, 1207 .vidioc_qbuf = vb2_ioctl_qbuf, 1208 .vidioc_dqbuf = vb2_ioctl_dqbuf, 1209 .vidioc_g_std = vidioc_g_std, 1210 .vidioc_s_std = vidioc_s_std, 1211 .vidioc_enum_input = vidioc_enum_input, 1212 .vidioc_g_input = vidioc_g_input, 1213 .vidioc_s_input = vidioc_s_input, 1214 .vidioc_streamon = vb2_ioctl_streamon, 1215 .vidioc_streamoff = vb2_ioctl_streamoff, 1216 .vidioc_g_tuner = vidioc_g_tuner, 1217 .vidioc_s_tuner = vidioc_s_tuner, 1218 .vidioc_g_frequency = vidioc_g_frequency, 1219 .vidioc_s_frequency = vidioc_s_frequency, 1220 #ifdef CONFIG_VIDEO_ADV_DEBUG 1221 .vidioc_g_register = vidioc_g_register, 1222 .vidioc_s_register = vidioc_s_register, 1223 #endif 1224 }; 1225 1226 static const struct video_device cx8800_vbi_template = { 1227 .name = "cx8800-vbi", 1228 .fops = &video_fops, 1229 .ioctl_ops = &vbi_ioctl_ops, 1230 .tvnorms = CX88_NORMS, 1231 }; 1232 1233 static const struct v4l2_file_operations radio_fops = 1234 { 1235 .owner = THIS_MODULE, 1236 .open = radio_open, 1237 .poll = v4l2_ctrl_poll, 1238 .release = v4l2_fh_release, 1239 .unlocked_ioctl = video_ioctl2, 1240 }; 1241 1242 static const struct v4l2_ioctl_ops radio_ioctl_ops = { 1243 .vidioc_querycap = vidioc_querycap, 1244 .vidioc_g_tuner = radio_g_tuner, 1245 .vidioc_s_tuner = radio_s_tuner, 1246 .vidioc_g_frequency = vidioc_g_frequency, 1247 .vidioc_s_frequency = vidioc_s_frequency, 1248 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, 1249 .vidioc_unsubscribe_event = v4l2_event_unsubscribe, 1250 #ifdef CONFIG_VIDEO_ADV_DEBUG 1251 .vidioc_g_register = vidioc_g_register, 1252 .vidioc_s_register = vidioc_s_register, 1253 #endif 1254 }; 1255 1256 static const struct video_device cx8800_radio_template = { 1257 .name = "cx8800-radio", 1258 .fops = &radio_fops, 1259 .ioctl_ops = &radio_ioctl_ops, 1260 }; 1261 1262 static const struct v4l2_ctrl_ops cx8800_ctrl_vid_ops = { 1263 .s_ctrl = cx8800_s_vid_ctrl, 1264 }; 1265 1266 static const struct v4l2_ctrl_ops cx8800_ctrl_aud_ops = { 1267 .s_ctrl = cx8800_s_aud_ctrl, 1268 }; 1269 1270 /* ----------------------------------------------------------- */ 1271 1272 static void cx8800_unregister_video(struct cx8800_dev *dev) 1273 { 1274 video_unregister_device(&dev->radio_dev); 1275 video_unregister_device(&dev->vbi_dev); 1276 video_unregister_device(&dev->video_dev); 1277 } 1278 1279 static int cx8800_initdev(struct pci_dev *pci_dev, 1280 const struct pci_device_id *pci_id) 1281 { 1282 struct cx8800_dev *dev; 1283 struct cx88_core *core; 1284 struct vb2_queue *q; 1285 int err; 1286 int i; 1287 1288 dev = kzalloc(sizeof(*dev),GFP_KERNEL); 1289 if (NULL == dev) 1290 return -ENOMEM; 1291 1292 /* pci init */ 1293 dev->pci = pci_dev; 1294 if (pci_enable_device(pci_dev)) { 1295 err = -EIO; 1296 goto fail_free; 1297 } 1298 core = cx88_core_get(dev->pci); 1299 if (NULL == core) { 1300 err = -EINVAL; 1301 goto fail_free; 1302 } 1303 dev->core = core; 1304 1305 /* print pci info */ 1306 dev->pci_rev = pci_dev->revision; 1307 pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &dev->pci_lat); 1308 printk(KERN_INFO "%s/0: found at %s, rev: %d, irq: %d, " 1309 "latency: %d, mmio: 0x%llx\n", core->name, 1310 pci_name(pci_dev), dev->pci_rev, pci_dev->irq, 1311 dev->pci_lat,(unsigned long long)pci_resource_start(pci_dev,0)); 1312 1313 pci_set_master(pci_dev); 1314 if (!pci_dma_supported(pci_dev,DMA_BIT_MASK(32))) { 1315 printk("%s/0: Oops: no 32bit PCI DMA ???\n",core->name); 1316 err = -EIO; 1317 goto fail_core; 1318 } 1319 dev->alloc_ctx = vb2_dma_sg_init_ctx(&pci_dev->dev); 1320 if (IS_ERR(dev->alloc_ctx)) { 1321 err = PTR_ERR(dev->alloc_ctx); 1322 goto fail_core; 1323 } 1324 1325 1326 /* initialize driver struct */ 1327 spin_lock_init(&dev->slock); 1328 1329 /* init video dma queues */ 1330 INIT_LIST_HEAD(&dev->vidq.active); 1331 1332 /* init vbi dma queues */ 1333 INIT_LIST_HEAD(&dev->vbiq.active); 1334 1335 /* get irq */ 1336 err = request_irq(pci_dev->irq, cx8800_irq, 1337 IRQF_SHARED, core->name, dev); 1338 if (err < 0) { 1339 printk(KERN_ERR "%s/0: can't get IRQ %d\n", 1340 core->name,pci_dev->irq); 1341 goto fail_core; 1342 } 1343 cx_set(MO_PCI_INTMSK, core->pci_irqmask); 1344 1345 for (i = 0; i < CX8800_AUD_CTLS; i++) { 1346 const struct cx88_ctrl *cc = &cx8800_aud_ctls[i]; 1347 struct v4l2_ctrl *vc; 1348 1349 vc = v4l2_ctrl_new_std(&core->audio_hdl, &cx8800_ctrl_aud_ops, 1350 cc->id, cc->minimum, cc->maximum, cc->step, cc->default_value); 1351 if (vc == NULL) { 1352 err = core->audio_hdl.error; 1353 goto fail_core; 1354 } 1355 vc->priv = (void *)cc; 1356 } 1357 1358 for (i = 0; i < CX8800_VID_CTLS; i++) { 1359 const struct cx88_ctrl *cc = &cx8800_vid_ctls[i]; 1360 struct v4l2_ctrl *vc; 1361 1362 vc = v4l2_ctrl_new_std(&core->video_hdl, &cx8800_ctrl_vid_ops, 1363 cc->id, cc->minimum, cc->maximum, cc->step, cc->default_value); 1364 if (vc == NULL) { 1365 err = core->video_hdl.error; 1366 goto fail_core; 1367 } 1368 vc->priv = (void *)cc; 1369 if (vc->id == V4L2_CID_CHROMA_AGC) 1370 core->chroma_agc = vc; 1371 } 1372 v4l2_ctrl_add_handler(&core->video_hdl, &core->audio_hdl, NULL); 1373 1374 /* load and configure helper modules */ 1375 1376 if (core->board.audio_chip == CX88_AUDIO_WM8775) { 1377 struct i2c_board_info wm8775_info = { 1378 .type = "wm8775", 1379 .addr = 0x36 >> 1, 1380 .platform_data = &core->wm8775_data, 1381 }; 1382 struct v4l2_subdev *sd; 1383 1384 if (core->boardnr == CX88_BOARD_HAUPPAUGE_NOVASPLUS_S1) 1385 core->wm8775_data.is_nova_s = true; 1386 else 1387 core->wm8775_data.is_nova_s = false; 1388 1389 sd = v4l2_i2c_new_subdev_board(&core->v4l2_dev, &core->i2c_adap, 1390 &wm8775_info, NULL); 1391 if (sd != NULL) { 1392 core->sd_wm8775 = sd; 1393 sd->grp_id = WM8775_GID; 1394 } 1395 } 1396 1397 if (core->board.audio_chip == CX88_AUDIO_TVAUDIO) { 1398 /* This probes for a tda9874 as is used on some 1399 Pixelview Ultra boards. */ 1400 v4l2_i2c_new_subdev(&core->v4l2_dev, &core->i2c_adap, 1401 "tvaudio", 0, I2C_ADDRS(0xb0 >> 1)); 1402 } 1403 1404 switch (core->boardnr) { 1405 case CX88_BOARD_DVICO_FUSIONHDTV_5_GOLD: 1406 case CX88_BOARD_DVICO_FUSIONHDTV_7_GOLD: { 1407 static const struct i2c_board_info rtc_info = { 1408 I2C_BOARD_INFO("isl1208", 0x6f) 1409 }; 1410 1411 request_module("rtc-isl1208"); 1412 core->i2c_rtc = i2c_new_device(&core->i2c_adap, &rtc_info); 1413 } 1414 /* break intentionally omitted */ 1415 case CX88_BOARD_DVICO_FUSIONHDTV_5_PCI_NANO: 1416 request_module("ir-kbd-i2c"); 1417 } 1418 1419 /* Sets device info at pci_dev */ 1420 pci_set_drvdata(pci_dev, dev); 1421 1422 dev->fmt = format_by_fourcc(V4L2_PIX_FMT_BGR24); 1423 1424 /* Maintain a reference so cx88-blackbird can query the 8800 device. */ 1425 core->v4ldev = dev; 1426 1427 /* initial device configuration */ 1428 mutex_lock(&core->lock); 1429 cx88_set_tvnorm(core, core->tvnorm); 1430 v4l2_ctrl_handler_setup(&core->video_hdl); 1431 v4l2_ctrl_handler_setup(&core->audio_hdl); 1432 cx88_video_mux(core, 0); 1433 1434 q = &dev->vb2_vidq; 1435 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; 1436 q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF | VB2_READ; 1437 q->gfp_flags = GFP_DMA32; 1438 q->min_buffers_needed = 2; 1439 q->drv_priv = dev; 1440 q->buf_struct_size = sizeof(struct cx88_buffer); 1441 q->ops = &cx8800_video_qops; 1442 q->mem_ops = &vb2_dma_sg_memops; 1443 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; 1444 q->lock = &core->lock; 1445 1446 err = vb2_queue_init(q); 1447 if (err < 0) 1448 goto fail_unreg; 1449 1450 q = &dev->vb2_vbiq; 1451 q->type = V4L2_BUF_TYPE_VBI_CAPTURE; 1452 q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF | VB2_READ; 1453 q->gfp_flags = GFP_DMA32; 1454 q->min_buffers_needed = 2; 1455 q->drv_priv = dev; 1456 q->buf_struct_size = sizeof(struct cx88_buffer); 1457 q->ops = &cx8800_vbi_qops; 1458 q->mem_ops = &vb2_dma_sg_memops; 1459 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; 1460 q->lock = &core->lock; 1461 1462 err = vb2_queue_init(q); 1463 if (err < 0) 1464 goto fail_unreg; 1465 1466 /* register v4l devices */ 1467 cx88_vdev_init(core, dev->pci, &dev->video_dev, 1468 &cx8800_video_template, "video"); 1469 video_set_drvdata(&dev->video_dev, dev); 1470 dev->video_dev.ctrl_handler = &core->video_hdl; 1471 dev->video_dev.queue = &dev->vb2_vidq; 1472 err = video_register_device(&dev->video_dev, VFL_TYPE_GRABBER, 1473 video_nr[core->nr]); 1474 if (err < 0) { 1475 printk(KERN_ERR "%s/0: can't register video device\n", 1476 core->name); 1477 goto fail_unreg; 1478 } 1479 printk(KERN_INFO "%s/0: registered device %s [v4l2]\n", 1480 core->name, video_device_node_name(&dev->video_dev)); 1481 1482 cx88_vdev_init(core, dev->pci, &dev->vbi_dev, 1483 &cx8800_vbi_template, "vbi"); 1484 video_set_drvdata(&dev->vbi_dev, dev); 1485 dev->vbi_dev.queue = &dev->vb2_vbiq; 1486 err = video_register_device(&dev->vbi_dev, VFL_TYPE_VBI, 1487 vbi_nr[core->nr]); 1488 if (err < 0) { 1489 printk(KERN_ERR "%s/0: can't register vbi device\n", 1490 core->name); 1491 goto fail_unreg; 1492 } 1493 printk(KERN_INFO "%s/0: registered device %s\n", 1494 core->name, video_device_node_name(&dev->vbi_dev)); 1495 1496 if (core->board.radio.type == CX88_RADIO) { 1497 cx88_vdev_init(core, dev->pci, &dev->radio_dev, 1498 &cx8800_radio_template, "radio"); 1499 video_set_drvdata(&dev->radio_dev, dev); 1500 dev->radio_dev.ctrl_handler = &core->audio_hdl; 1501 err = video_register_device(&dev->radio_dev, VFL_TYPE_RADIO, 1502 radio_nr[core->nr]); 1503 if (err < 0) { 1504 printk(KERN_ERR "%s/0: can't register radio device\n", 1505 core->name); 1506 goto fail_unreg; 1507 } 1508 printk(KERN_INFO "%s/0: registered device %s\n", 1509 core->name, video_device_node_name(&dev->radio_dev)); 1510 } 1511 1512 /* start tvaudio thread */ 1513 if (core->board.tuner_type != UNSET) { 1514 core->kthread = kthread_run(cx88_audio_thread, core, "cx88 tvaudio"); 1515 if (IS_ERR(core->kthread)) { 1516 err = PTR_ERR(core->kthread); 1517 printk(KERN_ERR "%s/0: failed to create cx88 audio thread, err=%d\n", 1518 core->name, err); 1519 } 1520 } 1521 mutex_unlock(&core->lock); 1522 1523 return 0; 1524 1525 fail_unreg: 1526 cx8800_unregister_video(dev); 1527 free_irq(pci_dev->irq, dev); 1528 mutex_unlock(&core->lock); 1529 fail_core: 1530 vb2_dma_sg_cleanup_ctx(dev->alloc_ctx); 1531 core->v4ldev = NULL; 1532 cx88_core_put(core,dev->pci); 1533 fail_free: 1534 kfree(dev); 1535 return err; 1536 } 1537 1538 static void cx8800_finidev(struct pci_dev *pci_dev) 1539 { 1540 struct cx8800_dev *dev = pci_get_drvdata(pci_dev); 1541 struct cx88_core *core = dev->core; 1542 1543 /* stop thread */ 1544 if (core->kthread) { 1545 kthread_stop(core->kthread); 1546 core->kthread = NULL; 1547 } 1548 1549 if (core->ir) 1550 cx88_ir_stop(core); 1551 1552 cx88_shutdown(core); /* FIXME */ 1553 1554 /* unregister stuff */ 1555 1556 free_irq(pci_dev->irq, dev); 1557 cx8800_unregister_video(dev); 1558 pci_disable_device(pci_dev); 1559 1560 core->v4ldev = NULL; 1561 1562 /* free memory */ 1563 cx88_core_put(core,dev->pci); 1564 vb2_dma_sg_cleanup_ctx(dev->alloc_ctx); 1565 kfree(dev); 1566 } 1567 1568 #ifdef CONFIG_PM 1569 static int cx8800_suspend(struct pci_dev *pci_dev, pm_message_t state) 1570 { 1571 struct cx8800_dev *dev = pci_get_drvdata(pci_dev); 1572 struct cx88_core *core = dev->core; 1573 unsigned long flags; 1574 1575 /* stop video+vbi capture */ 1576 spin_lock_irqsave(&dev->slock, flags); 1577 if (!list_empty(&dev->vidq.active)) { 1578 printk("%s/0: suspend video\n", core->name); 1579 stop_video_dma(dev); 1580 } 1581 if (!list_empty(&dev->vbiq.active)) { 1582 printk("%s/0: suspend vbi\n", core->name); 1583 cx8800_stop_vbi_dma(dev); 1584 } 1585 spin_unlock_irqrestore(&dev->slock, flags); 1586 1587 if (core->ir) 1588 cx88_ir_stop(core); 1589 /* FIXME -- shutdown device */ 1590 cx88_shutdown(core); 1591 1592 pci_save_state(pci_dev); 1593 if (0 != pci_set_power_state(pci_dev, pci_choose_state(pci_dev, state))) { 1594 pci_disable_device(pci_dev); 1595 dev->state.disabled = 1; 1596 } 1597 return 0; 1598 } 1599 1600 static int cx8800_resume(struct pci_dev *pci_dev) 1601 { 1602 struct cx8800_dev *dev = pci_get_drvdata(pci_dev); 1603 struct cx88_core *core = dev->core; 1604 unsigned long flags; 1605 int err; 1606 1607 if (dev->state.disabled) { 1608 err=pci_enable_device(pci_dev); 1609 if (err) { 1610 printk(KERN_ERR "%s/0: can't enable device\n", 1611 core->name); 1612 return err; 1613 } 1614 1615 dev->state.disabled = 0; 1616 } 1617 err= pci_set_power_state(pci_dev, PCI_D0); 1618 if (err) { 1619 printk(KERN_ERR "%s/0: can't set power state\n", core->name); 1620 pci_disable_device(pci_dev); 1621 dev->state.disabled = 1; 1622 1623 return err; 1624 } 1625 pci_restore_state(pci_dev); 1626 1627 /* FIXME: re-initialize hardware */ 1628 cx88_reset(core); 1629 if (core->ir) 1630 cx88_ir_start(core); 1631 1632 cx_set(MO_PCI_INTMSK, core->pci_irqmask); 1633 1634 /* restart video+vbi capture */ 1635 spin_lock_irqsave(&dev->slock, flags); 1636 if (!list_empty(&dev->vidq.active)) { 1637 printk("%s/0: resume video\n", core->name); 1638 restart_video_queue(dev,&dev->vidq); 1639 } 1640 if (!list_empty(&dev->vbiq.active)) { 1641 printk("%s/0: resume vbi\n", core->name); 1642 cx8800_restart_vbi_queue(dev,&dev->vbiq); 1643 } 1644 spin_unlock_irqrestore(&dev->slock, flags); 1645 1646 return 0; 1647 } 1648 #endif 1649 1650 /* ----------------------------------------------------------- */ 1651 1652 static const struct pci_device_id cx8800_pci_tbl[] = { 1653 { 1654 .vendor = 0x14f1, 1655 .device = 0x8800, 1656 .subvendor = PCI_ANY_ID, 1657 .subdevice = PCI_ANY_ID, 1658 },{ 1659 /* --- end of list --- */ 1660 } 1661 }; 1662 MODULE_DEVICE_TABLE(pci, cx8800_pci_tbl); 1663 1664 static struct pci_driver cx8800_pci_driver = { 1665 .name = "cx8800", 1666 .id_table = cx8800_pci_tbl, 1667 .probe = cx8800_initdev, 1668 .remove = cx8800_finidev, 1669 #ifdef CONFIG_PM 1670 .suspend = cx8800_suspend, 1671 .resume = cx8800_resume, 1672 #endif 1673 }; 1674 1675 module_pci_driver(cx8800_pci_driver); 1676