1 /* 2 * 3 * device driver for Conexant 2388x based TV cards 4 * driver core 5 * 6 * (c) 2003 Gerd Knorr <kraxel@bytesex.org> [SuSE Labs] 7 * 8 * (c) 2005-2006 Mauro Carvalho Chehab <mchehab@infradead.org> 9 * - Multituner support 10 * - video_ioctl2 conversion 11 * - PAL/M fixes 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of the GNU General Public License as published by 15 * the Free Software Foundation; either version 2 of the License, or 16 * (at your option) any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License 24 * along with this program; if not, write to the Free Software 25 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 26 */ 27 28 #include <linux/init.h> 29 #include <linux/list.h> 30 #include <linux/module.h> 31 #include <linux/kernel.h> 32 #include <linux/slab.h> 33 #include <linux/kmod.h> 34 #include <linux/sound.h> 35 #include <linux/interrupt.h> 36 #include <linux/pci.h> 37 #include <linux/delay.h> 38 #include <linux/videodev2.h> 39 #include <linux/mutex.h> 40 41 #include "cx88.h" 42 #include <media/v4l2-common.h> 43 #include <media/v4l2-ioctl.h> 44 45 MODULE_DESCRIPTION("v4l2 driver module for cx2388x based TV cards"); 46 MODULE_AUTHOR("Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]"); 47 MODULE_LICENSE("GPL"); 48 49 /* ------------------------------------------------------------------ */ 50 51 unsigned int cx88_core_debug; 52 module_param_named(core_debug, cx88_core_debug, int, 0644); 53 MODULE_PARM_DESC(core_debug, "enable debug messages [core]"); 54 55 static unsigned int nicam; 56 module_param(nicam,int,0644); 57 MODULE_PARM_DESC(nicam,"tv audio is nicam"); 58 59 static unsigned int nocomb; 60 module_param(nocomb,int,0644); 61 MODULE_PARM_DESC(nocomb,"disable comb filter"); 62 63 #define dprintk(level,fmt, arg...) do { \ 64 if (cx88_core_debug >= level) \ 65 printk(KERN_DEBUG "%s: " fmt, core->name , ## arg); \ 66 } while(0) 67 68 static unsigned int cx88_devcount; 69 static LIST_HEAD(cx88_devlist); 70 static DEFINE_MUTEX(devlist); 71 72 #define NO_SYNC_LINE (-1U) 73 74 /* @lpi: lines per IRQ, or 0 to not generate irqs. Note: IRQ to be 75 generated _after_ lpi lines are transferred. */ 76 static __le32* cx88_risc_field(__le32 *rp, struct scatterlist *sglist, 77 unsigned int offset, u32 sync_line, 78 unsigned int bpl, unsigned int padding, 79 unsigned int lines, unsigned int lpi, bool jump) 80 { 81 struct scatterlist *sg; 82 unsigned int line,todo,sol; 83 84 if (jump) { 85 (*rp++) = cpu_to_le32(RISC_JUMP); 86 (*rp++) = 0; 87 } 88 89 /* sync instruction */ 90 if (sync_line != NO_SYNC_LINE) 91 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line); 92 93 /* scan lines */ 94 sg = sglist; 95 for (line = 0; line < lines; line++) { 96 while (offset && offset >= sg_dma_len(sg)) { 97 offset -= sg_dma_len(sg); 98 sg = sg_next(sg); 99 } 100 if (lpi && line>0 && !(line % lpi)) 101 sol = RISC_SOL | RISC_IRQ1 | RISC_CNT_INC; 102 else 103 sol = RISC_SOL; 104 if (bpl <= sg_dma_len(sg)-offset) { 105 /* fits into current chunk */ 106 *(rp++)=cpu_to_le32(RISC_WRITE|sol|RISC_EOL|bpl); 107 *(rp++)=cpu_to_le32(sg_dma_address(sg)+offset); 108 offset+=bpl; 109 } else { 110 /* scanline needs to be split */ 111 todo = bpl; 112 *(rp++)=cpu_to_le32(RISC_WRITE|sol| 113 (sg_dma_len(sg)-offset)); 114 *(rp++)=cpu_to_le32(sg_dma_address(sg)+offset); 115 todo -= (sg_dma_len(sg)-offset); 116 offset = 0; 117 sg = sg_next(sg); 118 while (todo > sg_dma_len(sg)) { 119 *(rp++)=cpu_to_le32(RISC_WRITE| 120 sg_dma_len(sg)); 121 *(rp++)=cpu_to_le32(sg_dma_address(sg)); 122 todo -= sg_dma_len(sg); 123 sg = sg_next(sg); 124 } 125 *(rp++)=cpu_to_le32(RISC_WRITE|RISC_EOL|todo); 126 *(rp++)=cpu_to_le32(sg_dma_address(sg)); 127 offset += todo; 128 } 129 offset += padding; 130 } 131 132 return rp; 133 } 134 135 int cx88_risc_buffer(struct pci_dev *pci, struct cx88_riscmem *risc, 136 struct scatterlist *sglist, 137 unsigned int top_offset, unsigned int bottom_offset, 138 unsigned int bpl, unsigned int padding, unsigned int lines) 139 { 140 u32 instructions,fields; 141 __le32 *rp; 142 143 fields = 0; 144 if (UNSET != top_offset) 145 fields++; 146 if (UNSET != bottom_offset) 147 fields++; 148 149 /* estimate risc mem: worst case is one write per page border + 150 one write per scan line + syncs + jump (all 2 dwords). Padding 151 can cause next bpl to start close to a page border. First DMA 152 region may be smaller than PAGE_SIZE */ 153 instructions = fields * (1 + ((bpl + padding) * lines) / PAGE_SIZE + lines); 154 instructions += 4; 155 risc->size = instructions * 8; 156 risc->dma = 0; 157 risc->cpu = pci_zalloc_consistent(pci, risc->size, &risc->dma); 158 if (NULL == risc->cpu) 159 return -ENOMEM; 160 161 /* write risc instructions */ 162 rp = risc->cpu; 163 if (UNSET != top_offset) 164 rp = cx88_risc_field(rp, sglist, top_offset, 0, 165 bpl, padding, lines, 0, true); 166 if (UNSET != bottom_offset) 167 rp = cx88_risc_field(rp, sglist, bottom_offset, 0x200, 168 bpl, padding, lines, 0, top_offset == UNSET); 169 170 /* save pointer to jmp instruction address */ 171 risc->jmp = rp; 172 BUG_ON((risc->jmp - risc->cpu + 2) * sizeof (*risc->cpu) > risc->size); 173 return 0; 174 } 175 176 int cx88_risc_databuffer(struct pci_dev *pci, struct cx88_riscmem *risc, 177 struct scatterlist *sglist, unsigned int bpl, 178 unsigned int lines, unsigned int lpi) 179 { 180 u32 instructions; 181 __le32 *rp; 182 183 /* estimate risc mem: worst case is one write per page border + 184 one write per scan line + syncs + jump (all 2 dwords). Here 185 there is no padding and no sync. First DMA region may be smaller 186 than PAGE_SIZE */ 187 instructions = 1 + (bpl * lines) / PAGE_SIZE + lines; 188 instructions += 3; 189 risc->size = instructions * 8; 190 risc->dma = 0; 191 risc->cpu = pci_zalloc_consistent(pci, risc->size, &risc->dma); 192 if (NULL == risc->cpu) 193 return -ENOMEM; 194 195 /* write risc instructions */ 196 rp = risc->cpu; 197 rp = cx88_risc_field(rp, sglist, 0, NO_SYNC_LINE, bpl, 0, lines, lpi, !lpi); 198 199 /* save pointer to jmp instruction address */ 200 risc->jmp = rp; 201 BUG_ON((risc->jmp - risc->cpu + 2) * sizeof (*risc->cpu) > risc->size); 202 return 0; 203 } 204 205 /* ------------------------------------------------------------------ */ 206 /* our SRAM memory layout */ 207 208 /* we are going to put all thr risc programs into host memory, so we 209 * can use the whole SDRAM for the DMA fifos. To simplify things, we 210 * use a static memory layout. That surely will waste memory in case 211 * we don't use all DMA channels at the same time (which will be the 212 * case most of the time). But that still gives us enough FIFO space 213 * to be able to deal with insane long pci latencies ... 214 * 215 * FIFO space allocations: 216 * channel 21 (y video) - 10.0k 217 * channel 22 (u video) - 2.0k 218 * channel 23 (v video) - 2.0k 219 * channel 24 (vbi) - 4.0k 220 * channels 25+26 (audio) - 4.0k 221 * channel 28 (mpeg) - 4.0k 222 * channel 27 (audio rds)- 3.0k 223 * TOTAL = 29.0k 224 * 225 * Every channel has 160 bytes control data (64 bytes instruction 226 * queue and 6 CDT entries), which is close to 2k total. 227 * 228 * Address layout: 229 * 0x0000 - 0x03ff CMDs / reserved 230 * 0x0400 - 0x0bff instruction queues + CDs 231 * 0x0c00 - FIFOs 232 */ 233 234 const struct sram_channel cx88_sram_channels[] = { 235 [SRAM_CH21] = { 236 .name = "video y / packed", 237 .cmds_start = 0x180040, 238 .ctrl_start = 0x180400, 239 .cdt = 0x180400 + 64, 240 .fifo_start = 0x180c00, 241 .fifo_size = 0x002800, 242 .ptr1_reg = MO_DMA21_PTR1, 243 .ptr2_reg = MO_DMA21_PTR2, 244 .cnt1_reg = MO_DMA21_CNT1, 245 .cnt2_reg = MO_DMA21_CNT2, 246 }, 247 [SRAM_CH22] = { 248 .name = "video u", 249 .cmds_start = 0x180080, 250 .ctrl_start = 0x1804a0, 251 .cdt = 0x1804a0 + 64, 252 .fifo_start = 0x183400, 253 .fifo_size = 0x000800, 254 .ptr1_reg = MO_DMA22_PTR1, 255 .ptr2_reg = MO_DMA22_PTR2, 256 .cnt1_reg = MO_DMA22_CNT1, 257 .cnt2_reg = MO_DMA22_CNT2, 258 }, 259 [SRAM_CH23] = { 260 .name = "video v", 261 .cmds_start = 0x1800c0, 262 .ctrl_start = 0x180540, 263 .cdt = 0x180540 + 64, 264 .fifo_start = 0x183c00, 265 .fifo_size = 0x000800, 266 .ptr1_reg = MO_DMA23_PTR1, 267 .ptr2_reg = MO_DMA23_PTR2, 268 .cnt1_reg = MO_DMA23_CNT1, 269 .cnt2_reg = MO_DMA23_CNT2, 270 }, 271 [SRAM_CH24] = { 272 .name = "vbi", 273 .cmds_start = 0x180100, 274 .ctrl_start = 0x1805e0, 275 .cdt = 0x1805e0 + 64, 276 .fifo_start = 0x184400, 277 .fifo_size = 0x001000, 278 .ptr1_reg = MO_DMA24_PTR1, 279 .ptr2_reg = MO_DMA24_PTR2, 280 .cnt1_reg = MO_DMA24_CNT1, 281 .cnt2_reg = MO_DMA24_CNT2, 282 }, 283 [SRAM_CH25] = { 284 .name = "audio from", 285 .cmds_start = 0x180140, 286 .ctrl_start = 0x180680, 287 .cdt = 0x180680 + 64, 288 .fifo_start = 0x185400, 289 .fifo_size = 0x001000, 290 .ptr1_reg = MO_DMA25_PTR1, 291 .ptr2_reg = MO_DMA25_PTR2, 292 .cnt1_reg = MO_DMA25_CNT1, 293 .cnt2_reg = MO_DMA25_CNT2, 294 }, 295 [SRAM_CH26] = { 296 .name = "audio to", 297 .cmds_start = 0x180180, 298 .ctrl_start = 0x180720, 299 .cdt = 0x180680 + 64, /* same as audio IN */ 300 .fifo_start = 0x185400, /* same as audio IN */ 301 .fifo_size = 0x001000, /* same as audio IN */ 302 .ptr1_reg = MO_DMA26_PTR1, 303 .ptr2_reg = MO_DMA26_PTR2, 304 .cnt1_reg = MO_DMA26_CNT1, 305 .cnt2_reg = MO_DMA26_CNT2, 306 }, 307 [SRAM_CH28] = { 308 .name = "mpeg", 309 .cmds_start = 0x180200, 310 .ctrl_start = 0x1807C0, 311 .cdt = 0x1807C0 + 64, 312 .fifo_start = 0x186400, 313 .fifo_size = 0x001000, 314 .ptr1_reg = MO_DMA28_PTR1, 315 .ptr2_reg = MO_DMA28_PTR2, 316 .cnt1_reg = MO_DMA28_CNT1, 317 .cnt2_reg = MO_DMA28_CNT2, 318 }, 319 [SRAM_CH27] = { 320 .name = "audio rds", 321 .cmds_start = 0x1801C0, 322 .ctrl_start = 0x180860, 323 .cdt = 0x180860 + 64, 324 .fifo_start = 0x187400, 325 .fifo_size = 0x000C00, 326 .ptr1_reg = MO_DMA27_PTR1, 327 .ptr2_reg = MO_DMA27_PTR2, 328 .cnt1_reg = MO_DMA27_CNT1, 329 .cnt2_reg = MO_DMA27_CNT2, 330 }, 331 }; 332 333 int cx88_sram_channel_setup(struct cx88_core *core, 334 const struct sram_channel *ch, 335 unsigned int bpl, u32 risc) 336 { 337 unsigned int i,lines; 338 u32 cdt; 339 340 bpl = (bpl + 7) & ~7; /* alignment */ 341 cdt = ch->cdt; 342 lines = ch->fifo_size / bpl; 343 if (lines > 6) 344 lines = 6; 345 BUG_ON(lines < 2); 346 347 /* write CDT */ 348 for (i = 0; i < lines; i++) 349 cx_write(cdt + 16*i, ch->fifo_start + bpl*i); 350 351 /* write CMDS */ 352 cx_write(ch->cmds_start + 0, risc); 353 cx_write(ch->cmds_start + 4, cdt); 354 cx_write(ch->cmds_start + 8, (lines*16) >> 3); 355 cx_write(ch->cmds_start + 12, ch->ctrl_start); 356 cx_write(ch->cmds_start + 16, 64 >> 2); 357 for (i = 20; i < 64; i += 4) 358 cx_write(ch->cmds_start + i, 0); 359 360 /* fill registers */ 361 cx_write(ch->ptr1_reg, ch->fifo_start); 362 cx_write(ch->ptr2_reg, cdt); 363 cx_write(ch->cnt1_reg, (bpl >> 3) -1); 364 cx_write(ch->cnt2_reg, (lines*16) >> 3); 365 366 dprintk(2,"sram setup %s: bpl=%d lines=%d\n", ch->name, bpl, lines); 367 return 0; 368 } 369 370 /* ------------------------------------------------------------------ */ 371 /* debug helper code */ 372 373 static int cx88_risc_decode(u32 risc) 374 { 375 static const char * const instr[16] = { 376 [ RISC_SYNC >> 28 ] = "sync", 377 [ RISC_WRITE >> 28 ] = "write", 378 [ RISC_WRITEC >> 28 ] = "writec", 379 [ RISC_READ >> 28 ] = "read", 380 [ RISC_READC >> 28 ] = "readc", 381 [ RISC_JUMP >> 28 ] = "jump", 382 [ RISC_SKIP >> 28 ] = "skip", 383 [ RISC_WRITERM >> 28 ] = "writerm", 384 [ RISC_WRITECM >> 28 ] = "writecm", 385 [ RISC_WRITECR >> 28 ] = "writecr", 386 }; 387 static int const incr[16] = { 388 [ RISC_WRITE >> 28 ] = 2, 389 [ RISC_JUMP >> 28 ] = 2, 390 [ RISC_WRITERM >> 28 ] = 3, 391 [ RISC_WRITECM >> 28 ] = 3, 392 [ RISC_WRITECR >> 28 ] = 4, 393 }; 394 static const char * const bits[] = { 395 "12", "13", "14", "resync", 396 "cnt0", "cnt1", "18", "19", 397 "20", "21", "22", "23", 398 "irq1", "irq2", "eol", "sol", 399 }; 400 int i; 401 402 printk("0x%08x [ %s", risc, 403 instr[risc >> 28] ? instr[risc >> 28] : "INVALID"); 404 for (i = ARRAY_SIZE(bits)-1; i >= 0; i--) 405 if (risc & (1 << (i + 12))) 406 printk(" %s",bits[i]); 407 printk(" count=%d ]\n", risc & 0xfff); 408 return incr[risc >> 28] ? incr[risc >> 28] : 1; 409 } 410 411 412 void cx88_sram_channel_dump(struct cx88_core *core, 413 const struct sram_channel *ch) 414 { 415 static const char * const name[] = { 416 "initial risc", 417 "cdt base", 418 "cdt size", 419 "iq base", 420 "iq size", 421 "risc pc", 422 "iq wr ptr", 423 "iq rd ptr", 424 "cdt current", 425 "pci target", 426 "line / byte", 427 }; 428 u32 risc; 429 unsigned int i,j,n; 430 431 printk("%s: %s - dma channel status dump\n", 432 core->name,ch->name); 433 for (i = 0; i < ARRAY_SIZE(name); i++) 434 printk("%s: cmds: %-12s: 0x%08x\n", 435 core->name,name[i], 436 cx_read(ch->cmds_start + 4*i)); 437 for (n = 1, i = 0; i < 4; i++) { 438 risc = cx_read(ch->cmds_start + 4 * (i+11)); 439 printk("%s: risc%d: ", core->name, i); 440 if (--n) 441 printk("0x%08x [ arg #%d ]\n", risc, n); 442 else 443 n = cx88_risc_decode(risc); 444 } 445 for (i = 0; i < 16; i += n) { 446 risc = cx_read(ch->ctrl_start + 4 * i); 447 printk("%s: iq %x: ", core->name, i); 448 n = cx88_risc_decode(risc); 449 for (j = 1; j < n; j++) { 450 risc = cx_read(ch->ctrl_start + 4 * (i+j)); 451 printk("%s: iq %x: 0x%08x [ arg #%d ]\n", 452 core->name, i+j, risc, j); 453 } 454 } 455 456 printk("%s: fifo: 0x%08x -> 0x%x\n", 457 core->name, ch->fifo_start, ch->fifo_start+ch->fifo_size); 458 printk("%s: ctrl: 0x%08x -> 0x%x\n", 459 core->name, ch->ctrl_start, ch->ctrl_start+6*16); 460 printk("%s: ptr1_reg: 0x%08x\n", 461 core->name,cx_read(ch->ptr1_reg)); 462 printk("%s: ptr2_reg: 0x%08x\n", 463 core->name,cx_read(ch->ptr2_reg)); 464 printk("%s: cnt1_reg: 0x%08x\n", 465 core->name,cx_read(ch->cnt1_reg)); 466 printk("%s: cnt2_reg: 0x%08x\n", 467 core->name,cx_read(ch->cnt2_reg)); 468 } 469 470 static const char *cx88_pci_irqs[32] = { 471 "vid", "aud", "ts", "vip", "hst", "5", "6", "tm1", 472 "src_dma", "dst_dma", "risc_rd_err", "risc_wr_err", 473 "brdg_err", "src_dma_err", "dst_dma_err", "ipb_dma_err", 474 "i2c", "i2c_rack", "ir_smp", "gpio0", "gpio1" 475 }; 476 477 void cx88_print_irqbits(const char *name, const char *tag, const char *strings[], 478 int len, u32 bits, u32 mask) 479 { 480 unsigned int i; 481 482 printk(KERN_DEBUG "%s: %s [0x%x]", name, tag, bits); 483 for (i = 0; i < len; i++) { 484 if (!(bits & (1 << i))) 485 continue; 486 if (strings[i]) 487 printk(" %s", strings[i]); 488 else 489 printk(" %d", i); 490 if (!(mask & (1 << i))) 491 continue; 492 printk("*"); 493 } 494 printk("\n"); 495 } 496 497 /* ------------------------------------------------------------------ */ 498 499 int cx88_core_irq(struct cx88_core *core, u32 status) 500 { 501 int handled = 0; 502 503 if (status & PCI_INT_IR_SMPINT) { 504 cx88_ir_irq(core); 505 handled++; 506 } 507 if (!handled) 508 cx88_print_irqbits(core->name, "irq pci", 509 cx88_pci_irqs, ARRAY_SIZE(cx88_pci_irqs), 510 status, core->pci_irqmask); 511 return handled; 512 } 513 514 void cx88_wakeup(struct cx88_core *core, 515 struct cx88_dmaqueue *q, u32 count) 516 { 517 struct cx88_buffer *buf; 518 519 buf = list_entry(q->active.next, 520 struct cx88_buffer, list); 521 buf->vb.vb2_buf.timestamp = ktime_get_ns(); 522 buf->vb.field = core->field; 523 buf->vb.sequence = q->count++; 524 list_del(&buf->list); 525 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_DONE); 526 } 527 528 void cx88_shutdown(struct cx88_core *core) 529 { 530 /* disable RISC controller + IRQs */ 531 cx_write(MO_DEV_CNTRL2, 0); 532 533 /* stop dma transfers */ 534 cx_write(MO_VID_DMACNTRL, 0x0); 535 cx_write(MO_AUD_DMACNTRL, 0x0); 536 cx_write(MO_TS_DMACNTRL, 0x0); 537 cx_write(MO_VIP_DMACNTRL, 0x0); 538 cx_write(MO_GPHST_DMACNTRL, 0x0); 539 540 /* stop interrupts */ 541 cx_write(MO_PCI_INTMSK, 0x0); 542 cx_write(MO_VID_INTMSK, 0x0); 543 cx_write(MO_AUD_INTMSK, 0x0); 544 cx_write(MO_TS_INTMSK, 0x0); 545 cx_write(MO_VIP_INTMSK, 0x0); 546 cx_write(MO_GPHST_INTMSK, 0x0); 547 548 /* stop capturing */ 549 cx_write(VID_CAPTURE_CONTROL, 0); 550 } 551 552 int cx88_reset(struct cx88_core *core) 553 { 554 dprintk(1,"%s\n",__func__); 555 cx88_shutdown(core); 556 557 /* clear irq status */ 558 cx_write(MO_VID_INTSTAT, 0xFFFFFFFF); // Clear PIV int 559 cx_write(MO_PCI_INTSTAT, 0xFFFFFFFF); // Clear PCI int 560 cx_write(MO_INT1_STAT, 0xFFFFFFFF); // Clear RISC int 561 562 /* wait a bit */ 563 msleep(100); 564 565 /* init sram */ 566 cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH21], 720*4, 0); 567 cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH22], 128, 0); 568 cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH23], 128, 0); 569 cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH24], 128, 0); 570 cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH25], 128, 0); 571 cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH26], 128, 0); 572 cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH28], 188*4, 0); 573 cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH27], 128, 0); 574 575 /* misc init ... */ 576 cx_write(MO_INPUT_FORMAT, ((1 << 13) | // agc enable 577 (1 << 12) | // agc gain 578 (1 << 11) | // adaptibe agc 579 (0 << 10) | // chroma agc 580 (0 << 9) | // ckillen 581 (7))); 582 583 /* setup image format */ 584 cx_andor(MO_COLOR_CTRL, 0x4000, 0x4000); 585 586 /* setup FIFO Thresholds */ 587 cx_write(MO_PDMA_STHRSH, 0x0807); 588 cx_write(MO_PDMA_DTHRSH, 0x0807); 589 590 /* fixes flashing of image */ 591 cx_write(MO_AGC_SYNC_TIP1, 0x0380000F); 592 cx_write(MO_AGC_BACK_VBI, 0x00E00555); 593 594 cx_write(MO_VID_INTSTAT, 0xFFFFFFFF); // Clear PIV int 595 cx_write(MO_PCI_INTSTAT, 0xFFFFFFFF); // Clear PCI int 596 cx_write(MO_INT1_STAT, 0xFFFFFFFF); // Clear RISC int 597 598 /* Reset on-board parts */ 599 cx_write(MO_SRST_IO, 0); 600 msleep(10); 601 cx_write(MO_SRST_IO, 1); 602 603 return 0; 604 } 605 606 /* ------------------------------------------------------------------ */ 607 608 static inline unsigned int norm_swidth(v4l2_std_id norm) 609 { 610 return (norm & (V4L2_STD_MN & ~V4L2_STD_PAL_Nc)) ? 754 : 922; 611 } 612 613 static inline unsigned int norm_hdelay(v4l2_std_id norm) 614 { 615 return (norm & (V4L2_STD_MN & ~V4L2_STD_PAL_Nc)) ? 135 : 186; 616 } 617 618 static inline unsigned int norm_vdelay(v4l2_std_id norm) 619 { 620 return (norm & V4L2_STD_625_50) ? 0x24 : 0x18; 621 } 622 623 static inline unsigned int norm_fsc8(v4l2_std_id norm) 624 { 625 if (norm & V4L2_STD_PAL_M) 626 return 28604892; // 3.575611 MHz 627 628 if (norm & (V4L2_STD_PAL_Nc)) 629 return 28656448; // 3.582056 MHz 630 631 if (norm & V4L2_STD_NTSC) // All NTSC/M and variants 632 return 28636360; // 3.57954545 MHz +/- 10 Hz 633 634 /* SECAM have also different sub carrier for chroma, 635 but step_db and step_dr, at cx88_set_tvnorm already handles that. 636 637 The same FSC applies to PAL/BGDKIH, PAL/60, NTSC/4.43 and PAL/N 638 */ 639 640 return 35468950; // 4.43361875 MHz +/- 5 Hz 641 } 642 643 static inline unsigned int norm_htotal(v4l2_std_id norm) 644 { 645 646 unsigned int fsc4=norm_fsc8(norm)/2; 647 648 /* returns 4*FSC / vtotal / frames per seconds */ 649 return (norm & V4L2_STD_625_50) ? 650 ((fsc4+312)/625+12)/25 : 651 ((fsc4+262)/525*1001+15000)/30000; 652 } 653 654 static inline unsigned int norm_vbipack(v4l2_std_id norm) 655 { 656 return (norm & V4L2_STD_625_50) ? 511 : 400; 657 } 658 659 int cx88_set_scale(struct cx88_core *core, unsigned int width, unsigned int height, 660 enum v4l2_field field) 661 { 662 unsigned int swidth = norm_swidth(core->tvnorm); 663 unsigned int sheight = norm_maxh(core->tvnorm); 664 u32 value; 665 666 dprintk(1,"set_scale: %dx%d [%s%s,%s]\n", width, height, 667 V4L2_FIELD_HAS_TOP(field) ? "T" : "", 668 V4L2_FIELD_HAS_BOTTOM(field) ? "B" : "", 669 v4l2_norm_to_name(core->tvnorm)); 670 if (!V4L2_FIELD_HAS_BOTH(field)) 671 height *= 2; 672 673 // recalc H delay and scale registers 674 value = (width * norm_hdelay(core->tvnorm)) / swidth; 675 value &= 0x3fe; 676 cx_write(MO_HDELAY_EVEN, value); 677 cx_write(MO_HDELAY_ODD, value); 678 dprintk(1,"set_scale: hdelay 0x%04x (width %d)\n", value,swidth); 679 680 value = (swidth * 4096 / width) - 4096; 681 cx_write(MO_HSCALE_EVEN, value); 682 cx_write(MO_HSCALE_ODD, value); 683 dprintk(1,"set_scale: hscale 0x%04x\n", value); 684 685 cx_write(MO_HACTIVE_EVEN, width); 686 cx_write(MO_HACTIVE_ODD, width); 687 dprintk(1,"set_scale: hactive 0x%04x\n", width); 688 689 // recalc V scale Register (delay is constant) 690 cx_write(MO_VDELAY_EVEN, norm_vdelay(core->tvnorm)); 691 cx_write(MO_VDELAY_ODD, norm_vdelay(core->tvnorm)); 692 dprintk(1,"set_scale: vdelay 0x%04x\n", norm_vdelay(core->tvnorm)); 693 694 value = (0x10000 - (sheight * 512 / height - 512)) & 0x1fff; 695 cx_write(MO_VSCALE_EVEN, value); 696 cx_write(MO_VSCALE_ODD, value); 697 dprintk(1,"set_scale: vscale 0x%04x\n", value); 698 699 cx_write(MO_VACTIVE_EVEN, sheight); 700 cx_write(MO_VACTIVE_ODD, sheight); 701 dprintk(1,"set_scale: vactive 0x%04x\n", sheight); 702 703 // setup filters 704 value = 0; 705 value |= (1 << 19); // CFILT (default) 706 if (core->tvnorm & V4L2_STD_SECAM) { 707 value |= (1 << 15); 708 value |= (1 << 16); 709 } 710 if (INPUT(core->input).type == CX88_VMUX_SVIDEO) 711 value |= (1 << 13) | (1 << 5); 712 if (V4L2_FIELD_INTERLACED == field) 713 value |= (1 << 3); // VINT (interlaced vertical scaling) 714 if (width < 385) 715 value |= (1 << 0); // 3-tap interpolation 716 if (width < 193) 717 value |= (1 << 1); // 5-tap interpolation 718 if (nocomb) 719 value |= (3 << 5); // disable comb filter 720 721 cx_andor(MO_FILTER_EVEN, 0x7ffc7f, value); /* preserve PEAKEN, PSEL */ 722 cx_andor(MO_FILTER_ODD, 0x7ffc7f, value); 723 dprintk(1,"set_scale: filter 0x%04x\n", value); 724 725 return 0; 726 } 727 728 static const u32 xtal = 28636363; 729 730 static int set_pll(struct cx88_core *core, int prescale, u32 ofreq) 731 { 732 static const u32 pre[] = { 0, 0, 0, 3, 2, 1 }; 733 u64 pll; 734 u32 reg; 735 int i; 736 737 if (prescale < 2) 738 prescale = 2; 739 if (prescale > 5) 740 prescale = 5; 741 742 pll = ofreq * 8 * prescale * (u64)(1 << 20); 743 do_div(pll,xtal); 744 reg = (pll & 0x3ffffff) | (pre[prescale] << 26); 745 if (((reg >> 20) & 0x3f) < 14) { 746 printk("%s/0: pll out of range\n",core->name); 747 return -1; 748 } 749 750 dprintk(1,"set_pll: MO_PLL_REG 0x%08x [old=0x%08x,freq=%d]\n", 751 reg, cx_read(MO_PLL_REG), ofreq); 752 cx_write(MO_PLL_REG, reg); 753 for (i = 0; i < 100; i++) { 754 reg = cx_read(MO_DEVICE_STATUS); 755 if (reg & (1<<2)) { 756 dprintk(1,"pll locked [pre=%d,ofreq=%d]\n", 757 prescale,ofreq); 758 return 0; 759 } 760 dprintk(1,"pll not locked yet, waiting ...\n"); 761 msleep(10); 762 } 763 dprintk(1,"pll NOT locked [pre=%d,ofreq=%d]\n",prescale,ofreq); 764 return -1; 765 } 766 767 int cx88_start_audio_dma(struct cx88_core *core) 768 { 769 /* constant 128 made buzz in analog Nicam-stereo for bigger fifo_size */ 770 int bpl = cx88_sram_channels[SRAM_CH25].fifo_size/4; 771 772 int rds_bpl = cx88_sram_channels[SRAM_CH27].fifo_size/AUD_RDS_LINES; 773 774 /* If downstream RISC is enabled, bail out; ALSA is managing DMA */ 775 if (cx_read(MO_AUD_DMACNTRL) & 0x10) 776 return 0; 777 778 /* setup fifo + format */ 779 cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH25], bpl, 0); 780 cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH26], bpl, 0); 781 cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH27], 782 rds_bpl, 0); 783 784 cx_write(MO_AUDD_LNGTH, bpl); /* fifo bpl size */ 785 cx_write(MO_AUDR_LNGTH, rds_bpl); /* fifo bpl size */ 786 787 /* enable Up, Down and Audio RDS fifo */ 788 cx_write(MO_AUD_DMACNTRL, 0x0007); 789 790 return 0; 791 } 792 793 int cx88_stop_audio_dma(struct cx88_core *core) 794 { 795 /* If downstream RISC is enabled, bail out; ALSA is managing DMA */ 796 if (cx_read(MO_AUD_DMACNTRL) & 0x10) 797 return 0; 798 799 /* stop dma */ 800 cx_write(MO_AUD_DMACNTRL, 0x0000); 801 802 return 0; 803 } 804 805 static int set_tvaudio(struct cx88_core *core) 806 { 807 v4l2_std_id norm = core->tvnorm; 808 809 if (CX88_VMUX_TELEVISION != INPUT(core->input).type && 810 CX88_VMUX_CABLE != INPUT(core->input).type) 811 return 0; 812 813 if (V4L2_STD_PAL_BG & norm) { 814 core->tvaudio = WW_BG; 815 816 } else if (V4L2_STD_PAL_DK & norm) { 817 core->tvaudio = WW_DK; 818 819 } else if (V4L2_STD_PAL_I & norm) { 820 core->tvaudio = WW_I; 821 822 } else if (V4L2_STD_SECAM_L & norm) { 823 core->tvaudio = WW_L; 824 825 } else if ((V4L2_STD_SECAM_B | V4L2_STD_SECAM_G | V4L2_STD_SECAM_H) & norm) { 826 core->tvaudio = WW_BG; 827 828 } else if (V4L2_STD_SECAM_DK & norm) { 829 core->tvaudio = WW_DK; 830 831 } else if ((V4L2_STD_NTSC_M & norm) || 832 (V4L2_STD_PAL_M & norm)) { 833 core->tvaudio = WW_BTSC; 834 835 } else if (V4L2_STD_NTSC_M_JP & norm) { 836 core->tvaudio = WW_EIAJ; 837 838 } else { 839 printk("%s/0: tvaudio support needs work for this tv norm [%s], sorry\n", 840 core->name, v4l2_norm_to_name(core->tvnorm)); 841 core->tvaudio = WW_NONE; 842 return 0; 843 } 844 845 cx_andor(MO_AFECFG_IO, 0x1f, 0x0); 846 cx88_set_tvaudio(core); 847 /* cx88_set_stereo(dev,V4L2_TUNER_MODE_STEREO); */ 848 849 /* 850 This should be needed only on cx88-alsa. It seems that some cx88 chips have 851 bugs and does require DMA enabled for it to work. 852 */ 853 cx88_start_audio_dma(core); 854 return 0; 855 } 856 857 858 859 int cx88_set_tvnorm(struct cx88_core *core, v4l2_std_id norm) 860 { 861 u32 fsc8; 862 u32 adc_clock; 863 u32 vdec_clock; 864 u32 step_db,step_dr; 865 u64 tmp64; 866 u32 bdelay,agcdelay,htotal; 867 u32 cxiformat, cxoformat; 868 869 if (norm == core->tvnorm) 870 return 0; 871 if (core->v4ldev && (vb2_is_busy(&core->v4ldev->vb2_vidq) || 872 vb2_is_busy(&core->v4ldev->vb2_vbiq))) 873 return -EBUSY; 874 if (core->dvbdev && vb2_is_busy(&core->dvbdev->vb2_mpegq)) 875 return -EBUSY; 876 core->tvnorm = norm; 877 fsc8 = norm_fsc8(norm); 878 adc_clock = xtal; 879 vdec_clock = fsc8; 880 step_db = fsc8; 881 step_dr = fsc8; 882 883 if (norm & V4L2_STD_NTSC_M_JP) { 884 cxiformat = VideoFormatNTSCJapan; 885 cxoformat = 0x181f0008; 886 } else if (norm & V4L2_STD_NTSC_443) { 887 cxiformat = VideoFormatNTSC443; 888 cxoformat = 0x181f0008; 889 } else if (norm & V4L2_STD_PAL_M) { 890 cxiformat = VideoFormatPALM; 891 cxoformat = 0x1c1f0008; 892 } else if (norm & V4L2_STD_PAL_N) { 893 cxiformat = VideoFormatPALN; 894 cxoformat = 0x1c1f0008; 895 } else if (norm & V4L2_STD_PAL_Nc) { 896 cxiformat = VideoFormatPALNC; 897 cxoformat = 0x1c1f0008; 898 } else if (norm & V4L2_STD_PAL_60) { 899 cxiformat = VideoFormatPAL60; 900 cxoformat = 0x181f0008; 901 } else if (norm & V4L2_STD_NTSC) { 902 cxiformat = VideoFormatNTSC; 903 cxoformat = 0x181f0008; 904 } else if (norm & V4L2_STD_SECAM) { 905 step_db = 4250000 * 8; 906 step_dr = 4406250 * 8; 907 908 cxiformat = VideoFormatSECAM; 909 cxoformat = 0x181f0008; 910 } else { /* PAL */ 911 cxiformat = VideoFormatPAL; 912 cxoformat = 0x181f0008; 913 } 914 915 dprintk(1,"set_tvnorm: \"%s\" fsc8=%d adc=%d vdec=%d db/dr=%d/%d\n", 916 v4l2_norm_to_name(core->tvnorm), fsc8, adc_clock, vdec_clock, 917 step_db, step_dr); 918 set_pll(core,2,vdec_clock); 919 920 dprintk(1,"set_tvnorm: MO_INPUT_FORMAT 0x%08x [old=0x%08x]\n", 921 cxiformat, cx_read(MO_INPUT_FORMAT) & 0x0f); 922 /* Chroma AGC must be disabled if SECAM is used, we enable it 923 by default on PAL and NTSC */ 924 cx_andor(MO_INPUT_FORMAT, 0x40f, 925 norm & V4L2_STD_SECAM ? cxiformat : cxiformat | 0x400); 926 927 // FIXME: as-is from DScaler 928 dprintk(1,"set_tvnorm: MO_OUTPUT_FORMAT 0x%08x [old=0x%08x]\n", 929 cxoformat, cx_read(MO_OUTPUT_FORMAT)); 930 cx_write(MO_OUTPUT_FORMAT, cxoformat); 931 932 // MO_SCONV_REG = adc clock / video dec clock * 2^17 933 tmp64 = adc_clock * (u64)(1 << 17); 934 do_div(tmp64, vdec_clock); 935 dprintk(1,"set_tvnorm: MO_SCONV_REG 0x%08x [old=0x%08x]\n", 936 (u32)tmp64, cx_read(MO_SCONV_REG)); 937 cx_write(MO_SCONV_REG, (u32)tmp64); 938 939 // MO_SUB_STEP = 8 * fsc / video dec clock * 2^22 940 tmp64 = step_db * (u64)(1 << 22); 941 do_div(tmp64, vdec_clock); 942 dprintk(1,"set_tvnorm: MO_SUB_STEP 0x%08x [old=0x%08x]\n", 943 (u32)tmp64, cx_read(MO_SUB_STEP)); 944 cx_write(MO_SUB_STEP, (u32)tmp64); 945 946 // MO_SUB_STEP_DR = 8 * 4406250 / video dec clock * 2^22 947 tmp64 = step_dr * (u64)(1 << 22); 948 do_div(tmp64, vdec_clock); 949 dprintk(1,"set_tvnorm: MO_SUB_STEP_DR 0x%08x [old=0x%08x]\n", 950 (u32)tmp64, cx_read(MO_SUB_STEP_DR)); 951 cx_write(MO_SUB_STEP_DR, (u32)tmp64); 952 953 // bdelay + agcdelay 954 bdelay = vdec_clock * 65 / 20000000 + 21; 955 agcdelay = vdec_clock * 68 / 20000000 + 15; 956 dprintk(1,"set_tvnorm: MO_AGC_BURST 0x%08x [old=0x%08x,bdelay=%d,agcdelay=%d]\n", 957 (bdelay << 8) | agcdelay, cx_read(MO_AGC_BURST), bdelay, agcdelay); 958 cx_write(MO_AGC_BURST, (bdelay << 8) | agcdelay); 959 960 // htotal 961 tmp64 = norm_htotal(norm) * (u64)vdec_clock; 962 do_div(tmp64, fsc8); 963 htotal = (u32)tmp64; 964 dprintk(1,"set_tvnorm: MO_HTOTAL 0x%08x [old=0x%08x,htotal=%d]\n", 965 htotal, cx_read(MO_HTOTAL), (u32)tmp64); 966 cx_andor(MO_HTOTAL, 0x07ff, htotal); 967 968 // vbi stuff, set vbi offset to 10 (for 20 Clk*2 pixels), this makes 969 // the effective vbi offset ~244 samples, the same as the Bt8x8 970 cx_write(MO_VBI_PACKET, (10<<11) | norm_vbipack(norm)); 971 972 // this is needed as well to set all tvnorm parameter 973 cx88_set_scale(core, 320, 240, V4L2_FIELD_INTERLACED); 974 975 // audio 976 set_tvaudio(core); 977 978 // tell i2c chips 979 call_all(core, video, s_std, norm); 980 981 /* The chroma_agc control should be inaccessible if the video format is SECAM */ 982 v4l2_ctrl_grab(core->chroma_agc, cxiformat == VideoFormatSECAM); 983 984 // done 985 return 0; 986 } 987 988 /* ------------------------------------------------------------------ */ 989 990 void cx88_vdev_init(struct cx88_core *core, 991 struct pci_dev *pci, 992 struct video_device *vfd, 993 const struct video_device *template_, 994 const char *type) 995 { 996 *vfd = *template_; 997 998 /* 999 * The dev pointer of v4l2_device is NULL, instead we set the 1000 * video_device dev_parent pointer to the correct PCI bus device. 1001 * This driver is a rare example where there is one v4l2_device, 1002 * but the video nodes have different parent (PCI) devices. 1003 */ 1004 vfd->v4l2_dev = &core->v4l2_dev; 1005 vfd->dev_parent = &pci->dev; 1006 vfd->release = video_device_release_empty; 1007 vfd->lock = &core->lock; 1008 snprintf(vfd->name, sizeof(vfd->name), "%s %s (%s)", 1009 core->name, type, core->board.name); 1010 } 1011 1012 struct cx88_core* cx88_core_get(struct pci_dev *pci) 1013 { 1014 struct cx88_core *core; 1015 1016 mutex_lock(&devlist); 1017 list_for_each_entry(core, &cx88_devlist, devlist) { 1018 if (pci->bus->number != core->pci_bus) 1019 continue; 1020 if (PCI_SLOT(pci->devfn) != core->pci_slot) 1021 continue; 1022 1023 if (0 != cx88_get_resources(core, pci)) { 1024 mutex_unlock(&devlist); 1025 return NULL; 1026 } 1027 atomic_inc(&core->refcount); 1028 mutex_unlock(&devlist); 1029 return core; 1030 } 1031 1032 core = cx88_core_create(pci, cx88_devcount); 1033 if (NULL != core) { 1034 cx88_devcount++; 1035 list_add_tail(&core->devlist, &cx88_devlist); 1036 } 1037 1038 mutex_unlock(&devlist); 1039 return core; 1040 } 1041 1042 void cx88_core_put(struct cx88_core *core, struct pci_dev *pci) 1043 { 1044 release_mem_region(pci_resource_start(pci,0), 1045 pci_resource_len(pci,0)); 1046 1047 if (!atomic_dec_and_test(&core->refcount)) 1048 return; 1049 1050 mutex_lock(&devlist); 1051 cx88_ir_fini(core); 1052 if (0 == core->i2c_rc) { 1053 if (core->i2c_rtc) 1054 i2c_unregister_device(core->i2c_rtc); 1055 i2c_del_adapter(&core->i2c_adap); 1056 } 1057 list_del(&core->devlist); 1058 iounmap(core->lmmio); 1059 cx88_devcount--; 1060 mutex_unlock(&devlist); 1061 v4l2_ctrl_handler_free(&core->video_hdl); 1062 v4l2_ctrl_handler_free(&core->audio_hdl); 1063 v4l2_device_unregister(&core->v4l2_dev); 1064 kfree(core); 1065 } 1066 1067 /* ------------------------------------------------------------------ */ 1068 1069 EXPORT_SYMBOL(cx88_print_irqbits); 1070 1071 EXPORT_SYMBOL(cx88_core_irq); 1072 EXPORT_SYMBOL(cx88_wakeup); 1073 EXPORT_SYMBOL(cx88_reset); 1074 EXPORT_SYMBOL(cx88_shutdown); 1075 1076 EXPORT_SYMBOL(cx88_risc_buffer); 1077 EXPORT_SYMBOL(cx88_risc_databuffer); 1078 1079 EXPORT_SYMBOL(cx88_sram_channels); 1080 EXPORT_SYMBOL(cx88_sram_channel_setup); 1081 EXPORT_SYMBOL(cx88_sram_channel_dump); 1082 1083 EXPORT_SYMBOL(cx88_set_tvnorm); 1084 EXPORT_SYMBOL(cx88_set_scale); 1085 1086 EXPORT_SYMBOL(cx88_vdev_init); 1087 EXPORT_SYMBOL(cx88_core_get); 1088 EXPORT_SYMBOL(cx88_core_put); 1089 1090 EXPORT_SYMBOL(cx88_ir_start); 1091 EXPORT_SYMBOL(cx88_ir_stop); 1092