1 /* 2 * Driver for the Conexant CX25821 PCIe bridge 3 * 4 * Copyright (C) 2009 Conexant Systems Inc. 5 * Authors <shu.lin@conexant.com>, <hiep.huynh@conexant.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 24 25 #include "cx25821.h" 26 #include "cx25821-medusa-video.h" 27 #include "cx25821-biffuncs.h" 28 29 /* 30 * medusa_enable_bluefield_output() 31 * 32 * Enable the generation of blue filed output if no video 33 * 34 */ 35 static void medusa_enable_bluefield_output(struct cx25821_dev *dev, int channel, 36 int enable) 37 { 38 u32 value = 0; 39 u32 tmp = 0; 40 int out_ctrl = OUT_CTRL1; 41 int out_ctrl_ns = OUT_CTRL_NS; 42 43 switch (channel) { 44 default: 45 case VDEC_A: 46 break; 47 case VDEC_B: 48 out_ctrl = VDEC_B_OUT_CTRL1; 49 out_ctrl_ns = VDEC_B_OUT_CTRL_NS; 50 break; 51 case VDEC_C: 52 out_ctrl = VDEC_C_OUT_CTRL1; 53 out_ctrl_ns = VDEC_C_OUT_CTRL_NS; 54 break; 55 case VDEC_D: 56 out_ctrl = VDEC_D_OUT_CTRL1; 57 out_ctrl_ns = VDEC_D_OUT_CTRL_NS; 58 break; 59 case VDEC_E: 60 out_ctrl = VDEC_E_OUT_CTRL1; 61 out_ctrl_ns = VDEC_E_OUT_CTRL_NS; 62 return; 63 case VDEC_F: 64 out_ctrl = VDEC_F_OUT_CTRL1; 65 out_ctrl_ns = VDEC_F_OUT_CTRL_NS; 66 return; 67 case VDEC_G: 68 out_ctrl = VDEC_G_OUT_CTRL1; 69 out_ctrl_ns = VDEC_G_OUT_CTRL_NS; 70 return; 71 case VDEC_H: 72 out_ctrl = VDEC_H_OUT_CTRL1; 73 out_ctrl_ns = VDEC_H_OUT_CTRL_NS; 74 return; 75 } 76 77 value = cx25821_i2c_read(&dev->i2c_bus[0], out_ctrl, &tmp); 78 value &= 0xFFFFFF7F; /* clear BLUE_FIELD_EN */ 79 if (enable) 80 value |= 0x00000080; /* set BLUE_FIELD_EN */ 81 cx25821_i2c_write(&dev->i2c_bus[0], out_ctrl, value); 82 83 value = cx25821_i2c_read(&dev->i2c_bus[0], out_ctrl_ns, &tmp); 84 value &= 0xFFFFFF7F; 85 if (enable) 86 value |= 0x00000080; /* set BLUE_FIELD_EN */ 87 cx25821_i2c_write(&dev->i2c_bus[0], out_ctrl_ns, value); 88 } 89 90 static int medusa_initialize_ntsc(struct cx25821_dev *dev) 91 { 92 int ret_val = 0; 93 int i = 0; 94 u32 value = 0; 95 u32 tmp = 0; 96 97 mutex_lock(&dev->lock); 98 99 for (i = 0; i < MAX_DECODERS; i++) { 100 /* set video format NTSC-M */ 101 value = cx25821_i2c_read(&dev->i2c_bus[0], 102 MODE_CTRL + (0x200 * i), &tmp); 103 value &= 0xFFFFFFF0; 104 /* enable the fast locking mode bit[16] */ 105 value |= 0x10001; 106 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], 107 MODE_CTRL + (0x200 * i), value); 108 109 /* resolution NTSC 720x480 */ 110 value = cx25821_i2c_read(&dev->i2c_bus[0], 111 HORIZ_TIM_CTRL + (0x200 * i), &tmp); 112 value &= 0x00C00C00; 113 value |= 0x612D0074; 114 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], 115 HORIZ_TIM_CTRL + (0x200 * i), value); 116 117 value = cx25821_i2c_read(&dev->i2c_bus[0], 118 VERT_TIM_CTRL + (0x200 * i), &tmp); 119 value &= 0x00C00C00; 120 value |= 0x1C1E001A; /* vblank_cnt + 2 to get camera ID */ 121 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], 122 VERT_TIM_CTRL + (0x200 * i), value); 123 124 /* chroma subcarrier step size */ 125 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], 126 SC_STEP_SIZE + (0x200 * i), 0x43E00000); 127 128 /* enable VIP optional active */ 129 value = cx25821_i2c_read(&dev->i2c_bus[0], 130 OUT_CTRL_NS + (0x200 * i), &tmp); 131 value &= 0xFFFBFFFF; 132 value |= 0x00040000; 133 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], 134 OUT_CTRL_NS + (0x200 * i), value); 135 136 /* enable VIP optional active (VIP_OPT_AL) for direct output. */ 137 value = cx25821_i2c_read(&dev->i2c_bus[0], 138 OUT_CTRL1 + (0x200 * i), &tmp); 139 value &= 0xFFFBFFFF; 140 value |= 0x00040000; 141 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], 142 OUT_CTRL1 + (0x200 * i), value); 143 144 /* 145 * clear VPRES_VERT_EN bit, fixes the chroma run away problem 146 * when the input switching rate < 16 fields 147 */ 148 value = cx25821_i2c_read(&dev->i2c_bus[0], 149 MISC_TIM_CTRL + (0x200 * i), &tmp); 150 /* disable special play detection */ 151 value = setBitAtPos(value, 14); 152 value = clearBitAtPos(value, 15); 153 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], 154 MISC_TIM_CTRL + (0x200 * i), value); 155 156 /* set vbi_gate_en to 0 */ 157 value = cx25821_i2c_read(&dev->i2c_bus[0], 158 DFE_CTRL1 + (0x200 * i), &tmp); 159 value = clearBitAtPos(value, 29); 160 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], 161 DFE_CTRL1 + (0x200 * i), value); 162 163 /* Enable the generation of blue field output if no video */ 164 medusa_enable_bluefield_output(dev, i, 1); 165 } 166 167 for (i = 0; i < MAX_ENCODERS; i++) { 168 /* NTSC hclock */ 169 value = cx25821_i2c_read(&dev->i2c_bus[0], 170 DENC_A_REG_1 + (0x100 * i), &tmp); 171 value &= 0xF000FC00; 172 value |= 0x06B402D0; 173 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], 174 DENC_A_REG_1 + (0x100 * i), value); 175 176 /* burst begin and burst end */ 177 value = cx25821_i2c_read(&dev->i2c_bus[0], 178 DENC_A_REG_2 + (0x100 * i), &tmp); 179 value &= 0xFF000000; 180 value |= 0x007E9054; 181 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], 182 DENC_A_REG_2 + (0x100 * i), value); 183 184 value = cx25821_i2c_read(&dev->i2c_bus[0], 185 DENC_A_REG_3 + (0x100 * i), &tmp); 186 value &= 0xFC00FE00; 187 value |= 0x00EC00F0; 188 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], 189 DENC_A_REG_3 + (0x100 * i), value); 190 191 /* set NTSC vblank, no phase alternation, 7.5 IRE pedestal */ 192 value = cx25821_i2c_read(&dev->i2c_bus[0], 193 DENC_A_REG_4 + (0x100 * i), &tmp); 194 value &= 0x00FCFFFF; 195 value |= 0x13020000; 196 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], 197 DENC_A_REG_4 + (0x100 * i), value); 198 199 value = cx25821_i2c_read(&dev->i2c_bus[0], 200 DENC_A_REG_5 + (0x100 * i), &tmp); 201 value &= 0xFFFF0000; 202 value |= 0x0000E575; 203 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], 204 DENC_A_REG_5 + (0x100 * i), value); 205 206 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], 207 DENC_A_REG_6 + (0x100 * i), 0x009A89C1); 208 209 /* Subcarrier Increment */ 210 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], 211 DENC_A_REG_7 + (0x100 * i), 0x21F07C1F); 212 } 213 214 /* set picture resolutions */ 215 /* 0 - 720 */ 216 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], HSCALE_CTRL, 0x0); 217 /* 0 - 480 */ 218 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], VSCALE_CTRL, 0x0); 219 220 /* set Bypass input format to NTSC 525 lines */ 221 value = cx25821_i2c_read(&dev->i2c_bus[0], BYP_AB_CTRL, &tmp); 222 value |= 0x00080200; 223 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], BYP_AB_CTRL, value); 224 225 mutex_unlock(&dev->lock); 226 227 return ret_val; 228 } 229 230 static int medusa_PALCombInit(struct cx25821_dev *dev, int dec) 231 { 232 int ret_val = -1; 233 u32 value = 0, tmp = 0; 234 235 /* Setup for 2D threshold */ 236 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], 237 COMB_2D_HFS_CFG + (0x200 * dec), 0x20002861); 238 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], 239 COMB_2D_HFD_CFG + (0x200 * dec), 0x20002861); 240 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], 241 COMB_2D_LF_CFG + (0x200 * dec), 0x200A1023); 242 243 /* Setup flat chroma and luma thresholds */ 244 value = cx25821_i2c_read(&dev->i2c_bus[0], 245 COMB_FLAT_THRESH_CTRL + (0x200 * dec), &tmp); 246 value &= 0x06230000; 247 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], 248 COMB_FLAT_THRESH_CTRL + (0x200 * dec), value); 249 250 /* set comb 2D blend */ 251 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], 252 COMB_2D_BLEND + (0x200 * dec), 0x210F0F0F); 253 254 /* COMB MISC CONTROL */ 255 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], 256 COMB_MISC_CTRL + (0x200 * dec), 0x41120A7F); 257 258 return ret_val; 259 } 260 261 static int medusa_initialize_pal(struct cx25821_dev *dev) 262 { 263 int ret_val = 0; 264 int i = 0; 265 u32 value = 0; 266 u32 tmp = 0; 267 268 mutex_lock(&dev->lock); 269 270 for (i = 0; i < MAX_DECODERS; i++) { 271 /* set video format PAL-BDGHI */ 272 value = cx25821_i2c_read(&dev->i2c_bus[0], 273 MODE_CTRL + (0x200 * i), &tmp); 274 value &= 0xFFFFFFF0; 275 /* enable the fast locking mode bit[16] */ 276 value |= 0x10004; 277 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], 278 MODE_CTRL + (0x200 * i), value); 279 280 /* resolution PAL 720x576 */ 281 value = cx25821_i2c_read(&dev->i2c_bus[0], 282 HORIZ_TIM_CTRL + (0x200 * i), &tmp); 283 value &= 0x00C00C00; 284 value |= 0x632D007D; 285 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], 286 HORIZ_TIM_CTRL + (0x200 * i), value); 287 288 /* vblank656_cnt=x26, vactive_cnt=240h, vblank_cnt=x24 */ 289 value = cx25821_i2c_read(&dev->i2c_bus[0], 290 VERT_TIM_CTRL + (0x200 * i), &tmp); 291 value &= 0x00C00C00; 292 value |= 0x28240026; /* vblank_cnt + 2 to get camera ID */ 293 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], 294 VERT_TIM_CTRL + (0x200 * i), value); 295 296 /* chroma subcarrier step size */ 297 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], 298 SC_STEP_SIZE + (0x200 * i), 0x5411E2D0); 299 300 /* enable VIP optional active */ 301 value = cx25821_i2c_read(&dev->i2c_bus[0], 302 OUT_CTRL_NS + (0x200 * i), &tmp); 303 value &= 0xFFFBFFFF; 304 value |= 0x00040000; 305 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], 306 OUT_CTRL_NS + (0x200 * i), value); 307 308 /* enable VIP optional active (VIP_OPT_AL) for direct output. */ 309 value = cx25821_i2c_read(&dev->i2c_bus[0], 310 OUT_CTRL1 + (0x200 * i), &tmp); 311 value &= 0xFFFBFFFF; 312 value |= 0x00040000; 313 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], 314 OUT_CTRL1 + (0x200 * i), value); 315 316 /* 317 * clear VPRES_VERT_EN bit, fixes the chroma run away problem 318 * when the input switching rate < 16 fields 319 */ 320 value = cx25821_i2c_read(&dev->i2c_bus[0], 321 MISC_TIM_CTRL + (0x200 * i), &tmp); 322 /* disable special play detection */ 323 value = setBitAtPos(value, 14); 324 value = clearBitAtPos(value, 15); 325 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], 326 MISC_TIM_CTRL + (0x200 * i), value); 327 328 /* set vbi_gate_en to 0 */ 329 value = cx25821_i2c_read(&dev->i2c_bus[0], 330 DFE_CTRL1 + (0x200 * i), &tmp); 331 value = clearBitAtPos(value, 29); 332 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], 333 DFE_CTRL1 + (0x200 * i), value); 334 335 medusa_PALCombInit(dev, i); 336 337 /* Enable the generation of blue field output if no video */ 338 medusa_enable_bluefield_output(dev, i, 1); 339 } 340 341 for (i = 0; i < MAX_ENCODERS; i++) { 342 /* PAL hclock */ 343 value = cx25821_i2c_read(&dev->i2c_bus[0], 344 DENC_A_REG_1 + (0x100 * i), &tmp); 345 value &= 0xF000FC00; 346 value |= 0x06C002D0; 347 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], 348 DENC_A_REG_1 + (0x100 * i), value); 349 350 /* burst begin and burst end */ 351 value = cx25821_i2c_read(&dev->i2c_bus[0], 352 DENC_A_REG_2 + (0x100 * i), &tmp); 353 value &= 0xFF000000; 354 value |= 0x007E9754; 355 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], 356 DENC_A_REG_2 + (0x100 * i), value); 357 358 /* hblank and vactive */ 359 value = cx25821_i2c_read(&dev->i2c_bus[0], 360 DENC_A_REG_3 + (0x100 * i), &tmp); 361 value &= 0xFC00FE00; 362 value |= 0x00FC0120; 363 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], 364 DENC_A_REG_3 + (0x100 * i), value); 365 366 /* set PAL vblank, phase alternation, 0 IRE pedestal */ 367 value = cx25821_i2c_read(&dev->i2c_bus[0], 368 DENC_A_REG_4 + (0x100 * i), &tmp); 369 value &= 0x00FCFFFF; 370 value |= 0x14010000; 371 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], 372 DENC_A_REG_4 + (0x100 * i), value); 373 374 value = cx25821_i2c_read(&dev->i2c_bus[0], 375 DENC_A_REG_5 + (0x100 * i), &tmp); 376 value &= 0xFFFF0000; 377 value |= 0x0000F078; 378 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], 379 DENC_A_REG_5 + (0x100 * i), value); 380 381 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], 382 DENC_A_REG_6 + (0x100 * i), 0x00A493CF); 383 384 /* Subcarrier Increment */ 385 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], 386 DENC_A_REG_7 + (0x100 * i), 0x2A098ACB); 387 } 388 389 /* set picture resolutions */ 390 /* 0 - 720 */ 391 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], HSCALE_CTRL, 0x0); 392 /* 0 - 576 */ 393 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], VSCALE_CTRL, 0x0); 394 395 /* set Bypass input format to PAL 625 lines */ 396 value = cx25821_i2c_read(&dev->i2c_bus[0], BYP_AB_CTRL, &tmp); 397 value &= 0xFFF7FDFF; 398 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], BYP_AB_CTRL, value); 399 400 mutex_unlock(&dev->lock); 401 402 return ret_val; 403 } 404 405 int medusa_set_videostandard(struct cx25821_dev *dev) 406 { 407 int status = STATUS_SUCCESS; 408 u32 value = 0, tmp = 0; 409 410 if (dev->tvnorm & V4L2_STD_PAL_BG || dev->tvnorm & V4L2_STD_PAL_DK) 411 status = medusa_initialize_pal(dev); 412 else 413 status = medusa_initialize_ntsc(dev); 414 415 /* Enable DENC_A output */ 416 value = cx25821_i2c_read(&dev->i2c_bus[0], DENC_A_REG_4, &tmp); 417 value = setBitAtPos(value, 4); 418 status = cx25821_i2c_write(&dev->i2c_bus[0], DENC_A_REG_4, value); 419 420 /* Enable DENC_B output */ 421 value = cx25821_i2c_read(&dev->i2c_bus[0], DENC_B_REG_4, &tmp); 422 value = setBitAtPos(value, 4); 423 status = cx25821_i2c_write(&dev->i2c_bus[0], DENC_B_REG_4, value); 424 425 return status; 426 } 427 428 void medusa_set_resolution(struct cx25821_dev *dev, int width, 429 int decoder_select) 430 { 431 int decoder = 0; 432 int decoder_count = 0; 433 u32 hscale = 0x0; 434 u32 vscale = 0x0; 435 const int MAX_WIDTH = 720; 436 437 mutex_lock(&dev->lock); 438 439 /* validate the width */ 440 if (width > MAX_WIDTH) { 441 pr_info("%s(): width %d > MAX_WIDTH %d ! resetting to MAX_WIDTH\n", 442 __func__, width, MAX_WIDTH); 443 width = MAX_WIDTH; 444 } 445 446 if (decoder_select <= 7 && decoder_select >= 0) { 447 decoder = decoder_select; 448 decoder_count = decoder_select + 1; 449 } else { 450 decoder = 0; 451 decoder_count = _num_decoders; 452 } 453 454 switch (width) { 455 case 320: 456 hscale = 0x13E34B; 457 vscale = 0x0; 458 break; 459 460 case 352: 461 hscale = 0x10A273; 462 vscale = 0x0; 463 break; 464 465 case 176: 466 hscale = 0x3115B2; 467 vscale = 0x1E00; 468 break; 469 470 case 160: 471 hscale = 0x378D84; 472 vscale = 0x1E00; 473 break; 474 475 default: /* 720 */ 476 hscale = 0x0; 477 vscale = 0x0; 478 break; 479 } 480 481 for (; decoder < decoder_count; decoder++) { 482 /* write scaling values for each decoder */ 483 cx25821_i2c_write(&dev->i2c_bus[0], 484 HSCALE_CTRL + (0x200 * decoder), hscale); 485 cx25821_i2c_write(&dev->i2c_bus[0], 486 VSCALE_CTRL + (0x200 * decoder), vscale); 487 } 488 489 mutex_unlock(&dev->lock); 490 } 491 492 static void medusa_set_decoderduration(struct cx25821_dev *dev, int decoder, 493 int duration) 494 { 495 u32 fld_cnt = 0; 496 u32 tmp = 0; 497 u32 disp_cnt_reg = DISP_AB_CNT; 498 499 mutex_lock(&dev->lock); 500 501 /* no support */ 502 if (decoder < VDEC_A || decoder > VDEC_H) { 503 mutex_unlock(&dev->lock); 504 return; 505 } 506 507 switch (decoder) { 508 default: 509 break; 510 case VDEC_C: 511 case VDEC_D: 512 disp_cnt_reg = DISP_CD_CNT; 513 break; 514 case VDEC_E: 515 case VDEC_F: 516 disp_cnt_reg = DISP_EF_CNT; 517 break; 518 case VDEC_G: 519 case VDEC_H: 520 disp_cnt_reg = DISP_GH_CNT; 521 break; 522 } 523 524 _display_field_cnt[decoder] = duration; 525 526 /* update hardware */ 527 fld_cnt = cx25821_i2c_read(&dev->i2c_bus[0], disp_cnt_reg, &tmp); 528 529 if (!(decoder % 2)) { /* EVEN decoder */ 530 fld_cnt &= 0xFFFF0000; 531 fld_cnt |= duration; 532 } else { 533 fld_cnt &= 0x0000FFFF; 534 fld_cnt |= ((u32) duration) << 16; 535 } 536 537 cx25821_i2c_write(&dev->i2c_bus[0], disp_cnt_reg, fld_cnt); 538 539 mutex_unlock(&dev->lock); 540 } 541 542 /* Map to Medusa register setting */ 543 static int mapM(int srcMin, int srcMax, int srcVal, int dstMin, int dstMax, 544 int *dstVal) 545 { 546 int numerator; 547 int denominator; 548 int quotient; 549 550 if ((srcMin == srcMax) || (srcVal < srcMin) || (srcVal > srcMax)) 551 return -1; 552 /* 553 * This is the overall expression used: 554 * *dstVal = 555 * (srcVal - srcMin)*(dstMax - dstMin) / (srcMax - srcMin) + dstMin; 556 * but we need to account for rounding so below we use the modulus 557 * operator to find the remainder and increment if necessary. 558 */ 559 numerator = (srcVal - srcMin) * (dstMax - dstMin); 560 denominator = srcMax - srcMin; 561 quotient = numerator / denominator; 562 563 if (2 * (numerator % denominator) >= denominator) 564 quotient++; 565 566 *dstVal = quotient + dstMin; 567 568 return 0; 569 } 570 571 static unsigned long convert_to_twos(long numeric, unsigned long bits_len) 572 { 573 unsigned char temp; 574 575 if (numeric >= 0) 576 return numeric; 577 else { 578 temp = ~(abs(numeric) & 0xFF); 579 temp += 1; 580 return temp; 581 } 582 } 583 584 int medusa_set_brightness(struct cx25821_dev *dev, int brightness, int decoder) 585 { 586 int ret_val = 0; 587 int value = 0; 588 u32 val = 0, tmp = 0; 589 590 mutex_lock(&dev->lock); 591 if ((brightness > VIDEO_PROCAMP_MAX) || 592 (brightness < VIDEO_PROCAMP_MIN)) { 593 mutex_unlock(&dev->lock); 594 return -1; 595 } 596 ret_val = mapM(VIDEO_PROCAMP_MIN, VIDEO_PROCAMP_MAX, brightness, 597 SIGNED_BYTE_MIN, SIGNED_BYTE_MAX, &value); 598 value = convert_to_twos(value, 8); 599 val = cx25821_i2c_read(&dev->i2c_bus[0], 600 VDEC_A_BRITE_CTRL + (0x200 * decoder), &tmp); 601 val &= 0xFFFFFF00; 602 ret_val |= cx25821_i2c_write(&dev->i2c_bus[0], 603 VDEC_A_BRITE_CTRL + (0x200 * decoder), val | value); 604 mutex_unlock(&dev->lock); 605 return ret_val; 606 } 607 608 int medusa_set_contrast(struct cx25821_dev *dev, int contrast, int decoder) 609 { 610 int ret_val = 0; 611 int value = 0; 612 u32 val = 0, tmp = 0; 613 614 mutex_lock(&dev->lock); 615 616 if ((contrast > VIDEO_PROCAMP_MAX) || (contrast < VIDEO_PROCAMP_MIN)) { 617 mutex_unlock(&dev->lock); 618 return -1; 619 } 620 621 ret_val = mapM(VIDEO_PROCAMP_MIN, VIDEO_PROCAMP_MAX, contrast, 622 UNSIGNED_BYTE_MIN, UNSIGNED_BYTE_MAX, &value); 623 val = cx25821_i2c_read(&dev->i2c_bus[0], 624 VDEC_A_CNTRST_CTRL + (0x200 * decoder), &tmp); 625 val &= 0xFFFFFF00; 626 ret_val |= cx25821_i2c_write(&dev->i2c_bus[0], 627 VDEC_A_CNTRST_CTRL + (0x200 * decoder), val | value); 628 629 mutex_unlock(&dev->lock); 630 return ret_val; 631 } 632 633 int medusa_set_hue(struct cx25821_dev *dev, int hue, int decoder) 634 { 635 int ret_val = 0; 636 int value = 0; 637 u32 val = 0, tmp = 0; 638 639 mutex_lock(&dev->lock); 640 641 if ((hue > VIDEO_PROCAMP_MAX) || (hue < VIDEO_PROCAMP_MIN)) { 642 mutex_unlock(&dev->lock); 643 return -1; 644 } 645 646 ret_val = mapM(VIDEO_PROCAMP_MIN, VIDEO_PROCAMP_MAX, hue, 647 SIGNED_BYTE_MIN, SIGNED_BYTE_MAX, &value); 648 649 value = convert_to_twos(value, 8); 650 val = cx25821_i2c_read(&dev->i2c_bus[0], 651 VDEC_A_HUE_CTRL + (0x200 * decoder), &tmp); 652 val &= 0xFFFFFF00; 653 654 ret_val |= cx25821_i2c_write(&dev->i2c_bus[0], 655 VDEC_A_HUE_CTRL + (0x200 * decoder), val | value); 656 657 mutex_unlock(&dev->lock); 658 return ret_val; 659 } 660 661 int medusa_set_saturation(struct cx25821_dev *dev, int saturation, int decoder) 662 { 663 int ret_val = 0; 664 int value = 0; 665 u32 val = 0, tmp = 0; 666 667 mutex_lock(&dev->lock); 668 669 if ((saturation > VIDEO_PROCAMP_MAX) || 670 (saturation < VIDEO_PROCAMP_MIN)) { 671 mutex_unlock(&dev->lock); 672 return -1; 673 } 674 675 ret_val = mapM(VIDEO_PROCAMP_MIN, VIDEO_PROCAMP_MAX, saturation, 676 UNSIGNED_BYTE_MIN, UNSIGNED_BYTE_MAX, &value); 677 678 val = cx25821_i2c_read(&dev->i2c_bus[0], 679 VDEC_A_USAT_CTRL + (0x200 * decoder), &tmp); 680 val &= 0xFFFFFF00; 681 ret_val |= cx25821_i2c_write(&dev->i2c_bus[0], 682 VDEC_A_USAT_CTRL + (0x200 * decoder), val | value); 683 684 val = cx25821_i2c_read(&dev->i2c_bus[0], 685 VDEC_A_VSAT_CTRL + (0x200 * decoder), &tmp); 686 val &= 0xFFFFFF00; 687 ret_val |= cx25821_i2c_write(&dev->i2c_bus[0], 688 VDEC_A_VSAT_CTRL + (0x200 * decoder), val | value); 689 690 mutex_unlock(&dev->lock); 691 return ret_val; 692 } 693 694 /* Program the display sequence and monitor output. */ 695 696 int medusa_video_init(struct cx25821_dev *dev) 697 { 698 u32 value = 0, tmp = 0; 699 int ret_val = 0; 700 int i = 0; 701 702 mutex_lock(&dev->lock); 703 704 _num_decoders = dev->_max_num_decoders; 705 706 /* disable Auto source selection on all video decoders */ 707 value = cx25821_i2c_read(&dev->i2c_bus[0], MON_A_CTRL, &tmp); 708 value &= 0xFFFFF0FF; 709 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], MON_A_CTRL, value); 710 711 if (ret_val < 0) 712 goto error; 713 714 /* Turn off Master source switch enable */ 715 value = cx25821_i2c_read(&dev->i2c_bus[0], MON_A_CTRL, &tmp); 716 value &= 0xFFFFFFDF; 717 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], MON_A_CTRL, value); 718 719 if (ret_val < 0) 720 goto error; 721 722 mutex_unlock(&dev->lock); 723 724 for (i = 0; i < _num_decoders; i++) 725 medusa_set_decoderduration(dev, i, _display_field_cnt[i]); 726 727 mutex_lock(&dev->lock); 728 729 /* Select monitor as DENC A input, power up the DAC */ 730 value = cx25821_i2c_read(&dev->i2c_bus[0], DENC_AB_CTRL, &tmp); 731 value &= 0xFF70FF70; 732 value |= 0x00090008; /* set en_active */ 733 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], DENC_AB_CTRL, value); 734 735 if (ret_val < 0) 736 goto error; 737 738 /* enable input is VIP/656 */ 739 value = cx25821_i2c_read(&dev->i2c_bus[0], BYP_AB_CTRL, &tmp); 740 value |= 0x00040100; /* enable VIP */ 741 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], BYP_AB_CTRL, value); 742 743 if (ret_val < 0) 744 goto error; 745 746 /* select AFE clock to output mode */ 747 value = cx25821_i2c_read(&dev->i2c_bus[0], AFE_AB_DIAG_CTRL, &tmp); 748 value &= 0x83FFFFFF; 749 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], AFE_AB_DIAG_CTRL, 750 value | 0x10000000); 751 752 if (ret_val < 0) 753 goto error; 754 755 /* Turn on all of the data out and control output pins. */ 756 value = cx25821_i2c_read(&dev->i2c_bus[0], PIN_OE_CTRL, &tmp); 757 value &= 0xFEF0FE00; 758 if (_num_decoders == MAX_DECODERS) { 759 /* 760 * Note: The octal board does not support control pins(bit16-19) 761 * These bits are ignored in the octal board. 762 * 763 * disable VDEC A-C port, default to Mobilygen Interface 764 */ 765 value |= 0x010001F8; 766 } else { 767 /* disable VDEC A-C port, default to Mobilygen Interface */ 768 value |= 0x010F0108; 769 } 770 771 value |= 7; 772 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], PIN_OE_CTRL, value); 773 774 if (ret_val < 0) 775 goto error; 776 777 778 mutex_unlock(&dev->lock); 779 780 ret_val = medusa_set_videostandard(dev); 781 782 return ret_val; 783 784 error: 785 mutex_unlock(&dev->lock); 786 return ret_val; 787 } 788