1 /* 2 * Driver for the Conexant CX25821 PCIe bridge 3 * 4 * Copyright (C) 2009 Conexant Systems Inc. 5 * Authors <shu.lin@conexant.com>, <hiep.huynh@conexant.com> 6 * Based on Steven Toth <stoth@linuxtv.org> cx23885 driver 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 22 */ 23 24 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 25 26 #include <linux/i2c.h> 27 #include <linux/slab.h> 28 #include "cx25821.h" 29 #include "cx25821-sram.h" 30 #include "cx25821-video.h" 31 32 MODULE_DESCRIPTION("Driver for Athena cards"); 33 MODULE_AUTHOR("Shu Lin - Hiep Huynh"); 34 MODULE_LICENSE("GPL"); 35 36 static unsigned int debug; 37 module_param(debug, int, 0644); 38 MODULE_PARM_DESC(debug, "enable debug messages"); 39 40 static unsigned int card[] = {[0 ... (CX25821_MAXBOARDS - 1)] = UNSET }; 41 module_param_array(card, int, NULL, 0444); 42 MODULE_PARM_DESC(card, "card type"); 43 44 const struct sram_channel cx25821_sram_channels[] = { 45 [SRAM_CH00] = { 46 .i = SRAM_CH00, 47 .name = "VID A", 48 .cmds_start = VID_A_DOWN_CMDS, 49 .ctrl_start = VID_A_IQ, 50 .cdt = VID_A_CDT, 51 .fifo_start = VID_A_DOWN_CLUSTER_1, 52 .fifo_size = (VID_CLUSTER_SIZE << 2), 53 .ptr1_reg = DMA1_PTR1, 54 .ptr2_reg = DMA1_PTR2, 55 .cnt1_reg = DMA1_CNT1, 56 .cnt2_reg = DMA1_CNT2, 57 .int_msk = VID_A_INT_MSK, 58 .int_stat = VID_A_INT_STAT, 59 .int_mstat = VID_A_INT_MSTAT, 60 .dma_ctl = VID_DST_A_DMA_CTL, 61 .gpcnt_ctl = VID_DST_A_GPCNT_CTL, 62 .gpcnt = VID_DST_A_GPCNT, 63 .vip_ctl = VID_DST_A_VIP_CTL, 64 .pix_frmt = VID_DST_A_PIX_FRMT, 65 }, 66 67 [SRAM_CH01] = { 68 .i = SRAM_CH01, 69 .name = "VID B", 70 .cmds_start = VID_B_DOWN_CMDS, 71 .ctrl_start = VID_B_IQ, 72 .cdt = VID_B_CDT, 73 .fifo_start = VID_B_DOWN_CLUSTER_1, 74 .fifo_size = (VID_CLUSTER_SIZE << 2), 75 .ptr1_reg = DMA2_PTR1, 76 .ptr2_reg = DMA2_PTR2, 77 .cnt1_reg = DMA2_CNT1, 78 .cnt2_reg = DMA2_CNT2, 79 .int_msk = VID_B_INT_MSK, 80 .int_stat = VID_B_INT_STAT, 81 .int_mstat = VID_B_INT_MSTAT, 82 .dma_ctl = VID_DST_B_DMA_CTL, 83 .gpcnt_ctl = VID_DST_B_GPCNT_CTL, 84 .gpcnt = VID_DST_B_GPCNT, 85 .vip_ctl = VID_DST_B_VIP_CTL, 86 .pix_frmt = VID_DST_B_PIX_FRMT, 87 }, 88 89 [SRAM_CH02] = { 90 .i = SRAM_CH02, 91 .name = "VID C", 92 .cmds_start = VID_C_DOWN_CMDS, 93 .ctrl_start = VID_C_IQ, 94 .cdt = VID_C_CDT, 95 .fifo_start = VID_C_DOWN_CLUSTER_1, 96 .fifo_size = (VID_CLUSTER_SIZE << 2), 97 .ptr1_reg = DMA3_PTR1, 98 .ptr2_reg = DMA3_PTR2, 99 .cnt1_reg = DMA3_CNT1, 100 .cnt2_reg = DMA3_CNT2, 101 .int_msk = VID_C_INT_MSK, 102 .int_stat = VID_C_INT_STAT, 103 .int_mstat = VID_C_INT_MSTAT, 104 .dma_ctl = VID_DST_C_DMA_CTL, 105 .gpcnt_ctl = VID_DST_C_GPCNT_CTL, 106 .gpcnt = VID_DST_C_GPCNT, 107 .vip_ctl = VID_DST_C_VIP_CTL, 108 .pix_frmt = VID_DST_C_PIX_FRMT, 109 }, 110 111 [SRAM_CH03] = { 112 .i = SRAM_CH03, 113 .name = "VID D", 114 .cmds_start = VID_D_DOWN_CMDS, 115 .ctrl_start = VID_D_IQ, 116 .cdt = VID_D_CDT, 117 .fifo_start = VID_D_DOWN_CLUSTER_1, 118 .fifo_size = (VID_CLUSTER_SIZE << 2), 119 .ptr1_reg = DMA4_PTR1, 120 .ptr2_reg = DMA4_PTR2, 121 .cnt1_reg = DMA4_CNT1, 122 .cnt2_reg = DMA4_CNT2, 123 .int_msk = VID_D_INT_MSK, 124 .int_stat = VID_D_INT_STAT, 125 .int_mstat = VID_D_INT_MSTAT, 126 .dma_ctl = VID_DST_D_DMA_CTL, 127 .gpcnt_ctl = VID_DST_D_GPCNT_CTL, 128 .gpcnt = VID_DST_D_GPCNT, 129 .vip_ctl = VID_DST_D_VIP_CTL, 130 .pix_frmt = VID_DST_D_PIX_FRMT, 131 }, 132 133 [SRAM_CH04] = { 134 .i = SRAM_CH04, 135 .name = "VID E", 136 .cmds_start = VID_E_DOWN_CMDS, 137 .ctrl_start = VID_E_IQ, 138 .cdt = VID_E_CDT, 139 .fifo_start = VID_E_DOWN_CLUSTER_1, 140 .fifo_size = (VID_CLUSTER_SIZE << 2), 141 .ptr1_reg = DMA5_PTR1, 142 .ptr2_reg = DMA5_PTR2, 143 .cnt1_reg = DMA5_CNT1, 144 .cnt2_reg = DMA5_CNT2, 145 .int_msk = VID_E_INT_MSK, 146 .int_stat = VID_E_INT_STAT, 147 .int_mstat = VID_E_INT_MSTAT, 148 .dma_ctl = VID_DST_E_DMA_CTL, 149 .gpcnt_ctl = VID_DST_E_GPCNT_CTL, 150 .gpcnt = VID_DST_E_GPCNT, 151 .vip_ctl = VID_DST_E_VIP_CTL, 152 .pix_frmt = VID_DST_E_PIX_FRMT, 153 }, 154 155 [SRAM_CH05] = { 156 .i = SRAM_CH05, 157 .name = "VID F", 158 .cmds_start = VID_F_DOWN_CMDS, 159 .ctrl_start = VID_F_IQ, 160 .cdt = VID_F_CDT, 161 .fifo_start = VID_F_DOWN_CLUSTER_1, 162 .fifo_size = (VID_CLUSTER_SIZE << 2), 163 .ptr1_reg = DMA6_PTR1, 164 .ptr2_reg = DMA6_PTR2, 165 .cnt1_reg = DMA6_CNT1, 166 .cnt2_reg = DMA6_CNT2, 167 .int_msk = VID_F_INT_MSK, 168 .int_stat = VID_F_INT_STAT, 169 .int_mstat = VID_F_INT_MSTAT, 170 .dma_ctl = VID_DST_F_DMA_CTL, 171 .gpcnt_ctl = VID_DST_F_GPCNT_CTL, 172 .gpcnt = VID_DST_F_GPCNT, 173 .vip_ctl = VID_DST_F_VIP_CTL, 174 .pix_frmt = VID_DST_F_PIX_FRMT, 175 }, 176 177 [SRAM_CH06] = { 178 .i = SRAM_CH06, 179 .name = "VID G", 180 .cmds_start = VID_G_DOWN_CMDS, 181 .ctrl_start = VID_G_IQ, 182 .cdt = VID_G_CDT, 183 .fifo_start = VID_G_DOWN_CLUSTER_1, 184 .fifo_size = (VID_CLUSTER_SIZE << 2), 185 .ptr1_reg = DMA7_PTR1, 186 .ptr2_reg = DMA7_PTR2, 187 .cnt1_reg = DMA7_CNT1, 188 .cnt2_reg = DMA7_CNT2, 189 .int_msk = VID_G_INT_MSK, 190 .int_stat = VID_G_INT_STAT, 191 .int_mstat = VID_G_INT_MSTAT, 192 .dma_ctl = VID_DST_G_DMA_CTL, 193 .gpcnt_ctl = VID_DST_G_GPCNT_CTL, 194 .gpcnt = VID_DST_G_GPCNT, 195 .vip_ctl = VID_DST_G_VIP_CTL, 196 .pix_frmt = VID_DST_G_PIX_FRMT, 197 }, 198 199 [SRAM_CH07] = { 200 .i = SRAM_CH07, 201 .name = "VID H", 202 .cmds_start = VID_H_DOWN_CMDS, 203 .ctrl_start = VID_H_IQ, 204 .cdt = VID_H_CDT, 205 .fifo_start = VID_H_DOWN_CLUSTER_1, 206 .fifo_size = (VID_CLUSTER_SIZE << 2), 207 .ptr1_reg = DMA8_PTR1, 208 .ptr2_reg = DMA8_PTR2, 209 .cnt1_reg = DMA8_CNT1, 210 .cnt2_reg = DMA8_CNT2, 211 .int_msk = VID_H_INT_MSK, 212 .int_stat = VID_H_INT_STAT, 213 .int_mstat = VID_H_INT_MSTAT, 214 .dma_ctl = VID_DST_H_DMA_CTL, 215 .gpcnt_ctl = VID_DST_H_GPCNT_CTL, 216 .gpcnt = VID_DST_H_GPCNT, 217 .vip_ctl = VID_DST_H_VIP_CTL, 218 .pix_frmt = VID_DST_H_PIX_FRMT, 219 }, 220 221 [SRAM_CH08] = { 222 .name = "audio from", 223 .cmds_start = AUD_A_DOWN_CMDS, 224 .ctrl_start = AUD_A_IQ, 225 .cdt = AUD_A_CDT, 226 .fifo_start = AUD_A_DOWN_CLUSTER_1, 227 .fifo_size = AUDIO_CLUSTER_SIZE * 3, 228 .ptr1_reg = DMA17_PTR1, 229 .ptr2_reg = DMA17_PTR2, 230 .cnt1_reg = DMA17_CNT1, 231 .cnt2_reg = DMA17_CNT2, 232 }, 233 234 [SRAM_CH09] = { 235 .i = SRAM_CH09, 236 .name = "VID Upstream I", 237 .cmds_start = VID_I_UP_CMDS, 238 .ctrl_start = VID_I_IQ, 239 .cdt = VID_I_CDT, 240 .fifo_start = VID_I_UP_CLUSTER_1, 241 .fifo_size = (VID_CLUSTER_SIZE << 2), 242 .ptr1_reg = DMA15_PTR1, 243 .ptr2_reg = DMA15_PTR2, 244 .cnt1_reg = DMA15_CNT1, 245 .cnt2_reg = DMA15_CNT2, 246 .int_msk = VID_I_INT_MSK, 247 .int_stat = VID_I_INT_STAT, 248 .int_mstat = VID_I_INT_MSTAT, 249 .dma_ctl = VID_SRC_I_DMA_CTL, 250 .gpcnt_ctl = VID_SRC_I_GPCNT_CTL, 251 .gpcnt = VID_SRC_I_GPCNT, 252 253 .vid_fmt_ctl = VID_SRC_I_FMT_CTL, 254 .vid_active_ctl1 = VID_SRC_I_ACTIVE_CTL1, 255 .vid_active_ctl2 = VID_SRC_I_ACTIVE_CTL2, 256 .vid_cdt_size = VID_SRC_I_CDT_SZ, 257 .irq_bit = 8, 258 }, 259 260 [SRAM_CH10] = { 261 .i = SRAM_CH10, 262 .name = "VID Upstream J", 263 .cmds_start = VID_J_UP_CMDS, 264 .ctrl_start = VID_J_IQ, 265 .cdt = VID_J_CDT, 266 .fifo_start = VID_J_UP_CLUSTER_1, 267 .fifo_size = (VID_CLUSTER_SIZE << 2), 268 .ptr1_reg = DMA16_PTR1, 269 .ptr2_reg = DMA16_PTR2, 270 .cnt1_reg = DMA16_CNT1, 271 .cnt2_reg = DMA16_CNT2, 272 .int_msk = VID_J_INT_MSK, 273 .int_stat = VID_J_INT_STAT, 274 .int_mstat = VID_J_INT_MSTAT, 275 .dma_ctl = VID_SRC_J_DMA_CTL, 276 .gpcnt_ctl = VID_SRC_J_GPCNT_CTL, 277 .gpcnt = VID_SRC_J_GPCNT, 278 279 .vid_fmt_ctl = VID_SRC_J_FMT_CTL, 280 .vid_active_ctl1 = VID_SRC_J_ACTIVE_CTL1, 281 .vid_active_ctl2 = VID_SRC_J_ACTIVE_CTL2, 282 .vid_cdt_size = VID_SRC_J_CDT_SZ, 283 .irq_bit = 9, 284 }, 285 286 [SRAM_CH11] = { 287 .i = SRAM_CH11, 288 .name = "Audio Upstream Channel B", 289 .cmds_start = AUD_B_UP_CMDS, 290 .ctrl_start = AUD_B_IQ, 291 .cdt = AUD_B_CDT, 292 .fifo_start = AUD_B_UP_CLUSTER_1, 293 .fifo_size = (AUDIO_CLUSTER_SIZE * 3), 294 .ptr1_reg = DMA22_PTR1, 295 .ptr2_reg = DMA22_PTR2, 296 .cnt1_reg = DMA22_CNT1, 297 .cnt2_reg = DMA22_CNT2, 298 .int_msk = AUD_B_INT_MSK, 299 .int_stat = AUD_B_INT_STAT, 300 .int_mstat = AUD_B_INT_MSTAT, 301 .dma_ctl = AUD_INT_DMA_CTL, 302 .gpcnt_ctl = AUD_B_GPCNT_CTL, 303 .gpcnt = AUD_B_GPCNT, 304 .aud_length = AUD_B_LNGTH, 305 .aud_cfg = AUD_B_CFG, 306 .fld_aud_fifo_en = FLD_AUD_SRC_B_FIFO_EN, 307 .fld_aud_risc_en = FLD_AUD_SRC_B_RISC_EN, 308 .irq_bit = 11, 309 }, 310 }; 311 EXPORT_SYMBOL(cx25821_sram_channels); 312 313 static int cx25821_risc_decode(u32 risc) 314 { 315 static const char * const instr[16] = { 316 [RISC_SYNC >> 28] = "sync", 317 [RISC_WRITE >> 28] = "write", 318 [RISC_WRITEC >> 28] = "writec", 319 [RISC_READ >> 28] = "read", 320 [RISC_READC >> 28] = "readc", 321 [RISC_JUMP >> 28] = "jump", 322 [RISC_SKIP >> 28] = "skip", 323 [RISC_WRITERM >> 28] = "writerm", 324 [RISC_WRITECM >> 28] = "writecm", 325 [RISC_WRITECR >> 28] = "writecr", 326 }; 327 static const int incr[16] = { 328 [RISC_WRITE >> 28] = 3, 329 [RISC_JUMP >> 28] = 3, 330 [RISC_SKIP >> 28] = 1, 331 [RISC_SYNC >> 28] = 1, 332 [RISC_WRITERM >> 28] = 3, 333 [RISC_WRITECM >> 28] = 3, 334 [RISC_WRITECR >> 28] = 4, 335 }; 336 static const char * const bits[] = { 337 "12", "13", "14", "resync", 338 "cnt0", "cnt1", "18", "19", 339 "20", "21", "22", "23", 340 "irq1", "irq2", "eol", "sol", 341 }; 342 int i; 343 344 pr_cont("0x%08x [ %s", 345 risc, instr[risc >> 28] ? instr[risc >> 28] : "INVALID"); 346 for (i = ARRAY_SIZE(bits) - 1; i >= 0; i--) { 347 if (risc & (1 << (i + 12))) 348 pr_cont(" %s", bits[i]); 349 } 350 pr_cont(" count=%d ]\n", risc & 0xfff); 351 return incr[risc >> 28] ? incr[risc >> 28] : 1; 352 } 353 354 static inline int i2c_slave_did_ack(struct i2c_adapter *i2c_adap) 355 { 356 struct cx25821_i2c *bus = i2c_adap->algo_data; 357 struct cx25821_dev *dev = bus->dev; 358 return cx_read(bus->reg_stat) & 0x01; 359 } 360 361 static void cx25821_registers_init(struct cx25821_dev *dev) 362 { 363 u32 tmp; 364 365 /* enable RUN_RISC in Pecos */ 366 cx_write(DEV_CNTRL2, 0x20); 367 368 /* Set the master PCI interrupt masks to enable video, audio, MBIF, 369 * and GPIO interrupts 370 * I2C interrupt masking is handled by the I2C objects themselves. */ 371 cx_write(PCI_INT_MSK, 0x2001FFFF); 372 373 tmp = cx_read(RDR_TLCTL0); 374 tmp &= ~FLD_CFG_RCB_CK_EN; /* Clear the RCB_CK_EN bit */ 375 cx_write(RDR_TLCTL0, tmp); 376 377 /* PLL-A setting for the Audio Master Clock */ 378 cx_write(PLL_A_INT_FRAC, 0x9807A58B); 379 380 /* PLL_A_POST = 0x1C, PLL_A_OUT_TO_PIN = 0x1 */ 381 cx_write(PLL_A_POST_STAT_BIST, 0x8000019C); 382 383 /* clear reset bit [31] */ 384 tmp = cx_read(PLL_A_INT_FRAC); 385 cx_write(PLL_A_INT_FRAC, tmp & 0x7FFFFFFF); 386 387 /* PLL-B setting for Mobilygen Host Bus Interface */ 388 cx_write(PLL_B_INT_FRAC, 0x9883A86F); 389 390 /* PLL_B_POST = 0xD, PLL_B_OUT_TO_PIN = 0x0 */ 391 cx_write(PLL_B_POST_STAT_BIST, 0x8000018D); 392 393 /* clear reset bit [31] */ 394 tmp = cx_read(PLL_B_INT_FRAC); 395 cx_write(PLL_B_INT_FRAC, tmp & 0x7FFFFFFF); 396 397 /* PLL-C setting for video upstream channel */ 398 cx_write(PLL_C_INT_FRAC, 0x96A0EA3F); 399 400 /* PLL_C_POST = 0x3, PLL_C_OUT_TO_PIN = 0x0 */ 401 cx_write(PLL_C_POST_STAT_BIST, 0x80000103); 402 403 /* clear reset bit [31] */ 404 tmp = cx_read(PLL_C_INT_FRAC); 405 cx_write(PLL_C_INT_FRAC, tmp & 0x7FFFFFFF); 406 407 /* PLL-D setting for audio upstream channel */ 408 cx_write(PLL_D_INT_FRAC, 0x98757F5B); 409 410 /* PLL_D_POST = 0x13, PLL_D_OUT_TO_PIN = 0x0 */ 411 cx_write(PLL_D_POST_STAT_BIST, 0x80000113); 412 413 /* clear reset bit [31] */ 414 tmp = cx_read(PLL_D_INT_FRAC); 415 cx_write(PLL_D_INT_FRAC, tmp & 0x7FFFFFFF); 416 417 /* This selects the PLL C clock source for the video upstream channel 418 * I and J */ 419 tmp = cx_read(VID_CH_CLK_SEL); 420 cx_write(VID_CH_CLK_SEL, (tmp & 0x00FFFFFF) | 0x24000000); 421 422 /* 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface for 423 * channel A-C 424 * select 656/VIP DST for downstream Channel A - C */ 425 tmp = cx_read(VID_CH_MODE_SEL); 426 /* cx_write( VID_CH_MODE_SEL, tmp | 0x1B0001FF); */ 427 cx_write(VID_CH_MODE_SEL, tmp & 0xFFFFFE00); 428 429 /* enables 656 port I and J as output */ 430 tmp = cx_read(CLK_RST); 431 /* use external ALT_PLL_REF pin as its reference clock instead */ 432 tmp |= FLD_USE_ALT_PLL_REF; 433 cx_write(CLK_RST, tmp & ~(FLD_VID_I_CLK_NOE | FLD_VID_J_CLK_NOE)); 434 435 mdelay(100); 436 } 437 438 int cx25821_sram_channel_setup(struct cx25821_dev *dev, 439 const struct sram_channel *ch, 440 unsigned int bpl, u32 risc) 441 { 442 unsigned int i, lines; 443 u32 cdt; 444 445 if (ch->cmds_start == 0) { 446 cx_write(ch->ptr1_reg, 0); 447 cx_write(ch->ptr2_reg, 0); 448 cx_write(ch->cnt2_reg, 0); 449 cx_write(ch->cnt1_reg, 0); 450 return 0; 451 } 452 453 bpl = (bpl + 7) & ~7; /* alignment */ 454 cdt = ch->cdt; 455 lines = ch->fifo_size / bpl; 456 457 if (lines > 4) 458 lines = 4; 459 460 BUG_ON(lines < 2); 461 462 cx_write(8 + 0, RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC); 463 cx_write(8 + 4, 8); 464 cx_write(8 + 8, 0); 465 466 /* write CDT */ 467 for (i = 0; i < lines; i++) { 468 cx_write(cdt + 16 * i, ch->fifo_start + bpl * i); 469 cx_write(cdt + 16 * i + 4, 0); 470 cx_write(cdt + 16 * i + 8, 0); 471 cx_write(cdt + 16 * i + 12, 0); 472 } 473 474 /* init the first cdt buffer */ 475 for (i = 0; i < 128; i++) 476 cx_write(ch->fifo_start + 4 * i, i); 477 478 /* write CMDS */ 479 if (ch->jumponly) 480 cx_write(ch->cmds_start + 0, 8); 481 else 482 cx_write(ch->cmds_start + 0, risc); 483 484 cx_write(ch->cmds_start + 4, 0); /* 64 bits 63-32 */ 485 cx_write(ch->cmds_start + 8, cdt); 486 cx_write(ch->cmds_start + 12, (lines * 16) >> 3); 487 cx_write(ch->cmds_start + 16, ch->ctrl_start); 488 489 if (ch->jumponly) 490 cx_write(ch->cmds_start + 20, 0x80000000 | (64 >> 2)); 491 else 492 cx_write(ch->cmds_start + 20, 64 >> 2); 493 494 for (i = 24; i < 80; i += 4) 495 cx_write(ch->cmds_start + i, 0); 496 497 /* fill registers */ 498 cx_write(ch->ptr1_reg, ch->fifo_start); 499 cx_write(ch->ptr2_reg, cdt); 500 cx_write(ch->cnt2_reg, (lines * 16) >> 3); 501 cx_write(ch->cnt1_reg, (bpl >> 3) - 1); 502 503 return 0; 504 } 505 506 int cx25821_sram_channel_setup_audio(struct cx25821_dev *dev, 507 const struct sram_channel *ch, 508 unsigned int bpl, u32 risc) 509 { 510 unsigned int i, lines; 511 u32 cdt; 512 513 if (ch->cmds_start == 0) { 514 cx_write(ch->ptr1_reg, 0); 515 cx_write(ch->ptr2_reg, 0); 516 cx_write(ch->cnt2_reg, 0); 517 cx_write(ch->cnt1_reg, 0); 518 return 0; 519 } 520 521 bpl = (bpl + 7) & ~7; /* alignment */ 522 cdt = ch->cdt; 523 lines = ch->fifo_size / bpl; 524 525 if (lines > 3) 526 lines = 3; /* for AUDIO */ 527 528 BUG_ON(lines < 2); 529 530 cx_write(8 + 0, RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC); 531 cx_write(8 + 4, 8); 532 cx_write(8 + 8, 0); 533 534 /* write CDT */ 535 for (i = 0; i < lines; i++) { 536 cx_write(cdt + 16 * i, ch->fifo_start + bpl * i); 537 cx_write(cdt + 16 * i + 4, 0); 538 cx_write(cdt + 16 * i + 8, 0); 539 cx_write(cdt + 16 * i + 12, 0); 540 } 541 542 /* write CMDS */ 543 if (ch->jumponly) 544 cx_write(ch->cmds_start + 0, 8); 545 else 546 cx_write(ch->cmds_start + 0, risc); 547 548 cx_write(ch->cmds_start + 4, 0); /* 64 bits 63-32 */ 549 cx_write(ch->cmds_start + 8, cdt); 550 cx_write(ch->cmds_start + 12, (lines * 16) >> 3); 551 cx_write(ch->cmds_start + 16, ch->ctrl_start); 552 553 /* IQ size */ 554 if (ch->jumponly) 555 cx_write(ch->cmds_start + 20, 0x80000000 | (64 >> 2)); 556 else 557 cx_write(ch->cmds_start + 20, 64 >> 2); 558 559 /* zero out */ 560 for (i = 24; i < 80; i += 4) 561 cx_write(ch->cmds_start + i, 0); 562 563 /* fill registers */ 564 cx_write(ch->ptr1_reg, ch->fifo_start); 565 cx_write(ch->ptr2_reg, cdt); 566 cx_write(ch->cnt2_reg, (lines * 16) >> 3); 567 cx_write(ch->cnt1_reg, (bpl >> 3) - 1); 568 569 return 0; 570 } 571 EXPORT_SYMBOL(cx25821_sram_channel_setup_audio); 572 573 void cx25821_sram_channel_dump(struct cx25821_dev *dev, const struct sram_channel *ch) 574 { 575 static char *name[] = { 576 "init risc lo", 577 "init risc hi", 578 "cdt base", 579 "cdt size", 580 "iq base", 581 "iq size", 582 "risc pc lo", 583 "risc pc hi", 584 "iq wr ptr", 585 "iq rd ptr", 586 "cdt current", 587 "pci target lo", 588 "pci target hi", 589 "line / byte", 590 }; 591 u32 risc; 592 unsigned int i, j, n; 593 594 pr_warn("%s: %s - dma channel status dump\n", dev->name, ch->name); 595 for (i = 0; i < ARRAY_SIZE(name); i++) 596 pr_warn("cmds + 0x%2x: %-15s: 0x%08x\n", 597 i * 4, name[i], cx_read(ch->cmds_start + 4 * i)); 598 599 j = i * 4; 600 for (i = 0; i < 4;) { 601 risc = cx_read(ch->cmds_start + 4 * (i + 14)); 602 pr_warn("cmds + 0x%2x: risc%d: ", j + i * 4, i); 603 i += cx25821_risc_decode(risc); 604 } 605 606 for (i = 0; i < (64 >> 2); i += n) { 607 risc = cx_read(ch->ctrl_start + 4 * i); 608 /* No consideration for bits 63-32 */ 609 610 pr_warn("ctrl + 0x%2x (0x%08x): iq %x: ", 611 i * 4, ch->ctrl_start + 4 * i, i); 612 n = cx25821_risc_decode(risc); 613 for (j = 1; j < n; j++) { 614 risc = cx_read(ch->ctrl_start + 4 * (i + j)); 615 pr_warn("ctrl + 0x%2x : iq %x: 0x%08x [ arg #%d ]\n", 616 4 * (i + j), i + j, risc, j); 617 } 618 } 619 620 pr_warn(" : fifo: 0x%08x -> 0x%x\n", 621 ch->fifo_start, ch->fifo_start + ch->fifo_size); 622 pr_warn(" : ctrl: 0x%08x -> 0x%x\n", 623 ch->ctrl_start, ch->ctrl_start + 6 * 16); 624 pr_warn(" : ptr1_reg: 0x%08x\n", 625 cx_read(ch->ptr1_reg)); 626 pr_warn(" : ptr2_reg: 0x%08x\n", 627 cx_read(ch->ptr2_reg)); 628 pr_warn(" : cnt1_reg: 0x%08x\n", 629 cx_read(ch->cnt1_reg)); 630 pr_warn(" : cnt2_reg: 0x%08x\n", 631 cx_read(ch->cnt2_reg)); 632 } 633 634 void cx25821_sram_channel_dump_audio(struct cx25821_dev *dev, 635 const struct sram_channel *ch) 636 { 637 static const char * const name[] = { 638 "init risc lo", 639 "init risc hi", 640 "cdt base", 641 "cdt size", 642 "iq base", 643 "iq size", 644 "risc pc lo", 645 "risc pc hi", 646 "iq wr ptr", 647 "iq rd ptr", 648 "cdt current", 649 "pci target lo", 650 "pci target hi", 651 "line / byte", 652 }; 653 654 u32 risc, value, tmp; 655 unsigned int i, j, n; 656 657 pr_info("\n%s: %s - dma Audio channel status dump\n", 658 dev->name, ch->name); 659 660 for (i = 0; i < ARRAY_SIZE(name); i++) 661 pr_info("%s: cmds + 0x%2x: %-15s: 0x%08x\n", 662 dev->name, i * 4, name[i], 663 cx_read(ch->cmds_start + 4 * i)); 664 665 j = i * 4; 666 for (i = 0; i < 4;) { 667 risc = cx_read(ch->cmds_start + 4 * (i + 14)); 668 pr_warn("cmds + 0x%2x: risc%d: ", j + i * 4, i); 669 i += cx25821_risc_decode(risc); 670 } 671 672 for (i = 0; i < (64 >> 2); i += n) { 673 risc = cx_read(ch->ctrl_start + 4 * i); 674 /* No consideration for bits 63-32 */ 675 676 pr_warn("ctrl + 0x%2x (0x%08x): iq %x: ", 677 i * 4, ch->ctrl_start + 4 * i, i); 678 n = cx25821_risc_decode(risc); 679 680 for (j = 1; j < n; j++) { 681 risc = cx_read(ch->ctrl_start + 4 * (i + j)); 682 pr_warn("ctrl + 0x%2x : iq %x: 0x%08x [ arg #%d ]\n", 683 4 * (i + j), i + j, risc, j); 684 } 685 } 686 687 pr_warn(" : fifo: 0x%08x -> 0x%x\n", 688 ch->fifo_start, ch->fifo_start + ch->fifo_size); 689 pr_warn(" : ctrl: 0x%08x -> 0x%x\n", 690 ch->ctrl_start, ch->ctrl_start + 6 * 16); 691 pr_warn(" : ptr1_reg: 0x%08x\n", 692 cx_read(ch->ptr1_reg)); 693 pr_warn(" : ptr2_reg: 0x%08x\n", 694 cx_read(ch->ptr2_reg)); 695 pr_warn(" : cnt1_reg: 0x%08x\n", 696 cx_read(ch->cnt1_reg)); 697 pr_warn(" : cnt2_reg: 0x%08x\n", 698 cx_read(ch->cnt2_reg)); 699 700 for (i = 0; i < 4; i++) { 701 risc = cx_read(ch->cmds_start + 56 + (i * 4)); 702 pr_warn("instruction %d = 0x%x\n", i, risc); 703 } 704 705 /* read data from the first cdt buffer */ 706 risc = cx_read(AUD_A_CDT); 707 pr_warn("\nread cdt loc=0x%x\n", risc); 708 for (i = 0; i < 8; i++) { 709 n = cx_read(risc + i * 4); 710 pr_cont("0x%x ", n); 711 } 712 pr_cont("\n\n"); 713 714 value = cx_read(CLK_RST); 715 CX25821_INFO(" CLK_RST = 0x%x\n\n", value); 716 717 value = cx_read(PLL_A_POST_STAT_BIST); 718 CX25821_INFO(" PLL_A_POST_STAT_BIST = 0x%x\n\n", value); 719 value = cx_read(PLL_A_INT_FRAC); 720 CX25821_INFO(" PLL_A_INT_FRAC = 0x%x\n\n", value); 721 722 value = cx_read(PLL_B_POST_STAT_BIST); 723 CX25821_INFO(" PLL_B_POST_STAT_BIST = 0x%x\n\n", value); 724 value = cx_read(PLL_B_INT_FRAC); 725 CX25821_INFO(" PLL_B_INT_FRAC = 0x%x\n\n", value); 726 727 value = cx_read(PLL_C_POST_STAT_BIST); 728 CX25821_INFO(" PLL_C_POST_STAT_BIST = 0x%x\n\n", value); 729 value = cx_read(PLL_C_INT_FRAC); 730 CX25821_INFO(" PLL_C_INT_FRAC = 0x%x\n\n", value); 731 732 value = cx_read(PLL_D_POST_STAT_BIST); 733 CX25821_INFO(" PLL_D_POST_STAT_BIST = 0x%x\n\n", value); 734 value = cx_read(PLL_D_INT_FRAC); 735 CX25821_INFO(" PLL_D_INT_FRAC = 0x%x\n\n", value); 736 737 value = cx25821_i2c_read(&dev->i2c_bus[0], AFE_AB_DIAG_CTRL, &tmp); 738 CX25821_INFO(" AFE_AB_DIAG_CTRL (0x10900090) = 0x%x\n\n", value); 739 } 740 EXPORT_SYMBOL(cx25821_sram_channel_dump_audio); 741 742 static void cx25821_shutdown(struct cx25821_dev *dev) 743 { 744 int i; 745 746 /* disable RISC controller */ 747 cx_write(DEV_CNTRL2, 0); 748 749 /* Disable Video A/B activity */ 750 for (i = 0; i < VID_CHANNEL_NUM; i++) { 751 cx_write(dev->channels[i].sram_channels->dma_ctl, 0); 752 cx_write(dev->channels[i].sram_channels->int_msk, 0); 753 } 754 755 for (i = VID_UPSTREAM_SRAM_CHANNEL_I; 756 i <= VID_UPSTREAM_SRAM_CHANNEL_J; i++) { 757 cx_write(dev->channels[i].sram_channels->dma_ctl, 0); 758 cx_write(dev->channels[i].sram_channels->int_msk, 0); 759 } 760 761 /* Disable Audio activity */ 762 cx_write(AUD_INT_DMA_CTL, 0); 763 764 /* Disable Serial port */ 765 cx_write(UART_CTL, 0); 766 767 /* Disable Interrupts */ 768 cx_write(PCI_INT_MSK, 0); 769 cx_write(AUD_A_INT_MSK, 0); 770 } 771 772 void cx25821_set_pixel_format(struct cx25821_dev *dev, int channel_select, 773 u32 format) 774 { 775 if (channel_select <= 7 && channel_select >= 0) { 776 cx_write(dev->channels[channel_select].sram_channels->pix_frmt, 777 format); 778 } 779 dev->channels[channel_select].pixel_formats = format; 780 } 781 782 static void cx25821_set_vip_mode(struct cx25821_dev *dev, 783 const struct sram_channel *ch) 784 { 785 cx_write(ch->pix_frmt, PIXEL_FRMT_422); 786 cx_write(ch->vip_ctl, PIXEL_ENGINE_VIP1); 787 } 788 789 static void cx25821_initialize(struct cx25821_dev *dev) 790 { 791 int i; 792 793 dprintk(1, "%s()\n", __func__); 794 795 cx25821_shutdown(dev); 796 cx_write(PCI_INT_STAT, 0xffffffff); 797 798 for (i = 0; i < VID_CHANNEL_NUM; i++) 799 cx_write(dev->channels[i].sram_channels->int_stat, 0xffffffff); 800 801 cx_write(AUD_A_INT_STAT, 0xffffffff); 802 cx_write(AUD_B_INT_STAT, 0xffffffff); 803 cx_write(AUD_C_INT_STAT, 0xffffffff); 804 cx_write(AUD_D_INT_STAT, 0xffffffff); 805 cx_write(AUD_E_INT_STAT, 0xffffffff); 806 807 cx_write(CLK_DELAY, cx_read(CLK_DELAY) & 0x80000000); 808 cx_write(PAD_CTRL, 0x12); /* for I2C */ 809 cx25821_registers_init(dev); /* init Pecos registers */ 810 mdelay(100); 811 812 for (i = 0; i < VID_CHANNEL_NUM; i++) { 813 cx25821_set_vip_mode(dev, dev->channels[i].sram_channels); 814 cx25821_sram_channel_setup(dev, dev->channels[i].sram_channels, 815 1440, 0); 816 dev->channels[i].pixel_formats = PIXEL_FRMT_422; 817 dev->channels[i].use_cif_resolution = 0; 818 } 819 820 /* Probably only affect Downstream */ 821 for (i = VID_UPSTREAM_SRAM_CHANNEL_I; 822 i <= VID_UPSTREAM_SRAM_CHANNEL_J; i++) { 823 dev->channels[i].pixel_formats = PIXEL_FRMT_422; 824 cx25821_set_vip_mode(dev, dev->channels[i].sram_channels); 825 } 826 827 cx25821_sram_channel_setup_audio(dev, 828 dev->channels[SRAM_CH08].sram_channels, 128, 0); 829 830 cx25821_gpio_init(dev); 831 } 832 833 static int cx25821_get_resources(struct cx25821_dev *dev) 834 { 835 if (request_mem_region(pci_resource_start(dev->pci, 0), 836 pci_resource_len(dev->pci, 0), dev->name)) 837 return 0; 838 839 pr_err("%s: can't get MMIO memory @ 0x%llx\n", 840 dev->name, (unsigned long long)pci_resource_start(dev->pci, 0)); 841 842 return -EBUSY; 843 } 844 845 static void cx25821_dev_checkrevision(struct cx25821_dev *dev) 846 { 847 dev->hwrevision = cx_read(RDR_CFG2) & 0xff; 848 849 pr_info("Hardware revision = 0x%02x\n", dev->hwrevision); 850 } 851 852 static void cx25821_iounmap(struct cx25821_dev *dev) 853 { 854 if (dev == NULL) 855 return; 856 857 /* Releasing IO memory */ 858 if (dev->lmmio != NULL) { 859 iounmap(dev->lmmio); 860 dev->lmmio = NULL; 861 } 862 } 863 864 static int cx25821_dev_setup(struct cx25821_dev *dev) 865 { 866 static unsigned int cx25821_devcount; 867 int i; 868 869 mutex_init(&dev->lock); 870 871 dev->nr = ++cx25821_devcount; 872 sprintf(dev->name, "cx25821[%d]", dev->nr); 873 874 if (dev->pci->device != 0x8210) { 875 pr_info("%s(): Exiting. Incorrect Hardware device = 0x%02x\n", 876 __func__, dev->pci->device); 877 return -1; 878 } else { 879 pr_info("Athena Hardware device = 0x%02x\n", dev->pci->device); 880 } 881 882 /* Apply a sensible clock frequency for the PCIe bridge */ 883 dev->clk_freq = 28000000; 884 for (i = 0; i < MAX_VID_CHANNEL_NUM; i++) { 885 dev->channels[i].dev = dev; 886 dev->channels[i].id = i; 887 dev->channels[i].sram_channels = &cx25821_sram_channels[i]; 888 } 889 890 if (dev->nr > 1) 891 CX25821_INFO("dev->nr > 1!"); 892 893 /* board config */ 894 dev->board = 1; /* card[dev->nr]; */ 895 dev->_max_num_decoders = MAX_DECODERS; 896 897 dev->pci_bus = dev->pci->bus->number; 898 dev->pci_slot = PCI_SLOT(dev->pci->devfn); 899 dev->pci_irqmask = 0x001f00; 900 901 /* External Master 1 Bus */ 902 dev->i2c_bus[0].nr = 0; 903 dev->i2c_bus[0].dev = dev; 904 dev->i2c_bus[0].reg_stat = I2C1_STAT; 905 dev->i2c_bus[0].reg_ctrl = I2C1_CTRL; 906 dev->i2c_bus[0].reg_addr = I2C1_ADDR; 907 dev->i2c_bus[0].reg_rdata = I2C1_RDATA; 908 dev->i2c_bus[0].reg_wdata = I2C1_WDATA; 909 dev->i2c_bus[0].i2c_period = (0x07 << 24); /* 1.95MHz */ 910 911 if (cx25821_get_resources(dev) < 0) { 912 pr_err("%s: No more PCIe resources for subsystem: %04x:%04x\n", 913 dev->name, dev->pci->subsystem_vendor, 914 dev->pci->subsystem_device); 915 916 cx25821_devcount--; 917 return -EBUSY; 918 } 919 920 /* PCIe stuff */ 921 dev->base_io_addr = pci_resource_start(dev->pci, 0); 922 923 if (!dev->base_io_addr) { 924 CX25821_ERR("No PCI Memory resources, exiting!\n"); 925 return -ENODEV; 926 } 927 928 dev->lmmio = ioremap(dev->base_io_addr, pci_resource_len(dev->pci, 0)); 929 930 if (!dev->lmmio) { 931 CX25821_ERR("ioremap failed, maybe increasing __VMALLOC_RESERVE in page.h\n"); 932 cx25821_iounmap(dev); 933 return -ENOMEM; 934 } 935 936 dev->bmmio = (u8 __iomem *) dev->lmmio; 937 938 pr_info("%s: subsystem: %04x:%04x, board: %s [card=%d,%s]\n", 939 dev->name, dev->pci->subsystem_vendor, 940 dev->pci->subsystem_device, cx25821_boards[dev->board].name, 941 dev->board, card[dev->nr] == dev->board ? 942 "insmod option" : "autodetected"); 943 944 /* init hardware */ 945 cx25821_initialize(dev); 946 947 cx25821_i2c_register(&dev->i2c_bus[0]); 948 /* cx25821_i2c_register(&dev->i2c_bus[1]); 949 * cx25821_i2c_register(&dev->i2c_bus[2]); */ 950 951 if (medusa_video_init(dev) < 0) 952 CX25821_ERR("%s(): Failed to initialize medusa!\n", __func__); 953 954 cx25821_video_register(dev); 955 956 cx25821_dev_checkrevision(dev); 957 return 0; 958 } 959 960 void cx25821_dev_unregister(struct cx25821_dev *dev) 961 { 962 int i; 963 964 if (!dev->base_io_addr) 965 return; 966 967 release_mem_region(dev->base_io_addr, pci_resource_len(dev->pci, 0)); 968 969 for (i = 0; i < MAX_VID_CHANNEL_NUM - 1; i++) { 970 if (i == SRAM_CH08) /* audio channel */ 971 continue; 972 if (i == SRAM_CH09 || i == SRAM_CH10) 973 cx25821_free_mem_upstream(&dev->channels[i]); 974 cx25821_video_unregister(dev, i); 975 } 976 977 cx25821_i2c_unregister(&dev->i2c_bus[0]); 978 cx25821_iounmap(dev); 979 } 980 EXPORT_SYMBOL(cx25821_dev_unregister); 981 982 static __le32 *cx25821_risc_field(__le32 * rp, struct scatterlist *sglist, 983 unsigned int offset, u32 sync_line, 984 unsigned int bpl, unsigned int padding, 985 unsigned int lines) 986 { 987 struct scatterlist *sg; 988 unsigned int line, todo; 989 990 /* sync instruction */ 991 if (sync_line != NO_SYNC_LINE) 992 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line); 993 994 /* scan lines */ 995 sg = sglist; 996 for (line = 0; line < lines; line++) { 997 while (offset && offset >= sg_dma_len(sg)) { 998 offset -= sg_dma_len(sg); 999 sg = sg_next(sg); 1000 } 1001 if (bpl <= sg_dma_len(sg) - offset) { 1002 /* fits into current chunk */ 1003 *(rp++) = cpu_to_le32(RISC_WRITE | RISC_SOL | RISC_EOL | 1004 bpl); 1005 *(rp++) = cpu_to_le32(sg_dma_address(sg) + offset); 1006 *(rp++) = cpu_to_le32(0); /* bits 63-32 */ 1007 offset += bpl; 1008 } else { 1009 /* scanline needs to be split */ 1010 todo = bpl; 1011 *(rp++) = cpu_to_le32(RISC_WRITE | RISC_SOL | 1012 (sg_dma_len(sg) - offset)); 1013 *(rp++) = cpu_to_le32(sg_dma_address(sg) + offset); 1014 *(rp++) = cpu_to_le32(0); /* bits 63-32 */ 1015 todo -= (sg_dma_len(sg) - offset); 1016 offset = 0; 1017 sg = sg_next(sg); 1018 while (todo > sg_dma_len(sg)) { 1019 *(rp++) = cpu_to_le32(RISC_WRITE | 1020 sg_dma_len(sg)); 1021 *(rp++) = cpu_to_le32(sg_dma_address(sg)); 1022 *(rp++) = cpu_to_le32(0); /* bits 63-32 */ 1023 todo -= sg_dma_len(sg); 1024 sg = sg_next(sg); 1025 } 1026 *(rp++) = cpu_to_le32(RISC_WRITE | RISC_EOL | todo); 1027 *(rp++) = cpu_to_le32(sg_dma_address(sg)); 1028 *(rp++) = cpu_to_le32(0); /* bits 63-32 */ 1029 offset += todo; 1030 } 1031 1032 offset += padding; 1033 } 1034 1035 return rp; 1036 } 1037 1038 int cx25821_risc_buffer(struct pci_dev *pci, struct btcx_riscmem *risc, 1039 struct scatterlist *sglist, unsigned int top_offset, 1040 unsigned int bottom_offset, unsigned int bpl, 1041 unsigned int padding, unsigned int lines) 1042 { 1043 u32 instructions; 1044 u32 fields; 1045 __le32 *rp; 1046 int rc; 1047 1048 fields = 0; 1049 if (UNSET != top_offset) 1050 fields++; 1051 if (UNSET != bottom_offset) 1052 fields++; 1053 1054 /* estimate risc mem: worst case is one write per page border + 1055 one write per scan line + syncs + jump (all 2 dwords). Padding 1056 can cause next bpl to start close to a page border. First DMA 1057 region may be smaller than PAGE_SIZE */ 1058 /* write and jump need and extra dword */ 1059 instructions = fields * (1 + ((bpl + padding) * lines) / PAGE_SIZE + 1060 lines); 1061 instructions += 2; 1062 rc = btcx_riscmem_alloc(pci, risc, instructions * 12); 1063 1064 if (rc < 0) 1065 return rc; 1066 1067 /* write risc instructions */ 1068 rp = risc->cpu; 1069 1070 if (UNSET != top_offset) { 1071 rp = cx25821_risc_field(rp, sglist, top_offset, 0, bpl, padding, 1072 lines); 1073 } 1074 1075 if (UNSET != bottom_offset) { 1076 rp = cx25821_risc_field(rp, sglist, bottom_offset, 0x200, bpl, 1077 padding, lines); 1078 } 1079 1080 /* save pointer to jmp instruction address */ 1081 risc->jmp = rp; 1082 BUG_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size); 1083 1084 return 0; 1085 } 1086 1087 static __le32 *cx25821_risc_field_audio(__le32 * rp, struct scatterlist *sglist, 1088 unsigned int offset, u32 sync_line, 1089 unsigned int bpl, unsigned int padding, 1090 unsigned int lines, unsigned int lpi) 1091 { 1092 struct scatterlist *sg; 1093 unsigned int line, todo, sol; 1094 1095 /* sync instruction */ 1096 if (sync_line != NO_SYNC_LINE) 1097 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line); 1098 1099 /* scan lines */ 1100 sg = sglist; 1101 for (line = 0; line < lines; line++) { 1102 while (offset && offset >= sg_dma_len(sg)) { 1103 offset -= sg_dma_len(sg); 1104 sg = sg_next(sg); 1105 } 1106 1107 if (lpi && line > 0 && !(line % lpi)) 1108 sol = RISC_SOL | RISC_IRQ1 | RISC_CNT_INC; 1109 else 1110 sol = RISC_SOL; 1111 1112 if (bpl <= sg_dma_len(sg) - offset) { 1113 /* fits into current chunk */ 1114 *(rp++) = cpu_to_le32(RISC_WRITE | sol | RISC_EOL | 1115 bpl); 1116 *(rp++) = cpu_to_le32(sg_dma_address(sg) + offset); 1117 *(rp++) = cpu_to_le32(0); /* bits 63-32 */ 1118 offset += bpl; 1119 } else { 1120 /* scanline needs to be split */ 1121 todo = bpl; 1122 *(rp++) = cpu_to_le32(RISC_WRITE | sol | 1123 (sg_dma_len(sg) - offset)); 1124 *(rp++) = cpu_to_le32(sg_dma_address(sg) + offset); 1125 *(rp++) = cpu_to_le32(0); /* bits 63-32 */ 1126 todo -= (sg_dma_len(sg) - offset); 1127 offset = 0; 1128 sg = sg_next(sg); 1129 while (todo > sg_dma_len(sg)) { 1130 *(rp++) = cpu_to_le32(RISC_WRITE | 1131 sg_dma_len(sg)); 1132 *(rp++) = cpu_to_le32(sg_dma_address(sg)); 1133 *(rp++) = cpu_to_le32(0); /* bits 63-32 */ 1134 todo -= sg_dma_len(sg); 1135 sg = sg_next(sg); 1136 } 1137 *(rp++) = cpu_to_le32(RISC_WRITE | RISC_EOL | todo); 1138 *(rp++) = cpu_to_le32(sg_dma_address(sg)); 1139 *(rp++) = cpu_to_le32(0); /* bits 63-32 */ 1140 offset += todo; 1141 } 1142 offset += padding; 1143 } 1144 1145 return rp; 1146 } 1147 1148 int cx25821_risc_databuffer_audio(struct pci_dev *pci, 1149 struct btcx_riscmem *risc, 1150 struct scatterlist *sglist, 1151 unsigned int bpl, 1152 unsigned int lines, unsigned int lpi) 1153 { 1154 u32 instructions; 1155 __le32 *rp; 1156 int rc; 1157 1158 /* estimate risc mem: worst case is one write per page border + 1159 one write per scan line + syncs + jump (all 2 dwords). Here 1160 there is no padding and no sync. First DMA region may be smaller 1161 than PAGE_SIZE */ 1162 /* Jump and write need an extra dword */ 1163 instructions = 1 + (bpl * lines) / PAGE_SIZE + lines; 1164 instructions += 1; 1165 1166 rc = btcx_riscmem_alloc(pci, risc, instructions * 12); 1167 if (rc < 0) 1168 return rc; 1169 1170 /* write risc instructions */ 1171 rp = risc->cpu; 1172 rp = cx25821_risc_field_audio(rp, sglist, 0, NO_SYNC_LINE, bpl, 0, 1173 lines, lpi); 1174 1175 /* save pointer to jmp instruction address */ 1176 risc->jmp = rp; 1177 BUG_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size); 1178 return 0; 1179 } 1180 EXPORT_SYMBOL(cx25821_risc_databuffer_audio); 1181 1182 int cx25821_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc, 1183 u32 reg, u32 mask, u32 value) 1184 { 1185 __le32 *rp; 1186 int rc; 1187 1188 rc = btcx_riscmem_alloc(pci, risc, 4 * 16); 1189 1190 if (rc < 0) 1191 return rc; 1192 1193 /* write risc instructions */ 1194 rp = risc->cpu; 1195 1196 *(rp++) = cpu_to_le32(RISC_WRITECR | RISC_IRQ1); 1197 *(rp++) = cpu_to_le32(reg); 1198 *(rp++) = cpu_to_le32(value); 1199 *(rp++) = cpu_to_le32(mask); 1200 *(rp++) = cpu_to_le32(RISC_JUMP); 1201 *(rp++) = cpu_to_le32(risc->dma); 1202 *(rp++) = cpu_to_le32(0); /* bits 63-32 */ 1203 return 0; 1204 } 1205 1206 void cx25821_free_buffer(struct videobuf_queue *q, struct cx25821_buffer *buf) 1207 { 1208 struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb); 1209 1210 BUG_ON(in_interrupt()); 1211 videobuf_waiton(q, &buf->vb, 0, 0); 1212 videobuf_dma_unmap(q->dev, dma); 1213 videobuf_dma_free(dma); 1214 btcx_riscmem_free(to_pci_dev(q->dev), &buf->risc); 1215 buf->vb.state = VIDEOBUF_NEEDS_INIT; 1216 } 1217 1218 static irqreturn_t cx25821_irq(int irq, void *dev_id) 1219 { 1220 struct cx25821_dev *dev = dev_id; 1221 u32 pci_status; 1222 u32 vid_status; 1223 int i, handled = 0; 1224 u32 mask[8] = { 1, 2, 4, 8, 16, 32, 64, 128 }; 1225 1226 pci_status = cx_read(PCI_INT_STAT); 1227 1228 if (pci_status == 0) 1229 goto out; 1230 1231 for (i = 0; i < VID_CHANNEL_NUM; i++) { 1232 if (pci_status & mask[i]) { 1233 vid_status = cx_read(dev->channels[i]. 1234 sram_channels->int_stat); 1235 1236 if (vid_status) 1237 handled += cx25821_video_irq(dev, i, 1238 vid_status); 1239 1240 cx_write(PCI_INT_STAT, mask[i]); 1241 } 1242 } 1243 1244 out: 1245 return IRQ_RETVAL(handled); 1246 } 1247 1248 void cx25821_print_irqbits(char *name, char *tag, char **strings, 1249 int len, u32 bits, u32 mask) 1250 { 1251 unsigned int i; 1252 1253 printk(KERN_DEBUG pr_fmt("%s: %s [0x%x]"), name, tag, bits); 1254 1255 for (i = 0; i < len; i++) { 1256 if (!(bits & (1 << i))) 1257 continue; 1258 if (strings[i]) 1259 pr_cont(" %s", strings[i]); 1260 else 1261 pr_cont(" %d", i); 1262 if (!(mask & (1 << i))) 1263 continue; 1264 pr_cont("*"); 1265 } 1266 pr_cont("\n"); 1267 } 1268 EXPORT_SYMBOL(cx25821_print_irqbits); 1269 1270 struct cx25821_dev *cx25821_dev_get(struct pci_dev *pci) 1271 { 1272 struct cx25821_dev *dev = pci_get_drvdata(pci); 1273 return dev; 1274 } 1275 EXPORT_SYMBOL(cx25821_dev_get); 1276 1277 static int cx25821_initdev(struct pci_dev *pci_dev, 1278 const struct pci_device_id *pci_id) 1279 { 1280 struct cx25821_dev *dev; 1281 int err = 0; 1282 1283 dev = kzalloc(sizeof(*dev), GFP_KERNEL); 1284 if (NULL == dev) 1285 return -ENOMEM; 1286 1287 err = v4l2_device_register(&pci_dev->dev, &dev->v4l2_dev); 1288 if (err < 0) 1289 goto fail_free; 1290 1291 /* pci init */ 1292 dev->pci = pci_dev; 1293 if (pci_enable_device(pci_dev)) { 1294 err = -EIO; 1295 1296 pr_info("pci enable failed!\n"); 1297 1298 goto fail_unregister_device; 1299 } 1300 1301 err = cx25821_dev_setup(dev); 1302 if (err) { 1303 if (err == -EBUSY) 1304 goto fail_unregister_device; 1305 else 1306 goto fail_unregister_pci; 1307 } 1308 1309 /* print pci info */ 1310 pci_read_config_byte(pci_dev, PCI_CLASS_REVISION, &dev->pci_rev); 1311 pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &dev->pci_lat); 1312 pr_info("%s/0: found at %s, rev: %d, irq: %d, latency: %d, mmio: 0x%llx\n", 1313 dev->name, pci_name(pci_dev), dev->pci_rev, pci_dev->irq, 1314 dev->pci_lat, (unsigned long long)dev->base_io_addr); 1315 1316 pci_set_master(pci_dev); 1317 if (!pci_dma_supported(pci_dev, 0xffffffff)) { 1318 pr_err("%s/0: Oops: no 32bit PCI DMA ???\n", dev->name); 1319 err = -EIO; 1320 goto fail_irq; 1321 } 1322 1323 err = request_irq(pci_dev->irq, cx25821_irq, 1324 IRQF_SHARED, dev->name, dev); 1325 1326 if (err < 0) { 1327 pr_err("%s: can't get IRQ %d\n", dev->name, pci_dev->irq); 1328 goto fail_irq; 1329 } 1330 1331 return 0; 1332 1333 fail_irq: 1334 pr_info("cx25821_initdev() can't get IRQ !\n"); 1335 cx25821_dev_unregister(dev); 1336 1337 fail_unregister_pci: 1338 pci_disable_device(pci_dev); 1339 fail_unregister_device: 1340 v4l2_device_unregister(&dev->v4l2_dev); 1341 1342 fail_free: 1343 kfree(dev); 1344 return err; 1345 } 1346 1347 static void cx25821_finidev(struct pci_dev *pci_dev) 1348 { 1349 struct v4l2_device *v4l2_dev = pci_get_drvdata(pci_dev); 1350 struct cx25821_dev *dev = get_cx25821(v4l2_dev); 1351 1352 cx25821_shutdown(dev); 1353 pci_disable_device(pci_dev); 1354 1355 /* unregister stuff */ 1356 if (pci_dev->irq) 1357 free_irq(pci_dev->irq, dev); 1358 1359 cx25821_dev_unregister(dev); 1360 v4l2_device_unregister(v4l2_dev); 1361 kfree(dev); 1362 } 1363 1364 static const struct pci_device_id cx25821_pci_tbl[] = { 1365 { 1366 /* CX25821 Athena */ 1367 .vendor = 0x14f1, 1368 .device = 0x8210, 1369 .subvendor = 0x14f1, 1370 .subdevice = 0x0920, 1371 }, { 1372 /* CX25821 No Brand */ 1373 .vendor = 0x14f1, 1374 .device = 0x8210, 1375 .subvendor = 0x0000, 1376 .subdevice = 0x0000, 1377 }, { 1378 /* --- end of list --- */ 1379 } 1380 }; 1381 1382 MODULE_DEVICE_TABLE(pci, cx25821_pci_tbl); 1383 1384 static struct pci_driver cx25821_pci_driver = { 1385 .name = "cx25821", 1386 .id_table = cx25821_pci_tbl, 1387 .probe = cx25821_initdev, 1388 .remove = cx25821_finidev, 1389 /* TODO */ 1390 .suspend = NULL, 1391 .resume = NULL, 1392 }; 1393 1394 static int __init cx25821_init(void) 1395 { 1396 pr_info("driver version %d.%d.%d loaded\n", 1397 (CX25821_VERSION_CODE >> 16) & 0xff, 1398 (CX25821_VERSION_CODE >> 8) & 0xff, 1399 CX25821_VERSION_CODE & 0xff); 1400 return pci_register_driver(&cx25821_pci_driver); 1401 } 1402 1403 static void __exit cx25821_fini(void) 1404 { 1405 pci_unregister_driver(&cx25821_pci_driver); 1406 } 1407 1408 module_init(cx25821_init); 1409 module_exit(cx25821_fini); 1410