1 /*
2  *  Driver for the Conexant CX23885/7/8 PCIe bridge
3  *
4  *  CX23888 Integrated Consumer Infrared Controller
5  *
6  *  Copyright (C) 2009  Andy Walls <awalls@md.metrocast.net>
7  *
8  *  This program is free software; you can redistribute it and/or
9  *  modify it under the terms of the GNU General Public License
10  *  as published by the Free Software Foundation; either version 2
11  *  of the License, or (at your option) any later version.
12  *
13  *  This program is distributed in the hope that it will be useful,
14  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
15  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  *  GNU General Public License for more details.
17  */
18 
19 #include "cx23885.h"
20 #include "cx23888-ir.h"
21 
22 #include <linux/kfifo.h>
23 #include <linux/slab.h>
24 
25 #include <media/v4l2-device.h>
26 #include <media/rc-core.h>
27 
28 static unsigned int ir_888_debug;
29 module_param(ir_888_debug, int, 0644);
30 MODULE_PARM_DESC(ir_888_debug, "enable debug messages [CX23888 IR controller]");
31 
32 #define CX23888_IR_REG_BASE	0x170000
33 /*
34  * These CX23888 register offsets have a straightforward one to one mapping
35  * to the CX23885 register offsets of 0x200 through 0x218
36  */
37 #define CX23888_IR_CNTRL_REG	0x170000
38 #define CNTRL_WIN_3_3	0x00000000
39 #define CNTRL_WIN_4_3	0x00000001
40 #define CNTRL_WIN_3_4	0x00000002
41 #define CNTRL_WIN_4_4	0x00000003
42 #define CNTRL_WIN	0x00000003
43 #define CNTRL_EDG_NONE	0x00000000
44 #define CNTRL_EDG_FALL	0x00000004
45 #define CNTRL_EDG_RISE	0x00000008
46 #define CNTRL_EDG_BOTH	0x0000000C
47 #define CNTRL_EDG	0x0000000C
48 #define CNTRL_DMD	0x00000010
49 #define CNTRL_MOD	0x00000020
50 #define CNTRL_RFE	0x00000040
51 #define CNTRL_TFE	0x00000080
52 #define CNTRL_RXE	0x00000100
53 #define CNTRL_TXE	0x00000200
54 #define CNTRL_RIC	0x00000400
55 #define CNTRL_TIC	0x00000800
56 #define CNTRL_CPL	0x00001000
57 #define CNTRL_LBM	0x00002000
58 #define CNTRL_R		0x00004000
59 /* CX23888 specific control flag */
60 #define CNTRL_IVO	0x00008000
61 
62 #define CX23888_IR_TXCLK_REG	0x170004
63 #define TXCLK_TCD	0x0000FFFF
64 
65 #define CX23888_IR_RXCLK_REG	0x170008
66 #define RXCLK_RCD	0x0000FFFF
67 
68 #define CX23888_IR_CDUTY_REG	0x17000C
69 #define CDUTY_CDC	0x0000000F
70 
71 #define CX23888_IR_STATS_REG	0x170010
72 #define STATS_RTO	0x00000001
73 #define STATS_ROR	0x00000002
74 #define STATS_RBY	0x00000004
75 #define STATS_TBY	0x00000008
76 #define STATS_RSR	0x00000010
77 #define STATS_TSR	0x00000020
78 
79 #define CX23888_IR_IRQEN_REG	0x170014
80 #define IRQEN_RTE	0x00000001
81 #define IRQEN_ROE	0x00000002
82 #define IRQEN_RSE	0x00000010
83 #define IRQEN_TSE	0x00000020
84 
85 #define CX23888_IR_FILTR_REG	0x170018
86 #define FILTR_LPF	0x0000FFFF
87 
88 /* This register doesn't follow the pattern; it's 0x23C on a CX23885 */
89 #define CX23888_IR_FIFO_REG	0x170040
90 #define FIFO_RXTX	0x0000FFFF
91 #define FIFO_RXTX_LVL	0x00010000
92 #define FIFO_RXTX_RTO	0x0001FFFF
93 #define FIFO_RX_NDV	0x00020000
94 #define FIFO_RX_DEPTH	8
95 #define FIFO_TX_DEPTH	8
96 
97 /* CX23888 unique registers */
98 #define CX23888_IR_SEEDP_REG	0x17001C
99 #define CX23888_IR_TIMOL_REG	0x170020
100 #define CX23888_IR_WAKE0_REG	0x170024
101 #define CX23888_IR_WAKE1_REG	0x170028
102 #define CX23888_IR_WAKE2_REG	0x17002C
103 #define CX23888_IR_MASK0_REG	0x170030
104 #define CX23888_IR_MASK1_REG	0x170034
105 #define CX23888_IR_MAKS2_REG	0x170038
106 #define CX23888_IR_DPIPG_REG	0x17003C
107 #define CX23888_IR_LEARN_REG	0x170044
108 
109 #define CX23888_VIDCLK_FREQ	108000000 /* 108 MHz, BT.656 */
110 #define CX23888_IR_REFCLK_FREQ	(CX23888_VIDCLK_FREQ / 2)
111 
112 /*
113  * We use this union internally for convenience, but callers to tx_write
114  * and rx_read will be expecting records of type struct ir_raw_event.
115  * Always ensure the size of this union is dictated by struct ir_raw_event.
116  */
117 union cx23888_ir_fifo_rec {
118 	u32 hw_fifo_data;
119 	struct ir_raw_event ir_core_data;
120 };
121 
122 #define CX23888_IR_RX_KFIFO_SIZE    (256 * sizeof(union cx23888_ir_fifo_rec))
123 #define CX23888_IR_TX_KFIFO_SIZE    (256 * sizeof(union cx23888_ir_fifo_rec))
124 
125 struct cx23888_ir_state {
126 	struct v4l2_subdev sd;
127 	struct cx23885_dev *dev;
128 
129 	struct v4l2_subdev_ir_parameters rx_params;
130 	struct mutex rx_params_lock;
131 	atomic_t rxclk_divider;
132 	atomic_t rx_invert;
133 
134 	struct kfifo rx_kfifo;
135 	spinlock_t rx_kfifo_lock;
136 
137 	struct v4l2_subdev_ir_parameters tx_params;
138 	struct mutex tx_params_lock;
139 	atomic_t txclk_divider;
140 };
141 
142 static inline struct cx23888_ir_state *to_state(struct v4l2_subdev *sd)
143 {
144 	return v4l2_get_subdevdata(sd);
145 }
146 
147 /*
148  * IR register block read and write functions
149  */
150 static
151 inline int cx23888_ir_write4(struct cx23885_dev *dev, u32 addr, u32 value)
152 {
153 	cx_write(addr, value);
154 	return 0;
155 }
156 
157 static inline u32 cx23888_ir_read4(struct cx23885_dev *dev, u32 addr)
158 {
159 	return cx_read(addr);
160 }
161 
162 static inline int cx23888_ir_and_or4(struct cx23885_dev *dev, u32 addr,
163 				     u32 and_mask, u32 or_value)
164 {
165 	cx_andor(addr, ~and_mask, or_value);
166 	return 0;
167 }
168 
169 /*
170  * Rx and Tx Clock Divider register computations
171  *
172  * Note the largest clock divider value of 0xffff corresponds to:
173  *	(0xffff + 1) * 1000 / 108/2 MHz = 1,213,629.629... ns
174  * which fits in 21 bits, so we'll use unsigned int for time arguments.
175  */
176 static inline u16 count_to_clock_divider(unsigned int d)
177 {
178 	if (d > RXCLK_RCD + 1)
179 		d = RXCLK_RCD;
180 	else if (d < 2)
181 		d = 1;
182 	else
183 		d--;
184 	return (u16) d;
185 }
186 
187 static inline u16 ns_to_clock_divider(unsigned int ns)
188 {
189 	return count_to_clock_divider(
190 		DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ / 1000000 * ns, 1000));
191 }
192 
193 static inline unsigned int clock_divider_to_ns(unsigned int divider)
194 {
195 	/* Period of the Rx or Tx clock in ns */
196 	return DIV_ROUND_CLOSEST((divider + 1) * 1000,
197 				 CX23888_IR_REFCLK_FREQ / 1000000);
198 }
199 
200 static inline u16 carrier_freq_to_clock_divider(unsigned int freq)
201 {
202 	return count_to_clock_divider(
203 			  DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ, freq * 16));
204 }
205 
206 static inline unsigned int clock_divider_to_carrier_freq(unsigned int divider)
207 {
208 	return DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ, (divider + 1) * 16);
209 }
210 
211 static inline u16 freq_to_clock_divider(unsigned int freq,
212 					unsigned int rollovers)
213 {
214 	return count_to_clock_divider(
215 		   DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ, freq * rollovers));
216 }
217 
218 static inline unsigned int clock_divider_to_freq(unsigned int divider,
219 						 unsigned int rollovers)
220 {
221 	return DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ,
222 				 (divider + 1) * rollovers);
223 }
224 
225 /*
226  * Low Pass Filter register calculations
227  *
228  * Note the largest count value of 0xffff corresponds to:
229  *	0xffff * 1000 / 108/2 MHz = 1,213,611.11... ns
230  * which fits in 21 bits, so we'll use unsigned int for time arguments.
231  */
232 static inline u16 count_to_lpf_count(unsigned int d)
233 {
234 	if (d > FILTR_LPF)
235 		d = FILTR_LPF;
236 	else if (d < 4)
237 		d = 0;
238 	return (u16) d;
239 }
240 
241 static inline u16 ns_to_lpf_count(unsigned int ns)
242 {
243 	return count_to_lpf_count(
244 		DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ / 1000000 * ns, 1000));
245 }
246 
247 static inline unsigned int lpf_count_to_ns(unsigned int count)
248 {
249 	/* Duration of the Low Pass Filter rejection window in ns */
250 	return DIV_ROUND_CLOSEST(count * 1000,
251 				 CX23888_IR_REFCLK_FREQ / 1000000);
252 }
253 
254 static inline unsigned int lpf_count_to_us(unsigned int count)
255 {
256 	/* Duration of the Low Pass Filter rejection window in us */
257 	return DIV_ROUND_CLOSEST(count, CX23888_IR_REFCLK_FREQ / 1000000);
258 }
259 
260 /*
261  * FIFO register pulse width count computations
262  */
263 static u32 clock_divider_to_resolution(u16 divider)
264 {
265 	/*
266 	 * Resolution is the duration of 1 tick of the readable portion of
267 	 * of the pulse width counter as read from the FIFO.  The two lsb's are
268 	 * not readable, hence the << 2.  This function returns ns.
269 	 */
270 	return DIV_ROUND_CLOSEST((1 << 2)  * ((u32) divider + 1) * 1000,
271 				 CX23888_IR_REFCLK_FREQ / 1000000);
272 }
273 
274 static u64 pulse_width_count_to_ns(u16 count, u16 divider)
275 {
276 	u64 n;
277 	u32 rem;
278 
279 	/*
280 	 * The 2 lsb's of the pulse width timer count are not readable, hence
281 	 * the (count << 2) | 0x3
282 	 */
283 	n = (((u64) count << 2) | 0x3) * (divider + 1) * 1000; /* millicycles */
284 	rem = do_div(n, CX23888_IR_REFCLK_FREQ / 1000000);     /* / MHz => ns */
285 	if (rem >= CX23888_IR_REFCLK_FREQ / 1000000 / 2)
286 		n++;
287 	return n;
288 }
289 
290 static unsigned int pulse_width_count_to_us(u16 count, u16 divider)
291 {
292 	u64 n;
293 	u32 rem;
294 
295 	/*
296 	 * The 2 lsb's of the pulse width timer count are not readable, hence
297 	 * the (count << 2) | 0x3
298 	 */
299 	n = (((u64) count << 2) | 0x3) * (divider + 1);    /* cycles      */
300 	rem = do_div(n, CX23888_IR_REFCLK_FREQ / 1000000); /* / MHz => us */
301 	if (rem >= CX23888_IR_REFCLK_FREQ / 1000000 / 2)
302 		n++;
303 	return (unsigned int) n;
304 }
305 
306 /*
307  * Pulse Clocks computations: Combined Pulse Width Count & Rx Clock Counts
308  *
309  * The total pulse clock count is an 18 bit pulse width timer count as the most
310  * significant part and (up to) 16 bit clock divider count as a modulus.
311  * When the Rx clock divider ticks down to 0, it increments the 18 bit pulse
312  * width timer count's least significant bit.
313  */
314 static u64 ns_to_pulse_clocks(u32 ns)
315 {
316 	u64 clocks;
317 	u32 rem;
318 	clocks = CX23888_IR_REFCLK_FREQ / 1000000 * (u64) ns; /* millicycles  */
319 	rem = do_div(clocks, 1000);                         /* /1000 = cycles */
320 	if (rem >= 1000 / 2)
321 		clocks++;
322 	return clocks;
323 }
324 
325 static u16 pulse_clocks_to_clock_divider(u64 count)
326 {
327 	do_div(count, (FIFO_RXTX << 2) | 0x3);
328 
329 	/* net result needs to be rounded down and decremented by 1 */
330 	if (count > RXCLK_RCD + 1)
331 		count = RXCLK_RCD;
332 	else if (count < 2)
333 		count = 1;
334 	else
335 		count--;
336 	return (u16) count;
337 }
338 
339 /*
340  * IR Control Register helpers
341  */
342 enum tx_fifo_watermark {
343 	TX_FIFO_HALF_EMPTY = 0,
344 	TX_FIFO_EMPTY      = CNTRL_TIC,
345 };
346 
347 enum rx_fifo_watermark {
348 	RX_FIFO_HALF_FULL = 0,
349 	RX_FIFO_NOT_EMPTY = CNTRL_RIC,
350 };
351 
352 static inline void control_tx_irq_watermark(struct cx23885_dev *dev,
353 					    enum tx_fifo_watermark level)
354 {
355 	cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_TIC, level);
356 }
357 
358 static inline void control_rx_irq_watermark(struct cx23885_dev *dev,
359 					    enum rx_fifo_watermark level)
360 {
361 	cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_RIC, level);
362 }
363 
364 static inline void control_tx_enable(struct cx23885_dev *dev, bool enable)
365 {
366 	cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~(CNTRL_TXE | CNTRL_TFE),
367 			   enable ? (CNTRL_TXE | CNTRL_TFE) : 0);
368 }
369 
370 static inline void control_rx_enable(struct cx23885_dev *dev, bool enable)
371 {
372 	cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~(CNTRL_RXE | CNTRL_RFE),
373 			   enable ? (CNTRL_RXE | CNTRL_RFE) : 0);
374 }
375 
376 static inline void control_tx_modulation_enable(struct cx23885_dev *dev,
377 						bool enable)
378 {
379 	cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_MOD,
380 			   enable ? CNTRL_MOD : 0);
381 }
382 
383 static inline void control_rx_demodulation_enable(struct cx23885_dev *dev,
384 						  bool enable)
385 {
386 	cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_DMD,
387 			   enable ? CNTRL_DMD : 0);
388 }
389 
390 static inline void control_rx_s_edge_detection(struct cx23885_dev *dev,
391 					       u32 edge_types)
392 {
393 	cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_EDG_BOTH,
394 			   edge_types & CNTRL_EDG_BOTH);
395 }
396 
397 static void control_rx_s_carrier_window(struct cx23885_dev *dev,
398 					unsigned int carrier,
399 					unsigned int *carrier_range_low,
400 					unsigned int *carrier_range_high)
401 {
402 	u32 v;
403 	unsigned int c16 = carrier * 16;
404 
405 	if (*carrier_range_low < DIV_ROUND_CLOSEST(c16, 16 + 3)) {
406 		v = CNTRL_WIN_3_4;
407 		*carrier_range_low = DIV_ROUND_CLOSEST(c16, 16 + 4);
408 	} else {
409 		v = CNTRL_WIN_3_3;
410 		*carrier_range_low = DIV_ROUND_CLOSEST(c16, 16 + 3);
411 	}
412 
413 	if (*carrier_range_high > DIV_ROUND_CLOSEST(c16, 16 - 3)) {
414 		v |= CNTRL_WIN_4_3;
415 		*carrier_range_high = DIV_ROUND_CLOSEST(c16, 16 - 4);
416 	} else {
417 		v |= CNTRL_WIN_3_3;
418 		*carrier_range_high = DIV_ROUND_CLOSEST(c16, 16 - 3);
419 	}
420 	cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_WIN, v);
421 }
422 
423 static inline void control_tx_polarity_invert(struct cx23885_dev *dev,
424 					      bool invert)
425 {
426 	cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_CPL,
427 			   invert ? CNTRL_CPL : 0);
428 }
429 
430 static inline void control_tx_level_invert(struct cx23885_dev *dev,
431 					  bool invert)
432 {
433 	cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_IVO,
434 			   invert ? CNTRL_IVO : 0);
435 }
436 
437 /*
438  * IR Rx & Tx Clock Register helpers
439  */
440 static unsigned int txclk_tx_s_carrier(struct cx23885_dev *dev,
441 				       unsigned int freq,
442 				       u16 *divider)
443 {
444 	*divider = carrier_freq_to_clock_divider(freq);
445 	cx23888_ir_write4(dev, CX23888_IR_TXCLK_REG, *divider);
446 	return clock_divider_to_carrier_freq(*divider);
447 }
448 
449 static unsigned int rxclk_rx_s_carrier(struct cx23885_dev *dev,
450 				       unsigned int freq,
451 				       u16 *divider)
452 {
453 	*divider = carrier_freq_to_clock_divider(freq);
454 	cx23888_ir_write4(dev, CX23888_IR_RXCLK_REG, *divider);
455 	return clock_divider_to_carrier_freq(*divider);
456 }
457 
458 static u32 txclk_tx_s_max_pulse_width(struct cx23885_dev *dev, u32 ns,
459 				      u16 *divider)
460 {
461 	u64 pulse_clocks;
462 
463 	if (ns > IR_MAX_DURATION)
464 		ns = IR_MAX_DURATION;
465 	pulse_clocks = ns_to_pulse_clocks(ns);
466 	*divider = pulse_clocks_to_clock_divider(pulse_clocks);
467 	cx23888_ir_write4(dev, CX23888_IR_TXCLK_REG, *divider);
468 	return (u32) pulse_width_count_to_ns(FIFO_RXTX, *divider);
469 }
470 
471 static u32 rxclk_rx_s_max_pulse_width(struct cx23885_dev *dev, u32 ns,
472 				      u16 *divider)
473 {
474 	u64 pulse_clocks;
475 
476 	if (ns > IR_MAX_DURATION)
477 		ns = IR_MAX_DURATION;
478 	pulse_clocks = ns_to_pulse_clocks(ns);
479 	*divider = pulse_clocks_to_clock_divider(pulse_clocks);
480 	cx23888_ir_write4(dev, CX23888_IR_RXCLK_REG, *divider);
481 	return (u32) pulse_width_count_to_ns(FIFO_RXTX, *divider);
482 }
483 
484 /*
485  * IR Tx Carrier Duty Cycle register helpers
486  */
487 static unsigned int cduty_tx_s_duty_cycle(struct cx23885_dev *dev,
488 					  unsigned int duty_cycle)
489 {
490 	u32 n;
491 	n = DIV_ROUND_CLOSEST(duty_cycle * 100, 625); /* 16ths of 100% */
492 	if (n != 0)
493 		n--;
494 	if (n > 15)
495 		n = 15;
496 	cx23888_ir_write4(dev, CX23888_IR_CDUTY_REG, n);
497 	return DIV_ROUND_CLOSEST((n + 1) * 100, 16);
498 }
499 
500 /*
501  * IR Filter Register helpers
502  */
503 static u32 filter_rx_s_min_width(struct cx23885_dev *dev, u32 min_width_ns)
504 {
505 	u32 count = ns_to_lpf_count(min_width_ns);
506 	cx23888_ir_write4(dev, CX23888_IR_FILTR_REG, count);
507 	return lpf_count_to_ns(count);
508 }
509 
510 /*
511  * IR IRQ Enable Register helpers
512  */
513 static inline void irqenable_rx(struct cx23885_dev *dev, u32 mask)
514 {
515 	mask &= (IRQEN_RTE | IRQEN_ROE | IRQEN_RSE);
516 	cx23888_ir_and_or4(dev, CX23888_IR_IRQEN_REG,
517 			   ~(IRQEN_RTE | IRQEN_ROE | IRQEN_RSE), mask);
518 }
519 
520 static inline void irqenable_tx(struct cx23885_dev *dev, u32 mask)
521 {
522 	mask &= IRQEN_TSE;
523 	cx23888_ir_and_or4(dev, CX23888_IR_IRQEN_REG, ~IRQEN_TSE, mask);
524 }
525 
526 /*
527  * V4L2 Subdevice IR Ops
528  */
529 static int cx23888_ir_irq_handler(struct v4l2_subdev *sd, u32 status,
530 				  bool *handled)
531 {
532 	struct cx23888_ir_state *state = to_state(sd);
533 	struct cx23885_dev *dev = state->dev;
534 	unsigned long flags;
535 
536 	u32 cntrl = cx23888_ir_read4(dev, CX23888_IR_CNTRL_REG);
537 	u32 irqen = cx23888_ir_read4(dev, CX23888_IR_IRQEN_REG);
538 	u32 stats = cx23888_ir_read4(dev, CX23888_IR_STATS_REG);
539 
540 	union cx23888_ir_fifo_rec rx_data[FIFO_RX_DEPTH];
541 	unsigned int i, j, k;
542 	u32 events, v;
543 	int tsr, rsr, rto, ror, tse, rse, rte, roe, kror;
544 
545 	tsr = stats & STATS_TSR; /* Tx FIFO Service Request */
546 	rsr = stats & STATS_RSR; /* Rx FIFO Service Request */
547 	rto = stats & STATS_RTO; /* Rx Pulse Width Timer Time Out */
548 	ror = stats & STATS_ROR; /* Rx FIFO Over Run */
549 
550 	tse = irqen & IRQEN_TSE; /* Tx FIFO Service Request IRQ Enable */
551 	rse = irqen & IRQEN_RSE; /* Rx FIFO Service Request IRQ Enable */
552 	rte = irqen & IRQEN_RTE; /* Rx Pulse Width Timer Time Out IRQ Enable */
553 	roe = irqen & IRQEN_ROE; /* Rx FIFO Over Run IRQ Enable */
554 
555 	*handled = false;
556 	v4l2_dbg(2, ir_888_debug, sd, "IRQ Status:  %s %s %s %s %s %s\n",
557 		 tsr ? "tsr" : "   ", rsr ? "rsr" : "   ",
558 		 rto ? "rto" : "   ", ror ? "ror" : "   ",
559 		 stats & STATS_TBY ? "tby" : "   ",
560 		 stats & STATS_RBY ? "rby" : "   ");
561 
562 	v4l2_dbg(2, ir_888_debug, sd, "IRQ Enables: %s %s %s %s\n",
563 		 tse ? "tse" : "   ", rse ? "rse" : "   ",
564 		 rte ? "rte" : "   ", roe ? "roe" : "   ");
565 
566 	/*
567 	 * Transmitter interrupt service
568 	 */
569 	if (tse && tsr) {
570 		/*
571 		 * TODO:
572 		 * Check the watermark threshold setting
573 		 * Pull FIFO_TX_DEPTH or FIFO_TX_DEPTH/2 entries from tx_kfifo
574 		 * Push the data to the hardware FIFO.
575 		 * If there was nothing more to send in the tx_kfifo, disable
576 		 *	the TSR IRQ and notify the v4l2_device.
577 		 * If there was something in the tx_kfifo, check the tx_kfifo
578 		 *      level and notify the v4l2_device, if it is low.
579 		 */
580 		/* For now, inhibit TSR interrupt until Tx is implemented */
581 		irqenable_tx(dev, 0);
582 		events = V4L2_SUBDEV_IR_TX_FIFO_SERVICE_REQ;
583 		v4l2_subdev_notify(sd, V4L2_SUBDEV_IR_TX_NOTIFY, &events);
584 		*handled = true;
585 	}
586 
587 	/*
588 	 * Receiver interrupt service
589 	 */
590 	kror = 0;
591 	if ((rse && rsr) || (rte && rto)) {
592 		/*
593 		 * Receive data on RSR to clear the STATS_RSR.
594 		 * Receive data on RTO, since we may not have yet hit the RSR
595 		 * watermark when we receive the RTO.
596 		 */
597 		for (i = 0, v = FIFO_RX_NDV;
598 		     (v & FIFO_RX_NDV) && !kror; i = 0) {
599 			for (j = 0;
600 			     (v & FIFO_RX_NDV) && j < FIFO_RX_DEPTH; j++) {
601 				v = cx23888_ir_read4(dev, CX23888_IR_FIFO_REG);
602 				rx_data[i].hw_fifo_data = v & ~FIFO_RX_NDV;
603 				i++;
604 			}
605 			if (i == 0)
606 				break;
607 			j = i * sizeof(union cx23888_ir_fifo_rec);
608 			k = kfifo_in_locked(&state->rx_kfifo,
609 				      (unsigned char *) rx_data, j,
610 				      &state->rx_kfifo_lock);
611 			if (k != j)
612 				kror++; /* rx_kfifo over run */
613 		}
614 		*handled = true;
615 	}
616 
617 	events = 0;
618 	v = 0;
619 	if (kror) {
620 		events |= V4L2_SUBDEV_IR_RX_SW_FIFO_OVERRUN;
621 		v4l2_err(sd, "IR receiver software FIFO overrun\n");
622 	}
623 	if (roe && ror) {
624 		/*
625 		 * The RX FIFO Enable (CNTRL_RFE) must be toggled to clear
626 		 * the Rx FIFO Over Run status (STATS_ROR)
627 		 */
628 		v |= CNTRL_RFE;
629 		events |= V4L2_SUBDEV_IR_RX_HW_FIFO_OVERRUN;
630 		v4l2_err(sd, "IR receiver hardware FIFO overrun\n");
631 	}
632 	if (rte && rto) {
633 		/*
634 		 * The IR Receiver Enable (CNTRL_RXE) must be toggled to clear
635 		 * the Rx Pulse Width Timer Time Out (STATS_RTO)
636 		 */
637 		v |= CNTRL_RXE;
638 		events |= V4L2_SUBDEV_IR_RX_END_OF_RX_DETECTED;
639 	}
640 	if (v) {
641 		/* Clear STATS_ROR & STATS_RTO as needed by resetting hardware */
642 		cx23888_ir_write4(dev, CX23888_IR_CNTRL_REG, cntrl & ~v);
643 		cx23888_ir_write4(dev, CX23888_IR_CNTRL_REG, cntrl);
644 		*handled = true;
645 	}
646 
647 	spin_lock_irqsave(&state->rx_kfifo_lock, flags);
648 	if (kfifo_len(&state->rx_kfifo) >= CX23888_IR_RX_KFIFO_SIZE / 2)
649 		events |= V4L2_SUBDEV_IR_RX_FIFO_SERVICE_REQ;
650 	spin_unlock_irqrestore(&state->rx_kfifo_lock, flags);
651 
652 	if (events)
653 		v4l2_subdev_notify(sd, V4L2_SUBDEV_IR_RX_NOTIFY, &events);
654 	return 0;
655 }
656 
657 /* Receiver */
658 static int cx23888_ir_rx_read(struct v4l2_subdev *sd, u8 *buf, size_t count,
659 			      ssize_t *num)
660 {
661 	struct cx23888_ir_state *state = to_state(sd);
662 	bool invert = (bool) atomic_read(&state->rx_invert);
663 	u16 divider = (u16) atomic_read(&state->rxclk_divider);
664 
665 	unsigned int i, n;
666 	union cx23888_ir_fifo_rec *p;
667 	unsigned u, v, w;
668 
669 	n = count / sizeof(union cx23888_ir_fifo_rec)
670 		* sizeof(union cx23888_ir_fifo_rec);
671 	if (n == 0) {
672 		*num = 0;
673 		return 0;
674 	}
675 
676 	n = kfifo_out_locked(&state->rx_kfifo, buf, n, &state->rx_kfifo_lock);
677 
678 	n /= sizeof(union cx23888_ir_fifo_rec);
679 	*num = n * sizeof(union cx23888_ir_fifo_rec);
680 
681 	for (p = (union cx23888_ir_fifo_rec *) buf, i = 0; i < n; p++, i++) {
682 
683 		if ((p->hw_fifo_data & FIFO_RXTX_RTO) == FIFO_RXTX_RTO) {
684 			/* Assume RTO was because of no IR light input */
685 			u = 0;
686 			w = 1;
687 		} else {
688 			u = (p->hw_fifo_data & FIFO_RXTX_LVL) ? 1 : 0;
689 			if (invert)
690 				u = u ? 0 : 1;
691 			w = 0;
692 		}
693 
694 		v = (unsigned) pulse_width_count_to_ns(
695 				  (u16) (p->hw_fifo_data & FIFO_RXTX), divider);
696 		if (v > IR_MAX_DURATION)
697 			v = IR_MAX_DURATION;
698 
699 		p->ir_core_data = (struct ir_raw_event)
700 			{ .pulse = u, .duration = v, .timeout = w };
701 
702 		v4l2_dbg(2, ir_888_debug, sd, "rx read: %10u ns  %s  %s\n",
703 			 v, u ? "mark" : "space", w ? "(timed out)" : "");
704 		if (w)
705 			v4l2_dbg(2, ir_888_debug, sd, "rx read: end of rx\n");
706 	}
707 	return 0;
708 }
709 
710 static int cx23888_ir_rx_g_parameters(struct v4l2_subdev *sd,
711 				      struct v4l2_subdev_ir_parameters *p)
712 {
713 	struct cx23888_ir_state *state = to_state(sd);
714 	mutex_lock(&state->rx_params_lock);
715 	memcpy(p, &state->rx_params, sizeof(struct v4l2_subdev_ir_parameters));
716 	mutex_unlock(&state->rx_params_lock);
717 	return 0;
718 }
719 
720 static int cx23888_ir_rx_shutdown(struct v4l2_subdev *sd)
721 {
722 	struct cx23888_ir_state *state = to_state(sd);
723 	struct cx23885_dev *dev = state->dev;
724 
725 	mutex_lock(&state->rx_params_lock);
726 
727 	/* Disable or slow down all IR Rx circuits and counters */
728 	irqenable_rx(dev, 0);
729 	control_rx_enable(dev, false);
730 	control_rx_demodulation_enable(dev, false);
731 	control_rx_s_edge_detection(dev, CNTRL_EDG_NONE);
732 	filter_rx_s_min_width(dev, 0);
733 	cx23888_ir_write4(dev, CX23888_IR_RXCLK_REG, RXCLK_RCD);
734 
735 	state->rx_params.shutdown = true;
736 
737 	mutex_unlock(&state->rx_params_lock);
738 	return 0;
739 }
740 
741 static int cx23888_ir_rx_s_parameters(struct v4l2_subdev *sd,
742 				      struct v4l2_subdev_ir_parameters *p)
743 {
744 	struct cx23888_ir_state *state = to_state(sd);
745 	struct cx23885_dev *dev = state->dev;
746 	struct v4l2_subdev_ir_parameters *o = &state->rx_params;
747 	u16 rxclk_divider;
748 
749 	if (p->shutdown)
750 		return cx23888_ir_rx_shutdown(sd);
751 
752 	if (p->mode != V4L2_SUBDEV_IR_MODE_PULSE_WIDTH)
753 		return -ENOSYS;
754 
755 	mutex_lock(&state->rx_params_lock);
756 
757 	o->shutdown = p->shutdown;
758 
759 	o->mode = p->mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH;
760 
761 	o->bytes_per_data_element = p->bytes_per_data_element
762 				  = sizeof(union cx23888_ir_fifo_rec);
763 
764 	/* Before we tweak the hardware, we have to disable the receiver */
765 	irqenable_rx(dev, 0);
766 	control_rx_enable(dev, false);
767 
768 	control_rx_demodulation_enable(dev, p->modulation);
769 	o->modulation = p->modulation;
770 
771 	if (p->modulation) {
772 		p->carrier_freq = rxclk_rx_s_carrier(dev, p->carrier_freq,
773 						     &rxclk_divider);
774 
775 		o->carrier_freq = p->carrier_freq;
776 
777 		o->duty_cycle = p->duty_cycle = 50;
778 
779 		control_rx_s_carrier_window(dev, p->carrier_freq,
780 					    &p->carrier_range_lower,
781 					    &p->carrier_range_upper);
782 		o->carrier_range_lower = p->carrier_range_lower;
783 		o->carrier_range_upper = p->carrier_range_upper;
784 
785 		p->max_pulse_width =
786 			(u32) pulse_width_count_to_ns(FIFO_RXTX, rxclk_divider);
787 	} else {
788 		p->max_pulse_width =
789 			    rxclk_rx_s_max_pulse_width(dev, p->max_pulse_width,
790 						       &rxclk_divider);
791 	}
792 	o->max_pulse_width = p->max_pulse_width;
793 	atomic_set(&state->rxclk_divider, rxclk_divider);
794 
795 	p->noise_filter_min_width =
796 			  filter_rx_s_min_width(dev, p->noise_filter_min_width);
797 	o->noise_filter_min_width = p->noise_filter_min_width;
798 
799 	p->resolution = clock_divider_to_resolution(rxclk_divider);
800 	o->resolution = p->resolution;
801 
802 	/* FIXME - make this dependent on resolution for better performance */
803 	control_rx_irq_watermark(dev, RX_FIFO_HALF_FULL);
804 
805 	control_rx_s_edge_detection(dev, CNTRL_EDG_BOTH);
806 
807 	o->invert_level = p->invert_level;
808 	atomic_set(&state->rx_invert, p->invert_level);
809 
810 	o->interrupt_enable = p->interrupt_enable;
811 	o->enable = p->enable;
812 	if (p->enable) {
813 		unsigned long flags;
814 
815 		spin_lock_irqsave(&state->rx_kfifo_lock, flags);
816 		kfifo_reset(&state->rx_kfifo);
817 		/* reset tx_fifo too if there is one... */
818 		spin_unlock_irqrestore(&state->rx_kfifo_lock, flags);
819 		if (p->interrupt_enable)
820 			irqenable_rx(dev, IRQEN_RSE | IRQEN_RTE | IRQEN_ROE);
821 		control_rx_enable(dev, p->enable);
822 	}
823 
824 	mutex_unlock(&state->rx_params_lock);
825 	return 0;
826 }
827 
828 /* Transmitter */
829 static int cx23888_ir_tx_write(struct v4l2_subdev *sd, u8 *buf, size_t count,
830 			       ssize_t *num)
831 {
832 	struct cx23888_ir_state *state = to_state(sd);
833 	struct cx23885_dev *dev = state->dev;
834 	/* For now enable the Tx FIFO Service interrupt & pretend we did work */
835 	irqenable_tx(dev, IRQEN_TSE);
836 	*num = count;
837 	return 0;
838 }
839 
840 static int cx23888_ir_tx_g_parameters(struct v4l2_subdev *sd,
841 				      struct v4l2_subdev_ir_parameters *p)
842 {
843 	struct cx23888_ir_state *state = to_state(sd);
844 	mutex_lock(&state->tx_params_lock);
845 	memcpy(p, &state->tx_params, sizeof(struct v4l2_subdev_ir_parameters));
846 	mutex_unlock(&state->tx_params_lock);
847 	return 0;
848 }
849 
850 static int cx23888_ir_tx_shutdown(struct v4l2_subdev *sd)
851 {
852 	struct cx23888_ir_state *state = to_state(sd);
853 	struct cx23885_dev *dev = state->dev;
854 
855 	mutex_lock(&state->tx_params_lock);
856 
857 	/* Disable or slow down all IR Tx circuits and counters */
858 	irqenable_tx(dev, 0);
859 	control_tx_enable(dev, false);
860 	control_tx_modulation_enable(dev, false);
861 	cx23888_ir_write4(dev, CX23888_IR_TXCLK_REG, TXCLK_TCD);
862 
863 	state->tx_params.shutdown = true;
864 
865 	mutex_unlock(&state->tx_params_lock);
866 	return 0;
867 }
868 
869 static int cx23888_ir_tx_s_parameters(struct v4l2_subdev *sd,
870 				      struct v4l2_subdev_ir_parameters *p)
871 {
872 	struct cx23888_ir_state *state = to_state(sd);
873 	struct cx23885_dev *dev = state->dev;
874 	struct v4l2_subdev_ir_parameters *o = &state->tx_params;
875 	u16 txclk_divider;
876 
877 	if (p->shutdown)
878 		return cx23888_ir_tx_shutdown(sd);
879 
880 	if (p->mode != V4L2_SUBDEV_IR_MODE_PULSE_WIDTH)
881 		return -ENOSYS;
882 
883 	mutex_lock(&state->tx_params_lock);
884 
885 	o->shutdown = p->shutdown;
886 
887 	o->mode = p->mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH;
888 
889 	o->bytes_per_data_element = p->bytes_per_data_element
890 				  = sizeof(union cx23888_ir_fifo_rec);
891 
892 	/* Before we tweak the hardware, we have to disable the transmitter */
893 	irqenable_tx(dev, 0);
894 	control_tx_enable(dev, false);
895 
896 	control_tx_modulation_enable(dev, p->modulation);
897 	o->modulation = p->modulation;
898 
899 	if (p->modulation) {
900 		p->carrier_freq = txclk_tx_s_carrier(dev, p->carrier_freq,
901 						     &txclk_divider);
902 		o->carrier_freq = p->carrier_freq;
903 
904 		p->duty_cycle = cduty_tx_s_duty_cycle(dev, p->duty_cycle);
905 		o->duty_cycle = p->duty_cycle;
906 
907 		p->max_pulse_width =
908 			(u32) pulse_width_count_to_ns(FIFO_RXTX, txclk_divider);
909 	} else {
910 		p->max_pulse_width =
911 			    txclk_tx_s_max_pulse_width(dev, p->max_pulse_width,
912 						       &txclk_divider);
913 	}
914 	o->max_pulse_width = p->max_pulse_width;
915 	atomic_set(&state->txclk_divider, txclk_divider);
916 
917 	p->resolution = clock_divider_to_resolution(txclk_divider);
918 	o->resolution = p->resolution;
919 
920 	/* FIXME - make this dependent on resolution for better performance */
921 	control_tx_irq_watermark(dev, TX_FIFO_HALF_EMPTY);
922 
923 	control_tx_polarity_invert(dev, p->invert_carrier_sense);
924 	o->invert_carrier_sense = p->invert_carrier_sense;
925 
926 	control_tx_level_invert(dev, p->invert_level);
927 	o->invert_level = p->invert_level;
928 
929 	o->interrupt_enable = p->interrupt_enable;
930 	o->enable = p->enable;
931 	if (p->enable) {
932 		if (p->interrupt_enable)
933 			irqenable_tx(dev, IRQEN_TSE);
934 		control_tx_enable(dev, p->enable);
935 	}
936 
937 	mutex_unlock(&state->tx_params_lock);
938 	return 0;
939 }
940 
941 
942 /*
943  * V4L2 Subdevice Core Ops
944  */
945 static int cx23888_ir_log_status(struct v4l2_subdev *sd)
946 {
947 	struct cx23888_ir_state *state = to_state(sd);
948 	struct cx23885_dev *dev = state->dev;
949 	char *s;
950 	int i, j;
951 
952 	u32 cntrl = cx23888_ir_read4(dev, CX23888_IR_CNTRL_REG);
953 	u32 txclk = cx23888_ir_read4(dev, CX23888_IR_TXCLK_REG) & TXCLK_TCD;
954 	u32 rxclk = cx23888_ir_read4(dev, CX23888_IR_RXCLK_REG) & RXCLK_RCD;
955 	u32 cduty = cx23888_ir_read4(dev, CX23888_IR_CDUTY_REG) & CDUTY_CDC;
956 	u32 stats = cx23888_ir_read4(dev, CX23888_IR_STATS_REG);
957 	u32 irqen = cx23888_ir_read4(dev, CX23888_IR_IRQEN_REG);
958 	u32 filtr = cx23888_ir_read4(dev, CX23888_IR_FILTR_REG) & FILTR_LPF;
959 
960 	v4l2_info(sd, "IR Receiver:\n");
961 	v4l2_info(sd, "\tEnabled:                           %s\n",
962 		  cntrl & CNTRL_RXE ? "yes" : "no");
963 	v4l2_info(sd, "\tDemodulation from a carrier:       %s\n",
964 		  cntrl & CNTRL_DMD ? "enabled" : "disabled");
965 	v4l2_info(sd, "\tFIFO:                              %s\n",
966 		  cntrl & CNTRL_RFE ? "enabled" : "disabled");
967 	switch (cntrl & CNTRL_EDG) {
968 	case CNTRL_EDG_NONE:
969 		s = "disabled";
970 		break;
971 	case CNTRL_EDG_FALL:
972 		s = "falling edge";
973 		break;
974 	case CNTRL_EDG_RISE:
975 		s = "rising edge";
976 		break;
977 	case CNTRL_EDG_BOTH:
978 		s = "rising & falling edges";
979 		break;
980 	default:
981 		s = "??? edge";
982 		break;
983 	}
984 	v4l2_info(sd, "\tPulse timers' start/stop trigger:  %s\n", s);
985 	v4l2_info(sd, "\tFIFO data on pulse timer overflow: %s\n",
986 		  cntrl & CNTRL_R ? "not loaded" : "overflow marker");
987 	v4l2_info(sd, "\tFIFO interrupt watermark:          %s\n",
988 		  cntrl & CNTRL_RIC ? "not empty" : "half full or greater");
989 	v4l2_info(sd, "\tLoopback mode:                     %s\n",
990 		  cntrl & CNTRL_LBM ? "loopback active" : "normal receive");
991 	if (cntrl & CNTRL_DMD) {
992 		v4l2_info(sd, "\tExpected carrier (16 clocks):      %u Hz\n",
993 			  clock_divider_to_carrier_freq(rxclk));
994 		switch (cntrl & CNTRL_WIN) {
995 		case CNTRL_WIN_3_3:
996 			i = 3;
997 			j = 3;
998 			break;
999 		case CNTRL_WIN_4_3:
1000 			i = 4;
1001 			j = 3;
1002 			break;
1003 		case CNTRL_WIN_3_4:
1004 			i = 3;
1005 			j = 4;
1006 			break;
1007 		case CNTRL_WIN_4_4:
1008 			i = 4;
1009 			j = 4;
1010 			break;
1011 		default:
1012 			i = 0;
1013 			j = 0;
1014 			break;
1015 		}
1016 		v4l2_info(sd, "\tNext carrier edge window:	    16 clocks -%1d/+%1d, %u to %u Hz\n",
1017 			  i, j,
1018 			  clock_divider_to_freq(rxclk, 16 + j),
1019 			  clock_divider_to_freq(rxclk, 16 - i));
1020 	}
1021 	v4l2_info(sd, "\tMax measurable pulse width:        %u us, %llu ns\n",
1022 		  pulse_width_count_to_us(FIFO_RXTX, rxclk),
1023 		  pulse_width_count_to_ns(FIFO_RXTX, rxclk));
1024 	v4l2_info(sd, "\tLow pass filter:                   %s\n",
1025 		  filtr ? "enabled" : "disabled");
1026 	if (filtr)
1027 		v4l2_info(sd, "\tMin acceptable pulse width (LPF):  %u us, %u ns\n",
1028 			  lpf_count_to_us(filtr),
1029 			  lpf_count_to_ns(filtr));
1030 	v4l2_info(sd, "\tPulse width timer timed-out:       %s\n",
1031 		  stats & STATS_RTO ? "yes" : "no");
1032 	v4l2_info(sd, "\tPulse width timer time-out intr:   %s\n",
1033 		  irqen & IRQEN_RTE ? "enabled" : "disabled");
1034 	v4l2_info(sd, "\tFIFO overrun:                      %s\n",
1035 		  stats & STATS_ROR ? "yes" : "no");
1036 	v4l2_info(sd, "\tFIFO overrun interrupt:            %s\n",
1037 		  irqen & IRQEN_ROE ? "enabled" : "disabled");
1038 	v4l2_info(sd, "\tBusy:                              %s\n",
1039 		  stats & STATS_RBY ? "yes" : "no");
1040 	v4l2_info(sd, "\tFIFO service requested:            %s\n",
1041 		  stats & STATS_RSR ? "yes" : "no");
1042 	v4l2_info(sd, "\tFIFO service request interrupt:    %s\n",
1043 		  irqen & IRQEN_RSE ? "enabled" : "disabled");
1044 
1045 	v4l2_info(sd, "IR Transmitter:\n");
1046 	v4l2_info(sd, "\tEnabled:                           %s\n",
1047 		  cntrl & CNTRL_TXE ? "yes" : "no");
1048 	v4l2_info(sd, "\tModulation onto a carrier:         %s\n",
1049 		  cntrl & CNTRL_MOD ? "enabled" : "disabled");
1050 	v4l2_info(sd, "\tFIFO:                              %s\n",
1051 		  cntrl & CNTRL_TFE ? "enabled" : "disabled");
1052 	v4l2_info(sd, "\tFIFO interrupt watermark:          %s\n",
1053 		  cntrl & CNTRL_TIC ? "not empty" : "half full or less");
1054 	v4l2_info(sd, "\tOutput pin level inversion         %s\n",
1055 		  cntrl & CNTRL_IVO ? "yes" : "no");
1056 	v4l2_info(sd, "\tCarrier polarity:                  %s\n",
1057 		  cntrl & CNTRL_CPL ? "space:burst mark:noburst"
1058 				    : "space:noburst mark:burst");
1059 	if (cntrl & CNTRL_MOD) {
1060 		v4l2_info(sd, "\tCarrier (16 clocks):               %u Hz\n",
1061 			  clock_divider_to_carrier_freq(txclk));
1062 		v4l2_info(sd, "\tCarrier duty cycle:                %2u/16\n",
1063 			  cduty + 1);
1064 	}
1065 	v4l2_info(sd, "\tMax pulse width:                   %u us, %llu ns\n",
1066 		  pulse_width_count_to_us(FIFO_RXTX, txclk),
1067 		  pulse_width_count_to_ns(FIFO_RXTX, txclk));
1068 	v4l2_info(sd, "\tBusy:                              %s\n",
1069 		  stats & STATS_TBY ? "yes" : "no");
1070 	v4l2_info(sd, "\tFIFO service requested:            %s\n",
1071 		  stats & STATS_TSR ? "yes" : "no");
1072 	v4l2_info(sd, "\tFIFO service request interrupt:    %s\n",
1073 		  irqen & IRQEN_TSE ? "enabled" : "disabled");
1074 
1075 	return 0;
1076 }
1077 
1078 #ifdef CONFIG_VIDEO_ADV_DEBUG
1079 static int cx23888_ir_g_register(struct v4l2_subdev *sd,
1080 				 struct v4l2_dbg_register *reg)
1081 {
1082 	struct cx23888_ir_state *state = to_state(sd);
1083 	u32 addr = CX23888_IR_REG_BASE + (u32) reg->reg;
1084 
1085 	if ((addr & 0x3) != 0)
1086 		return -EINVAL;
1087 	if (addr < CX23888_IR_CNTRL_REG || addr > CX23888_IR_LEARN_REG)
1088 		return -EINVAL;
1089 	reg->size = 4;
1090 	reg->val = cx23888_ir_read4(state->dev, addr);
1091 	return 0;
1092 }
1093 
1094 static int cx23888_ir_s_register(struct v4l2_subdev *sd,
1095 				 const struct v4l2_dbg_register *reg)
1096 {
1097 	struct cx23888_ir_state *state = to_state(sd);
1098 	u32 addr = CX23888_IR_REG_BASE + (u32) reg->reg;
1099 
1100 	if ((addr & 0x3) != 0)
1101 		return -EINVAL;
1102 	if (addr < CX23888_IR_CNTRL_REG || addr > CX23888_IR_LEARN_REG)
1103 		return -EINVAL;
1104 	cx23888_ir_write4(state->dev, addr, reg->val);
1105 	return 0;
1106 }
1107 #endif
1108 
1109 static const struct v4l2_subdev_core_ops cx23888_ir_core_ops = {
1110 	.log_status = cx23888_ir_log_status,
1111 #ifdef CONFIG_VIDEO_ADV_DEBUG
1112 	.g_register = cx23888_ir_g_register,
1113 	.s_register = cx23888_ir_s_register,
1114 #endif
1115 	.interrupt_service_routine = cx23888_ir_irq_handler,
1116 };
1117 
1118 static const struct v4l2_subdev_ir_ops cx23888_ir_ir_ops = {
1119 	.rx_read = cx23888_ir_rx_read,
1120 	.rx_g_parameters = cx23888_ir_rx_g_parameters,
1121 	.rx_s_parameters = cx23888_ir_rx_s_parameters,
1122 
1123 	.tx_write = cx23888_ir_tx_write,
1124 	.tx_g_parameters = cx23888_ir_tx_g_parameters,
1125 	.tx_s_parameters = cx23888_ir_tx_s_parameters,
1126 };
1127 
1128 static const struct v4l2_subdev_ops cx23888_ir_controller_ops = {
1129 	.core = &cx23888_ir_core_ops,
1130 	.ir = &cx23888_ir_ir_ops,
1131 };
1132 
1133 static const struct v4l2_subdev_ir_parameters default_rx_params = {
1134 	.bytes_per_data_element = sizeof(union cx23888_ir_fifo_rec),
1135 	.mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH,
1136 
1137 	.enable = false,
1138 	.interrupt_enable = false,
1139 	.shutdown = true,
1140 
1141 	.modulation = true,
1142 	.carrier_freq = 36000, /* 36 kHz - RC-5, RC-6, and RC-6A carrier */
1143 
1144 	/* RC-5:    666,667 ns = 1/36 kHz * 32 cycles * 1 mark * 0.75 */
1145 	/* RC-6A:   333,333 ns = 1/36 kHz * 16 cycles * 1 mark * 0.75 */
1146 	.noise_filter_min_width = 333333, /* ns */
1147 	.carrier_range_lower = 35000,
1148 	.carrier_range_upper = 37000,
1149 	.invert_level = false,
1150 };
1151 
1152 static const struct v4l2_subdev_ir_parameters default_tx_params = {
1153 	.bytes_per_data_element = sizeof(union cx23888_ir_fifo_rec),
1154 	.mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH,
1155 
1156 	.enable = false,
1157 	.interrupt_enable = false,
1158 	.shutdown = true,
1159 
1160 	.modulation = true,
1161 	.carrier_freq = 36000, /* 36 kHz - RC-5 carrier */
1162 	.duty_cycle = 25,      /* 25 %   - RC-5 carrier */
1163 	.invert_level = false,
1164 	.invert_carrier_sense = false,
1165 };
1166 
1167 int cx23888_ir_probe(struct cx23885_dev *dev)
1168 {
1169 	struct cx23888_ir_state *state;
1170 	struct v4l2_subdev *sd;
1171 	struct v4l2_subdev_ir_parameters default_params;
1172 	int ret;
1173 
1174 	state = kzalloc(sizeof(struct cx23888_ir_state), GFP_KERNEL);
1175 	if (state == NULL)
1176 		return -ENOMEM;
1177 
1178 	spin_lock_init(&state->rx_kfifo_lock);
1179 	if (kfifo_alloc(&state->rx_kfifo, CX23888_IR_RX_KFIFO_SIZE, GFP_KERNEL))
1180 		return -ENOMEM;
1181 
1182 	state->dev = dev;
1183 	sd = &state->sd;
1184 
1185 	v4l2_subdev_init(sd, &cx23888_ir_controller_ops);
1186 	v4l2_set_subdevdata(sd, state);
1187 	/* FIXME - fix the formatting of dev->v4l2_dev.name and use it */
1188 	snprintf(sd->name, sizeof(sd->name), "%s/888-ir", dev->name);
1189 	sd->grp_id = CX23885_HW_888_IR;
1190 
1191 	ret = v4l2_device_register_subdev(&dev->v4l2_dev, sd);
1192 	if (ret == 0) {
1193 		/*
1194 		 * Ensure no interrupts arrive from '888 specific conditions,
1195 		 * since we ignore them in this driver to have commonality with
1196 		 * similar IR controller cores.
1197 		 */
1198 		cx23888_ir_write4(dev, CX23888_IR_IRQEN_REG, 0);
1199 
1200 		mutex_init(&state->rx_params_lock);
1201 		default_params = default_rx_params;
1202 		v4l2_subdev_call(sd, ir, rx_s_parameters, &default_params);
1203 
1204 		mutex_init(&state->tx_params_lock);
1205 		default_params = default_tx_params;
1206 		v4l2_subdev_call(sd, ir, tx_s_parameters, &default_params);
1207 	} else {
1208 		kfifo_free(&state->rx_kfifo);
1209 	}
1210 	return ret;
1211 }
1212 
1213 int cx23888_ir_remove(struct cx23885_dev *dev)
1214 {
1215 	struct v4l2_subdev *sd;
1216 	struct cx23888_ir_state *state;
1217 
1218 	sd = cx23885_find_hw(dev, CX23885_HW_888_IR);
1219 	if (sd == NULL)
1220 		return -ENODEV;
1221 
1222 	cx23888_ir_rx_shutdown(sd);
1223 	cx23888_ir_tx_shutdown(sd);
1224 
1225 	state = to_state(sd);
1226 	v4l2_device_unregister_subdev(sd);
1227 	kfifo_free(&state->rx_kfifo);
1228 	kfree(state);
1229 	/* Nothing more to free() as state held the actual v4l2_subdev object */
1230 	return 0;
1231 }
1232