1 /*
2  *  Driver for the Conexant CX23885 PCIe bridge
3  *
4  *  Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
5  *
6  *  This program is free software; you can redistribute it and/or modify
7  *  it under the terms of the GNU General Public License as published by
8  *  the Free Software Foundation; either version 2 of the License, or
9  *  (at your option) any later version.
10  *
11  *  This program is distributed in the hope that it will be useful,
12  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
13  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  *
15  *  GNU General Public License for more details.
16  */
17 
18 #ifndef _CX23885_REG_H_
19 #define _CX23885_REG_H_
20 
21 /*
22 Address Map
23 0x00000000 -> 0x00009000   TX SRAM  (Fifos)
24 0x00010000 -> 0x00013c00   RX SRAM  CMDS + CDT
25 
26 EACH CMDS struct is 0x80 bytes long
27 
28 DMAx_PTR1 = 0x03040 address of first cluster
29 DMAx_PTR2 = 0x10600 address of the CDT
30 DMAx_CNT1 = cluster size in (bytes >> 4) -1
31 DMAx_CNT2 = total cdt size for all entries >> 3
32 
33 Cluster Descriptor entry = 4 DWORDS
34  DWORD 0 -> ptr to cluster
35  DWORD 1 Reserved
36  DWORD 2 Reserved
37  DWORD 3 Reserved
38 
39 Channel manager Data Structure entry = 20 DWORD
40   0  IntialProgramCounterLow
41   1  IntialProgramCounterHigh
42   2  ClusterDescriptorTableBase
43   3  ClusterDescriptorTableSize
44   4  InstructionQueueBase
45   5  InstructionQueueSize
46 ...  Reserved
47  19  Reserved
48 */
49 
50 /* Risc Instructions */
51 #define RISC_CNT_INC		 0x00010000
52 #define RISC_CNT_RESET		 0x00030000
53 #define RISC_IRQ1		 0x01000000
54 #define RISC_IRQ2		 0x02000000
55 #define RISC_EOL		 0x04000000
56 #define RISC_SOL		 0x08000000
57 #define RISC_WRITE		 0x10000000
58 #define RISC_SKIP		 0x20000000
59 #define RISC_JUMP		 0x70000000
60 #define RISC_SYNC		 0x80000000
61 #define RISC_RESYNC		 0x80008000
62 #define RISC_READ		 0x90000000
63 #define RISC_WRITERM		 0xB0000000
64 #define RISC_WRITECM		 0xC0000000
65 #define RISC_WRITECR		 0xD0000000
66 #define RISC_WRITEC		 0x50000000
67 #define RISC_READC		 0xA0000000
68 
69 
70 /* Audio and Video Core */
71 #define HOST_REG1		0x00000000
72 #define HOST_REG2		0x00000001
73 #define HOST_REG3		0x00000002
74 
75 /* Chip Configuration Registers */
76 #define CHIP_CTRL		0x00000100
77 #define AFE_CTRL		0x00000104
78 #define VID_PLL_INT_POST	0x00000108
79 #define VID_PLL_FRAC		0x0000010C
80 #define AUX_PLL_INT_POST	0x00000110
81 #define AUX_PLL_FRAC		0x00000114
82 #define SYS_PLL_INT_POST	0x00000118
83 #define SYS_PLL_FRAC		0x0000011C
84 #define PIN_CTRL		0x00000120
85 #define AUD_IO_CTRL		0x00000124
86 #define AUD_LOCK1		0x00000128
87 #define AUD_LOCK2		0x0000012C
88 #define POWER_CTRL		0x00000130
89 #define AFE_DIAG_CTRL1		0x00000134
90 #define AFE_DIAG_CTRL3		0x0000013C
91 #define PLL_DIAG_CTRL		0x00000140
92 #define AFE_CLK_OUT_CTRL	0x00000144
93 #define DLL1_DIAG_CTRL		0x0000015C
94 
95 /* GPIO[23:19] Output Enable */
96 #define GPIO2_OUT_EN_REG	0x00000160
97 /* GPIO[23:19] Data Registers */
98 #define GPIO2			0x00000164
99 
100 #define IFADC_CTRL		0x00000180
101 
102 /* Infrared Remote Registers */
103 #define IR_CNTRL_REG	0x00000200
104 #define IR_TXCLK_REG	0x00000204
105 #define IR_RXCLK_REG	0x00000208
106 #define IR_CDUTY_REG	0x0000020C
107 #define IR_STAT_REG	0x00000210
108 #define IR_IRQEN_REG	0x00000214
109 #define IR_FILTR_REG	0x00000218
110 #define IR_FIFO_REG	0x0000023C
111 
112 /* Video Decoder Registers */
113 #define MODE_CTRL		0x00000400
114 #define OUT_CTRL1		0x00000404
115 #define OUT_CTRL2		0x00000408
116 #define GEN_STAT		0x0000040C
117 #define INT_STAT_MASK		0x00000410
118 #define LUMA_CTRL		0x00000414
119 #define HSCALE_CTRL		0x00000418
120 #define VSCALE_CTRL		0x0000041C
121 #define CHROMA_CTRL		0x00000420
122 #define VBI_LINE_CTRL1		0x00000424
123 #define VBI_LINE_CTRL2		0x00000428
124 #define VBI_LINE_CTRL3		0x0000042C
125 #define VBI_LINE_CTRL4		0x00000430
126 #define VBI_LINE_CTRL5		0x00000434
127 #define VBI_FC_CFG		0x00000438
128 #define VBI_MISC_CFG1		0x0000043C
129 #define VBI_MISC_CFG2		0x00000440
130 #define VBI_PAY1		0x00000444
131 #define VBI_PAY2		0x00000448
132 #define VBI_CUST1_CFG1		0x0000044C
133 #define VBI_CUST1_CFG2		0x00000450
134 #define VBI_CUST1_CFG3		0x00000454
135 #define VBI_CUST2_CFG1		0x00000458
136 #define VBI_CUST2_CFG2		0x0000045C
137 #define VBI_CUST2_CFG3		0x00000460
138 #define VBI_CUST3_CFG1		0x00000464
139 #define VBI_CUST3_CFG2		0x00000468
140 #define VBI_CUST3_CFG3		0x0000046C
141 #define HORIZ_TIM_CTRL		0x00000470
142 #define VERT_TIM_CTRL		0x00000474
143 #define SRC_COMB_CFG		0x00000478
144 #define CHROMA_VBIOFF_CFG	0x0000047C
145 #define FIELD_COUNT		0x00000480
146 #define MISC_TIM_CTRL		0x00000484
147 #define DFE_CTRL1		0x00000488
148 #define DFE_CTRL2		0x0000048C
149 #define DFE_CTRL3		0x00000490
150 #define PLL_CTRL		0x00000494
151 #define HTL_CTRL		0x00000498
152 #define COMB_CTRL		0x0000049C
153 #define CRUSH_CTRL		0x000004A0
154 #define SOFT_RST_CTRL		0x000004A4
155 #define CX885_VERSION		0x000004B4
156 #define VBI_PASS_CTRL		0x000004BC
157 
158 /* Audio Decoder Registers */
159 /* 8051 Configuration */
160 #define DL_CTL		0x00000800
161 #define STD_DET_STATUS	0x00000804
162 #define STD_DET_CTL	0x00000808
163 #define DW8051_INT	0x0000080C
164 #define GENERAL_CTL	0x00000810
165 #define AAGC_CTL	0x00000814
166 #define DEMATRIX_CTL	0x000008CC
167 #define PATH1_CTL1	0x000008D0
168 #define PATH1_VOL_CTL	0x000008D4
169 #define PATH1_EQ_CTL	0x000008D8
170 #define PATH1_SC_CTL	0x000008DC
171 #define PATH2_CTL1	0x000008E0
172 #define PATH2_VOL_CTL	0x000008E4
173 #define PATH2_EQ_CTL	0x000008E8
174 #define PATH2_SC_CTL	0x000008EC
175 
176 /* Sample Rate Converter */
177 #define SRC_CTL		0x000008F0
178 #define SRC_LF_COEF	0x000008F4
179 #define SRC1_CTL	0x000008F8
180 #define SRC2_CTL	0x000008FC
181 #define SRC3_CTL	0x00000900
182 #define SRC4_CTL	0x00000904
183 #define SRC5_CTL	0x00000908
184 #define SRC6_CTL	0x0000090C
185 #define BAND_OUT_SEL	0x00000910
186 #define I2S_N_CTL	0x00000914
187 #define I2S_OUT_CTL	0x00000918
188 #define AUTOCONFIG_REG	0x000009C4
189 
190 /* Audio ADC Registers */
191 #define DSM_CTRL1	0x00000000
192 #define DSM_CTRL2	0x00000001
193 #define CHP_EN_CTRL	0x00000002
194 #define CHP_CLK_CTRL1	0x00000004
195 #define CHP_CLK_CTRL2	0x00000005
196 #define BG_REF_CTRL	0x00000006
197 #define SD2_SW_CTRL1	0x00000008
198 #define SD2_SW_CTRL2	0x00000009
199 #define SD2_BIAS_CTRL	0x0000000A
200 #define AMP_BIAS_CTRL	0x0000000C
201 #define CH_PWR_CTRL1	0x0000000E
202 #define FLD_CH_SEL      (1 << 3)
203 #define CH_PWR_CTRL2	0x0000000F
204 #define DSM_STATUS1	0x00000010
205 #define DSM_STATUS2	0x00000011
206 #define DIG_CTL1	0x00000012
207 #define DIG_CTL2	0x00000013
208 #define I2S_TX_CFG	0x0000001A
209 
210 #define DEV_CNTRL2	0x00040000
211 
212 #define PCI_MSK_IR        (1 << 28)
213 #define PCI_MSK_AV_CORE   (1 << 27)
214 #define PCI_MSK_GPIO1     (1 << 24)
215 #define PCI_MSK_GPIO0     (1 << 23)
216 #define PCI_MSK_APB_DMA   (1 << 12)
217 #define PCI_MSK_AL_WR     (1 << 11)
218 #define PCI_MSK_AL_RD     (1 << 10)
219 #define PCI_MSK_RISC_WR   (1 <<  9)
220 #define PCI_MSK_RISC_RD   (1 <<  8)
221 #define PCI_MSK_AUD_EXT   (1 <<  4)
222 #define PCI_MSK_AUD_INT   (1 <<  3)
223 #define PCI_MSK_VID_C     (1 <<  2)
224 #define PCI_MSK_VID_B     (1 <<  1)
225 #define PCI_MSK_VID_A      1
226 #define PCI_INT_MSK	0x00040010
227 
228 #define PCI_INT_STAT	0x00040014
229 #define PCI_INT_MSTAT	0x00040018
230 
231 #define VID_A_INT_MSK	0x00040020
232 #define VID_A_INT_STAT	0x00040024
233 #define VID_A_INT_MSTAT	0x00040028
234 #define VID_A_INT_SSTAT	0x0004002C
235 
236 #define VID_B_INT_MSK	0x00040030
237 #define VID_B_MSK_BAD_PKT     (1 << 20)
238 #define VID_B_MSK_VBI_OPC_ERR (1 << 17)
239 #define VID_B_MSK_OPC_ERR     (1 << 16)
240 #define VID_B_MSK_VBI_SYNC    (1 << 13)
241 #define VID_B_MSK_SYNC        (1 << 12)
242 #define VID_B_MSK_VBI_OF      (1 <<  9)
243 #define VID_B_MSK_OF          (1 <<  8)
244 #define VID_B_MSK_VBI_RISCI2  (1 <<  5)
245 #define VID_B_MSK_RISCI2      (1 <<  4)
246 #define VID_B_MSK_VBI_RISCI1  (1 <<  1)
247 #define VID_B_MSK_RISCI1       1
248 #define VID_B_INT_STAT	0x00040034
249 #define VID_B_INT_MSTAT	0x00040038
250 #define VID_B_INT_SSTAT	0x0004003C
251 
252 #define VID_B_MSK_BAD_PKT (1 << 20)
253 #define VID_B_MSK_OPC_ERR (1 << 16)
254 #define VID_B_MSK_SYNC    (1 << 12)
255 #define VID_B_MSK_OF      (1 <<  8)
256 #define VID_B_MSK_RISCI2  (1 <<  4)
257 #define VID_B_MSK_RISCI1   1
258 
259 #define VID_C_MSK_BAD_PKT (1 << 20)
260 #define VID_C_MSK_OPC_ERR (1 << 16)
261 #define VID_C_MSK_SYNC    (1 << 12)
262 #define VID_C_MSK_OF      (1 <<  8)
263 #define VID_C_MSK_RISCI2  (1 <<  4)
264 #define VID_C_MSK_RISCI1   1
265 
266 /* A superset for testing purposes */
267 #define VID_BC_MSK_BAD_PKT (1 << 20)
268 #define VID_BC_MSK_OPC_ERR (1 << 16)
269 #define VID_BC_MSK_SYNC    (1 << 12)
270 #define VID_BC_MSK_OF      (1 <<  8)
271 #define VID_BC_MSK_VBI_RISCI2 (1 <<  5)
272 #define VID_BC_MSK_RISCI2  (1 <<  4)
273 #define VID_BC_MSK_VBI_RISCI1 (1 <<  1)
274 #define VID_BC_MSK_RISCI1   1
275 
276 #define VID_C_INT_MSK	0x00040040
277 #define VID_C_INT_STAT	0x00040044
278 #define VID_C_INT_MSTAT	0x00040048
279 #define VID_C_INT_SSTAT	0x0004004C
280 
281 #define AUDIO_INT_INT_MSK	0x00040050
282 #define AUDIO_INT_INT_STAT	0x00040054
283 #define AUDIO_INT_INT_MSTAT	0x00040058
284 #define AUDIO_INT_INT_SSTAT	0x0004005C
285 
286 #define AUDIO_EXT_INT_MSK	0x00040060
287 #define AUDIO_EXT_INT_STAT	0x00040064
288 #define AUDIO_EXT_INT_MSTAT	0x00040068
289 #define AUDIO_EXT_INT_SSTAT	0x0004006C
290 
291 #define RDR_CFG0	0x00050000
292 #define RDR_CFG1	0x00050004
293 #define RDR_CFG2	0x00050008
294 #define RDR_RDRCTL1	0x0005030c
295 #define RDR_TLCTL0	0x00050318
296 
297 /* APB DMAC Current Buffer Pointer */
298 #define DMA1_PTR1	0x00100000
299 #define DMA2_PTR1	0x00100004
300 #define DMA3_PTR1	0x00100008
301 #define DMA4_PTR1	0x0010000C
302 #define DMA5_PTR1	0x00100010
303 #define DMA6_PTR1	0x00100014
304 #define DMA7_PTR1	0x00100018
305 #define DMA8_PTR1	0x0010001C
306 
307 /* APB DMAC Current Table Pointer */
308 #define DMA1_PTR2	0x00100040
309 #define DMA2_PTR2	0x00100044
310 #define DMA3_PTR2	0x00100048
311 #define DMA4_PTR2	0x0010004C
312 #define DMA5_PTR2	0x00100050
313 #define DMA6_PTR2	0x00100054
314 #define DMA7_PTR2	0x00100058
315 #define DMA8_PTR2	0x0010005C
316 
317 /* APB DMAC Buffer Limit */
318 #define DMA1_CNT1	0x00100080
319 #define DMA2_CNT1	0x00100084
320 #define DMA3_CNT1	0x00100088
321 #define DMA4_CNT1	0x0010008C
322 #define DMA5_CNT1	0x00100090
323 #define DMA6_CNT1	0x00100094
324 #define DMA7_CNT1	0x00100098
325 #define DMA8_CNT1	0x0010009C
326 
327 /* APB DMAC Table Size */
328 #define DMA1_CNT2	0x001000C0
329 #define DMA2_CNT2	0x001000C4
330 #define DMA3_CNT2	0x001000C8
331 #define DMA4_CNT2	0x001000CC
332 #define DMA5_CNT2	0x001000D0
333 #define DMA6_CNT2	0x001000D4
334 #define DMA7_CNT2	0x001000D8
335 #define DMA8_CNT2	0x001000DC
336 
337 /* Timer Counters */
338 #define TM_CNT_LDW	0x00110000
339 #define TM_CNT_UW	0x00110004
340 #define TM_LMT_LDW	0x00110008
341 #define TM_LMT_UW	0x0011000C
342 
343 /* GPIO */
344 #define GP0_IO		0x00110010
345 #define GPIO_ISM	0x00110014
346 #define SOFT_RESET	0x0011001C
347 
348 /* GPIO (417 Microsoftcontroller) RW Data */
349 #define MC417_RWD	0x00110020
350 
351 /* GPIO (417 Microsoftcontroller) Output Enable, Low Active */
352 #define MC417_OEN	0x00110024
353 #define MC417_CTL	0x00110028
354 #define ALT_PIN_OUT_SEL 0x0011002C
355 #define CLK_DELAY	0x00110048
356 #define PAD_CTRL	0x0011004C
357 
358 /* Video A Interface */
359 #define VID_A_GPCNT		0x00130020
360 #define VBI_A_GPCNT		0x00130024
361 #define VID_A_GPCNT_CTL		0x00130030
362 #define VBI_A_GPCNT_CTL		0x00130034
363 #define VID_A_DMA_CTL		0x00130040
364 #define VID_A_VIP_CTRL		0x00130080
365 #define VID_A_PIXEL_FRMT	0x00130084
366 #define VID_A_VBI_CTRL		0x00130088
367 
368 /* Video B Interface */
369 #define VID_B_DMA		0x00130100
370 #define VBI_B_DMA		0x00130108
371 #define VID_B_GPCNT		0x00130120
372 #define VBI_B_GPCNT		0x00130124
373 #define VID_B_GPCNT_CTL		0x00130134
374 #define VBI_B_GPCNT_CTL		0x00130138
375 #define VID_B_DMA_CTL		0x00130140
376 #define VID_B_SRC_SEL		0x00130144
377 #define VID_B_LNGTH		0x00130150
378 #define VID_B_HW_SOP_CTL	0x00130154
379 #define VID_B_GEN_CTL		0x00130158
380 #define VID_B_BD_PKT_STATUS	0x0013015C
381 #define VID_B_SOP_STATUS	0x00130160
382 #define VID_B_FIFO_OVFL_STAT	0x00130164
383 #define VID_B_VLD_MISC		0x00130168
384 #define VID_B_TS_CLK_EN		0x0013016C
385 #define VID_B_VIP_CTRL		0x00130180
386 #define VID_B_PIXEL_FRMT	0x00130184
387 
388 /* Video C Interface */
389 #define VID_C_GPCNT		0x00130220
390 #define VID_C_GPCNT_CTL		0x00130230
391 #define VBI_C_GPCNT_CTL		0x00130234
392 #define VID_C_DMA_CTL		0x00130240
393 #define VID_C_LNGTH		0x00130250
394 #define VID_C_HW_SOP_CTL	0x00130254
395 #define VID_C_GEN_CTL		0x00130258
396 #define VID_C_BD_PKT_STATUS	0x0013025C
397 #define VID_C_SOP_STATUS	0x00130260
398 #define VID_C_FIFO_OVFL_STAT	0x00130264
399 #define VID_C_VLD_MISC		0x00130268
400 #define VID_C_TS_CLK_EN		0x0013026C
401 
402 /* Internal Audio Interface */
403 #define AUD_INT_A_GPCNT		0x00140020
404 #define AUD_INT_B_GPCNT		0x00140024
405 #define AUD_INT_A_GPCNT_CTL	0x00140030
406 #define AUD_INT_B_GPCNT_CTL	0x00140034
407 #define AUD_INT_DMA_CTL		0x00140040
408 #define AUD_INT_A_LNGTH		0x00140050
409 #define AUD_INT_B_LNGTH		0x00140054
410 #define AUD_INT_A_MODE		0x00140058
411 #define AUD_INT_B_MODE		0x0014005C
412 
413 /* External Audio Interface */
414 #define AUD_EXT_DMA		0x00140100
415 #define AUD_EXT_GPCNT		0x00140120
416 #define AUD_EXT_GPCNT_CTL	0x00140130
417 #define AUD_EXT_DMA_CTL		0x00140140
418 #define AUD_EXT_LNGTH		0x00140150
419 #define AUD_EXT_A_MODE		0x00140158
420 
421 /* I2C Bus 1 */
422 #define I2C1_ADDR	0x00180000
423 #define I2C1_WDATA	0x00180004
424 #define I2C1_CTRL	0x00180008
425 #define I2C1_RDATA	0x0018000C
426 #define I2C1_STAT	0x00180010
427 
428 /* I2C Bus 2 */
429 #define I2C2_ADDR	0x00190000
430 #define I2C2_WDATA	0x00190004
431 #define I2C2_CTRL	0x00190008
432 #define I2C2_RDATA	0x0019000C
433 #define I2C2_STAT	0x00190010
434 
435 /* I2C Bus 3 */
436 #define I2C3_ADDR	0x001A0000
437 #define I2C3_WDATA	0x001A0004
438 #define I2C3_CTRL	0x001A0008
439 #define I2C3_RDATA	0x001A000C
440 #define I2C3_STAT	0x001A0010
441 
442 /* UART */
443 #define UART_CTL	0x001B0000
444 #define UART_BRD	0x001B0004
445 #define UART_ISR	0x001B000C
446 #define UART_CNT	0x001B0010
447 
448 #endif /* _CX23885_REG_H_ */
449