1 /* 2 * Driver for the Conexant CX23885 PCIe bridge 3 * 4 * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 20 */ 21 22 #include <linux/module.h> 23 #include <linux/init.h> 24 #include <linux/device.h> 25 #include <linux/fs.h> 26 #include <linux/kthread.h> 27 #include <linux/file.h> 28 #include <linux/suspend.h> 29 30 #include "cx23885.h" 31 #include <media/v4l2-common.h> 32 33 #include "dvb_ca_en50221.h" 34 #include "s5h1409.h" 35 #include "s5h1411.h" 36 #include "mt2131.h" 37 #include "tda8290.h" 38 #include "tda18271.h" 39 #include "lgdt330x.h" 40 #include "xc4000.h" 41 #include "xc5000.h" 42 #include "max2165.h" 43 #include "tda10048.h" 44 #include "tuner-xc2028.h" 45 #include "tuner-simple.h" 46 #include "dib7000p.h" 47 #include "dibx000_common.h" 48 #include "zl10353.h" 49 #include "stv0900.h" 50 #include "stv0900_reg.h" 51 #include "stv6110.h" 52 #include "lnbh24.h" 53 #include "cx24116.h" 54 #include "cx24117.h" 55 #include "cimax2.h" 56 #include "lgs8gxx.h" 57 #include "netup-eeprom.h" 58 #include "netup-init.h" 59 #include "lgdt3305.h" 60 #include "atbm8830.h" 61 #include "ts2020.h" 62 #include "ds3000.h" 63 #include "cx23885-f300.h" 64 #include "altera-ci.h" 65 #include "stv0367.h" 66 #include "drxk.h" 67 #include "mt2063.h" 68 #include "stv090x.h" 69 #include "stb6100.h" 70 #include "stb6100_cfg.h" 71 #include "tda10071.h" 72 #include "a8293.h" 73 #include "mb86a20s.h" 74 75 static unsigned int debug; 76 77 #define dprintk(level, fmt, arg...)\ 78 do { if (debug >= level)\ 79 printk(KERN_DEBUG "%s/0: " fmt, dev->name, ## arg);\ 80 } while (0) 81 82 /* ------------------------------------------------------------------ */ 83 84 static unsigned int alt_tuner; 85 module_param(alt_tuner, int, 0644); 86 MODULE_PARM_DESC(alt_tuner, "Enable alternate tuner configuration"); 87 88 DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr); 89 90 /* ------------------------------------------------------------------ */ 91 92 static int dvb_buf_setup(struct videobuf_queue *q, 93 unsigned int *count, unsigned int *size) 94 { 95 struct cx23885_tsport *port = q->priv_data; 96 97 port->ts_packet_size = 188 * 4; 98 port->ts_packet_count = 32; 99 100 *size = port->ts_packet_size * port->ts_packet_count; 101 *count = 32; 102 return 0; 103 } 104 105 static int dvb_buf_prepare(struct videobuf_queue *q, 106 struct videobuf_buffer *vb, enum v4l2_field field) 107 { 108 struct cx23885_tsport *port = q->priv_data; 109 return cx23885_buf_prepare(q, port, (struct cx23885_buffer *)vb, field); 110 } 111 112 static void dvb_buf_queue(struct videobuf_queue *q, struct videobuf_buffer *vb) 113 { 114 struct cx23885_tsport *port = q->priv_data; 115 cx23885_buf_queue(port, (struct cx23885_buffer *)vb); 116 } 117 118 static void dvb_buf_release(struct videobuf_queue *q, 119 struct videobuf_buffer *vb) 120 { 121 cx23885_free_buffer(q, (struct cx23885_buffer *)vb); 122 } 123 124 static void cx23885_dvb_gate_ctrl(struct cx23885_tsport *port, int open) 125 { 126 struct videobuf_dvb_frontends *f; 127 struct videobuf_dvb_frontend *fe; 128 129 f = &port->frontends; 130 131 if (f->gate <= 1) /* undefined or fe0 */ 132 fe = videobuf_dvb_get_frontend(f, 1); 133 else 134 fe = videobuf_dvb_get_frontend(f, f->gate); 135 136 if (fe && fe->dvb.frontend && fe->dvb.frontend->ops.i2c_gate_ctrl) 137 fe->dvb.frontend->ops.i2c_gate_ctrl(fe->dvb.frontend, open); 138 } 139 140 static struct videobuf_queue_ops dvb_qops = { 141 .buf_setup = dvb_buf_setup, 142 .buf_prepare = dvb_buf_prepare, 143 .buf_queue = dvb_buf_queue, 144 .buf_release = dvb_buf_release, 145 }; 146 147 static struct s5h1409_config hauppauge_generic_config = { 148 .demod_address = 0x32 >> 1, 149 .output_mode = S5H1409_SERIAL_OUTPUT, 150 .gpio = S5H1409_GPIO_ON, 151 .qam_if = 44000, 152 .inversion = S5H1409_INVERSION_OFF, 153 .status_mode = S5H1409_DEMODLOCKING, 154 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK, 155 }; 156 157 static struct tda10048_config hauppauge_hvr1200_config = { 158 .demod_address = 0x10 >> 1, 159 .output_mode = TDA10048_SERIAL_OUTPUT, 160 .fwbulkwritelen = TDA10048_BULKWRITE_200, 161 .inversion = TDA10048_INVERSION_ON, 162 .dtv6_if_freq_khz = TDA10048_IF_3300, 163 .dtv7_if_freq_khz = TDA10048_IF_3800, 164 .dtv8_if_freq_khz = TDA10048_IF_4300, 165 .clk_freq_khz = TDA10048_CLK_16000, 166 }; 167 168 static struct tda10048_config hauppauge_hvr1210_config = { 169 .demod_address = 0x10 >> 1, 170 .output_mode = TDA10048_SERIAL_OUTPUT, 171 .fwbulkwritelen = TDA10048_BULKWRITE_200, 172 .inversion = TDA10048_INVERSION_ON, 173 .dtv6_if_freq_khz = TDA10048_IF_3300, 174 .dtv7_if_freq_khz = TDA10048_IF_3500, 175 .dtv8_if_freq_khz = TDA10048_IF_4000, 176 .clk_freq_khz = TDA10048_CLK_16000, 177 }; 178 179 static struct s5h1409_config hauppauge_ezqam_config = { 180 .demod_address = 0x32 >> 1, 181 .output_mode = S5H1409_SERIAL_OUTPUT, 182 .gpio = S5H1409_GPIO_OFF, 183 .qam_if = 4000, 184 .inversion = S5H1409_INVERSION_ON, 185 .status_mode = S5H1409_DEMODLOCKING, 186 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK, 187 }; 188 189 static struct s5h1409_config hauppauge_hvr1800lp_config = { 190 .demod_address = 0x32 >> 1, 191 .output_mode = S5H1409_SERIAL_OUTPUT, 192 .gpio = S5H1409_GPIO_OFF, 193 .qam_if = 44000, 194 .inversion = S5H1409_INVERSION_OFF, 195 .status_mode = S5H1409_DEMODLOCKING, 196 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK, 197 }; 198 199 static struct s5h1409_config hauppauge_hvr1500_config = { 200 .demod_address = 0x32 >> 1, 201 .output_mode = S5H1409_SERIAL_OUTPUT, 202 .gpio = S5H1409_GPIO_OFF, 203 .inversion = S5H1409_INVERSION_OFF, 204 .status_mode = S5H1409_DEMODLOCKING, 205 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK, 206 }; 207 208 static struct mt2131_config hauppauge_generic_tunerconfig = { 209 0x61 210 }; 211 212 static struct lgdt330x_config fusionhdtv_5_express = { 213 .demod_address = 0x0e, 214 .demod_chip = LGDT3303, 215 .serial_mpeg = 0x40, 216 }; 217 218 static struct s5h1409_config hauppauge_hvr1500q_config = { 219 .demod_address = 0x32 >> 1, 220 .output_mode = S5H1409_SERIAL_OUTPUT, 221 .gpio = S5H1409_GPIO_ON, 222 .qam_if = 44000, 223 .inversion = S5H1409_INVERSION_OFF, 224 .status_mode = S5H1409_DEMODLOCKING, 225 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK, 226 }; 227 228 static struct s5h1409_config dvico_s5h1409_config = { 229 .demod_address = 0x32 >> 1, 230 .output_mode = S5H1409_SERIAL_OUTPUT, 231 .gpio = S5H1409_GPIO_ON, 232 .qam_if = 44000, 233 .inversion = S5H1409_INVERSION_OFF, 234 .status_mode = S5H1409_DEMODLOCKING, 235 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK, 236 }; 237 238 static struct s5h1411_config dvico_s5h1411_config = { 239 .output_mode = S5H1411_SERIAL_OUTPUT, 240 .gpio = S5H1411_GPIO_ON, 241 .qam_if = S5H1411_IF_44000, 242 .vsb_if = S5H1411_IF_44000, 243 .inversion = S5H1411_INVERSION_OFF, 244 .status_mode = S5H1411_DEMODLOCKING, 245 .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK, 246 }; 247 248 static struct s5h1411_config hcw_s5h1411_config = { 249 .output_mode = S5H1411_SERIAL_OUTPUT, 250 .gpio = S5H1411_GPIO_OFF, 251 .vsb_if = S5H1411_IF_44000, 252 .qam_if = S5H1411_IF_4000, 253 .inversion = S5H1411_INVERSION_ON, 254 .status_mode = S5H1411_DEMODLOCKING, 255 .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK, 256 }; 257 258 static struct xc5000_config hauppauge_hvr1500q_tunerconfig = { 259 .i2c_address = 0x61, 260 .if_khz = 5380, 261 }; 262 263 static struct xc5000_config dvico_xc5000_tunerconfig = { 264 .i2c_address = 0x64, 265 .if_khz = 5380, 266 }; 267 268 static struct tda829x_config tda829x_no_probe = { 269 .probe_tuner = TDA829X_DONT_PROBE, 270 }; 271 272 static struct tda18271_std_map hauppauge_tda18271_std_map = { 273 .atsc_6 = { .if_freq = 5380, .agc_mode = 3, .std = 3, 274 .if_lvl = 6, .rfagc_top = 0x37 }, 275 .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 0, 276 .if_lvl = 6, .rfagc_top = 0x37 }, 277 }; 278 279 static struct tda18271_std_map hauppauge_hvr1200_tda18271_std_map = { 280 .dvbt_6 = { .if_freq = 3300, .agc_mode = 3, .std = 4, 281 .if_lvl = 1, .rfagc_top = 0x37, }, 282 .dvbt_7 = { .if_freq = 3800, .agc_mode = 3, .std = 5, 283 .if_lvl = 1, .rfagc_top = 0x37, }, 284 .dvbt_8 = { .if_freq = 4300, .agc_mode = 3, .std = 6, 285 .if_lvl = 1, .rfagc_top = 0x37, }, 286 }; 287 288 static struct tda18271_config hauppauge_tda18271_config = { 289 .std_map = &hauppauge_tda18271_std_map, 290 .gate = TDA18271_GATE_ANALOG, 291 .output_opt = TDA18271_OUTPUT_LT_OFF, 292 }; 293 294 static struct tda18271_config hauppauge_hvr1200_tuner_config = { 295 .std_map = &hauppauge_hvr1200_tda18271_std_map, 296 .gate = TDA18271_GATE_ANALOG, 297 .output_opt = TDA18271_OUTPUT_LT_OFF, 298 }; 299 300 static struct tda18271_config hauppauge_hvr1210_tuner_config = { 301 .gate = TDA18271_GATE_DIGITAL, 302 .output_opt = TDA18271_OUTPUT_LT_OFF, 303 }; 304 305 static struct tda18271_std_map hauppauge_hvr127x_std_map = { 306 .atsc_6 = { .if_freq = 3250, .agc_mode = 3, .std = 4, 307 .if_lvl = 1, .rfagc_top = 0x58 }, 308 .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 5, 309 .if_lvl = 1, .rfagc_top = 0x58 }, 310 }; 311 312 static struct tda18271_config hauppauge_hvr127x_config = { 313 .std_map = &hauppauge_hvr127x_std_map, 314 .output_opt = TDA18271_OUTPUT_LT_OFF, 315 }; 316 317 static struct lgdt3305_config hauppauge_lgdt3305_config = { 318 .i2c_addr = 0x0e, 319 .mpeg_mode = LGDT3305_MPEG_SERIAL, 320 .tpclk_edge = LGDT3305_TPCLK_FALLING_EDGE, 321 .tpvalid_polarity = LGDT3305_TP_VALID_HIGH, 322 .deny_i2c_rptr = 1, 323 .spectral_inversion = 1, 324 .qam_if_khz = 4000, 325 .vsb_if_khz = 3250, 326 }; 327 328 static struct dibx000_agc_config xc3028_agc_config = { 329 BAND_VHF | BAND_UHF, /* band_caps */ 330 331 /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=0, 332 * P_agc_inv_pwm1=0, P_agc_inv_pwm2=0, 333 * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0, 334 * P_agc_nb_est=2, P_agc_write=0 335 */ 336 (0 << 15) | (0 << 14) | (0 << 11) | (0 << 10) | (0 << 9) | (0 << 8) | 337 (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0), /* setup */ 338 339 712, /* inv_gain */ 340 21, /* time_stabiliz */ 341 342 0, /* alpha_level */ 343 118, /* thlock */ 344 345 0, /* wbd_inv */ 346 2867, /* wbd_ref */ 347 0, /* wbd_sel */ 348 2, /* wbd_alpha */ 349 350 0, /* agc1_max */ 351 0, /* agc1_min */ 352 39718, /* agc2_max */ 353 9930, /* agc2_min */ 354 0, /* agc1_pt1 */ 355 0, /* agc1_pt2 */ 356 0, /* agc1_pt3 */ 357 0, /* agc1_slope1 */ 358 0, /* agc1_slope2 */ 359 0, /* agc2_pt1 */ 360 128, /* agc2_pt2 */ 361 29, /* agc2_slope1 */ 362 29, /* agc2_slope2 */ 363 364 17, /* alpha_mant */ 365 27, /* alpha_exp */ 366 23, /* beta_mant */ 367 51, /* beta_exp */ 368 369 1, /* perform_agc_softsplit */ 370 }; 371 372 /* PLL Configuration for COFDM BW_MHz = 8.000000 373 * With external clock = 30.000000 */ 374 static struct dibx000_bandwidth_config xc3028_bw_config = { 375 60000, /* internal */ 376 30000, /* sampling */ 377 1, /* pll_cfg: prediv */ 378 8, /* pll_cfg: ratio */ 379 3, /* pll_cfg: range */ 380 1, /* pll_cfg: reset */ 381 0, /* pll_cfg: bypass */ 382 0, /* misc: refdiv */ 383 0, /* misc: bypclk_div */ 384 1, /* misc: IO_CLK_en_core */ 385 1, /* misc: ADClkSrc */ 386 0, /* misc: modulo */ 387 (3 << 14) | (1 << 12) | (524 << 0), /* sad_cfg: refsel, sel, freq_15k */ 388 (1 << 25) | 5816102, /* ifreq = 5.200000 MHz */ 389 20452225, /* timf */ 390 30000000 /* xtal_hz */ 391 }; 392 393 static struct dib7000p_config hauppauge_hvr1400_dib7000_config = { 394 .output_mpeg2_in_188_bytes = 1, 395 .hostbus_diversity = 1, 396 .tuner_is_baseband = 0, 397 .update_lna = NULL, 398 399 .agc_config_count = 1, 400 .agc = &xc3028_agc_config, 401 .bw = &xc3028_bw_config, 402 403 .gpio_dir = DIB7000P_GPIO_DEFAULT_DIRECTIONS, 404 .gpio_val = DIB7000P_GPIO_DEFAULT_VALUES, 405 .gpio_pwm_pos = DIB7000P_GPIO_DEFAULT_PWM_POS, 406 407 .pwm_freq_div = 0, 408 .agc_control = NULL, 409 .spur_protect = 0, 410 411 .output_mode = OUTMODE_MPEG2_SERIAL, 412 }; 413 414 static struct zl10353_config dvico_fusionhdtv_xc3028 = { 415 .demod_address = 0x0f, 416 .if2 = 45600, 417 .no_tuner = 1, 418 .disable_i2c_gate_ctrl = 1, 419 }; 420 421 static struct stv0900_reg stv0900_ts_regs[] = { 422 { R0900_TSGENERAL, 0x00 }, 423 { R0900_P1_TSSPEED, 0x40 }, 424 { R0900_P2_TSSPEED, 0x40 }, 425 { R0900_P1_TSCFGM, 0xc0 }, 426 { R0900_P2_TSCFGM, 0xc0 }, 427 { R0900_P1_TSCFGH, 0xe0 }, 428 { R0900_P2_TSCFGH, 0xe0 }, 429 { R0900_P1_TSCFGL, 0x20 }, 430 { R0900_P2_TSCFGL, 0x20 }, 431 { 0xffff, 0xff }, /* terminate */ 432 }; 433 434 static struct stv0900_config netup_stv0900_config = { 435 .demod_address = 0x68, 436 .demod_mode = 1, /* dual */ 437 .xtal = 8000000, 438 .clkmode = 3,/* 0-CLKI, 2-XTALI, else AUTO */ 439 .diseqc_mode = 2,/* 2/3 PWM */ 440 .ts_config_regs = stv0900_ts_regs, 441 .tun1_maddress = 0,/* 0x60 */ 442 .tun2_maddress = 3,/* 0x63 */ 443 .tun1_adc = 1,/* 1 Vpp */ 444 .tun2_adc = 1,/* 1 Vpp */ 445 }; 446 447 static struct stv6110_config netup_stv6110_tunerconfig_a = { 448 .i2c_address = 0x60, 449 .mclk = 16000000, 450 .clk_div = 1, 451 .gain = 8, /* +16 dB - maximum gain */ 452 }; 453 454 static struct stv6110_config netup_stv6110_tunerconfig_b = { 455 .i2c_address = 0x63, 456 .mclk = 16000000, 457 .clk_div = 1, 458 .gain = 8, /* +16 dB - maximum gain */ 459 }; 460 461 static struct cx24116_config tbs_cx24116_config = { 462 .demod_address = 0x55, 463 }; 464 465 static struct cx24117_config tbs_cx24117_config = { 466 .demod_address = 0x55, 467 }; 468 469 static struct ds3000_config tevii_ds3000_config = { 470 .demod_address = 0x68, 471 }; 472 473 static struct ts2020_config tevii_ts2020_config = { 474 .tuner_address = 0x60, 475 .clk_out_div = 1, 476 .frequency_div = 1146000, 477 }; 478 479 static struct cx24116_config dvbworld_cx24116_config = { 480 .demod_address = 0x05, 481 }; 482 483 static struct lgs8gxx_config mygica_x8506_lgs8gl5_config = { 484 .prod = LGS8GXX_PROD_LGS8GL5, 485 .demod_address = 0x19, 486 .serial_ts = 0, 487 .ts_clk_pol = 1, 488 .ts_clk_gated = 1, 489 .if_clk_freq = 30400, /* 30.4 MHz */ 490 .if_freq = 5380, /* 5.38 MHz */ 491 .if_neg_center = 1, 492 .ext_adc = 0, 493 .adc_signed = 0, 494 .if_neg_edge = 0, 495 }; 496 497 static struct xc5000_config mygica_x8506_xc5000_config = { 498 .i2c_address = 0x61, 499 .if_khz = 5380, 500 }; 501 502 static struct mb86a20s_config mygica_x8507_mb86a20s_config = { 503 .demod_address = 0x10, 504 }; 505 506 static struct xc5000_config mygica_x8507_xc5000_config = { 507 .i2c_address = 0x61, 508 .if_khz = 4000, 509 }; 510 511 static struct stv090x_config prof_8000_stv090x_config = { 512 .device = STV0903, 513 .demod_mode = STV090x_SINGLE, 514 .clk_mode = STV090x_CLK_EXT, 515 .xtal = 27000000, 516 .address = 0x6A, 517 .ts1_mode = STV090x_TSMODE_PARALLEL_PUNCTURED, 518 .repeater_level = STV090x_RPTLEVEL_64, 519 .adc1_range = STV090x_ADC_2Vpp, 520 .diseqc_envelope_mode = false, 521 522 .tuner_get_frequency = stb6100_get_frequency, 523 .tuner_set_frequency = stb6100_set_frequency, 524 .tuner_set_bandwidth = stb6100_set_bandwidth, 525 .tuner_get_bandwidth = stb6100_get_bandwidth, 526 }; 527 528 static struct stb6100_config prof_8000_stb6100_config = { 529 .tuner_address = 0x60, 530 .refclock = 27000000, 531 }; 532 533 static int p8000_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage) 534 { 535 struct cx23885_tsport *port = fe->dvb->priv; 536 struct cx23885_dev *dev = port->dev; 537 538 if (voltage == SEC_VOLTAGE_18) 539 cx_write(MC417_RWD, 0x00001e00); 540 else if (voltage == SEC_VOLTAGE_13) 541 cx_write(MC417_RWD, 0x00001a00); 542 else 543 cx_write(MC417_RWD, 0x00001800); 544 return 0; 545 } 546 547 static int cx23885_dvb_set_frontend(struct dvb_frontend *fe) 548 { 549 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 550 struct cx23885_tsport *port = fe->dvb->priv; 551 struct cx23885_dev *dev = port->dev; 552 553 switch (dev->board) { 554 case CX23885_BOARD_HAUPPAUGE_HVR1275: 555 switch (p->modulation) { 556 case VSB_8: 557 cx23885_gpio_clear(dev, GPIO_5); 558 break; 559 case QAM_64: 560 case QAM_256: 561 default: 562 cx23885_gpio_set(dev, GPIO_5); 563 break; 564 } 565 break; 566 case CX23885_BOARD_MYGICA_X8506: 567 case CX23885_BOARD_MYGICA_X8507: 568 case CX23885_BOARD_MAGICPRO_PROHDTVE2: 569 /* Select Digital TV */ 570 cx23885_gpio_set(dev, GPIO_0); 571 break; 572 } 573 574 /* Call the real set_frontend */ 575 if (port->set_frontend) 576 return port->set_frontend(fe); 577 578 return 0; 579 } 580 581 static void cx23885_set_frontend_hook(struct cx23885_tsport *port, 582 struct dvb_frontend *fe) 583 { 584 port->set_frontend = fe->ops.set_frontend; 585 fe->ops.set_frontend = cx23885_dvb_set_frontend; 586 } 587 588 static struct lgs8gxx_config magicpro_prohdtve2_lgs8g75_config = { 589 .prod = LGS8GXX_PROD_LGS8G75, 590 .demod_address = 0x19, 591 .serial_ts = 0, 592 .ts_clk_pol = 1, 593 .ts_clk_gated = 1, 594 .if_clk_freq = 30400, /* 30.4 MHz */ 595 .if_freq = 6500, /* 6.50 MHz */ 596 .if_neg_center = 1, 597 .ext_adc = 0, 598 .adc_signed = 1, 599 .adc_vpp = 2, /* 1.6 Vpp */ 600 .if_neg_edge = 1, 601 }; 602 603 static struct xc5000_config magicpro_prohdtve2_xc5000_config = { 604 .i2c_address = 0x61, 605 .if_khz = 6500, 606 }; 607 608 static struct atbm8830_config mygica_x8558pro_atbm8830_cfg1 = { 609 .prod = ATBM8830_PROD_8830, 610 .demod_address = 0x44, 611 .serial_ts = 0, 612 .ts_sampling_edge = 1, 613 .ts_clk_gated = 0, 614 .osc_clk_freq = 30400, /* in kHz */ 615 .if_freq = 0, /* zero IF */ 616 .zif_swap_iq = 1, 617 .agc_min = 0x2E, 618 .agc_max = 0xFF, 619 .agc_hold_loop = 0, 620 }; 621 622 static struct max2165_config mygic_x8558pro_max2165_cfg1 = { 623 .i2c_address = 0x60, 624 .osc_clk = 20 625 }; 626 627 static struct atbm8830_config mygica_x8558pro_atbm8830_cfg2 = { 628 .prod = ATBM8830_PROD_8830, 629 .demod_address = 0x44, 630 .serial_ts = 1, 631 .ts_sampling_edge = 1, 632 .ts_clk_gated = 0, 633 .osc_clk_freq = 30400, /* in kHz */ 634 .if_freq = 0, /* zero IF */ 635 .zif_swap_iq = 1, 636 .agc_min = 0x2E, 637 .agc_max = 0xFF, 638 .agc_hold_loop = 0, 639 }; 640 641 static struct max2165_config mygic_x8558pro_max2165_cfg2 = { 642 .i2c_address = 0x60, 643 .osc_clk = 20 644 }; 645 static struct stv0367_config netup_stv0367_config[] = { 646 { 647 .demod_address = 0x1c, 648 .xtal = 27000000, 649 .if_khz = 4500, 650 .if_iq_mode = 0, 651 .ts_mode = 1, 652 .clk_pol = 0, 653 }, { 654 .demod_address = 0x1d, 655 .xtal = 27000000, 656 .if_khz = 4500, 657 .if_iq_mode = 0, 658 .ts_mode = 1, 659 .clk_pol = 0, 660 }, 661 }; 662 663 static struct xc5000_config netup_xc5000_config[] = { 664 { 665 .i2c_address = 0x61, 666 .if_khz = 4500, 667 }, { 668 .i2c_address = 0x64, 669 .if_khz = 4500, 670 }, 671 }; 672 673 static struct drxk_config terratec_drxk_config[] = { 674 { 675 .adr = 0x29, 676 .no_i2c_bridge = 1, 677 }, { 678 .adr = 0x2a, 679 .no_i2c_bridge = 1, 680 }, 681 }; 682 683 static struct mt2063_config terratec_mt2063_config[] = { 684 { 685 .tuner_address = 0x60, 686 }, { 687 .tuner_address = 0x67, 688 }, 689 }; 690 691 static const struct tda10071_config hauppauge_tda10071_config = { 692 .demod_i2c_addr = 0x05, 693 .tuner_i2c_addr = 0x54, 694 .i2c_wr_max = 64, 695 .ts_mode = TDA10071_TS_SERIAL, 696 .spec_inv = 0, 697 .xtal = 40444000, /* 40.444 MHz */ 698 .pll_multiplier = 20, 699 }; 700 701 static const struct a8293_config hauppauge_a8293_config = { 702 .i2c_addr = 0x0b, 703 }; 704 705 static int netup_altera_fpga_rw(void *device, int flag, int data, int read) 706 { 707 struct cx23885_dev *dev = (struct cx23885_dev *)device; 708 unsigned long timeout = jiffies + msecs_to_jiffies(1); 709 uint32_t mem = 0; 710 711 mem = cx_read(MC417_RWD); 712 if (read) 713 cx_set(MC417_OEN, ALT_DATA); 714 else { 715 cx_clear(MC417_OEN, ALT_DATA);/* D0-D7 out */ 716 mem &= ~ALT_DATA; 717 mem |= (data & ALT_DATA); 718 } 719 720 if (flag) 721 mem |= ALT_AD_RG; 722 else 723 mem &= ~ALT_AD_RG; 724 725 mem &= ~ALT_CS; 726 if (read) 727 mem = (mem & ~ALT_RD) | ALT_WR; 728 else 729 mem = (mem & ~ALT_WR) | ALT_RD; 730 731 cx_write(MC417_RWD, mem); /* start RW cycle */ 732 733 for (;;) { 734 mem = cx_read(MC417_RWD); 735 if ((mem & ALT_RDY) == 0) 736 break; 737 if (time_after(jiffies, timeout)) 738 break; 739 udelay(1); 740 } 741 742 cx_set(MC417_RWD, ALT_RD | ALT_WR | ALT_CS); 743 if (read) 744 return mem & ALT_DATA; 745 746 return 0; 747 }; 748 749 static int dvb_register(struct cx23885_tsport *port) 750 { 751 struct cx23885_dev *dev = port->dev; 752 struct cx23885_i2c *i2c_bus = NULL, *i2c_bus2 = NULL; 753 struct videobuf_dvb_frontend *fe0, *fe1 = NULL; 754 int mfe_shared = 0; /* bus not shared by default */ 755 int ret; 756 757 /* Get the first frontend */ 758 fe0 = videobuf_dvb_get_frontend(&port->frontends, 1); 759 if (!fe0) 760 return -EINVAL; 761 762 /* init struct videobuf_dvb */ 763 fe0->dvb.name = dev->name; 764 765 /* multi-frontend gate control is undefined or defaults to fe0 */ 766 port->frontends.gate = 0; 767 768 /* Sets the gate control callback to be used by i2c command calls */ 769 port->gate_ctrl = cx23885_dvb_gate_ctrl; 770 771 /* init frontend */ 772 switch (dev->board) { 773 case CX23885_BOARD_HAUPPAUGE_HVR1250: 774 i2c_bus = &dev->i2c_bus[0]; 775 fe0->dvb.frontend = dvb_attach(s5h1409_attach, 776 &hauppauge_generic_config, 777 &i2c_bus->i2c_adap); 778 if (fe0->dvb.frontend != NULL) { 779 dvb_attach(mt2131_attach, fe0->dvb.frontend, 780 &i2c_bus->i2c_adap, 781 &hauppauge_generic_tunerconfig, 0); 782 } 783 break; 784 case CX23885_BOARD_HAUPPAUGE_HVR1270: 785 case CX23885_BOARD_HAUPPAUGE_HVR1275: 786 i2c_bus = &dev->i2c_bus[0]; 787 fe0->dvb.frontend = dvb_attach(lgdt3305_attach, 788 &hauppauge_lgdt3305_config, 789 &i2c_bus->i2c_adap); 790 if (fe0->dvb.frontend != NULL) { 791 dvb_attach(tda18271_attach, fe0->dvb.frontend, 792 0x60, &dev->i2c_bus[1].i2c_adap, 793 &hauppauge_hvr127x_config); 794 } 795 if (dev->board == CX23885_BOARD_HAUPPAUGE_HVR1275) 796 cx23885_set_frontend_hook(port, fe0->dvb.frontend); 797 break; 798 case CX23885_BOARD_HAUPPAUGE_HVR1255: 799 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111: 800 i2c_bus = &dev->i2c_bus[0]; 801 fe0->dvb.frontend = dvb_attach(s5h1411_attach, 802 &hcw_s5h1411_config, 803 &i2c_bus->i2c_adap); 804 if (fe0->dvb.frontend != NULL) { 805 dvb_attach(tda18271_attach, fe0->dvb.frontend, 806 0x60, &dev->i2c_bus[1].i2c_adap, 807 &hauppauge_tda18271_config); 808 } 809 810 tda18271_attach(&dev->ts1.analog_fe, 811 0x60, &dev->i2c_bus[1].i2c_adap, 812 &hauppauge_tda18271_config); 813 814 break; 815 case CX23885_BOARD_HAUPPAUGE_HVR1800: 816 i2c_bus = &dev->i2c_bus[0]; 817 switch (alt_tuner) { 818 case 1: 819 fe0->dvb.frontend = 820 dvb_attach(s5h1409_attach, 821 &hauppauge_ezqam_config, 822 &i2c_bus->i2c_adap); 823 if (fe0->dvb.frontend != NULL) { 824 dvb_attach(tda829x_attach, fe0->dvb.frontend, 825 &dev->i2c_bus[1].i2c_adap, 0x42, 826 &tda829x_no_probe); 827 dvb_attach(tda18271_attach, fe0->dvb.frontend, 828 0x60, &dev->i2c_bus[1].i2c_adap, 829 &hauppauge_tda18271_config); 830 } 831 break; 832 case 0: 833 default: 834 fe0->dvb.frontend = 835 dvb_attach(s5h1409_attach, 836 &hauppauge_generic_config, 837 &i2c_bus->i2c_adap); 838 if (fe0->dvb.frontend != NULL) 839 dvb_attach(mt2131_attach, fe0->dvb.frontend, 840 &i2c_bus->i2c_adap, 841 &hauppauge_generic_tunerconfig, 0); 842 break; 843 } 844 break; 845 case CX23885_BOARD_HAUPPAUGE_HVR1800lp: 846 i2c_bus = &dev->i2c_bus[0]; 847 fe0->dvb.frontend = dvb_attach(s5h1409_attach, 848 &hauppauge_hvr1800lp_config, 849 &i2c_bus->i2c_adap); 850 if (fe0->dvb.frontend != NULL) { 851 dvb_attach(mt2131_attach, fe0->dvb.frontend, 852 &i2c_bus->i2c_adap, 853 &hauppauge_generic_tunerconfig, 0); 854 } 855 break; 856 case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP: 857 i2c_bus = &dev->i2c_bus[0]; 858 fe0->dvb.frontend = dvb_attach(lgdt330x_attach, 859 &fusionhdtv_5_express, 860 &i2c_bus->i2c_adap); 861 if (fe0->dvb.frontend != NULL) { 862 dvb_attach(simple_tuner_attach, fe0->dvb.frontend, 863 &i2c_bus->i2c_adap, 0x61, 864 TUNER_LG_TDVS_H06XF); 865 } 866 break; 867 case CX23885_BOARD_HAUPPAUGE_HVR1500Q: 868 i2c_bus = &dev->i2c_bus[1]; 869 fe0->dvb.frontend = dvb_attach(s5h1409_attach, 870 &hauppauge_hvr1500q_config, 871 &dev->i2c_bus[0].i2c_adap); 872 if (fe0->dvb.frontend != NULL) 873 dvb_attach(xc5000_attach, fe0->dvb.frontend, 874 &i2c_bus->i2c_adap, 875 &hauppauge_hvr1500q_tunerconfig); 876 break; 877 case CX23885_BOARD_HAUPPAUGE_HVR1500: 878 i2c_bus = &dev->i2c_bus[1]; 879 fe0->dvb.frontend = dvb_attach(s5h1409_attach, 880 &hauppauge_hvr1500_config, 881 &dev->i2c_bus[0].i2c_adap); 882 if (fe0->dvb.frontend != NULL) { 883 struct dvb_frontend *fe; 884 struct xc2028_config cfg = { 885 .i2c_adap = &i2c_bus->i2c_adap, 886 .i2c_addr = 0x61, 887 }; 888 static struct xc2028_ctrl ctl = { 889 .fname = XC2028_DEFAULT_FIRMWARE, 890 .max_len = 64, 891 .demod = XC3028_FE_OREN538, 892 }; 893 894 fe = dvb_attach(xc2028_attach, 895 fe0->dvb.frontend, &cfg); 896 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL) 897 fe->ops.tuner_ops.set_config(fe, &ctl); 898 } 899 break; 900 case CX23885_BOARD_HAUPPAUGE_HVR1200: 901 case CX23885_BOARD_HAUPPAUGE_HVR1700: 902 i2c_bus = &dev->i2c_bus[0]; 903 fe0->dvb.frontend = dvb_attach(tda10048_attach, 904 &hauppauge_hvr1200_config, 905 &i2c_bus->i2c_adap); 906 if (fe0->dvb.frontend != NULL) { 907 dvb_attach(tda829x_attach, fe0->dvb.frontend, 908 &dev->i2c_bus[1].i2c_adap, 0x42, 909 &tda829x_no_probe); 910 dvb_attach(tda18271_attach, fe0->dvb.frontend, 911 0x60, &dev->i2c_bus[1].i2c_adap, 912 &hauppauge_hvr1200_tuner_config); 913 } 914 break; 915 case CX23885_BOARD_HAUPPAUGE_HVR1210: 916 i2c_bus = &dev->i2c_bus[0]; 917 fe0->dvb.frontend = dvb_attach(tda10048_attach, 918 &hauppauge_hvr1210_config, 919 &i2c_bus->i2c_adap); 920 if (fe0->dvb.frontend != NULL) { 921 dvb_attach(tda18271_attach, fe0->dvb.frontend, 922 0x60, &dev->i2c_bus[1].i2c_adap, 923 &hauppauge_hvr1210_tuner_config); 924 } 925 break; 926 case CX23885_BOARD_HAUPPAUGE_HVR1400: 927 i2c_bus = &dev->i2c_bus[0]; 928 fe0->dvb.frontend = dvb_attach(dib7000p_attach, 929 &i2c_bus->i2c_adap, 930 0x12, &hauppauge_hvr1400_dib7000_config); 931 if (fe0->dvb.frontend != NULL) { 932 struct dvb_frontend *fe; 933 struct xc2028_config cfg = { 934 .i2c_adap = &dev->i2c_bus[1].i2c_adap, 935 .i2c_addr = 0x64, 936 }; 937 static struct xc2028_ctrl ctl = { 938 .fname = XC3028L_DEFAULT_FIRMWARE, 939 .max_len = 64, 940 .demod = XC3028_FE_DIBCOM52, 941 /* This is true for all demods with 942 v36 firmware? */ 943 .type = XC2028_D2633, 944 }; 945 946 fe = dvb_attach(xc2028_attach, 947 fe0->dvb.frontend, &cfg); 948 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL) 949 fe->ops.tuner_ops.set_config(fe, &ctl); 950 } 951 break; 952 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP: 953 i2c_bus = &dev->i2c_bus[port->nr - 1]; 954 955 fe0->dvb.frontend = dvb_attach(s5h1409_attach, 956 &dvico_s5h1409_config, 957 &i2c_bus->i2c_adap); 958 if (fe0->dvb.frontend == NULL) 959 fe0->dvb.frontend = dvb_attach(s5h1411_attach, 960 &dvico_s5h1411_config, 961 &i2c_bus->i2c_adap); 962 if (fe0->dvb.frontend != NULL) 963 dvb_attach(xc5000_attach, fe0->dvb.frontend, 964 &i2c_bus->i2c_adap, 965 &dvico_xc5000_tunerconfig); 966 break; 967 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: { 968 i2c_bus = &dev->i2c_bus[port->nr - 1]; 969 970 fe0->dvb.frontend = dvb_attach(zl10353_attach, 971 &dvico_fusionhdtv_xc3028, 972 &i2c_bus->i2c_adap); 973 if (fe0->dvb.frontend != NULL) { 974 struct dvb_frontend *fe; 975 struct xc2028_config cfg = { 976 .i2c_adap = &i2c_bus->i2c_adap, 977 .i2c_addr = 0x61, 978 }; 979 static struct xc2028_ctrl ctl = { 980 .fname = XC2028_DEFAULT_FIRMWARE, 981 .max_len = 64, 982 .demod = XC3028_FE_ZARLINK456, 983 }; 984 985 fe = dvb_attach(xc2028_attach, fe0->dvb.frontend, 986 &cfg); 987 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL) 988 fe->ops.tuner_ops.set_config(fe, &ctl); 989 } 990 break; 991 } 992 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H: 993 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F: 994 case CX23885_BOARD_COMPRO_VIDEOMATE_E800: 995 i2c_bus = &dev->i2c_bus[0]; 996 997 fe0->dvb.frontend = dvb_attach(zl10353_attach, 998 &dvico_fusionhdtv_xc3028, 999 &i2c_bus->i2c_adap); 1000 if (fe0->dvb.frontend != NULL) { 1001 struct dvb_frontend *fe; 1002 struct xc2028_config cfg = { 1003 .i2c_adap = &dev->i2c_bus[1].i2c_adap, 1004 .i2c_addr = 0x61, 1005 }; 1006 static struct xc2028_ctrl ctl = { 1007 .fname = XC2028_DEFAULT_FIRMWARE, 1008 .max_len = 64, 1009 .demod = XC3028_FE_ZARLINK456, 1010 }; 1011 1012 fe = dvb_attach(xc2028_attach, fe0->dvb.frontend, 1013 &cfg); 1014 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL) 1015 fe->ops.tuner_ops.set_config(fe, &ctl); 1016 } 1017 break; 1018 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000: 1019 i2c_bus = &dev->i2c_bus[0]; 1020 1021 fe0->dvb.frontend = dvb_attach(zl10353_attach, 1022 &dvico_fusionhdtv_xc3028, 1023 &i2c_bus->i2c_adap); 1024 if (fe0->dvb.frontend != NULL) { 1025 struct dvb_frontend *fe; 1026 struct xc4000_config cfg = { 1027 .i2c_address = 0x61, 1028 .default_pm = 0, 1029 .dvb_amplitude = 134, 1030 .set_smoothedcvbs = 1, 1031 .if_khz = 4560 1032 }; 1033 1034 fe = dvb_attach(xc4000_attach, fe0->dvb.frontend, 1035 &dev->i2c_bus[1].i2c_adap, &cfg); 1036 if (!fe) { 1037 printk(KERN_ERR "%s/2: xc4000 attach failed\n", 1038 dev->name); 1039 goto frontend_detach; 1040 } 1041 } 1042 break; 1043 case CX23885_BOARD_TBS_6920: 1044 i2c_bus = &dev->i2c_bus[1]; 1045 1046 fe0->dvb.frontend = dvb_attach(cx24116_attach, 1047 &tbs_cx24116_config, 1048 &i2c_bus->i2c_adap); 1049 if (fe0->dvb.frontend != NULL) 1050 fe0->dvb.frontend->ops.set_voltage = f300_set_voltage; 1051 1052 break; 1053 case CX23885_BOARD_TBS_6980: 1054 case CX23885_BOARD_TBS_6981: 1055 i2c_bus = &dev->i2c_bus[1]; 1056 1057 switch (port->nr) { 1058 /* PORT B */ 1059 case 1: 1060 fe0->dvb.frontend = dvb_attach(cx24117_attach, 1061 &tbs_cx24117_config, 1062 &i2c_bus->i2c_adap); 1063 break; 1064 /* PORT C */ 1065 case 2: 1066 fe0->dvb.frontend = dvb_attach(cx24117_attach, 1067 &tbs_cx24117_config, 1068 &i2c_bus->i2c_adap); 1069 break; 1070 } 1071 break; 1072 case CX23885_BOARD_TEVII_S470: 1073 i2c_bus = &dev->i2c_bus[1]; 1074 1075 fe0->dvb.frontend = dvb_attach(ds3000_attach, 1076 &tevii_ds3000_config, 1077 &i2c_bus->i2c_adap); 1078 if (fe0->dvb.frontend != NULL) { 1079 dvb_attach(ts2020_attach, fe0->dvb.frontend, 1080 &tevii_ts2020_config, &i2c_bus->i2c_adap); 1081 fe0->dvb.frontend->ops.set_voltage = f300_set_voltage; 1082 } 1083 1084 break; 1085 case CX23885_BOARD_DVBWORLD_2005: 1086 i2c_bus = &dev->i2c_bus[1]; 1087 1088 fe0->dvb.frontend = dvb_attach(cx24116_attach, 1089 &dvbworld_cx24116_config, 1090 &i2c_bus->i2c_adap); 1091 break; 1092 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: 1093 i2c_bus = &dev->i2c_bus[0]; 1094 switch (port->nr) { 1095 /* port B */ 1096 case 1: 1097 fe0->dvb.frontend = dvb_attach(stv0900_attach, 1098 &netup_stv0900_config, 1099 &i2c_bus->i2c_adap, 0); 1100 if (fe0->dvb.frontend != NULL) { 1101 if (dvb_attach(stv6110_attach, 1102 fe0->dvb.frontend, 1103 &netup_stv6110_tunerconfig_a, 1104 &i2c_bus->i2c_adap)) { 1105 if (!dvb_attach(lnbh24_attach, 1106 fe0->dvb.frontend, 1107 &i2c_bus->i2c_adap, 1108 LNBH24_PCL | LNBH24_TTX, 1109 LNBH24_TEN, 0x09)) 1110 printk(KERN_ERR 1111 "No LNBH24 found!\n"); 1112 1113 } 1114 } 1115 break; 1116 /* port C */ 1117 case 2: 1118 fe0->dvb.frontend = dvb_attach(stv0900_attach, 1119 &netup_stv0900_config, 1120 &i2c_bus->i2c_adap, 1); 1121 if (fe0->dvb.frontend != NULL) { 1122 if (dvb_attach(stv6110_attach, 1123 fe0->dvb.frontend, 1124 &netup_stv6110_tunerconfig_b, 1125 &i2c_bus->i2c_adap)) { 1126 if (!dvb_attach(lnbh24_attach, 1127 fe0->dvb.frontend, 1128 &i2c_bus->i2c_adap, 1129 LNBH24_PCL | LNBH24_TTX, 1130 LNBH24_TEN, 0x0a)) 1131 printk(KERN_ERR 1132 "No LNBH24 found!\n"); 1133 1134 } 1135 } 1136 break; 1137 } 1138 break; 1139 case CX23885_BOARD_MYGICA_X8506: 1140 i2c_bus = &dev->i2c_bus[0]; 1141 i2c_bus2 = &dev->i2c_bus[1]; 1142 fe0->dvb.frontend = dvb_attach(lgs8gxx_attach, 1143 &mygica_x8506_lgs8gl5_config, 1144 &i2c_bus->i2c_adap); 1145 if (fe0->dvb.frontend != NULL) { 1146 dvb_attach(xc5000_attach, 1147 fe0->dvb.frontend, 1148 &i2c_bus2->i2c_adap, 1149 &mygica_x8506_xc5000_config); 1150 } 1151 cx23885_set_frontend_hook(port, fe0->dvb.frontend); 1152 break; 1153 case CX23885_BOARD_MYGICA_X8507: 1154 i2c_bus = &dev->i2c_bus[0]; 1155 i2c_bus2 = &dev->i2c_bus[1]; 1156 fe0->dvb.frontend = dvb_attach(mb86a20s_attach, 1157 &mygica_x8507_mb86a20s_config, 1158 &i2c_bus->i2c_adap); 1159 if (fe0->dvb.frontend != NULL) { 1160 dvb_attach(xc5000_attach, 1161 fe0->dvb.frontend, 1162 &i2c_bus2->i2c_adap, 1163 &mygica_x8507_xc5000_config); 1164 } 1165 cx23885_set_frontend_hook(port, fe0->dvb.frontend); 1166 break; 1167 case CX23885_BOARD_MAGICPRO_PROHDTVE2: 1168 i2c_bus = &dev->i2c_bus[0]; 1169 i2c_bus2 = &dev->i2c_bus[1]; 1170 fe0->dvb.frontend = dvb_attach(lgs8gxx_attach, 1171 &magicpro_prohdtve2_lgs8g75_config, 1172 &i2c_bus->i2c_adap); 1173 if (fe0->dvb.frontend != NULL) { 1174 dvb_attach(xc5000_attach, 1175 fe0->dvb.frontend, 1176 &i2c_bus2->i2c_adap, 1177 &magicpro_prohdtve2_xc5000_config); 1178 } 1179 cx23885_set_frontend_hook(port, fe0->dvb.frontend); 1180 break; 1181 case CX23885_BOARD_HAUPPAUGE_HVR1850: 1182 i2c_bus = &dev->i2c_bus[0]; 1183 fe0->dvb.frontend = dvb_attach(s5h1411_attach, 1184 &hcw_s5h1411_config, 1185 &i2c_bus->i2c_adap); 1186 if (fe0->dvb.frontend != NULL) 1187 dvb_attach(tda18271_attach, fe0->dvb.frontend, 1188 0x60, &dev->i2c_bus[0].i2c_adap, 1189 &hauppauge_tda18271_config); 1190 1191 tda18271_attach(&dev->ts1.analog_fe, 1192 0x60, &dev->i2c_bus[1].i2c_adap, 1193 &hauppauge_tda18271_config); 1194 1195 break; 1196 case CX23885_BOARD_HAUPPAUGE_HVR1290: 1197 i2c_bus = &dev->i2c_bus[0]; 1198 fe0->dvb.frontend = dvb_attach(s5h1411_attach, 1199 &hcw_s5h1411_config, 1200 &i2c_bus->i2c_adap); 1201 if (fe0->dvb.frontend != NULL) 1202 dvb_attach(tda18271_attach, fe0->dvb.frontend, 1203 0x60, &dev->i2c_bus[0].i2c_adap, 1204 &hauppauge_tda18271_config); 1205 break; 1206 case CX23885_BOARD_MYGICA_X8558PRO: 1207 switch (port->nr) { 1208 /* port B */ 1209 case 1: 1210 i2c_bus = &dev->i2c_bus[0]; 1211 fe0->dvb.frontend = dvb_attach(atbm8830_attach, 1212 &mygica_x8558pro_atbm8830_cfg1, 1213 &i2c_bus->i2c_adap); 1214 if (fe0->dvb.frontend != NULL) { 1215 dvb_attach(max2165_attach, 1216 fe0->dvb.frontend, 1217 &i2c_bus->i2c_adap, 1218 &mygic_x8558pro_max2165_cfg1); 1219 } 1220 break; 1221 /* port C */ 1222 case 2: 1223 i2c_bus = &dev->i2c_bus[1]; 1224 fe0->dvb.frontend = dvb_attach(atbm8830_attach, 1225 &mygica_x8558pro_atbm8830_cfg2, 1226 &i2c_bus->i2c_adap); 1227 if (fe0->dvb.frontend != NULL) { 1228 dvb_attach(max2165_attach, 1229 fe0->dvb.frontend, 1230 &i2c_bus->i2c_adap, 1231 &mygic_x8558pro_max2165_cfg2); 1232 } 1233 break; 1234 } 1235 break; 1236 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: 1237 i2c_bus = &dev->i2c_bus[0]; 1238 mfe_shared = 1;/* MFE */ 1239 port->frontends.gate = 0;/* not clear for me yet */ 1240 /* ports B, C */ 1241 /* MFE frontend 1 DVB-T */ 1242 fe0->dvb.frontend = dvb_attach(stv0367ter_attach, 1243 &netup_stv0367_config[port->nr - 1], 1244 &i2c_bus->i2c_adap); 1245 if (fe0->dvb.frontend != NULL) { 1246 if (NULL == dvb_attach(xc5000_attach, 1247 fe0->dvb.frontend, 1248 &i2c_bus->i2c_adap, 1249 &netup_xc5000_config[port->nr - 1])) 1250 goto frontend_detach; 1251 /* load xc5000 firmware */ 1252 fe0->dvb.frontend->ops.tuner_ops.init(fe0->dvb.frontend); 1253 } 1254 /* MFE frontend 2 */ 1255 fe1 = videobuf_dvb_get_frontend(&port->frontends, 2); 1256 if (fe1 == NULL) 1257 goto frontend_detach; 1258 /* DVB-C init */ 1259 fe1->dvb.frontend = dvb_attach(stv0367cab_attach, 1260 &netup_stv0367_config[port->nr - 1], 1261 &i2c_bus->i2c_adap); 1262 if (fe1->dvb.frontend != NULL) { 1263 fe1->dvb.frontend->id = 1; 1264 if (NULL == dvb_attach(xc5000_attach, 1265 fe1->dvb.frontend, 1266 &i2c_bus->i2c_adap, 1267 &netup_xc5000_config[port->nr - 1])) 1268 goto frontend_detach; 1269 } 1270 break; 1271 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL: 1272 i2c_bus = &dev->i2c_bus[0]; 1273 i2c_bus2 = &dev->i2c_bus[1]; 1274 1275 switch (port->nr) { 1276 /* port b */ 1277 case 1: 1278 fe0->dvb.frontend = dvb_attach(drxk_attach, 1279 &terratec_drxk_config[0], 1280 &i2c_bus->i2c_adap); 1281 if (fe0->dvb.frontend != NULL) { 1282 if (!dvb_attach(mt2063_attach, 1283 fe0->dvb.frontend, 1284 &terratec_mt2063_config[0], 1285 &i2c_bus2->i2c_adap)) 1286 goto frontend_detach; 1287 } 1288 break; 1289 /* port c */ 1290 case 2: 1291 fe0->dvb.frontend = dvb_attach(drxk_attach, 1292 &terratec_drxk_config[1], 1293 &i2c_bus->i2c_adap); 1294 if (fe0->dvb.frontend != NULL) { 1295 if (!dvb_attach(mt2063_attach, 1296 fe0->dvb.frontend, 1297 &terratec_mt2063_config[1], 1298 &i2c_bus2->i2c_adap)) 1299 goto frontend_detach; 1300 } 1301 break; 1302 } 1303 break; 1304 case CX23885_BOARD_TEVII_S471: 1305 i2c_bus = &dev->i2c_bus[1]; 1306 1307 fe0->dvb.frontend = dvb_attach(ds3000_attach, 1308 &tevii_ds3000_config, 1309 &i2c_bus->i2c_adap); 1310 if (fe0->dvb.frontend != NULL) { 1311 dvb_attach(ts2020_attach, fe0->dvb.frontend, 1312 &tevii_ts2020_config, &i2c_bus->i2c_adap); 1313 } 1314 break; 1315 case CX23885_BOARD_PROF_8000: 1316 i2c_bus = &dev->i2c_bus[0]; 1317 1318 fe0->dvb.frontend = dvb_attach(stv090x_attach, 1319 &prof_8000_stv090x_config, 1320 &i2c_bus->i2c_adap, 1321 STV090x_DEMODULATOR_0); 1322 if (fe0->dvb.frontend != NULL) { 1323 if (!dvb_attach(stb6100_attach, 1324 fe0->dvb.frontend, 1325 &prof_8000_stb6100_config, 1326 &i2c_bus->i2c_adap)) 1327 goto frontend_detach; 1328 1329 fe0->dvb.frontend->ops.set_voltage = p8000_set_voltage; 1330 } 1331 break; 1332 case CX23885_BOARD_HAUPPAUGE_HVR4400: 1333 i2c_bus = &dev->i2c_bus[0]; 1334 fe0->dvb.frontend = dvb_attach(tda10071_attach, 1335 &hauppauge_tda10071_config, 1336 &i2c_bus->i2c_adap); 1337 if (fe0->dvb.frontend != NULL) { 1338 dvb_attach(a8293_attach, fe0->dvb.frontend, 1339 &i2c_bus->i2c_adap, 1340 &hauppauge_a8293_config); 1341 } 1342 break; 1343 default: 1344 printk(KERN_INFO "%s: The frontend of your DVB/ATSC card " 1345 " isn't supported yet\n", 1346 dev->name); 1347 break; 1348 } 1349 1350 if ((NULL == fe0->dvb.frontend) || (fe1 && NULL == fe1->dvb.frontend)) { 1351 printk(KERN_ERR "%s: frontend initialization failed\n", 1352 dev->name); 1353 goto frontend_detach; 1354 } 1355 1356 /* define general-purpose callback pointer */ 1357 fe0->dvb.frontend->callback = cx23885_tuner_callback; 1358 if (fe1) 1359 fe1->dvb.frontend->callback = cx23885_tuner_callback; 1360 #if 0 1361 /* Ensure all frontends negotiate bus access */ 1362 fe0->dvb.frontend->ops.ts_bus_ctrl = cx23885_dvb_bus_ctrl; 1363 if (fe1) 1364 fe1->dvb.frontend->ops.ts_bus_ctrl = cx23885_dvb_bus_ctrl; 1365 #endif 1366 1367 /* Put the analog decoder in standby to keep it quiet */ 1368 call_all(dev, core, s_power, 0); 1369 1370 if (fe0->dvb.frontend->ops.analog_ops.standby) 1371 fe0->dvb.frontend->ops.analog_ops.standby(fe0->dvb.frontend); 1372 1373 /* register everything */ 1374 ret = videobuf_dvb_register_bus(&port->frontends, THIS_MODULE, port, 1375 &dev->pci->dev, adapter_nr, mfe_shared); 1376 if (ret) 1377 goto frontend_detach; 1378 1379 /* init CI & MAC */ 1380 switch (dev->board) { 1381 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: { 1382 static struct netup_card_info cinfo; 1383 1384 netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo); 1385 memcpy(port->frontends.adapter.proposed_mac, 1386 cinfo.port[port->nr - 1].mac, 6); 1387 printk(KERN_INFO "NetUP Dual DVB-S2 CI card port%d MAC=%pM\n", 1388 port->nr, port->frontends.adapter.proposed_mac); 1389 1390 netup_ci_init(port); 1391 break; 1392 } 1393 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: { 1394 struct altera_ci_config netup_ci_cfg = { 1395 .dev = dev,/* magic number to identify*/ 1396 .adapter = &port->frontends.adapter,/* for CI */ 1397 .demux = &fe0->dvb.demux,/* for hw pid filter */ 1398 .fpga_rw = netup_altera_fpga_rw, 1399 }; 1400 1401 altera_ci_init(&netup_ci_cfg, port->nr); 1402 break; 1403 } 1404 case CX23885_BOARD_TEVII_S470: { 1405 u8 eeprom[256]; /* 24C02 i2c eeprom */ 1406 1407 if (port->nr != 1) 1408 break; 1409 1410 /* Read entire EEPROM */ 1411 dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1; 1412 tveeprom_read(&dev->i2c_bus[0].i2c_client, eeprom, sizeof(eeprom)); 1413 printk(KERN_INFO "TeVii S470 MAC= %pM\n", eeprom + 0xa0); 1414 memcpy(port->frontends.adapter.proposed_mac, eeprom + 0xa0, 6); 1415 break; 1416 } 1417 } 1418 1419 return ret; 1420 1421 frontend_detach: 1422 port->gate_ctrl = NULL; 1423 videobuf_dvb_dealloc_frontends(&port->frontends); 1424 return -EINVAL; 1425 } 1426 1427 int cx23885_dvb_register(struct cx23885_tsport *port) 1428 { 1429 1430 struct videobuf_dvb_frontend *fe0; 1431 struct cx23885_dev *dev = port->dev; 1432 int err, i; 1433 1434 /* Here we need to allocate the correct number of frontends, 1435 * as reflected in the cards struct. The reality is that currently 1436 * no cx23885 boards support this - yet. But, if we don't modify this 1437 * code then the second frontend would never be allocated (later) 1438 * and fail with error before the attach in dvb_register(). 1439 * Without these changes we risk an OOPS later. The changes here 1440 * are for safety, and should provide a good foundation for the 1441 * future addition of any multi-frontend cx23885 based boards. 1442 */ 1443 printk(KERN_INFO "%s() allocating %d frontend(s)\n", __func__, 1444 port->num_frontends); 1445 1446 for (i = 1; i <= port->num_frontends; i++) { 1447 if (videobuf_dvb_alloc_frontend( 1448 &port->frontends, i) == NULL) { 1449 printk(KERN_ERR "%s() failed to alloc\n", __func__); 1450 return -ENOMEM; 1451 } 1452 1453 fe0 = videobuf_dvb_get_frontend(&port->frontends, i); 1454 if (!fe0) 1455 err = -EINVAL; 1456 1457 dprintk(1, "%s\n", __func__); 1458 dprintk(1, " ->probed by Card=%d Name=%s, PCI %02x:%02x\n", 1459 dev->board, 1460 dev->name, 1461 dev->pci_bus, 1462 dev->pci_slot); 1463 1464 err = -ENODEV; 1465 1466 /* dvb stuff */ 1467 /* We have to init the queue for each frontend on a port. */ 1468 printk(KERN_INFO "%s: cx23885 based dvb card\n", dev->name); 1469 videobuf_queue_sg_init(&fe0->dvb.dvbq, &dvb_qops, 1470 &dev->pci->dev, &port->slock, 1471 V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_TOP, 1472 sizeof(struct cx23885_buffer), port, NULL); 1473 } 1474 err = dvb_register(port); 1475 if (err != 0) 1476 printk(KERN_ERR "%s() dvb_register failed err = %d\n", 1477 __func__, err); 1478 1479 return err; 1480 } 1481 1482 int cx23885_dvb_unregister(struct cx23885_tsport *port) 1483 { 1484 struct videobuf_dvb_frontend *fe0; 1485 1486 /* FIXME: in an error condition where the we have 1487 * an expected number of frontends (attach problem) 1488 * then this might not clean up correctly, if 1 1489 * is invalid. 1490 * This comment only applies to future boards IF they 1491 * implement MFE support. 1492 */ 1493 fe0 = videobuf_dvb_get_frontend(&port->frontends, 1); 1494 if (fe0 && fe0->dvb.frontend) 1495 videobuf_dvb_unregister_bus(&port->frontends); 1496 1497 switch (port->dev->board) { 1498 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: 1499 netup_ci_exit(port); 1500 break; 1501 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: 1502 altera_ci_release(port->dev, port->nr); 1503 break; 1504 } 1505 1506 port->gate_ctrl = NULL; 1507 1508 return 0; 1509 } 1510 1511