1 /* 2 * Driver for the Conexant CX23885 PCIe bridge 3 * 4 * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * 15 * GNU General Public License for more details. 16 */ 17 18 #include <linux/init.h> 19 #include <linux/module.h> 20 #include <linux/pci.h> 21 #include <linux/delay.h> 22 #include <media/cx25840.h> 23 #include <linux/firmware.h> 24 #include <misc/altera.h> 25 26 #include "cx23885.h" 27 #include "tuner-xc2028.h" 28 #include "netup-eeprom.h" 29 #include "netup-init.h" 30 #include "altera-ci.h" 31 #include "xc4000.h" 32 #include "xc5000.h" 33 #include "cx23888-ir.h" 34 35 static unsigned int netup_card_rev = 4; 36 module_param(netup_card_rev, int, 0644); 37 MODULE_PARM_DESC(netup_card_rev, 38 "NetUP Dual DVB-T/C CI card revision"); 39 static unsigned int enable_885_ir; 40 module_param(enable_885_ir, int, 0644); 41 MODULE_PARM_DESC(enable_885_ir, 42 "Enable integrated IR controller for supported\n" 43 "\t\t CX2388[57] boards that are wired for it:\n" 44 "\t\t\tHVR-1250 (reported safe)\n" 45 "\t\t\tTerraTec Cinergy T PCIe Dual (not well tested, appears to be safe)\n" 46 "\t\t\tTeVii S470 (reported unsafe)\n" 47 "\t\t This can cause an interrupt storm with some cards.\n" 48 "\t\t Default: 0 [Disabled]"); 49 50 /* ------------------------------------------------------------------ */ 51 /* board config info */ 52 53 struct cx23885_board cx23885_boards[] = { 54 [CX23885_BOARD_UNKNOWN] = { 55 .name = "UNKNOWN/GENERIC", 56 /* Ensure safe default for unknown boards */ 57 .clk_freq = 0, 58 .input = {{ 59 .type = CX23885_VMUX_COMPOSITE1, 60 .vmux = 0, 61 }, { 62 .type = CX23885_VMUX_COMPOSITE2, 63 .vmux = 1, 64 }, { 65 .type = CX23885_VMUX_COMPOSITE3, 66 .vmux = 2, 67 }, { 68 .type = CX23885_VMUX_COMPOSITE4, 69 .vmux = 3, 70 } }, 71 }, 72 [CX23885_BOARD_HAUPPAUGE_HVR1800lp] = { 73 .name = "Hauppauge WinTV-HVR1800lp", 74 .portc = CX23885_MPEG_DVB, 75 .input = {{ 76 .type = CX23885_VMUX_TELEVISION, 77 .vmux = 0, 78 .gpio0 = 0xff00, 79 }, { 80 .type = CX23885_VMUX_DEBUG, 81 .vmux = 0, 82 .gpio0 = 0xff01, 83 }, { 84 .type = CX23885_VMUX_COMPOSITE1, 85 .vmux = 1, 86 .gpio0 = 0xff02, 87 }, { 88 .type = CX23885_VMUX_SVIDEO, 89 .vmux = 2, 90 .gpio0 = 0xff02, 91 } }, 92 }, 93 [CX23885_BOARD_HAUPPAUGE_HVR1800] = { 94 .name = "Hauppauge WinTV-HVR1800", 95 .porta = CX23885_ANALOG_VIDEO, 96 .portb = CX23885_MPEG_ENCODER, 97 .portc = CX23885_MPEG_DVB, 98 .tuner_type = TUNER_PHILIPS_TDA8290, 99 .tuner_addr = 0x42, /* 0x84 >> 1 */ 100 .tuner_bus = 1, 101 .input = {{ 102 .type = CX23885_VMUX_TELEVISION, 103 .vmux = CX25840_VIN7_CH3 | 104 CX25840_VIN5_CH2 | 105 CX25840_VIN2_CH1, 106 .amux = CX25840_AUDIO8, 107 .gpio0 = 0, 108 }, { 109 .type = CX23885_VMUX_COMPOSITE1, 110 .vmux = CX25840_VIN7_CH3 | 111 CX25840_VIN4_CH2 | 112 CX25840_VIN6_CH1, 113 .amux = CX25840_AUDIO7, 114 .gpio0 = 0, 115 }, { 116 .type = CX23885_VMUX_SVIDEO, 117 .vmux = CX25840_VIN7_CH3 | 118 CX25840_VIN4_CH2 | 119 CX25840_VIN8_CH1 | 120 CX25840_SVIDEO_ON, 121 .amux = CX25840_AUDIO7, 122 .gpio0 = 0, 123 } }, 124 }, 125 [CX23885_BOARD_HAUPPAUGE_HVR1250] = { 126 .name = "Hauppauge WinTV-HVR1250", 127 .porta = CX23885_ANALOG_VIDEO, 128 .portc = CX23885_MPEG_DVB, 129 #ifdef MT2131_NO_ANALOG_SUPPORT_YET 130 .tuner_type = TUNER_PHILIPS_TDA8290, 131 .tuner_addr = 0x42, /* 0x84 >> 1 */ 132 .tuner_bus = 1, 133 #endif 134 .force_bff = 1, 135 .input = {{ 136 #ifdef MT2131_NO_ANALOG_SUPPORT_YET 137 .type = CX23885_VMUX_TELEVISION, 138 .vmux = CX25840_VIN7_CH3 | 139 CX25840_VIN5_CH2 | 140 CX25840_VIN2_CH1, 141 .amux = CX25840_AUDIO8, 142 .gpio0 = 0xff00, 143 }, { 144 #endif 145 .type = CX23885_VMUX_COMPOSITE1, 146 .vmux = CX25840_VIN7_CH3 | 147 CX25840_VIN4_CH2 | 148 CX25840_VIN6_CH1, 149 .amux = CX25840_AUDIO7, 150 .gpio0 = 0xff02, 151 }, { 152 .type = CX23885_VMUX_SVIDEO, 153 .vmux = CX25840_VIN7_CH3 | 154 CX25840_VIN4_CH2 | 155 CX25840_VIN8_CH1 | 156 CX25840_SVIDEO_ON, 157 .amux = CX25840_AUDIO7, 158 .gpio0 = 0xff02, 159 } }, 160 }, 161 [CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP] = { 162 .name = "DViCO FusionHDTV5 Express", 163 .portb = CX23885_MPEG_DVB, 164 }, 165 [CX23885_BOARD_HAUPPAUGE_HVR1500Q] = { 166 .name = "Hauppauge WinTV-HVR1500Q", 167 .portc = CX23885_MPEG_DVB, 168 }, 169 [CX23885_BOARD_HAUPPAUGE_HVR1500] = { 170 .name = "Hauppauge WinTV-HVR1500", 171 .porta = CX23885_ANALOG_VIDEO, 172 .portc = CX23885_MPEG_DVB, 173 .tuner_type = TUNER_XC2028, 174 .tuner_addr = 0x61, /* 0xc2 >> 1 */ 175 .input = {{ 176 .type = CX23885_VMUX_TELEVISION, 177 .vmux = CX25840_VIN7_CH3 | 178 CX25840_VIN5_CH2 | 179 CX25840_VIN2_CH1, 180 .gpio0 = 0, 181 }, { 182 .type = CX23885_VMUX_COMPOSITE1, 183 .vmux = CX25840_VIN7_CH3 | 184 CX25840_VIN4_CH2 | 185 CX25840_VIN6_CH1, 186 .gpio0 = 0, 187 }, { 188 .type = CX23885_VMUX_SVIDEO, 189 .vmux = CX25840_VIN7_CH3 | 190 CX25840_VIN4_CH2 | 191 CX25840_VIN8_CH1 | 192 CX25840_SVIDEO_ON, 193 .gpio0 = 0, 194 } }, 195 }, 196 [CX23885_BOARD_HAUPPAUGE_HVR1200] = { 197 .name = "Hauppauge WinTV-HVR1200", 198 .portc = CX23885_MPEG_DVB, 199 }, 200 [CX23885_BOARD_HAUPPAUGE_HVR1700] = { 201 .name = "Hauppauge WinTV-HVR1700", 202 .portc = CX23885_MPEG_DVB, 203 }, 204 [CX23885_BOARD_HAUPPAUGE_HVR1400] = { 205 .name = "Hauppauge WinTV-HVR1400", 206 .portc = CX23885_MPEG_DVB, 207 }, 208 [CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP] = { 209 .name = "DViCO FusionHDTV7 Dual Express", 210 .portb = CX23885_MPEG_DVB, 211 .portc = CX23885_MPEG_DVB, 212 }, 213 [CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP] = { 214 .name = "DViCO FusionHDTV DVB-T Dual Express", 215 .portb = CX23885_MPEG_DVB, 216 .portc = CX23885_MPEG_DVB, 217 }, 218 [CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H] = { 219 .name = "Leadtek Winfast PxDVR3200 H", 220 .portc = CX23885_MPEG_DVB, 221 }, 222 [CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200] = { 223 .name = "Leadtek Winfast PxPVR2200", 224 .porta = CX23885_ANALOG_VIDEO, 225 .tuner_type = TUNER_XC2028, 226 .tuner_addr = 0x61, 227 .tuner_bus = 1, 228 .input = {{ 229 .type = CX23885_VMUX_TELEVISION, 230 .vmux = CX25840_VIN2_CH1 | 231 CX25840_VIN5_CH2, 232 .amux = CX25840_AUDIO8, 233 .gpio0 = 0x704040, 234 }, { 235 .type = CX23885_VMUX_COMPOSITE1, 236 .vmux = CX25840_COMPOSITE1, 237 .amux = CX25840_AUDIO7, 238 .gpio0 = 0x704040, 239 }, { 240 .type = CX23885_VMUX_SVIDEO, 241 .vmux = CX25840_SVIDEO_LUMA3 | 242 CX25840_SVIDEO_CHROMA4, 243 .amux = CX25840_AUDIO7, 244 .gpio0 = 0x704040, 245 }, { 246 .type = CX23885_VMUX_COMPONENT, 247 .vmux = CX25840_VIN7_CH1 | 248 CX25840_VIN6_CH2 | 249 CX25840_VIN8_CH3 | 250 CX25840_COMPONENT_ON, 251 .amux = CX25840_AUDIO7, 252 .gpio0 = 0x704040, 253 } }, 254 }, 255 [CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000] = { 256 .name = "Leadtek Winfast PxDVR3200 H XC4000", 257 .porta = CX23885_ANALOG_VIDEO, 258 .portc = CX23885_MPEG_DVB, 259 .tuner_type = TUNER_XC4000, 260 .tuner_addr = 0x61, 261 .radio_type = UNSET, 262 .radio_addr = ADDR_UNSET, 263 .input = {{ 264 .type = CX23885_VMUX_TELEVISION, 265 .vmux = CX25840_VIN2_CH1 | 266 CX25840_VIN5_CH2 | 267 CX25840_NONE0_CH3, 268 }, { 269 .type = CX23885_VMUX_COMPOSITE1, 270 .vmux = CX25840_COMPOSITE1, 271 }, { 272 .type = CX23885_VMUX_SVIDEO, 273 .vmux = CX25840_SVIDEO_LUMA3 | 274 CX25840_SVIDEO_CHROMA4, 275 }, { 276 .type = CX23885_VMUX_COMPONENT, 277 .vmux = CX25840_VIN7_CH1 | 278 CX25840_VIN6_CH2 | 279 CX25840_VIN8_CH3 | 280 CX25840_COMPONENT_ON, 281 } }, 282 }, 283 [CX23885_BOARD_COMPRO_VIDEOMATE_E650F] = { 284 .name = "Compro VideoMate E650F", 285 .portc = CX23885_MPEG_DVB, 286 }, 287 [CX23885_BOARD_TBS_6920] = { 288 .name = "TurboSight TBS 6920", 289 .portb = CX23885_MPEG_DVB, 290 }, 291 [CX23885_BOARD_TBS_6980] = { 292 .name = "TurboSight TBS 6980", 293 .portb = CX23885_MPEG_DVB, 294 .portc = CX23885_MPEG_DVB, 295 }, 296 [CX23885_BOARD_TBS_6981] = { 297 .name = "TurboSight TBS 6981", 298 .portb = CX23885_MPEG_DVB, 299 .portc = CX23885_MPEG_DVB, 300 }, 301 [CX23885_BOARD_TEVII_S470] = { 302 .name = "TeVii S470", 303 .portb = CX23885_MPEG_DVB, 304 }, 305 [CX23885_BOARD_DVBWORLD_2005] = { 306 .name = "DVBWorld DVB-S2 2005", 307 .portb = CX23885_MPEG_DVB, 308 }, 309 [CX23885_BOARD_NETUP_DUAL_DVBS2_CI] = { 310 .ci_type = 1, 311 .name = "NetUP Dual DVB-S2 CI", 312 .portb = CX23885_MPEG_DVB, 313 .portc = CX23885_MPEG_DVB, 314 }, 315 [CX23885_BOARD_HAUPPAUGE_HVR1270] = { 316 .name = "Hauppauge WinTV-HVR1270", 317 .portc = CX23885_MPEG_DVB, 318 }, 319 [CX23885_BOARD_HAUPPAUGE_HVR1275] = { 320 .name = "Hauppauge WinTV-HVR1275", 321 .portc = CX23885_MPEG_DVB, 322 }, 323 [CX23885_BOARD_HAUPPAUGE_HVR1255] = { 324 .name = "Hauppauge WinTV-HVR1255", 325 .porta = CX23885_ANALOG_VIDEO, 326 .portc = CX23885_MPEG_DVB, 327 .tuner_type = TUNER_ABSENT, 328 .tuner_addr = 0x42, /* 0x84 >> 1 */ 329 .force_bff = 1, 330 .input = {{ 331 .type = CX23885_VMUX_TELEVISION, 332 .vmux = CX25840_VIN7_CH3 | 333 CX25840_VIN5_CH2 | 334 CX25840_VIN2_CH1 | 335 CX25840_DIF_ON, 336 .amux = CX25840_AUDIO8, 337 }, { 338 .type = CX23885_VMUX_COMPOSITE1, 339 .vmux = CX25840_VIN7_CH3 | 340 CX25840_VIN4_CH2 | 341 CX25840_VIN6_CH1, 342 .amux = CX25840_AUDIO7, 343 }, { 344 .type = CX23885_VMUX_SVIDEO, 345 .vmux = CX25840_VIN7_CH3 | 346 CX25840_VIN4_CH2 | 347 CX25840_VIN8_CH1 | 348 CX25840_SVIDEO_ON, 349 .amux = CX25840_AUDIO7, 350 } }, 351 }, 352 [CX23885_BOARD_HAUPPAUGE_HVR1255_22111] = { 353 .name = "Hauppauge WinTV-HVR1255", 354 .porta = CX23885_ANALOG_VIDEO, 355 .portc = CX23885_MPEG_DVB, 356 .tuner_type = TUNER_ABSENT, 357 .tuner_addr = 0x42, /* 0x84 >> 1 */ 358 .force_bff = 1, 359 .input = {{ 360 .type = CX23885_VMUX_TELEVISION, 361 .vmux = CX25840_VIN7_CH3 | 362 CX25840_VIN5_CH2 | 363 CX25840_VIN2_CH1 | 364 CX25840_DIF_ON, 365 .amux = CX25840_AUDIO8, 366 }, { 367 .type = CX23885_VMUX_SVIDEO, 368 .vmux = CX25840_VIN7_CH3 | 369 CX25840_VIN4_CH2 | 370 CX25840_VIN8_CH1 | 371 CX25840_SVIDEO_ON, 372 .amux = CX25840_AUDIO7, 373 } }, 374 }, 375 [CX23885_BOARD_HAUPPAUGE_HVR1210] = { 376 .name = "Hauppauge WinTV-HVR1210", 377 .portc = CX23885_MPEG_DVB, 378 }, 379 [CX23885_BOARD_MYGICA_X8506] = { 380 .name = "Mygica X8506 DMB-TH", 381 .tuner_type = TUNER_XC5000, 382 .tuner_addr = 0x61, 383 .tuner_bus = 1, 384 .porta = CX23885_ANALOG_VIDEO, 385 .portb = CX23885_MPEG_DVB, 386 .input = { 387 { 388 .type = CX23885_VMUX_TELEVISION, 389 .vmux = CX25840_COMPOSITE2, 390 }, 391 { 392 .type = CX23885_VMUX_COMPOSITE1, 393 .vmux = CX25840_COMPOSITE8, 394 }, 395 { 396 .type = CX23885_VMUX_SVIDEO, 397 .vmux = CX25840_SVIDEO_LUMA3 | 398 CX25840_SVIDEO_CHROMA4, 399 }, 400 { 401 .type = CX23885_VMUX_COMPONENT, 402 .vmux = CX25840_COMPONENT_ON | 403 CX25840_VIN1_CH1 | 404 CX25840_VIN6_CH2 | 405 CX25840_VIN7_CH3, 406 }, 407 }, 408 }, 409 [CX23885_BOARD_MAGICPRO_PROHDTVE2] = { 410 .name = "Magic-Pro ProHDTV Extreme 2", 411 .tuner_type = TUNER_XC5000, 412 .tuner_addr = 0x61, 413 .tuner_bus = 1, 414 .porta = CX23885_ANALOG_VIDEO, 415 .portb = CX23885_MPEG_DVB, 416 .input = { 417 { 418 .type = CX23885_VMUX_TELEVISION, 419 .vmux = CX25840_COMPOSITE2, 420 }, 421 { 422 .type = CX23885_VMUX_COMPOSITE1, 423 .vmux = CX25840_COMPOSITE8, 424 }, 425 { 426 .type = CX23885_VMUX_SVIDEO, 427 .vmux = CX25840_SVIDEO_LUMA3 | 428 CX25840_SVIDEO_CHROMA4, 429 }, 430 { 431 .type = CX23885_VMUX_COMPONENT, 432 .vmux = CX25840_COMPONENT_ON | 433 CX25840_VIN1_CH1 | 434 CX25840_VIN6_CH2 | 435 CX25840_VIN7_CH3, 436 }, 437 }, 438 }, 439 [CX23885_BOARD_HAUPPAUGE_HVR1850] = { 440 .name = "Hauppauge WinTV-HVR1850", 441 .porta = CX23885_ANALOG_VIDEO, 442 .portb = CX23885_MPEG_ENCODER, 443 .portc = CX23885_MPEG_DVB, 444 .tuner_type = TUNER_ABSENT, 445 .tuner_addr = 0x42, /* 0x84 >> 1 */ 446 .force_bff = 1, 447 .input = {{ 448 .type = CX23885_VMUX_TELEVISION, 449 .vmux = CX25840_VIN7_CH3 | 450 CX25840_VIN5_CH2 | 451 CX25840_VIN2_CH1 | 452 CX25840_DIF_ON, 453 .amux = CX25840_AUDIO8, 454 }, { 455 .type = CX23885_VMUX_COMPOSITE1, 456 .vmux = CX25840_VIN7_CH3 | 457 CX25840_VIN4_CH2 | 458 CX25840_VIN6_CH1, 459 .amux = CX25840_AUDIO7, 460 }, { 461 .type = CX23885_VMUX_SVIDEO, 462 .vmux = CX25840_VIN7_CH3 | 463 CX25840_VIN4_CH2 | 464 CX25840_VIN8_CH1 | 465 CX25840_SVIDEO_ON, 466 .amux = CX25840_AUDIO7, 467 } }, 468 }, 469 [CX23885_BOARD_COMPRO_VIDEOMATE_E800] = { 470 .name = "Compro VideoMate E800", 471 .portc = CX23885_MPEG_DVB, 472 }, 473 [CX23885_BOARD_HAUPPAUGE_HVR1290] = { 474 .name = "Hauppauge WinTV-HVR1290", 475 .portc = CX23885_MPEG_DVB, 476 }, 477 [CX23885_BOARD_MYGICA_X8558PRO] = { 478 .name = "Mygica X8558 PRO DMB-TH", 479 .portb = CX23885_MPEG_DVB, 480 .portc = CX23885_MPEG_DVB, 481 }, 482 [CX23885_BOARD_LEADTEK_WINFAST_PXTV1200] = { 483 .name = "LEADTEK WinFast PxTV1200", 484 .porta = CX23885_ANALOG_VIDEO, 485 .tuner_type = TUNER_XC2028, 486 .tuner_addr = 0x61, 487 .tuner_bus = 1, 488 .input = {{ 489 .type = CX23885_VMUX_TELEVISION, 490 .vmux = CX25840_VIN2_CH1 | 491 CX25840_VIN5_CH2 | 492 CX25840_NONE0_CH3, 493 }, { 494 .type = CX23885_VMUX_COMPOSITE1, 495 .vmux = CX25840_COMPOSITE1, 496 }, { 497 .type = CX23885_VMUX_SVIDEO, 498 .vmux = CX25840_SVIDEO_LUMA3 | 499 CX25840_SVIDEO_CHROMA4, 500 }, { 501 .type = CX23885_VMUX_COMPONENT, 502 .vmux = CX25840_VIN7_CH1 | 503 CX25840_VIN6_CH2 | 504 CX25840_VIN8_CH3 | 505 CX25840_COMPONENT_ON, 506 } }, 507 }, 508 [CX23885_BOARD_GOTVIEW_X5_3D_HYBRID] = { 509 .name = "GoTView X5 3D Hybrid", 510 .tuner_type = TUNER_XC5000, 511 .tuner_addr = 0x64, 512 .tuner_bus = 1, 513 .porta = CX23885_ANALOG_VIDEO, 514 .portb = CX23885_MPEG_DVB, 515 .input = {{ 516 .type = CX23885_VMUX_TELEVISION, 517 .vmux = CX25840_VIN2_CH1 | 518 CX25840_VIN5_CH2, 519 .gpio0 = 0x02, 520 }, { 521 .type = CX23885_VMUX_COMPOSITE1, 522 .vmux = CX23885_VMUX_COMPOSITE1, 523 }, { 524 .type = CX23885_VMUX_SVIDEO, 525 .vmux = CX25840_SVIDEO_LUMA3 | 526 CX25840_SVIDEO_CHROMA4, 527 } }, 528 }, 529 [CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF] = { 530 .ci_type = 2, 531 .name = "NetUP Dual DVB-T/C-CI RF", 532 .porta = CX23885_ANALOG_VIDEO, 533 .portb = CX23885_MPEG_DVB, 534 .portc = CX23885_MPEG_DVB, 535 .num_fds_portb = 2, 536 .num_fds_portc = 2, 537 .tuner_type = TUNER_XC5000, 538 .tuner_addr = 0x64, 539 .input = { { 540 .type = CX23885_VMUX_TELEVISION, 541 .vmux = CX25840_COMPOSITE1, 542 } }, 543 }, 544 [CX23885_BOARD_MPX885] = { 545 .name = "MPX-885", 546 .porta = CX23885_ANALOG_VIDEO, 547 .input = {{ 548 .type = CX23885_VMUX_COMPOSITE1, 549 .vmux = CX25840_COMPOSITE1, 550 .amux = CX25840_AUDIO6, 551 .gpio0 = 0, 552 }, { 553 .type = CX23885_VMUX_COMPOSITE2, 554 .vmux = CX25840_COMPOSITE2, 555 .amux = CX25840_AUDIO6, 556 .gpio0 = 0, 557 }, { 558 .type = CX23885_VMUX_COMPOSITE3, 559 .vmux = CX25840_COMPOSITE3, 560 .amux = CX25840_AUDIO7, 561 .gpio0 = 0, 562 }, { 563 .type = CX23885_VMUX_COMPOSITE4, 564 .vmux = CX25840_COMPOSITE4, 565 .amux = CX25840_AUDIO7, 566 .gpio0 = 0, 567 } }, 568 }, 569 [CX23885_BOARD_MYGICA_X8507] = { 570 .name = "Mygica X8502/X8507 ISDB-T", 571 .tuner_type = TUNER_XC5000, 572 .tuner_addr = 0x61, 573 .tuner_bus = 1, 574 .porta = CX23885_ANALOG_VIDEO, 575 .portb = CX23885_MPEG_DVB, 576 .input = { 577 { 578 .type = CX23885_VMUX_TELEVISION, 579 .vmux = CX25840_COMPOSITE2, 580 .amux = CX25840_AUDIO8, 581 }, 582 { 583 .type = CX23885_VMUX_COMPOSITE1, 584 .vmux = CX25840_COMPOSITE8, 585 .amux = CX25840_AUDIO7, 586 }, 587 { 588 .type = CX23885_VMUX_SVIDEO, 589 .vmux = CX25840_SVIDEO_LUMA3 | 590 CX25840_SVIDEO_CHROMA4, 591 .amux = CX25840_AUDIO7, 592 }, 593 { 594 .type = CX23885_VMUX_COMPONENT, 595 .vmux = CX25840_COMPONENT_ON | 596 CX25840_VIN1_CH1 | 597 CX25840_VIN6_CH2 | 598 CX25840_VIN7_CH3, 599 .amux = CX25840_AUDIO7, 600 }, 601 }, 602 }, 603 [CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL] = { 604 .name = "TerraTec Cinergy T PCIe Dual", 605 .portb = CX23885_MPEG_DVB, 606 .portc = CX23885_MPEG_DVB, 607 }, 608 [CX23885_BOARD_TEVII_S471] = { 609 .name = "TeVii S471", 610 .portb = CX23885_MPEG_DVB, 611 }, 612 [CX23885_BOARD_PROF_8000] = { 613 .name = "Prof Revolution DVB-S2 8000", 614 .portb = CX23885_MPEG_DVB, 615 }, 616 [CX23885_BOARD_HAUPPAUGE_HVR4400] = { 617 .name = "Hauppauge WinTV-HVR4400", 618 .porta = CX23885_ANALOG_VIDEO, 619 .portb = CX23885_MPEG_DVB, 620 .portc = CX23885_MPEG_DVB, 621 .tuner_type = TUNER_NXP_TDA18271, 622 .tuner_addr = 0x60, /* 0xc0 >> 1 */ 623 .tuner_bus = 1, 624 }, 625 [CX23885_BOARD_AVERMEDIA_HC81R] = { 626 .name = "AVerTV Hybrid Express Slim HC81R", 627 .tuner_type = TUNER_XC2028, 628 .tuner_addr = 0x61, /* 0xc2 >> 1 */ 629 .tuner_bus = 1, 630 .porta = CX23885_ANALOG_VIDEO, 631 .input = {{ 632 .type = CX23885_VMUX_TELEVISION, 633 .vmux = CX25840_VIN2_CH1 | 634 CX25840_VIN5_CH2 | 635 CX25840_NONE0_CH3 | 636 CX25840_NONE1_CH3, 637 .amux = CX25840_AUDIO8, 638 }, { 639 .type = CX23885_VMUX_SVIDEO, 640 .vmux = CX25840_VIN8_CH1 | 641 CX25840_NONE_CH2 | 642 CX25840_VIN7_CH3 | 643 CX25840_SVIDEO_ON, 644 .amux = CX25840_AUDIO6, 645 }, { 646 .type = CX23885_VMUX_COMPONENT, 647 .vmux = CX25840_VIN1_CH1 | 648 CX25840_NONE_CH2 | 649 CX25840_NONE0_CH3 | 650 CX25840_NONE1_CH3, 651 .amux = CX25840_AUDIO6, 652 } }, 653 }, 654 [CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2] = { 655 .name = "DViCO FusionHDTV DVB-T Dual Express2", 656 .portb = CX23885_MPEG_DVB, 657 .portc = CX23885_MPEG_DVB, 658 }, 659 [CX23885_BOARD_HAUPPAUGE_IMPACTVCBE] = { 660 .name = "Hauppauge ImpactVCB-e", 661 .tuner_type = TUNER_ABSENT, 662 .porta = CX23885_ANALOG_VIDEO, 663 .input = {{ 664 .type = CX23885_VMUX_COMPOSITE1, 665 .vmux = CX25840_VIN7_CH3 | 666 CX25840_VIN4_CH2 | 667 CX25840_VIN6_CH1, 668 .amux = CX25840_AUDIO7, 669 }, { 670 .type = CX23885_VMUX_SVIDEO, 671 .vmux = CX25840_VIN7_CH3 | 672 CX25840_VIN4_CH2 | 673 CX25840_VIN8_CH1 | 674 CX25840_SVIDEO_ON, 675 .amux = CX25840_AUDIO7, 676 } }, 677 }, 678 [CX23885_BOARD_DVBSKY_T9580] = { 679 .name = "DVBSky T9580", 680 .portb = CX23885_MPEG_DVB, 681 .portc = CX23885_MPEG_DVB, 682 }, 683 [CX23885_BOARD_DVBSKY_T980C] = { 684 .name = "DVBSky T980C", 685 .portb = CX23885_MPEG_DVB, 686 }, 687 [CX23885_BOARD_DVBSKY_S950C] = { 688 .name = "DVBSky S950C", 689 .portb = CX23885_MPEG_DVB, 690 }, 691 [CX23885_BOARD_TT_CT2_4500_CI] = { 692 .name = "Technotrend TT-budget CT2-4500 CI", 693 .portb = CX23885_MPEG_DVB, 694 }, 695 [CX23885_BOARD_DVBSKY_S950] = { 696 .name = "DVBSky S950", 697 .portb = CX23885_MPEG_DVB, 698 }, 699 [CX23885_BOARD_DVBSKY_S952] = { 700 .name = "DVBSky S952", 701 .portb = CX23885_MPEG_DVB, 702 .portc = CX23885_MPEG_DVB, 703 }, 704 [CX23885_BOARD_DVBSKY_T982] = { 705 .name = "DVBSky T982", 706 .portb = CX23885_MPEG_DVB, 707 .portc = CX23885_MPEG_DVB, 708 }, 709 }; 710 const unsigned int cx23885_bcount = ARRAY_SIZE(cx23885_boards); 711 712 /* ------------------------------------------------------------------ */ 713 /* PCI subsystem IDs */ 714 715 struct cx23885_subid cx23885_subids[] = { 716 { 717 .subvendor = 0x0070, 718 .subdevice = 0x3400, 719 .card = CX23885_BOARD_UNKNOWN, 720 }, { 721 .subvendor = 0x0070, 722 .subdevice = 0x7600, 723 .card = CX23885_BOARD_HAUPPAUGE_HVR1800lp, 724 }, { 725 .subvendor = 0x0070, 726 .subdevice = 0x7800, 727 .card = CX23885_BOARD_HAUPPAUGE_HVR1800, 728 }, { 729 .subvendor = 0x0070, 730 .subdevice = 0x7801, 731 .card = CX23885_BOARD_HAUPPAUGE_HVR1800, 732 }, { 733 .subvendor = 0x0070, 734 .subdevice = 0x7809, 735 .card = CX23885_BOARD_HAUPPAUGE_HVR1800, 736 }, { 737 .subvendor = 0x0070, 738 .subdevice = 0x7911, 739 .card = CX23885_BOARD_HAUPPAUGE_HVR1250, 740 }, { 741 .subvendor = 0x18ac, 742 .subdevice = 0xd500, 743 .card = CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP, 744 }, { 745 .subvendor = 0x0070, 746 .subdevice = 0x7790, 747 .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q, 748 }, { 749 .subvendor = 0x0070, 750 .subdevice = 0x7797, 751 .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q, 752 }, { 753 .subvendor = 0x0070, 754 .subdevice = 0x7710, 755 .card = CX23885_BOARD_HAUPPAUGE_HVR1500, 756 }, { 757 .subvendor = 0x0070, 758 .subdevice = 0x7717, 759 .card = CX23885_BOARD_HAUPPAUGE_HVR1500, 760 }, { 761 .subvendor = 0x0070, 762 .subdevice = 0x71d1, 763 .card = CX23885_BOARD_HAUPPAUGE_HVR1200, 764 }, { 765 .subvendor = 0x0070, 766 .subdevice = 0x71d3, 767 .card = CX23885_BOARD_HAUPPAUGE_HVR1200, 768 }, { 769 .subvendor = 0x0070, 770 .subdevice = 0x8101, 771 .card = CX23885_BOARD_HAUPPAUGE_HVR1700, 772 }, { 773 .subvendor = 0x0070, 774 .subdevice = 0x8010, 775 .card = CX23885_BOARD_HAUPPAUGE_HVR1400, 776 }, { 777 .subvendor = 0x18ac, 778 .subdevice = 0xd618, 779 .card = CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP, 780 }, { 781 .subvendor = 0x18ac, 782 .subdevice = 0xdb78, 783 .card = CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP, 784 }, { 785 .subvendor = 0x107d, 786 .subdevice = 0x6681, 787 .card = CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H, 788 }, { 789 .subvendor = 0x107d, 790 .subdevice = 0x6f21, 791 .card = CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200, 792 }, { 793 .subvendor = 0x107d, 794 .subdevice = 0x6f39, 795 .card = CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000, 796 }, { 797 .subvendor = 0x185b, 798 .subdevice = 0xe800, 799 .card = CX23885_BOARD_COMPRO_VIDEOMATE_E650F, 800 }, { 801 .subvendor = 0x6920, 802 .subdevice = 0x8888, 803 .card = CX23885_BOARD_TBS_6920, 804 }, { 805 .subvendor = 0x6980, 806 .subdevice = 0x8888, 807 .card = CX23885_BOARD_TBS_6980, 808 }, { 809 .subvendor = 0x6981, 810 .subdevice = 0x8888, 811 .card = CX23885_BOARD_TBS_6981, 812 }, { 813 .subvendor = 0xd470, 814 .subdevice = 0x9022, 815 .card = CX23885_BOARD_TEVII_S470, 816 }, { 817 .subvendor = 0x0001, 818 .subdevice = 0x2005, 819 .card = CX23885_BOARD_DVBWORLD_2005, 820 }, { 821 .subvendor = 0x1b55, 822 .subdevice = 0x2a2c, 823 .card = CX23885_BOARD_NETUP_DUAL_DVBS2_CI, 824 }, { 825 .subvendor = 0x0070, 826 .subdevice = 0x2211, 827 .card = CX23885_BOARD_HAUPPAUGE_HVR1270, 828 }, { 829 .subvendor = 0x0070, 830 .subdevice = 0x2215, 831 .card = CX23885_BOARD_HAUPPAUGE_HVR1275, 832 }, { 833 .subvendor = 0x0070, 834 .subdevice = 0x221d, 835 .card = CX23885_BOARD_HAUPPAUGE_HVR1275, 836 }, { 837 .subvendor = 0x0070, 838 .subdevice = 0x2251, 839 .card = CX23885_BOARD_HAUPPAUGE_HVR1255, 840 }, { 841 .subvendor = 0x0070, 842 .subdevice = 0x2259, 843 .card = CX23885_BOARD_HAUPPAUGE_HVR1255_22111, 844 }, { 845 .subvendor = 0x0070, 846 .subdevice = 0x2291, 847 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, 848 }, { 849 .subvendor = 0x0070, 850 .subdevice = 0x2295, 851 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, 852 }, { 853 .subvendor = 0x0070, 854 .subdevice = 0x2299, 855 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, 856 }, { 857 .subvendor = 0x0070, 858 .subdevice = 0x229d, 859 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */ 860 }, { 861 .subvendor = 0x0070, 862 .subdevice = 0x22f0, 863 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, 864 }, { 865 .subvendor = 0x0070, 866 .subdevice = 0x22f1, 867 .card = CX23885_BOARD_HAUPPAUGE_HVR1255, 868 }, { 869 .subvendor = 0x0070, 870 .subdevice = 0x22f2, 871 .card = CX23885_BOARD_HAUPPAUGE_HVR1275, 872 }, { 873 .subvendor = 0x0070, 874 .subdevice = 0x22f3, 875 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */ 876 }, { 877 .subvendor = 0x0070, 878 .subdevice = 0x22f4, 879 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, 880 }, { 881 .subvendor = 0x0070, 882 .subdevice = 0x22f5, 883 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */ 884 }, { 885 .subvendor = 0x14f1, 886 .subdevice = 0x8651, 887 .card = CX23885_BOARD_MYGICA_X8506, 888 }, { 889 .subvendor = 0x14f1, 890 .subdevice = 0x8657, 891 .card = CX23885_BOARD_MAGICPRO_PROHDTVE2, 892 }, { 893 .subvendor = 0x0070, 894 .subdevice = 0x8541, 895 .card = CX23885_BOARD_HAUPPAUGE_HVR1850, 896 }, { 897 .subvendor = 0x1858, 898 .subdevice = 0xe800, 899 .card = CX23885_BOARD_COMPRO_VIDEOMATE_E800, 900 }, { 901 .subvendor = 0x0070, 902 .subdevice = 0x8551, 903 .card = CX23885_BOARD_HAUPPAUGE_HVR1290, 904 }, { 905 .subvendor = 0x14f1, 906 .subdevice = 0x8578, 907 .card = CX23885_BOARD_MYGICA_X8558PRO, 908 }, { 909 .subvendor = 0x107d, 910 .subdevice = 0x6f22, 911 .card = CX23885_BOARD_LEADTEK_WINFAST_PXTV1200, 912 }, { 913 .subvendor = 0x5654, 914 .subdevice = 0x2390, 915 .card = CX23885_BOARD_GOTVIEW_X5_3D_HYBRID, 916 }, { 917 .subvendor = 0x1b55, 918 .subdevice = 0xe2e4, 919 .card = CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF, 920 }, { 921 .subvendor = 0x14f1, 922 .subdevice = 0x8502, 923 .card = CX23885_BOARD_MYGICA_X8507, 924 }, { 925 .subvendor = 0x153b, 926 .subdevice = 0x117e, 927 .card = CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL, 928 }, { 929 .subvendor = 0xd471, 930 .subdevice = 0x9022, 931 .card = CX23885_BOARD_TEVII_S471, 932 }, { 933 .subvendor = 0x8000, 934 .subdevice = 0x3034, 935 .card = CX23885_BOARD_PROF_8000, 936 }, { 937 .subvendor = 0x0070, 938 .subdevice = 0xc108, 939 .card = CX23885_BOARD_HAUPPAUGE_HVR4400, 940 }, { 941 .subvendor = 0x0070, 942 .subdevice = 0xc138, 943 .card = CX23885_BOARD_HAUPPAUGE_HVR4400, 944 }, { 945 .subvendor = 0x0070, 946 .subdevice = 0xc12a, 947 .card = CX23885_BOARD_HAUPPAUGE_HVR4400, 948 }, { 949 .subvendor = 0x0070, 950 .subdevice = 0xc1f8, 951 .card = CX23885_BOARD_HAUPPAUGE_HVR4400, 952 }, { 953 .subvendor = 0x1461, 954 .subdevice = 0xd939, 955 .card = CX23885_BOARD_AVERMEDIA_HC81R, 956 }, { 957 .subvendor = 0x0070, 958 .subdevice = 0x7133, 959 .card = CX23885_BOARD_HAUPPAUGE_IMPACTVCBE, 960 }, { 961 .subvendor = 0x18ac, 962 .subdevice = 0xdb98, 963 .card = CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2, 964 }, { 965 .subvendor = 0x4254, 966 .subdevice = 0x9580, 967 .card = CX23885_BOARD_DVBSKY_T9580, 968 }, { 969 .subvendor = 0x4254, 970 .subdevice = 0x980c, 971 .card = CX23885_BOARD_DVBSKY_T980C, 972 }, { 973 .subvendor = 0x4254, 974 .subdevice = 0x950c, 975 .card = CX23885_BOARD_DVBSKY_S950C, 976 }, { 977 .subvendor = 0x13c2, 978 .subdevice = 0x3013, 979 .card = CX23885_BOARD_TT_CT2_4500_CI, 980 }, { 981 .subvendor = 0x4254, 982 .subdevice = 0x0950, 983 .card = CX23885_BOARD_DVBSKY_S950, 984 }, { 985 .subvendor = 0x4254, 986 .subdevice = 0x0952, 987 .card = CX23885_BOARD_DVBSKY_S952, 988 }, { 989 .subvendor = 0x4254, 990 .subdevice = 0x0982, 991 .card = CX23885_BOARD_DVBSKY_T982, 992 }, 993 }; 994 const unsigned int cx23885_idcount = ARRAY_SIZE(cx23885_subids); 995 996 void cx23885_card_list(struct cx23885_dev *dev) 997 { 998 int i; 999 1000 if (0 == dev->pci->subsystem_vendor && 1001 0 == dev->pci->subsystem_device) { 1002 printk(KERN_INFO 1003 "%s: Board has no valid PCIe Subsystem ID and can't\n" 1004 "%s: be autodetected. Pass card=<n> insmod option\n" 1005 "%s: to workaround that. Redirect complaints to the\n" 1006 "%s: vendor of the TV card. Best regards,\n" 1007 "%s: -- tux\n", 1008 dev->name, dev->name, dev->name, dev->name, dev->name); 1009 } else { 1010 printk(KERN_INFO 1011 "%s: Your board isn't known (yet) to the driver.\n" 1012 "%s: Try to pick one of the existing card configs via\n" 1013 "%s: card=<n> insmod option. Updating to the latest\n" 1014 "%s: version might help as well.\n", 1015 dev->name, dev->name, dev->name, dev->name); 1016 } 1017 printk(KERN_INFO "%s: Here is a list of valid choices for the card=<n> insmod option:\n", 1018 dev->name); 1019 for (i = 0; i < cx23885_bcount; i++) 1020 printk(KERN_INFO "%s: card=%d -> %s\n", 1021 dev->name, i, cx23885_boards[i].name); 1022 } 1023 1024 static void hauppauge_eeprom(struct cx23885_dev *dev, u8 *eeprom_data) 1025 { 1026 struct tveeprom tv; 1027 1028 tveeprom_hauppauge_analog(&dev->i2c_bus[0].i2c_client, &tv, 1029 eeprom_data); 1030 1031 /* Make sure we support the board model */ 1032 switch (tv.model) { 1033 case 22001: 1034 /* WinTV-HVR1270 (PCIe, Retail, half height) 1035 * ATSC/QAM and basic analog, IR Blast */ 1036 case 22009: 1037 /* WinTV-HVR1210 (PCIe, Retail, half height) 1038 * DVB-T and basic analog, IR Blast */ 1039 case 22011: 1040 /* WinTV-HVR1270 (PCIe, Retail, half height) 1041 * ATSC/QAM and basic analog, IR Recv */ 1042 case 22019: 1043 /* WinTV-HVR1210 (PCIe, Retail, half height) 1044 * DVB-T and basic analog, IR Recv */ 1045 case 22021: 1046 /* WinTV-HVR1275 (PCIe, Retail, half height) 1047 * ATSC/QAM and basic analog, IR Recv */ 1048 case 22029: 1049 /* WinTV-HVR1210 (PCIe, Retail, half height) 1050 * DVB-T and basic analog, IR Recv */ 1051 case 22101: 1052 /* WinTV-HVR1270 (PCIe, Retail, full height) 1053 * ATSC/QAM and basic analog, IR Blast */ 1054 case 22109: 1055 /* WinTV-HVR1210 (PCIe, Retail, full height) 1056 * DVB-T and basic analog, IR Blast */ 1057 case 22111: 1058 /* WinTV-HVR1270 (PCIe, Retail, full height) 1059 * ATSC/QAM and basic analog, IR Recv */ 1060 case 22119: 1061 /* WinTV-HVR1210 (PCIe, Retail, full height) 1062 * DVB-T and basic analog, IR Recv */ 1063 case 22121: 1064 /* WinTV-HVR1275 (PCIe, Retail, full height) 1065 * ATSC/QAM and basic analog, IR Recv */ 1066 case 22129: 1067 /* WinTV-HVR1210 (PCIe, Retail, full height) 1068 * DVB-T and basic analog, IR Recv */ 1069 case 71009: 1070 /* WinTV-HVR1200 (PCIe, Retail, full height) 1071 * DVB-T and basic analog */ 1072 case 71100: 1073 /* WinTV-ImpactVCB-e (PCIe, Retail, half height) 1074 * Basic analog */ 1075 case 71359: 1076 /* WinTV-HVR1200 (PCIe, OEM, half height) 1077 * DVB-T and basic analog */ 1078 case 71439: 1079 /* WinTV-HVR1200 (PCIe, OEM, half height) 1080 * DVB-T and basic analog */ 1081 case 71449: 1082 /* WinTV-HVR1200 (PCIe, OEM, full height) 1083 * DVB-T and basic analog */ 1084 case 71939: 1085 /* WinTV-HVR1200 (PCIe, OEM, half height) 1086 * DVB-T and basic analog */ 1087 case 71949: 1088 /* WinTV-HVR1200 (PCIe, OEM, full height) 1089 * DVB-T and basic analog */ 1090 case 71959: 1091 /* WinTV-HVR1200 (PCIe, OEM, full height) 1092 * DVB-T and basic analog */ 1093 case 71979: 1094 /* WinTV-HVR1200 (PCIe, OEM, half height) 1095 * DVB-T and basic analog */ 1096 case 71999: 1097 /* WinTV-HVR1200 (PCIe, OEM, full height) 1098 * DVB-T and basic analog */ 1099 case 76601: 1100 /* WinTV-HVR1800lp (PCIe, Retail, No IR, Dual 1101 channel ATSC and MPEG2 HW Encoder */ 1102 case 77001: 1103 /* WinTV-HVR1500 (Express Card, OEM, No IR, ATSC 1104 and Basic analog */ 1105 case 77011: 1106 /* WinTV-HVR1500 (Express Card, Retail, No IR, ATSC 1107 and Basic analog */ 1108 case 77041: 1109 /* WinTV-HVR1500Q (Express Card, OEM, No IR, ATSC/QAM 1110 and Basic analog */ 1111 case 77051: 1112 /* WinTV-HVR1500Q (Express Card, Retail, No IR, ATSC/QAM 1113 and Basic analog */ 1114 case 78011: 1115 /* WinTV-HVR1800 (PCIe, Retail, 3.5mm in, IR, No FM, 1116 Dual channel ATSC and MPEG2 HW Encoder */ 1117 case 78501: 1118 /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM, 1119 Dual channel ATSC and MPEG2 HW Encoder */ 1120 case 78521: 1121 /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM, 1122 Dual channel ATSC and MPEG2 HW Encoder */ 1123 case 78531: 1124 /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, No FM, 1125 Dual channel ATSC and MPEG2 HW Encoder */ 1126 case 78631: 1127 /* WinTV-HVR1800 (PCIe, OEM, No IR, No FM, 1128 Dual channel ATSC and MPEG2 HW Encoder */ 1129 case 79001: 1130 /* WinTV-HVR1250 (PCIe, Retail, IR, full height, 1131 ATSC and Basic analog */ 1132 case 79101: 1133 /* WinTV-HVR1250 (PCIe, Retail, IR, half height, 1134 ATSC and Basic analog */ 1135 case 79501: 1136 /* WinTV-HVR1250 (PCIe, No IR, half height, 1137 ATSC [at least] and Basic analog) */ 1138 case 79561: 1139 /* WinTV-HVR1250 (PCIe, OEM, No IR, half height, 1140 ATSC and Basic analog */ 1141 case 79571: 1142 /* WinTV-HVR1250 (PCIe, OEM, No IR, full height, 1143 ATSC and Basic analog */ 1144 case 79671: 1145 /* WinTV-HVR1250 (PCIe, OEM, No IR, half height, 1146 ATSC and Basic analog */ 1147 case 80019: 1148 /* WinTV-HVR1400 (Express Card, Retail, IR, 1149 * DVB-T and Basic analog */ 1150 case 81509: 1151 /* WinTV-HVR1700 (PCIe, OEM, No IR, half height) 1152 * DVB-T and MPEG2 HW Encoder */ 1153 case 81519: 1154 /* WinTV-HVR1700 (PCIe, OEM, No IR, full height) 1155 * DVB-T and MPEG2 HW Encoder */ 1156 break; 1157 case 85021: 1158 /* WinTV-HVR1850 (PCIe, Retail, 3.5mm in, IR, FM, 1159 Dual channel ATSC and MPEG2 HW Encoder */ 1160 break; 1161 case 85721: 1162 /* WinTV-HVR1290 (PCIe, OEM, RCA in, IR, 1163 Dual channel ATSC and Basic analog */ 1164 break; 1165 default: 1166 printk(KERN_WARNING "%s: warning: " 1167 "unknown hauppauge model #%d\n", 1168 dev->name, tv.model); 1169 break; 1170 } 1171 1172 printk(KERN_INFO "%s: hauppauge eeprom: model=%d\n", 1173 dev->name, tv.model); 1174 } 1175 1176 /* Some TBS cards require initing a chip using a bitbanged SPI attached 1177 to the cx23885 gpio's. If this chip doesn't get init'ed the demod 1178 doesn't respond to any command. */ 1179 static void tbs_card_init(struct cx23885_dev *dev) 1180 { 1181 int i; 1182 const u8 buf[] = { 1183 0xe0, 0x06, 0x66, 0x33, 0x65, 1184 0x01, 0x17, 0x06, 0xde}; 1185 1186 switch (dev->board) { 1187 case CX23885_BOARD_TBS_6980: 1188 case CX23885_BOARD_TBS_6981: 1189 cx_set(GP0_IO, 0x00070007); 1190 usleep_range(1000, 10000); 1191 cx_clear(GP0_IO, 2); 1192 usleep_range(1000, 10000); 1193 for (i = 0; i < 9 * 8; i++) { 1194 cx_clear(GP0_IO, 7); 1195 usleep_range(1000, 10000); 1196 cx_set(GP0_IO, 1197 ((buf[i >> 3] >> (7 - (i & 7))) & 1) | 4); 1198 usleep_range(1000, 10000); 1199 } 1200 cx_set(GP0_IO, 7); 1201 break; 1202 } 1203 } 1204 1205 int cx23885_tuner_callback(void *priv, int component, int command, int arg) 1206 { 1207 struct cx23885_tsport *port = priv; 1208 struct cx23885_dev *dev = port->dev; 1209 u32 bitmask = 0; 1210 1211 if ((command == XC2028_RESET_CLK) || (command == XC2028_I2C_FLUSH)) 1212 return 0; 1213 1214 if (command != 0) { 1215 printk(KERN_ERR "%s(): Unknown command 0x%x.\n", 1216 __func__, command); 1217 return -EINVAL; 1218 } 1219 1220 switch (dev->board) { 1221 case CX23885_BOARD_HAUPPAUGE_HVR1400: 1222 case CX23885_BOARD_HAUPPAUGE_HVR1500: 1223 case CX23885_BOARD_HAUPPAUGE_HVR1500Q: 1224 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H: 1225 case CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200: 1226 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000: 1227 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F: 1228 case CX23885_BOARD_COMPRO_VIDEOMATE_E800: 1229 case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200: 1230 /* Tuner Reset Command */ 1231 bitmask = 0x04; 1232 break; 1233 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP: 1234 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: 1235 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2: 1236 /* Two identical tuners on two different i2c buses, 1237 * we need to reset the correct gpio. */ 1238 if (port->nr == 1) 1239 bitmask = 0x01; 1240 else if (port->nr == 2) 1241 bitmask = 0x04; 1242 break; 1243 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID: 1244 /* Tuner Reset Command */ 1245 bitmask = 0x02; 1246 break; 1247 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: 1248 altera_ci_tuner_reset(dev, port->nr); 1249 break; 1250 case CX23885_BOARD_AVERMEDIA_HC81R: 1251 /* XC3028L Reset Command */ 1252 bitmask = 1 << 2; 1253 break; 1254 } 1255 1256 if (bitmask) { 1257 /* Drive the tuner into reset and back out */ 1258 cx_clear(GP0_IO, bitmask); 1259 mdelay(200); 1260 cx_set(GP0_IO, bitmask); 1261 } 1262 1263 return 0; 1264 } 1265 1266 void cx23885_gpio_setup(struct cx23885_dev *dev) 1267 { 1268 switch (dev->board) { 1269 case CX23885_BOARD_HAUPPAUGE_HVR1250: 1270 /* GPIO-0 cx24227 demodulator reset */ 1271 cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */ 1272 break; 1273 case CX23885_BOARD_HAUPPAUGE_HVR1500: 1274 /* GPIO-0 cx24227 demodulator */ 1275 /* GPIO-2 xc3028 tuner */ 1276 1277 /* Put the parts into reset */ 1278 cx_set(GP0_IO, 0x00050000); 1279 cx_clear(GP0_IO, 0x00000005); 1280 msleep(5); 1281 1282 /* Bring the parts out of reset */ 1283 cx_set(GP0_IO, 0x00050005); 1284 break; 1285 case CX23885_BOARD_HAUPPAUGE_HVR1500Q: 1286 /* GPIO-0 cx24227 demodulator reset */ 1287 /* GPIO-2 xc5000 tuner reset */ 1288 cx_set(GP0_IO, 0x00050005); /* Bring the part out of reset */ 1289 break; 1290 case CX23885_BOARD_HAUPPAUGE_HVR1800: 1291 /* GPIO-0 656_CLK */ 1292 /* GPIO-1 656_D0 */ 1293 /* GPIO-2 8295A Reset */ 1294 /* GPIO-3-10 cx23417 data0-7 */ 1295 /* GPIO-11-14 cx23417 addr0-3 */ 1296 /* GPIO-15-18 cx23417 READY, CS, RD, WR */ 1297 /* GPIO-19 IR_RX */ 1298 1299 /* CX23417 GPIO's */ 1300 /* EIO15 Zilog Reset */ 1301 /* EIO14 S5H1409/CX24227 Reset */ 1302 mc417_gpio_enable(dev, GPIO_15 | GPIO_14, 1); 1303 1304 /* Put the demod into reset and protect the eeprom */ 1305 mc417_gpio_clear(dev, GPIO_15 | GPIO_14); 1306 mdelay(100); 1307 1308 /* Bring the demod and blaster out of reset */ 1309 mc417_gpio_set(dev, GPIO_15 | GPIO_14); 1310 mdelay(100); 1311 1312 /* Force the TDA8295A into reset and back */ 1313 cx23885_gpio_enable(dev, GPIO_2, 1); 1314 cx23885_gpio_set(dev, GPIO_2); 1315 mdelay(20); 1316 cx23885_gpio_clear(dev, GPIO_2); 1317 mdelay(20); 1318 cx23885_gpio_set(dev, GPIO_2); 1319 mdelay(20); 1320 break; 1321 case CX23885_BOARD_HAUPPAUGE_HVR1200: 1322 /* GPIO-0 tda10048 demodulator reset */ 1323 /* GPIO-2 tda18271 tuner reset */ 1324 1325 /* Put the parts into reset and back */ 1326 cx_set(GP0_IO, 0x00050000); 1327 mdelay(20); 1328 cx_clear(GP0_IO, 0x00000005); 1329 mdelay(20); 1330 cx_set(GP0_IO, 0x00050005); 1331 break; 1332 case CX23885_BOARD_HAUPPAUGE_HVR1700: 1333 /* GPIO-0 TDA10048 demodulator reset */ 1334 /* GPIO-2 TDA8295A Reset */ 1335 /* GPIO-3-10 cx23417 data0-7 */ 1336 /* GPIO-11-14 cx23417 addr0-3 */ 1337 /* GPIO-15-18 cx23417 READY, CS, RD, WR */ 1338 1339 /* The following GPIO's are on the interna AVCore (cx25840) */ 1340 /* GPIO-19 IR_RX */ 1341 /* GPIO-20 IR_TX 416/DVBT Select */ 1342 /* GPIO-21 IIS DAT */ 1343 /* GPIO-22 IIS WCLK */ 1344 /* GPIO-23 IIS BCLK */ 1345 1346 /* Put the parts into reset and back */ 1347 cx_set(GP0_IO, 0x00050000); 1348 mdelay(20); 1349 cx_clear(GP0_IO, 0x00000005); 1350 mdelay(20); 1351 cx_set(GP0_IO, 0x00050005); 1352 break; 1353 case CX23885_BOARD_HAUPPAUGE_HVR1400: 1354 /* GPIO-0 Dibcom7000p demodulator reset */ 1355 /* GPIO-2 xc3028L tuner reset */ 1356 /* GPIO-13 LED */ 1357 1358 /* Put the parts into reset and back */ 1359 cx_set(GP0_IO, 0x00050000); 1360 mdelay(20); 1361 cx_clear(GP0_IO, 0x00000005); 1362 mdelay(20); 1363 cx_set(GP0_IO, 0x00050005); 1364 break; 1365 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP: 1366 /* GPIO-0 xc5000 tuner reset i2c bus 0 */ 1367 /* GPIO-1 s5h1409 demod reset i2c bus 0 */ 1368 /* GPIO-2 xc5000 tuner reset i2c bus 1 */ 1369 /* GPIO-3 s5h1409 demod reset i2c bus 0 */ 1370 1371 /* Put the parts into reset and back */ 1372 cx_set(GP0_IO, 0x000f0000); 1373 mdelay(20); 1374 cx_clear(GP0_IO, 0x0000000f); 1375 mdelay(20); 1376 cx_set(GP0_IO, 0x000f000f); 1377 break; 1378 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: 1379 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2: 1380 /* GPIO-0 portb xc3028 reset */ 1381 /* GPIO-1 portb zl10353 reset */ 1382 /* GPIO-2 portc xc3028 reset */ 1383 /* GPIO-3 portc zl10353 reset */ 1384 1385 /* Put the parts into reset and back */ 1386 cx_set(GP0_IO, 0x000f0000); 1387 mdelay(20); 1388 cx_clear(GP0_IO, 0x0000000f); 1389 mdelay(20); 1390 cx_set(GP0_IO, 0x000f000f); 1391 break; 1392 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H: 1393 case CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200: 1394 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000: 1395 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F: 1396 case CX23885_BOARD_COMPRO_VIDEOMATE_E800: 1397 case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200: 1398 /* GPIO-2 xc3028 tuner reset */ 1399 1400 /* The following GPIO's are on the internal AVCore (cx25840) */ 1401 /* GPIO-? zl10353 demod reset */ 1402 1403 /* Put the parts into reset and back */ 1404 cx_set(GP0_IO, 0x00040000); 1405 mdelay(20); 1406 cx_clear(GP0_IO, 0x00000004); 1407 mdelay(20); 1408 cx_set(GP0_IO, 0x00040004); 1409 break; 1410 case CX23885_BOARD_TBS_6920: 1411 case CX23885_BOARD_TBS_6980: 1412 case CX23885_BOARD_TBS_6981: 1413 case CX23885_BOARD_PROF_8000: 1414 cx_write(MC417_CTL, 0x00000036); 1415 cx_write(MC417_OEN, 0x00001000); 1416 cx_set(MC417_RWD, 0x00000002); 1417 mdelay(200); 1418 cx_clear(MC417_RWD, 0x00000800); 1419 mdelay(200); 1420 cx_set(MC417_RWD, 0x00000800); 1421 mdelay(200); 1422 break; 1423 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: 1424 /* GPIO-0 INTA from CiMax1 1425 GPIO-1 INTB from CiMax2 1426 GPIO-2 reset chips 1427 GPIO-3 to GPIO-10 data/addr for CA 1428 GPIO-11 ~CS0 to CiMax1 1429 GPIO-12 ~CS1 to CiMax2 1430 GPIO-13 ADL0 load LSB addr 1431 GPIO-14 ADL1 load MSB addr 1432 GPIO-15 ~RDY from CiMax 1433 GPIO-17 ~RD to CiMax 1434 GPIO-18 ~WR to CiMax 1435 */ 1436 cx_set(GP0_IO, 0x00040000); /* GPIO as out */ 1437 /* GPIO1 and GPIO2 as INTA and INTB from CiMaxes, reset low */ 1438 cx_clear(GP0_IO, 0x00030004); 1439 mdelay(100);/* reset delay */ 1440 cx_set(GP0_IO, 0x00040004); /* GPIO as out, reset high */ 1441 cx_write(MC417_CTL, 0x00000037);/* enable GPIO3-18 pins */ 1442 /* GPIO-15 IN as ~ACK, rest as OUT */ 1443 cx_write(MC417_OEN, 0x00001000); 1444 /* ~RD, ~WR high; ADL0, ADL1 low; ~CS0, ~CS1 high */ 1445 cx_write(MC417_RWD, 0x0000c300); 1446 /* enable irq */ 1447 cx_write(GPIO_ISM, 0x00000000);/* INTERRUPTS active low*/ 1448 break; 1449 case CX23885_BOARD_HAUPPAUGE_HVR1270: 1450 case CX23885_BOARD_HAUPPAUGE_HVR1275: 1451 case CX23885_BOARD_HAUPPAUGE_HVR1255: 1452 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111: 1453 case CX23885_BOARD_HAUPPAUGE_HVR1210: 1454 /* GPIO-5 RF Control: 0 = RF1 Terrestrial, 1 = RF2 Cable */ 1455 /* GPIO-6 I2C Gate which can isolate the demod from the bus */ 1456 /* GPIO-9 Demod reset */ 1457 1458 /* Put the parts into reset and back */ 1459 cx23885_gpio_enable(dev, GPIO_9 | GPIO_6 | GPIO_5, 1); 1460 cx23885_gpio_set(dev, GPIO_9 | GPIO_6 | GPIO_5); 1461 cx23885_gpio_clear(dev, GPIO_9); 1462 mdelay(20); 1463 cx23885_gpio_set(dev, GPIO_9); 1464 break; 1465 case CX23885_BOARD_MYGICA_X8506: 1466 case CX23885_BOARD_MAGICPRO_PROHDTVE2: 1467 case CX23885_BOARD_MYGICA_X8507: 1468 /* GPIO-0 (0)Analog / (1)Digital TV */ 1469 /* GPIO-1 reset XC5000 */ 1470 /* GPIO-2 demod reset */ 1471 cx23885_gpio_enable(dev, GPIO_0 | GPIO_1 | GPIO_2, 1); 1472 cx23885_gpio_clear(dev, GPIO_1 | GPIO_2); 1473 mdelay(100); 1474 cx23885_gpio_set(dev, GPIO_0 | GPIO_1 | GPIO_2); 1475 mdelay(100); 1476 break; 1477 case CX23885_BOARD_MYGICA_X8558PRO: 1478 /* GPIO-0 reset first ATBM8830 */ 1479 /* GPIO-1 reset second ATBM8830 */ 1480 cx23885_gpio_enable(dev, GPIO_0 | GPIO_1, 1); 1481 cx23885_gpio_clear(dev, GPIO_0 | GPIO_1); 1482 mdelay(100); 1483 cx23885_gpio_set(dev, GPIO_0 | GPIO_1); 1484 mdelay(100); 1485 break; 1486 case CX23885_BOARD_HAUPPAUGE_HVR1850: 1487 case CX23885_BOARD_HAUPPAUGE_HVR1290: 1488 /* GPIO-0 656_CLK */ 1489 /* GPIO-1 656_D0 */ 1490 /* GPIO-2 Wake# */ 1491 /* GPIO-3-10 cx23417 data0-7 */ 1492 /* GPIO-11-14 cx23417 addr0-3 */ 1493 /* GPIO-15-18 cx23417 READY, CS, RD, WR */ 1494 /* GPIO-19 IR_RX */ 1495 /* GPIO-20 C_IR_TX */ 1496 /* GPIO-21 I2S DAT */ 1497 /* GPIO-22 I2S WCLK */ 1498 /* GPIO-23 I2S BCLK */ 1499 /* ALT GPIO: EXP GPIO LATCH */ 1500 1501 /* CX23417 GPIO's */ 1502 /* GPIO-14 S5H1411/CX24228 Reset */ 1503 /* GPIO-13 EEPROM write protect */ 1504 mc417_gpio_enable(dev, GPIO_14 | GPIO_13, 1); 1505 1506 /* Put the demod into reset and protect the eeprom */ 1507 mc417_gpio_clear(dev, GPIO_14 | GPIO_13); 1508 mdelay(100); 1509 1510 /* Bring the demod out of reset */ 1511 mc417_gpio_set(dev, GPIO_14); 1512 mdelay(100); 1513 1514 /* CX24228 GPIO */ 1515 /* Connected to IF / Mux */ 1516 break; 1517 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID: 1518 cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */ 1519 break; 1520 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: 1521 /* GPIO-0 ~INT in 1522 GPIO-1 TMS out 1523 GPIO-2 ~reset chips out 1524 GPIO-3 to GPIO-10 data/addr for CA in/out 1525 GPIO-11 ~CS out 1526 GPIO-12 ADDR out 1527 GPIO-13 ~WR out 1528 GPIO-14 ~RD out 1529 GPIO-15 ~RDY in 1530 GPIO-16 TCK out 1531 GPIO-17 TDO in 1532 GPIO-18 TDI out 1533 */ 1534 cx_set(GP0_IO, 0x00060000); /* GPIO-1,2 as out */ 1535 /* GPIO-0 as INT, reset & TMS low */ 1536 cx_clear(GP0_IO, 0x00010006); 1537 mdelay(100);/* reset delay */ 1538 cx_set(GP0_IO, 0x00000004); /* reset high */ 1539 cx_write(MC417_CTL, 0x00000037);/* enable GPIO-3..18 pins */ 1540 /* GPIO-17 is TDO in, GPIO-15 is ~RDY in, rest is out */ 1541 cx_write(MC417_OEN, 0x00005000); 1542 /* ~RD, ~WR high; ADDR low; ~CS high */ 1543 cx_write(MC417_RWD, 0x00000d00); 1544 /* enable irq */ 1545 cx_write(GPIO_ISM, 0x00000000);/* INTERRUPTS active low*/ 1546 break; 1547 case CX23885_BOARD_HAUPPAUGE_HVR4400: 1548 /* GPIO-8 tda10071 demod reset */ 1549 /* GPIO-9 si2165 demod reset */ 1550 1551 /* Put the parts into reset and back */ 1552 cx23885_gpio_enable(dev, GPIO_8 | GPIO_9, 1); 1553 1554 cx23885_gpio_clear(dev, GPIO_8 | GPIO_9); 1555 mdelay(100); 1556 cx23885_gpio_set(dev, GPIO_8 | GPIO_9); 1557 mdelay(100); 1558 1559 break; 1560 case CX23885_BOARD_AVERMEDIA_HC81R: 1561 cx_clear(MC417_CTL, 1); 1562 /* GPIO-0,1,2 setup direction as output */ 1563 cx_set(GP0_IO, 0x00070000); 1564 mdelay(10); 1565 /* AF9013 demod reset */ 1566 cx_set(GP0_IO, 0x00010001); 1567 mdelay(10); 1568 cx_clear(GP0_IO, 0x00010001); 1569 mdelay(10); 1570 cx_set(GP0_IO, 0x00010001); 1571 mdelay(10); 1572 /* demod tune? */ 1573 cx_clear(GP0_IO, 0x00030003); 1574 mdelay(10); 1575 cx_set(GP0_IO, 0x00020002); 1576 mdelay(10); 1577 cx_set(GP0_IO, 0x00010001); 1578 mdelay(10); 1579 cx_clear(GP0_IO, 0x00020002); 1580 /* XC3028L tuner reset */ 1581 cx_set(GP0_IO, 0x00040004); 1582 cx_clear(GP0_IO, 0x00040004); 1583 cx_set(GP0_IO, 0x00040004); 1584 mdelay(60); 1585 break; 1586 case CX23885_BOARD_DVBSKY_T9580: 1587 case CX23885_BOARD_DVBSKY_S952: 1588 case CX23885_BOARD_DVBSKY_T982: 1589 /* enable GPIO3-18 pins */ 1590 cx_write(MC417_CTL, 0x00000037); 1591 cx23885_gpio_enable(dev, GPIO_2 | GPIO_11, 1); 1592 cx23885_gpio_clear(dev, GPIO_2 | GPIO_11); 1593 mdelay(100); 1594 cx23885_gpio_set(dev, GPIO_2 | GPIO_11); 1595 break; 1596 case CX23885_BOARD_DVBSKY_T980C: 1597 case CX23885_BOARD_DVBSKY_S950C: 1598 case CX23885_BOARD_TT_CT2_4500_CI: 1599 /* 1600 * GPIO-0 INTA from CiMax, input 1601 * GPIO-1 reset CiMax, output, high active 1602 * GPIO-2 reset demod, output, low active 1603 * GPIO-3 to GPIO-10 data/addr for CAM 1604 * GPIO-11 ~CS0 to CiMax1 1605 * GPIO-12 ~CS1 to CiMax2 1606 * GPIO-13 ADL0 load LSB addr 1607 * GPIO-14 ADL1 load MSB addr 1608 * GPIO-15 ~RDY from CiMax 1609 * GPIO-17 ~RD to CiMax 1610 * GPIO-18 ~WR to CiMax 1611 */ 1612 1613 cx_set(GP0_IO, 0x00060002); /* GPIO 1/2 as output */ 1614 cx_clear(GP0_IO, 0x00010004); /* GPIO 0 as input */ 1615 mdelay(100); /* reset delay */ 1616 cx_set(GP0_IO, 0x00060004); /* GPIO as out, reset high */ 1617 cx_clear(GP0_IO, 0x00010002); 1618 cx_write(MC417_CTL, 0x00000037); /* enable GPIO3-18 pins */ 1619 1620 /* GPIO-15 IN as ~ACK, rest as OUT */ 1621 cx_write(MC417_OEN, 0x00001000); 1622 1623 /* ~RD, ~WR high; ADL0, ADL1 low; ~CS0, ~CS1 high */ 1624 cx_write(MC417_RWD, 0x0000c300); 1625 1626 /* enable irq */ 1627 cx_write(GPIO_ISM, 0x00000000); /* INTERRUPTS active low */ 1628 break; 1629 case CX23885_BOARD_DVBSKY_S950: 1630 cx23885_gpio_enable(dev, GPIO_2, 1); 1631 cx23885_gpio_clear(dev, GPIO_2); 1632 msleep(100); 1633 cx23885_gpio_set(dev, GPIO_2); 1634 break; 1635 } 1636 } 1637 1638 int cx23885_ir_init(struct cx23885_dev *dev) 1639 { 1640 static struct v4l2_subdev_io_pin_config ir_rxtx_pin_cfg[] = { 1641 { 1642 .flags = V4L2_SUBDEV_IO_PIN_INPUT, 1643 .pin = CX23885_PIN_IR_RX_GPIO19, 1644 .function = CX23885_PAD_IR_RX, 1645 .value = 0, 1646 .strength = CX25840_PIN_DRIVE_MEDIUM, 1647 }, { 1648 .flags = V4L2_SUBDEV_IO_PIN_OUTPUT, 1649 .pin = CX23885_PIN_IR_TX_GPIO20, 1650 .function = CX23885_PAD_IR_TX, 1651 .value = 0, 1652 .strength = CX25840_PIN_DRIVE_MEDIUM, 1653 } 1654 }; 1655 const size_t ir_rxtx_pin_cfg_count = ARRAY_SIZE(ir_rxtx_pin_cfg); 1656 1657 static struct v4l2_subdev_io_pin_config ir_rx_pin_cfg[] = { 1658 { 1659 .flags = V4L2_SUBDEV_IO_PIN_INPUT, 1660 .pin = CX23885_PIN_IR_RX_GPIO19, 1661 .function = CX23885_PAD_IR_RX, 1662 .value = 0, 1663 .strength = CX25840_PIN_DRIVE_MEDIUM, 1664 } 1665 }; 1666 const size_t ir_rx_pin_cfg_count = ARRAY_SIZE(ir_rx_pin_cfg); 1667 1668 struct v4l2_subdev_ir_parameters params; 1669 int ret = 0; 1670 switch (dev->board) { 1671 case CX23885_BOARD_HAUPPAUGE_HVR1500: 1672 case CX23885_BOARD_HAUPPAUGE_HVR1500Q: 1673 case CX23885_BOARD_HAUPPAUGE_HVR1800: 1674 case CX23885_BOARD_HAUPPAUGE_HVR1200: 1675 case CX23885_BOARD_HAUPPAUGE_HVR1400: 1676 case CX23885_BOARD_HAUPPAUGE_HVR1275: 1677 case CX23885_BOARD_HAUPPAUGE_HVR1255: 1678 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111: 1679 case CX23885_BOARD_HAUPPAUGE_HVR1210: 1680 /* FIXME: Implement me */ 1681 break; 1682 case CX23885_BOARD_HAUPPAUGE_HVR1270: 1683 ret = cx23888_ir_probe(dev); 1684 if (ret) 1685 break; 1686 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_888_IR); 1687 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config, 1688 ir_rx_pin_cfg_count, ir_rx_pin_cfg); 1689 break; 1690 case CX23885_BOARD_HAUPPAUGE_HVR1850: 1691 case CX23885_BOARD_HAUPPAUGE_HVR1290: 1692 ret = cx23888_ir_probe(dev); 1693 if (ret) 1694 break; 1695 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_888_IR); 1696 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config, 1697 ir_rxtx_pin_cfg_count, ir_rxtx_pin_cfg); 1698 /* 1699 * For these boards we need to invert the Tx output via the 1700 * IR controller to have the LED off while idle 1701 */ 1702 v4l2_subdev_call(dev->sd_ir, ir, tx_g_parameters, ¶ms); 1703 params.enable = false; 1704 params.shutdown = false; 1705 params.invert_level = true; 1706 v4l2_subdev_call(dev->sd_ir, ir, tx_s_parameters, ¶ms); 1707 params.shutdown = true; 1708 v4l2_subdev_call(dev->sd_ir, ir, tx_s_parameters, ¶ms); 1709 break; 1710 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL: 1711 case CX23885_BOARD_TEVII_S470: 1712 case CX23885_BOARD_MYGICA_X8507: 1713 case CX23885_BOARD_TBS_6980: 1714 case CX23885_BOARD_TBS_6981: 1715 case CX23885_BOARD_DVBSKY_T9580: 1716 case CX23885_BOARD_DVBSKY_T980C: 1717 case CX23885_BOARD_DVBSKY_S950C: 1718 case CX23885_BOARD_TT_CT2_4500_CI: 1719 case CX23885_BOARD_DVBSKY_S950: 1720 case CX23885_BOARD_DVBSKY_S952: 1721 case CX23885_BOARD_DVBSKY_T982: 1722 if (!enable_885_ir) 1723 break; 1724 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_AV_CORE); 1725 if (dev->sd_ir == NULL) { 1726 ret = -ENODEV; 1727 break; 1728 } 1729 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config, 1730 ir_rx_pin_cfg_count, ir_rx_pin_cfg); 1731 break; 1732 case CX23885_BOARD_HAUPPAUGE_HVR1250: 1733 if (!enable_885_ir) 1734 break; 1735 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_AV_CORE); 1736 if (dev->sd_ir == NULL) { 1737 ret = -ENODEV; 1738 break; 1739 } 1740 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config, 1741 ir_rxtx_pin_cfg_count, ir_rxtx_pin_cfg); 1742 break; 1743 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: 1744 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2: 1745 request_module("ir-kbd-i2c"); 1746 break; 1747 } 1748 1749 return ret; 1750 } 1751 1752 void cx23885_ir_fini(struct cx23885_dev *dev) 1753 { 1754 switch (dev->board) { 1755 case CX23885_BOARD_HAUPPAUGE_HVR1270: 1756 case CX23885_BOARD_HAUPPAUGE_HVR1850: 1757 case CX23885_BOARD_HAUPPAUGE_HVR1290: 1758 cx23885_irq_remove(dev, PCI_MSK_IR); 1759 cx23888_ir_remove(dev); 1760 dev->sd_ir = NULL; 1761 break; 1762 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL: 1763 case CX23885_BOARD_TEVII_S470: 1764 case CX23885_BOARD_HAUPPAUGE_HVR1250: 1765 case CX23885_BOARD_MYGICA_X8507: 1766 case CX23885_BOARD_TBS_6980: 1767 case CX23885_BOARD_TBS_6981: 1768 case CX23885_BOARD_DVBSKY_T9580: 1769 case CX23885_BOARD_DVBSKY_T980C: 1770 case CX23885_BOARD_DVBSKY_S950C: 1771 case CX23885_BOARD_TT_CT2_4500_CI: 1772 case CX23885_BOARD_DVBSKY_S950: 1773 case CX23885_BOARD_DVBSKY_S952: 1774 case CX23885_BOARD_DVBSKY_T982: 1775 cx23885_irq_remove(dev, PCI_MSK_AV_CORE); 1776 /* sd_ir is a duplicate pointer to the AV Core, just clear it */ 1777 dev->sd_ir = NULL; 1778 break; 1779 } 1780 } 1781 1782 static int netup_jtag_io(void *device, int tms, int tdi, int read_tdo) 1783 { 1784 int data; 1785 int tdo = 0; 1786 struct cx23885_dev *dev = (struct cx23885_dev *)device; 1787 /*TMS*/ 1788 data = ((cx_read(GP0_IO)) & (~0x00000002)); 1789 data |= (tms ? 0x00020002 : 0x00020000); 1790 cx_write(GP0_IO, data); 1791 1792 /*TDI*/ 1793 data = ((cx_read(MC417_RWD)) & (~0x0000a000)); 1794 data |= (tdi ? 0x00008000 : 0); 1795 cx_write(MC417_RWD, data); 1796 if (read_tdo) 1797 tdo = (data & 0x00004000) ? 1 : 0; /*TDO*/ 1798 1799 cx_write(MC417_RWD, data | 0x00002000); 1800 udelay(1); 1801 /*TCK*/ 1802 cx_write(MC417_RWD, data); 1803 1804 return tdo; 1805 } 1806 1807 void cx23885_ir_pci_int_enable(struct cx23885_dev *dev) 1808 { 1809 switch (dev->board) { 1810 case CX23885_BOARD_HAUPPAUGE_HVR1270: 1811 case CX23885_BOARD_HAUPPAUGE_HVR1850: 1812 case CX23885_BOARD_HAUPPAUGE_HVR1290: 1813 if (dev->sd_ir) 1814 cx23885_irq_add_enable(dev, PCI_MSK_IR); 1815 break; 1816 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL: 1817 case CX23885_BOARD_TEVII_S470: 1818 case CX23885_BOARD_HAUPPAUGE_HVR1250: 1819 case CX23885_BOARD_MYGICA_X8507: 1820 case CX23885_BOARD_TBS_6980: 1821 case CX23885_BOARD_TBS_6981: 1822 case CX23885_BOARD_DVBSKY_T9580: 1823 case CX23885_BOARD_DVBSKY_T980C: 1824 case CX23885_BOARD_DVBSKY_S950C: 1825 case CX23885_BOARD_TT_CT2_4500_CI: 1826 case CX23885_BOARD_DVBSKY_S950: 1827 case CX23885_BOARD_DVBSKY_S952: 1828 case CX23885_BOARD_DVBSKY_T982: 1829 if (dev->sd_ir) 1830 cx23885_irq_add_enable(dev, PCI_MSK_AV_CORE); 1831 break; 1832 } 1833 } 1834 1835 void cx23885_card_setup(struct cx23885_dev *dev) 1836 { 1837 struct cx23885_tsport *ts1 = &dev->ts1; 1838 struct cx23885_tsport *ts2 = &dev->ts2; 1839 1840 static u8 eeprom[256]; 1841 1842 if (dev->i2c_bus[0].i2c_rc == 0) { 1843 dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1; 1844 tveeprom_read(&dev->i2c_bus[0].i2c_client, 1845 eeprom, sizeof(eeprom)); 1846 } 1847 1848 switch (dev->board) { 1849 case CX23885_BOARD_HAUPPAUGE_HVR1250: 1850 if (dev->i2c_bus[0].i2c_rc == 0) { 1851 if (eeprom[0x80] != 0x84) 1852 hauppauge_eeprom(dev, eeprom+0xc0); 1853 else 1854 hauppauge_eeprom(dev, eeprom+0x80); 1855 } 1856 break; 1857 case CX23885_BOARD_HAUPPAUGE_HVR1500: 1858 case CX23885_BOARD_HAUPPAUGE_HVR1500Q: 1859 case CX23885_BOARD_HAUPPAUGE_HVR1400: 1860 if (dev->i2c_bus[0].i2c_rc == 0) 1861 hauppauge_eeprom(dev, eeprom+0x80); 1862 break; 1863 case CX23885_BOARD_HAUPPAUGE_HVR1800: 1864 case CX23885_BOARD_HAUPPAUGE_HVR1800lp: 1865 case CX23885_BOARD_HAUPPAUGE_HVR1200: 1866 case CX23885_BOARD_HAUPPAUGE_HVR1700: 1867 case CX23885_BOARD_HAUPPAUGE_HVR1270: 1868 case CX23885_BOARD_HAUPPAUGE_HVR1275: 1869 case CX23885_BOARD_HAUPPAUGE_HVR1255: 1870 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111: 1871 case CX23885_BOARD_HAUPPAUGE_HVR1210: 1872 case CX23885_BOARD_HAUPPAUGE_HVR1850: 1873 case CX23885_BOARD_HAUPPAUGE_HVR1290: 1874 case CX23885_BOARD_HAUPPAUGE_HVR4400: 1875 case CX23885_BOARD_HAUPPAUGE_IMPACTVCBE: 1876 if (dev->i2c_bus[0].i2c_rc == 0) 1877 hauppauge_eeprom(dev, eeprom+0xc0); 1878 break; 1879 } 1880 1881 switch (dev->board) { 1882 case CX23885_BOARD_AVERMEDIA_HC81R: 1883 /* Defaults for VID B */ 1884 ts1->gen_ctrl_val = 0x4; /* Parallel */ 1885 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1886 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1887 /* Defaults for VID C */ 1888 /* DREQ_POL, SMODE, PUNC_CLK, MCLK_POL Serial bus + punc clk */ 1889 ts2->gen_ctrl_val = 0x10e; 1890 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1891 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1892 break; 1893 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP: 1894 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: 1895 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2: 1896 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 1897 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1898 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1899 /* break omitted intentionally */ 1900 case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP: 1901 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 1902 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1903 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1904 break; 1905 case CX23885_BOARD_HAUPPAUGE_HVR1850: 1906 case CX23885_BOARD_HAUPPAUGE_HVR1800: 1907 /* Defaults for VID B - Analog encoder */ 1908 /* DREQ_POL, SMODE, PUNC_CLK, MCLK_POL Serial bus + punc clk */ 1909 ts1->gen_ctrl_val = 0x10e; 1910 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1911 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1912 1913 /* APB_TSVALERR_POL (active low)*/ 1914 ts1->vld_misc_val = 0x2000; 1915 ts1->hw_sop_ctrl_val = (0x47 << 16 | 188 << 4 | 0xc); 1916 cx_write(0x130184, 0xc); 1917 1918 /* Defaults for VID C */ 1919 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 1920 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1921 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1922 break; 1923 case CX23885_BOARD_TBS_6920: 1924 ts1->gen_ctrl_val = 0x4; /* Parallel */ 1925 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1926 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1927 break; 1928 case CX23885_BOARD_TEVII_S470: 1929 case CX23885_BOARD_TEVII_S471: 1930 case CX23885_BOARD_DVBWORLD_2005: 1931 case CX23885_BOARD_PROF_8000: 1932 case CX23885_BOARD_DVBSKY_T980C: 1933 case CX23885_BOARD_DVBSKY_S950C: 1934 case CX23885_BOARD_TT_CT2_4500_CI: 1935 case CX23885_BOARD_DVBSKY_S950: 1936 ts1->gen_ctrl_val = 0x5; /* Parallel */ 1937 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1938 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1939 break; 1940 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: 1941 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: 1942 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL: 1943 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 1944 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1945 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1946 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 1947 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1948 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1949 break; 1950 case CX23885_BOARD_TBS_6980: 1951 case CX23885_BOARD_TBS_6981: 1952 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 1953 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1954 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1955 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 1956 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1957 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1958 tbs_card_init(dev); 1959 break; 1960 case CX23885_BOARD_MYGICA_X8506: 1961 case CX23885_BOARD_MAGICPRO_PROHDTVE2: 1962 case CX23885_BOARD_MYGICA_X8507: 1963 ts1->gen_ctrl_val = 0x5; /* Parallel */ 1964 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1965 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1966 break; 1967 case CX23885_BOARD_MYGICA_X8558PRO: 1968 ts1->gen_ctrl_val = 0x5; /* Parallel */ 1969 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1970 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1971 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 1972 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1973 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1974 break; 1975 case CX23885_BOARD_HAUPPAUGE_HVR4400: 1976 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 1977 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1978 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1979 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 1980 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1981 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1982 break; 1983 case CX23885_BOARD_DVBSKY_T9580: 1984 case CX23885_BOARD_DVBSKY_T982: 1985 ts1->gen_ctrl_val = 0x5; /* Parallel */ 1986 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1987 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1988 ts2->gen_ctrl_val = 0x8; /* Serial bus */ 1989 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1990 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1991 break; 1992 case CX23885_BOARD_DVBSKY_S952: 1993 ts1->gen_ctrl_val = 0x5; /* Parallel */ 1994 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1995 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1996 ts2->gen_ctrl_val = 0xe; /* Serial bus */ 1997 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1998 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1999 break; 2000 case CX23885_BOARD_HAUPPAUGE_HVR1250: 2001 case CX23885_BOARD_HAUPPAUGE_HVR1500: 2002 case CX23885_BOARD_HAUPPAUGE_HVR1500Q: 2003 case CX23885_BOARD_HAUPPAUGE_HVR1800lp: 2004 case CX23885_BOARD_HAUPPAUGE_HVR1200: 2005 case CX23885_BOARD_HAUPPAUGE_HVR1700: 2006 case CX23885_BOARD_HAUPPAUGE_HVR1400: 2007 case CX23885_BOARD_HAUPPAUGE_IMPACTVCBE: 2008 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H: 2009 case CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200: 2010 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000: 2011 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F: 2012 case CX23885_BOARD_HAUPPAUGE_HVR1270: 2013 case CX23885_BOARD_HAUPPAUGE_HVR1275: 2014 case CX23885_BOARD_HAUPPAUGE_HVR1255: 2015 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111: 2016 case CX23885_BOARD_HAUPPAUGE_HVR1210: 2017 case CX23885_BOARD_COMPRO_VIDEOMATE_E800: 2018 case CX23885_BOARD_HAUPPAUGE_HVR1290: 2019 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID: 2020 default: 2021 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 2022 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2023 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2024 } 2025 2026 /* Certain boards support analog, or require the avcore to be 2027 * loaded, ensure this happens. 2028 */ 2029 switch (dev->board) { 2030 case CX23885_BOARD_TEVII_S470: 2031 /* Currently only enabled for the integrated IR controller */ 2032 if (!enable_885_ir) 2033 break; 2034 case CX23885_BOARD_HAUPPAUGE_HVR1250: 2035 case CX23885_BOARD_HAUPPAUGE_HVR1800: 2036 case CX23885_BOARD_HAUPPAUGE_IMPACTVCBE: 2037 case CX23885_BOARD_HAUPPAUGE_HVR1800lp: 2038 case CX23885_BOARD_HAUPPAUGE_HVR1700: 2039 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H: 2040 case CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200: 2041 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000: 2042 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F: 2043 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: 2044 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: 2045 case CX23885_BOARD_COMPRO_VIDEOMATE_E800: 2046 case CX23885_BOARD_HAUPPAUGE_HVR1255: 2047 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111: 2048 case CX23885_BOARD_HAUPPAUGE_HVR1270: 2049 case CX23885_BOARD_HAUPPAUGE_HVR1850: 2050 case CX23885_BOARD_MYGICA_X8506: 2051 case CX23885_BOARD_MAGICPRO_PROHDTVE2: 2052 case CX23885_BOARD_HAUPPAUGE_HVR1290: 2053 case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200: 2054 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID: 2055 case CX23885_BOARD_HAUPPAUGE_HVR1500: 2056 case CX23885_BOARD_MPX885: 2057 case CX23885_BOARD_MYGICA_X8507: 2058 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL: 2059 case CX23885_BOARD_AVERMEDIA_HC81R: 2060 case CX23885_BOARD_TBS_6980: 2061 case CX23885_BOARD_TBS_6981: 2062 case CX23885_BOARD_DVBSKY_T9580: 2063 case CX23885_BOARD_DVBSKY_T980C: 2064 case CX23885_BOARD_DVBSKY_S950C: 2065 case CX23885_BOARD_TT_CT2_4500_CI: 2066 case CX23885_BOARD_DVBSKY_S950: 2067 case CX23885_BOARD_DVBSKY_S952: 2068 case CX23885_BOARD_DVBSKY_T982: 2069 dev->sd_cx25840 = v4l2_i2c_new_subdev(&dev->v4l2_dev, 2070 &dev->i2c_bus[2].i2c_adap, 2071 "cx25840", 0x88 >> 1, NULL); 2072 if (dev->sd_cx25840) { 2073 dev->sd_cx25840->grp_id = CX23885_HW_AV_CORE; 2074 v4l2_subdev_call(dev->sd_cx25840, core, load_fw); 2075 } 2076 break; 2077 } 2078 2079 /* AUX-PLL 27MHz CLK */ 2080 switch (dev->board) { 2081 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: 2082 netup_initialize(dev); 2083 break; 2084 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: { 2085 int ret; 2086 const struct firmware *fw; 2087 const char *filename = "dvb-netup-altera-01.fw"; 2088 char *action = "configure"; 2089 static struct netup_card_info cinfo; 2090 struct altera_config netup_config = { 2091 .dev = dev, 2092 .action = action, 2093 .jtag_io = netup_jtag_io, 2094 }; 2095 2096 netup_initialize(dev); 2097 2098 netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo); 2099 if (netup_card_rev) 2100 cinfo.rev = netup_card_rev; 2101 2102 switch (cinfo.rev) { 2103 case 0x4: 2104 filename = "dvb-netup-altera-04.fw"; 2105 break; 2106 default: 2107 filename = "dvb-netup-altera-01.fw"; 2108 break; 2109 } 2110 printk(KERN_INFO "NetUP card rev=0x%x fw_filename=%s\n", 2111 cinfo.rev, filename); 2112 2113 ret = request_firmware(&fw, filename, &dev->pci->dev); 2114 if (ret != 0) 2115 printk(KERN_ERR "did not find the firmware file. (%s) " 2116 "Please see linux/Documentation/dvb/ for more details " 2117 "on firmware-problems.", filename); 2118 else 2119 altera_init(&netup_config, fw); 2120 2121 release_firmware(fw); 2122 break; 2123 } 2124 } 2125 } 2126