1 /* 2 * Driver for the Conexant CX23885 PCIe bridge 3 * 4 * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * 15 * GNU General Public License for more details. 16 */ 17 18 #include <linux/init.h> 19 #include <linux/module.h> 20 #include <linux/pci.h> 21 #include <linux/delay.h> 22 #include <media/drv-intf/cx25840.h> 23 #include <linux/firmware.h> 24 #include <misc/altera.h> 25 26 #include "cx23885.h" 27 #include "tuner-xc2028.h" 28 #include "netup-eeprom.h" 29 #include "netup-init.h" 30 #include "altera-ci.h" 31 #include "xc4000.h" 32 #include "xc5000.h" 33 #include "cx23888-ir.h" 34 35 static unsigned int netup_card_rev = 4; 36 module_param(netup_card_rev, int, 0644); 37 MODULE_PARM_DESC(netup_card_rev, 38 "NetUP Dual DVB-T/C CI card revision"); 39 static unsigned int enable_885_ir; 40 module_param(enable_885_ir, int, 0644); 41 MODULE_PARM_DESC(enable_885_ir, 42 "Enable integrated IR controller for supported\n" 43 "\t\t CX2388[57] boards that are wired for it:\n" 44 "\t\t\tHVR-1250 (reported safe)\n" 45 "\t\t\tTerraTec Cinergy T PCIe Dual (not well tested, appears to be safe)\n" 46 "\t\t\tTeVii S470 (reported unsafe)\n" 47 "\t\t This can cause an interrupt storm with some cards.\n" 48 "\t\t Default: 0 [Disabled]"); 49 50 /* ------------------------------------------------------------------ */ 51 /* board config info */ 52 53 struct cx23885_board cx23885_boards[] = { 54 [CX23885_BOARD_UNKNOWN] = { 55 .name = "UNKNOWN/GENERIC", 56 /* Ensure safe default for unknown boards */ 57 .clk_freq = 0, 58 .input = {{ 59 .type = CX23885_VMUX_COMPOSITE1, 60 .vmux = 0, 61 }, { 62 .type = CX23885_VMUX_COMPOSITE2, 63 .vmux = 1, 64 }, { 65 .type = CX23885_VMUX_COMPOSITE3, 66 .vmux = 2, 67 }, { 68 .type = CX23885_VMUX_COMPOSITE4, 69 .vmux = 3, 70 } }, 71 }, 72 [CX23885_BOARD_HAUPPAUGE_HVR1800lp] = { 73 .name = "Hauppauge WinTV-HVR1800lp", 74 .portc = CX23885_MPEG_DVB, 75 .input = {{ 76 .type = CX23885_VMUX_TELEVISION, 77 .vmux = 0, 78 .gpio0 = 0xff00, 79 }, { 80 .type = CX23885_VMUX_DEBUG, 81 .vmux = 0, 82 .gpio0 = 0xff01, 83 }, { 84 .type = CX23885_VMUX_COMPOSITE1, 85 .vmux = 1, 86 .gpio0 = 0xff02, 87 }, { 88 .type = CX23885_VMUX_SVIDEO, 89 .vmux = 2, 90 .gpio0 = 0xff02, 91 } }, 92 }, 93 [CX23885_BOARD_HAUPPAUGE_HVR1800] = { 94 .name = "Hauppauge WinTV-HVR1800", 95 .porta = CX23885_ANALOG_VIDEO, 96 .portb = CX23885_MPEG_ENCODER, 97 .portc = CX23885_MPEG_DVB, 98 .tuner_type = TUNER_PHILIPS_TDA8290, 99 .tuner_addr = 0x42, /* 0x84 >> 1 */ 100 .tuner_bus = 1, 101 .input = {{ 102 .type = CX23885_VMUX_TELEVISION, 103 .vmux = CX25840_VIN7_CH3 | 104 CX25840_VIN5_CH2 | 105 CX25840_VIN2_CH1, 106 .amux = CX25840_AUDIO8, 107 .gpio0 = 0, 108 }, { 109 .type = CX23885_VMUX_COMPOSITE1, 110 .vmux = CX25840_VIN7_CH3 | 111 CX25840_VIN4_CH2 | 112 CX25840_VIN6_CH1, 113 .amux = CX25840_AUDIO7, 114 .gpio0 = 0, 115 }, { 116 .type = CX23885_VMUX_SVIDEO, 117 .vmux = CX25840_VIN7_CH3 | 118 CX25840_VIN4_CH2 | 119 CX25840_VIN8_CH1 | 120 CX25840_SVIDEO_ON, 121 .amux = CX25840_AUDIO7, 122 .gpio0 = 0, 123 } }, 124 }, 125 [CX23885_BOARD_HAUPPAUGE_HVR1250] = { 126 .name = "Hauppauge WinTV-HVR1250", 127 .porta = CX23885_ANALOG_VIDEO, 128 .portc = CX23885_MPEG_DVB, 129 #ifdef MT2131_NO_ANALOG_SUPPORT_YET 130 .tuner_type = TUNER_PHILIPS_TDA8290, 131 .tuner_addr = 0x42, /* 0x84 >> 1 */ 132 .tuner_bus = 1, 133 #endif 134 .force_bff = 1, 135 .input = {{ 136 #ifdef MT2131_NO_ANALOG_SUPPORT_YET 137 .type = CX23885_VMUX_TELEVISION, 138 .vmux = CX25840_VIN7_CH3 | 139 CX25840_VIN5_CH2 | 140 CX25840_VIN2_CH1, 141 .amux = CX25840_AUDIO8, 142 .gpio0 = 0xff00, 143 }, { 144 #endif 145 .type = CX23885_VMUX_COMPOSITE1, 146 .vmux = CX25840_VIN7_CH3 | 147 CX25840_VIN4_CH2 | 148 CX25840_VIN6_CH1, 149 .amux = CX25840_AUDIO7, 150 .gpio0 = 0xff02, 151 }, { 152 .type = CX23885_VMUX_SVIDEO, 153 .vmux = CX25840_VIN7_CH3 | 154 CX25840_VIN4_CH2 | 155 CX25840_VIN8_CH1 | 156 CX25840_SVIDEO_ON, 157 .amux = CX25840_AUDIO7, 158 .gpio0 = 0xff02, 159 } }, 160 }, 161 [CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP] = { 162 .name = "DViCO FusionHDTV5 Express", 163 .portb = CX23885_MPEG_DVB, 164 }, 165 [CX23885_BOARD_HAUPPAUGE_HVR1500Q] = { 166 .name = "Hauppauge WinTV-HVR1500Q", 167 .portc = CX23885_MPEG_DVB, 168 }, 169 [CX23885_BOARD_HAUPPAUGE_HVR1500] = { 170 .name = "Hauppauge WinTV-HVR1500", 171 .porta = CX23885_ANALOG_VIDEO, 172 .portc = CX23885_MPEG_DVB, 173 .tuner_type = TUNER_XC2028, 174 .tuner_addr = 0x61, /* 0xc2 >> 1 */ 175 .input = {{ 176 .type = CX23885_VMUX_TELEVISION, 177 .vmux = CX25840_VIN7_CH3 | 178 CX25840_VIN5_CH2 | 179 CX25840_VIN2_CH1, 180 .gpio0 = 0, 181 }, { 182 .type = CX23885_VMUX_COMPOSITE1, 183 .vmux = CX25840_VIN7_CH3 | 184 CX25840_VIN4_CH2 | 185 CX25840_VIN6_CH1, 186 .gpio0 = 0, 187 }, { 188 .type = CX23885_VMUX_SVIDEO, 189 .vmux = CX25840_VIN7_CH3 | 190 CX25840_VIN4_CH2 | 191 CX25840_VIN8_CH1 | 192 CX25840_SVIDEO_ON, 193 .gpio0 = 0, 194 } }, 195 }, 196 [CX23885_BOARD_HAUPPAUGE_HVR1200] = { 197 .name = "Hauppauge WinTV-HVR1200", 198 .portc = CX23885_MPEG_DVB, 199 }, 200 [CX23885_BOARD_HAUPPAUGE_HVR1700] = { 201 .name = "Hauppauge WinTV-HVR1700", 202 .portc = CX23885_MPEG_DVB, 203 }, 204 [CX23885_BOARD_HAUPPAUGE_HVR1400] = { 205 .name = "Hauppauge WinTV-HVR1400", 206 .portc = CX23885_MPEG_DVB, 207 }, 208 [CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP] = { 209 .name = "DViCO FusionHDTV7 Dual Express", 210 .portb = CX23885_MPEG_DVB, 211 .portc = CX23885_MPEG_DVB, 212 }, 213 [CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP] = { 214 .name = "DViCO FusionHDTV DVB-T Dual Express", 215 .portb = CX23885_MPEG_DVB, 216 .portc = CX23885_MPEG_DVB, 217 }, 218 [CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H] = { 219 .name = "Leadtek Winfast PxDVR3200 H", 220 .portc = CX23885_MPEG_DVB, 221 }, 222 [CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200] = { 223 .name = "Leadtek Winfast PxPVR2200", 224 .porta = CX23885_ANALOG_VIDEO, 225 .tuner_type = TUNER_XC2028, 226 .tuner_addr = 0x61, 227 .tuner_bus = 1, 228 .input = {{ 229 .type = CX23885_VMUX_TELEVISION, 230 .vmux = CX25840_VIN2_CH1 | 231 CX25840_VIN5_CH2, 232 .amux = CX25840_AUDIO8, 233 .gpio0 = 0x704040, 234 }, { 235 .type = CX23885_VMUX_COMPOSITE1, 236 .vmux = CX25840_COMPOSITE1, 237 .amux = CX25840_AUDIO7, 238 .gpio0 = 0x704040, 239 }, { 240 .type = CX23885_VMUX_SVIDEO, 241 .vmux = CX25840_SVIDEO_LUMA3 | 242 CX25840_SVIDEO_CHROMA4, 243 .amux = CX25840_AUDIO7, 244 .gpio0 = 0x704040, 245 }, { 246 .type = CX23885_VMUX_COMPONENT, 247 .vmux = CX25840_VIN7_CH1 | 248 CX25840_VIN6_CH2 | 249 CX25840_VIN8_CH3 | 250 CX25840_COMPONENT_ON, 251 .amux = CX25840_AUDIO7, 252 .gpio0 = 0x704040, 253 } }, 254 }, 255 [CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000] = { 256 .name = "Leadtek Winfast PxDVR3200 H XC4000", 257 .porta = CX23885_ANALOG_VIDEO, 258 .portc = CX23885_MPEG_DVB, 259 .tuner_type = TUNER_XC4000, 260 .tuner_addr = 0x61, 261 .radio_type = UNSET, 262 .radio_addr = ADDR_UNSET, 263 .input = {{ 264 .type = CX23885_VMUX_TELEVISION, 265 .vmux = CX25840_VIN2_CH1 | 266 CX25840_VIN5_CH2 | 267 CX25840_NONE0_CH3, 268 }, { 269 .type = CX23885_VMUX_COMPOSITE1, 270 .vmux = CX25840_COMPOSITE1, 271 }, { 272 .type = CX23885_VMUX_SVIDEO, 273 .vmux = CX25840_SVIDEO_LUMA3 | 274 CX25840_SVIDEO_CHROMA4, 275 }, { 276 .type = CX23885_VMUX_COMPONENT, 277 .vmux = CX25840_VIN7_CH1 | 278 CX25840_VIN6_CH2 | 279 CX25840_VIN8_CH3 | 280 CX25840_COMPONENT_ON, 281 } }, 282 }, 283 [CX23885_BOARD_COMPRO_VIDEOMATE_E650F] = { 284 .name = "Compro VideoMate E650F", 285 .portc = CX23885_MPEG_DVB, 286 }, 287 [CX23885_BOARD_TBS_6920] = { 288 .name = "TurboSight TBS 6920", 289 .portb = CX23885_MPEG_DVB, 290 }, 291 [CX23885_BOARD_TBS_6980] = { 292 .name = "TurboSight TBS 6980", 293 .portb = CX23885_MPEG_DVB, 294 .portc = CX23885_MPEG_DVB, 295 }, 296 [CX23885_BOARD_TBS_6981] = { 297 .name = "TurboSight TBS 6981", 298 .portb = CX23885_MPEG_DVB, 299 .portc = CX23885_MPEG_DVB, 300 }, 301 [CX23885_BOARD_TEVII_S470] = { 302 .name = "TeVii S470", 303 .portb = CX23885_MPEG_DVB, 304 }, 305 [CX23885_BOARD_DVBWORLD_2005] = { 306 .name = "DVBWorld DVB-S2 2005", 307 .portb = CX23885_MPEG_DVB, 308 }, 309 [CX23885_BOARD_NETUP_DUAL_DVBS2_CI] = { 310 .ci_type = 1, 311 .name = "NetUP Dual DVB-S2 CI", 312 .portb = CX23885_MPEG_DVB, 313 .portc = CX23885_MPEG_DVB, 314 }, 315 [CX23885_BOARD_HAUPPAUGE_HVR1270] = { 316 .name = "Hauppauge WinTV-HVR1270", 317 .portc = CX23885_MPEG_DVB, 318 }, 319 [CX23885_BOARD_HAUPPAUGE_HVR1275] = { 320 .name = "Hauppauge WinTV-HVR1275", 321 .portc = CX23885_MPEG_DVB, 322 }, 323 [CX23885_BOARD_HAUPPAUGE_HVR1255] = { 324 .name = "Hauppauge WinTV-HVR1255", 325 .porta = CX23885_ANALOG_VIDEO, 326 .portc = CX23885_MPEG_DVB, 327 .tuner_type = TUNER_ABSENT, 328 .tuner_addr = 0x42, /* 0x84 >> 1 */ 329 .force_bff = 1, 330 .input = {{ 331 .type = CX23885_VMUX_TELEVISION, 332 .vmux = CX25840_VIN7_CH3 | 333 CX25840_VIN5_CH2 | 334 CX25840_VIN2_CH1 | 335 CX25840_DIF_ON, 336 .amux = CX25840_AUDIO8, 337 }, { 338 .type = CX23885_VMUX_COMPOSITE1, 339 .vmux = CX25840_VIN7_CH3 | 340 CX25840_VIN4_CH2 | 341 CX25840_VIN6_CH1, 342 .amux = CX25840_AUDIO7, 343 }, { 344 .type = CX23885_VMUX_SVIDEO, 345 .vmux = CX25840_VIN7_CH3 | 346 CX25840_VIN4_CH2 | 347 CX25840_VIN8_CH1 | 348 CX25840_SVIDEO_ON, 349 .amux = CX25840_AUDIO7, 350 } }, 351 }, 352 [CX23885_BOARD_HAUPPAUGE_HVR1255_22111] = { 353 .name = "Hauppauge WinTV-HVR1255", 354 .porta = CX23885_ANALOG_VIDEO, 355 .portc = CX23885_MPEG_DVB, 356 .tuner_type = TUNER_ABSENT, 357 .tuner_addr = 0x42, /* 0x84 >> 1 */ 358 .force_bff = 1, 359 .input = {{ 360 .type = CX23885_VMUX_TELEVISION, 361 .vmux = CX25840_VIN7_CH3 | 362 CX25840_VIN5_CH2 | 363 CX25840_VIN2_CH1 | 364 CX25840_DIF_ON, 365 .amux = CX25840_AUDIO8, 366 }, { 367 .type = CX23885_VMUX_SVIDEO, 368 .vmux = CX25840_VIN7_CH3 | 369 CX25840_VIN4_CH2 | 370 CX25840_VIN8_CH1 | 371 CX25840_SVIDEO_ON, 372 .amux = CX25840_AUDIO7, 373 } }, 374 }, 375 [CX23885_BOARD_HAUPPAUGE_HVR1210] = { 376 .name = "Hauppauge WinTV-HVR1210", 377 .portc = CX23885_MPEG_DVB, 378 }, 379 [CX23885_BOARD_MYGICA_X8506] = { 380 .name = "Mygica X8506 DMB-TH", 381 .tuner_type = TUNER_XC5000, 382 .tuner_addr = 0x61, 383 .tuner_bus = 1, 384 .porta = CX23885_ANALOG_VIDEO, 385 .portb = CX23885_MPEG_DVB, 386 .input = { 387 { 388 .type = CX23885_VMUX_TELEVISION, 389 .vmux = CX25840_COMPOSITE2, 390 }, 391 { 392 .type = CX23885_VMUX_COMPOSITE1, 393 .vmux = CX25840_COMPOSITE8, 394 }, 395 { 396 .type = CX23885_VMUX_SVIDEO, 397 .vmux = CX25840_SVIDEO_LUMA3 | 398 CX25840_SVIDEO_CHROMA4, 399 }, 400 { 401 .type = CX23885_VMUX_COMPONENT, 402 .vmux = CX25840_COMPONENT_ON | 403 CX25840_VIN1_CH1 | 404 CX25840_VIN6_CH2 | 405 CX25840_VIN7_CH3, 406 }, 407 }, 408 }, 409 [CX23885_BOARD_MAGICPRO_PROHDTVE2] = { 410 .name = "Magic-Pro ProHDTV Extreme 2", 411 .tuner_type = TUNER_XC5000, 412 .tuner_addr = 0x61, 413 .tuner_bus = 1, 414 .porta = CX23885_ANALOG_VIDEO, 415 .portb = CX23885_MPEG_DVB, 416 .input = { 417 { 418 .type = CX23885_VMUX_TELEVISION, 419 .vmux = CX25840_COMPOSITE2, 420 }, 421 { 422 .type = CX23885_VMUX_COMPOSITE1, 423 .vmux = CX25840_COMPOSITE8, 424 }, 425 { 426 .type = CX23885_VMUX_SVIDEO, 427 .vmux = CX25840_SVIDEO_LUMA3 | 428 CX25840_SVIDEO_CHROMA4, 429 }, 430 { 431 .type = CX23885_VMUX_COMPONENT, 432 .vmux = CX25840_COMPONENT_ON | 433 CX25840_VIN1_CH1 | 434 CX25840_VIN6_CH2 | 435 CX25840_VIN7_CH3, 436 }, 437 }, 438 }, 439 [CX23885_BOARD_HAUPPAUGE_HVR1850] = { 440 .name = "Hauppauge WinTV-HVR1850", 441 .porta = CX23885_ANALOG_VIDEO, 442 .portb = CX23885_MPEG_ENCODER, 443 .portc = CX23885_MPEG_DVB, 444 .tuner_type = TUNER_ABSENT, 445 .tuner_addr = 0x42, /* 0x84 >> 1 */ 446 .force_bff = 1, 447 .input = {{ 448 .type = CX23885_VMUX_TELEVISION, 449 .vmux = CX25840_VIN7_CH3 | 450 CX25840_VIN5_CH2 | 451 CX25840_VIN2_CH1 | 452 CX25840_DIF_ON, 453 .amux = CX25840_AUDIO8, 454 }, { 455 .type = CX23885_VMUX_COMPOSITE1, 456 .vmux = CX25840_VIN7_CH3 | 457 CX25840_VIN4_CH2 | 458 CX25840_VIN6_CH1, 459 .amux = CX25840_AUDIO7, 460 }, { 461 .type = CX23885_VMUX_SVIDEO, 462 .vmux = CX25840_VIN7_CH3 | 463 CX25840_VIN4_CH2 | 464 CX25840_VIN8_CH1 | 465 CX25840_SVIDEO_ON, 466 .amux = CX25840_AUDIO7, 467 } }, 468 }, 469 [CX23885_BOARD_COMPRO_VIDEOMATE_E800] = { 470 .name = "Compro VideoMate E800", 471 .portc = CX23885_MPEG_DVB, 472 }, 473 [CX23885_BOARD_HAUPPAUGE_HVR1290] = { 474 .name = "Hauppauge WinTV-HVR1290", 475 .portc = CX23885_MPEG_DVB, 476 }, 477 [CX23885_BOARD_MYGICA_X8558PRO] = { 478 .name = "Mygica X8558 PRO DMB-TH", 479 .portb = CX23885_MPEG_DVB, 480 .portc = CX23885_MPEG_DVB, 481 }, 482 [CX23885_BOARD_LEADTEK_WINFAST_PXTV1200] = { 483 .name = "LEADTEK WinFast PxTV1200", 484 .porta = CX23885_ANALOG_VIDEO, 485 .tuner_type = TUNER_XC2028, 486 .tuner_addr = 0x61, 487 .tuner_bus = 1, 488 .input = {{ 489 .type = CX23885_VMUX_TELEVISION, 490 .vmux = CX25840_VIN2_CH1 | 491 CX25840_VIN5_CH2 | 492 CX25840_NONE0_CH3, 493 }, { 494 .type = CX23885_VMUX_COMPOSITE1, 495 .vmux = CX25840_COMPOSITE1, 496 }, { 497 .type = CX23885_VMUX_SVIDEO, 498 .vmux = CX25840_SVIDEO_LUMA3 | 499 CX25840_SVIDEO_CHROMA4, 500 }, { 501 .type = CX23885_VMUX_COMPONENT, 502 .vmux = CX25840_VIN7_CH1 | 503 CX25840_VIN6_CH2 | 504 CX25840_VIN8_CH3 | 505 CX25840_COMPONENT_ON, 506 } }, 507 }, 508 [CX23885_BOARD_GOTVIEW_X5_3D_HYBRID] = { 509 .name = "GoTView X5 3D Hybrid", 510 .tuner_type = TUNER_XC5000, 511 .tuner_addr = 0x64, 512 .tuner_bus = 1, 513 .porta = CX23885_ANALOG_VIDEO, 514 .portb = CX23885_MPEG_DVB, 515 .input = {{ 516 .type = CX23885_VMUX_TELEVISION, 517 .vmux = CX25840_VIN2_CH1 | 518 CX25840_VIN5_CH2, 519 .gpio0 = 0x02, 520 }, { 521 .type = CX23885_VMUX_COMPOSITE1, 522 .vmux = CX23885_VMUX_COMPOSITE1, 523 }, { 524 .type = CX23885_VMUX_SVIDEO, 525 .vmux = CX25840_SVIDEO_LUMA3 | 526 CX25840_SVIDEO_CHROMA4, 527 } }, 528 }, 529 [CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF] = { 530 .ci_type = 2, 531 .name = "NetUP Dual DVB-T/C-CI RF", 532 .porta = CX23885_ANALOG_VIDEO, 533 .portb = CX23885_MPEG_DVB, 534 .portc = CX23885_MPEG_DVB, 535 .num_fds_portb = 2, 536 .num_fds_portc = 2, 537 .tuner_type = TUNER_XC5000, 538 .tuner_addr = 0x64, 539 .input = { { 540 .type = CX23885_VMUX_TELEVISION, 541 .vmux = CX25840_COMPOSITE1, 542 } }, 543 }, 544 [CX23885_BOARD_MPX885] = { 545 .name = "MPX-885", 546 .porta = CX23885_ANALOG_VIDEO, 547 .input = {{ 548 .type = CX23885_VMUX_COMPOSITE1, 549 .vmux = CX25840_COMPOSITE1, 550 .amux = CX25840_AUDIO6, 551 .gpio0 = 0, 552 }, { 553 .type = CX23885_VMUX_COMPOSITE2, 554 .vmux = CX25840_COMPOSITE2, 555 .amux = CX25840_AUDIO6, 556 .gpio0 = 0, 557 }, { 558 .type = CX23885_VMUX_COMPOSITE3, 559 .vmux = CX25840_COMPOSITE3, 560 .amux = CX25840_AUDIO7, 561 .gpio0 = 0, 562 }, { 563 .type = CX23885_VMUX_COMPOSITE4, 564 .vmux = CX25840_COMPOSITE4, 565 .amux = CX25840_AUDIO7, 566 .gpio0 = 0, 567 } }, 568 }, 569 [CX23885_BOARD_MYGICA_X8507] = { 570 .name = "Mygica X8502/X8507 ISDB-T", 571 .tuner_type = TUNER_XC5000, 572 .tuner_addr = 0x61, 573 .tuner_bus = 1, 574 .porta = CX23885_ANALOG_VIDEO, 575 .portb = CX23885_MPEG_DVB, 576 .input = { 577 { 578 .type = CX23885_VMUX_TELEVISION, 579 .vmux = CX25840_COMPOSITE2, 580 .amux = CX25840_AUDIO8, 581 }, 582 { 583 .type = CX23885_VMUX_COMPOSITE1, 584 .vmux = CX25840_COMPOSITE8, 585 .amux = CX25840_AUDIO7, 586 }, 587 { 588 .type = CX23885_VMUX_SVIDEO, 589 .vmux = CX25840_SVIDEO_LUMA3 | 590 CX25840_SVIDEO_CHROMA4, 591 .amux = CX25840_AUDIO7, 592 }, 593 { 594 .type = CX23885_VMUX_COMPONENT, 595 .vmux = CX25840_COMPONENT_ON | 596 CX25840_VIN1_CH1 | 597 CX25840_VIN6_CH2 | 598 CX25840_VIN7_CH3, 599 .amux = CX25840_AUDIO7, 600 }, 601 }, 602 }, 603 [CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL] = { 604 .name = "TerraTec Cinergy T PCIe Dual", 605 .portb = CX23885_MPEG_DVB, 606 .portc = CX23885_MPEG_DVB, 607 }, 608 [CX23885_BOARD_TEVII_S471] = { 609 .name = "TeVii S471", 610 .portb = CX23885_MPEG_DVB, 611 }, 612 [CX23885_BOARD_PROF_8000] = { 613 .name = "Prof Revolution DVB-S2 8000", 614 .portb = CX23885_MPEG_DVB, 615 }, 616 [CX23885_BOARD_HAUPPAUGE_HVR4400] = { 617 .name = "Hauppauge WinTV-HVR4400/HVR5500", 618 .porta = CX23885_ANALOG_VIDEO, 619 .portb = CX23885_MPEG_DVB, 620 .portc = CX23885_MPEG_DVB, 621 .tuner_type = TUNER_NXP_TDA18271, 622 .tuner_addr = 0x60, /* 0xc0 >> 1 */ 623 .tuner_bus = 1, 624 }, 625 [CX23885_BOARD_HAUPPAUGE_STARBURST] = { 626 .name = "Hauppauge WinTV Starburst", 627 .portb = CX23885_MPEG_DVB, 628 }, 629 [CX23885_BOARD_AVERMEDIA_HC81R] = { 630 .name = "AVerTV Hybrid Express Slim HC81R", 631 .tuner_type = TUNER_XC2028, 632 .tuner_addr = 0x61, /* 0xc2 >> 1 */ 633 .tuner_bus = 1, 634 .porta = CX23885_ANALOG_VIDEO, 635 .input = {{ 636 .type = CX23885_VMUX_TELEVISION, 637 .vmux = CX25840_VIN2_CH1 | 638 CX25840_VIN5_CH2 | 639 CX25840_NONE0_CH3 | 640 CX25840_NONE1_CH3, 641 .amux = CX25840_AUDIO8, 642 }, { 643 .type = CX23885_VMUX_SVIDEO, 644 .vmux = CX25840_VIN8_CH1 | 645 CX25840_NONE_CH2 | 646 CX25840_VIN7_CH3 | 647 CX25840_SVIDEO_ON, 648 .amux = CX25840_AUDIO6, 649 }, { 650 .type = CX23885_VMUX_COMPONENT, 651 .vmux = CX25840_VIN1_CH1 | 652 CX25840_NONE_CH2 | 653 CX25840_NONE0_CH3 | 654 CX25840_NONE1_CH3, 655 .amux = CX25840_AUDIO6, 656 } }, 657 }, 658 [CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2] = { 659 .name = "DViCO FusionHDTV DVB-T Dual Express2", 660 .portb = CX23885_MPEG_DVB, 661 .portc = CX23885_MPEG_DVB, 662 }, 663 [CX23885_BOARD_HAUPPAUGE_IMPACTVCBE] = { 664 .name = "Hauppauge ImpactVCB-e", 665 .tuner_type = TUNER_ABSENT, 666 .porta = CX23885_ANALOG_VIDEO, 667 .input = {{ 668 .type = CX23885_VMUX_COMPOSITE1, 669 .vmux = CX25840_VIN7_CH3 | 670 CX25840_VIN4_CH2 | 671 CX25840_VIN6_CH1, 672 .amux = CX25840_AUDIO7, 673 }, { 674 .type = CX23885_VMUX_SVIDEO, 675 .vmux = CX25840_VIN7_CH3 | 676 CX25840_VIN4_CH2 | 677 CX25840_VIN8_CH1 | 678 CX25840_SVIDEO_ON, 679 .amux = CX25840_AUDIO7, 680 } }, 681 }, 682 [CX23885_BOARD_DVBSKY_T9580] = { 683 .name = "DVBSky T9580", 684 .portb = CX23885_MPEG_DVB, 685 .portc = CX23885_MPEG_DVB, 686 }, 687 [CX23885_BOARD_DVBSKY_T980C] = { 688 .name = "DVBSky T980C", 689 .portb = CX23885_MPEG_DVB, 690 }, 691 [CX23885_BOARD_DVBSKY_S950C] = { 692 .name = "DVBSky S950C", 693 .portb = CX23885_MPEG_DVB, 694 }, 695 [CX23885_BOARD_TT_CT2_4500_CI] = { 696 .name = "Technotrend TT-budget CT2-4500 CI", 697 .portb = CX23885_MPEG_DVB, 698 }, 699 [CX23885_BOARD_DVBSKY_S950] = { 700 .name = "DVBSky S950", 701 .portb = CX23885_MPEG_DVB, 702 }, 703 [CX23885_BOARD_DVBSKY_S952] = { 704 .name = "DVBSky S952", 705 .portb = CX23885_MPEG_DVB, 706 .portc = CX23885_MPEG_DVB, 707 }, 708 [CX23885_BOARD_DVBSKY_T982] = { 709 .name = "DVBSky T982", 710 .portb = CX23885_MPEG_DVB, 711 .portc = CX23885_MPEG_DVB, 712 }, 713 [CX23885_BOARD_HAUPPAUGE_HVR5525] = { 714 .name = "Hauppauge WinTV-HVR5525", 715 .portb = CX23885_MPEG_DVB, 716 .portc = CX23885_MPEG_DVB, 717 }, 718 [CX23885_BOARD_VIEWCAST_260E] = { 719 .name = "ViewCast 260e", 720 .porta = CX23885_ANALOG_VIDEO, 721 .force_bff = 1, 722 .input = {{ 723 .type = CX23885_VMUX_COMPOSITE1, 724 .vmux = CX25840_VIN6_CH1, 725 .amux = CX25840_AUDIO7, 726 }, { 727 .type = CX23885_VMUX_SVIDEO, 728 .vmux = CX25840_VIN7_CH3 | 729 CX25840_VIN5_CH1 | 730 CX25840_SVIDEO_ON, 731 .amux = CX25840_AUDIO7, 732 }, { 733 .type = CX23885_VMUX_COMPONENT, 734 .vmux = CX25840_VIN7_CH3 | 735 CX25840_VIN6_CH2 | 736 CX25840_VIN5_CH1 | 737 CX25840_COMPONENT_ON, 738 .amux = CX25840_AUDIO7, 739 } }, 740 }, 741 [CX23885_BOARD_VIEWCAST_460E] = { 742 .name = "ViewCast 460e", 743 .porta = CX23885_ANALOG_VIDEO, 744 .force_bff = 1, 745 .input = {{ 746 .type = CX23885_VMUX_COMPOSITE1, 747 .vmux = CX25840_VIN4_CH1, 748 .amux = CX25840_AUDIO7, 749 }, { 750 .type = CX23885_VMUX_SVIDEO, 751 .vmux = CX25840_VIN7_CH3 | 752 CX25840_VIN6_CH1 | 753 CX25840_SVIDEO_ON, 754 .amux = CX25840_AUDIO7, 755 }, { 756 .type = CX23885_VMUX_COMPONENT, 757 .vmux = CX25840_VIN7_CH3 | 758 CX25840_VIN6_CH1 | 759 CX25840_VIN5_CH2 | 760 CX25840_COMPONENT_ON, 761 .amux = CX25840_AUDIO7, 762 }, { 763 .type = CX23885_VMUX_COMPOSITE2, 764 .vmux = CX25840_VIN6_CH1, 765 .amux = CX25840_AUDIO7, 766 } }, 767 }, 768 [CX23885_BOARD_HAUPPAUGE_QUADHD_DVB] = { 769 .name = "Hauppauge WinTV-QuadHD-DVB", 770 .portb = CX23885_MPEG_DVB, 771 .portc = CX23885_MPEG_DVB, 772 }, 773 [CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC] = { 774 .name = "Hauppauge WinTV-QuadHD-ATSC", 775 .portb = CX23885_MPEG_DVB, 776 .portc = CX23885_MPEG_DVB, 777 }, 778 }; 779 const unsigned int cx23885_bcount = ARRAY_SIZE(cx23885_boards); 780 781 /* ------------------------------------------------------------------ */ 782 /* PCI subsystem IDs */ 783 784 struct cx23885_subid cx23885_subids[] = { 785 { 786 .subvendor = 0x0070, 787 .subdevice = 0x3400, 788 .card = CX23885_BOARD_UNKNOWN, 789 }, { 790 .subvendor = 0x0070, 791 .subdevice = 0x7600, 792 .card = CX23885_BOARD_HAUPPAUGE_HVR1800lp, 793 }, { 794 .subvendor = 0x0070, 795 .subdevice = 0x7800, 796 .card = CX23885_BOARD_HAUPPAUGE_HVR1800, 797 }, { 798 .subvendor = 0x0070, 799 .subdevice = 0x7801, 800 .card = CX23885_BOARD_HAUPPAUGE_HVR1800, 801 }, { 802 .subvendor = 0x0070, 803 .subdevice = 0x7809, 804 .card = CX23885_BOARD_HAUPPAUGE_HVR1800, 805 }, { 806 .subvendor = 0x0070, 807 .subdevice = 0x7911, 808 .card = CX23885_BOARD_HAUPPAUGE_HVR1250, 809 }, { 810 .subvendor = 0x18ac, 811 .subdevice = 0xd500, 812 .card = CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP, 813 }, { 814 .subvendor = 0x0070, 815 .subdevice = 0x7790, 816 .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q, 817 }, { 818 .subvendor = 0x0070, 819 .subdevice = 0x7797, 820 .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q, 821 }, { 822 .subvendor = 0x0070, 823 .subdevice = 0x7710, 824 .card = CX23885_BOARD_HAUPPAUGE_HVR1500, 825 }, { 826 .subvendor = 0x0070, 827 .subdevice = 0x7717, 828 .card = CX23885_BOARD_HAUPPAUGE_HVR1500, 829 }, { 830 .subvendor = 0x0070, 831 .subdevice = 0x71d1, 832 .card = CX23885_BOARD_HAUPPAUGE_HVR1200, 833 }, { 834 .subvendor = 0x0070, 835 .subdevice = 0x71d3, 836 .card = CX23885_BOARD_HAUPPAUGE_HVR1200, 837 }, { 838 .subvendor = 0x0070, 839 .subdevice = 0x8101, 840 .card = CX23885_BOARD_HAUPPAUGE_HVR1700, 841 }, { 842 .subvendor = 0x0070, 843 .subdevice = 0x8010, 844 .card = CX23885_BOARD_HAUPPAUGE_HVR1400, 845 }, { 846 .subvendor = 0x18ac, 847 .subdevice = 0xd618, 848 .card = CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP, 849 }, { 850 .subvendor = 0x18ac, 851 .subdevice = 0xdb78, 852 .card = CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP, 853 }, { 854 .subvendor = 0x107d, 855 .subdevice = 0x6681, 856 .card = CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H, 857 }, { 858 .subvendor = 0x107d, 859 .subdevice = 0x6f21, 860 .card = CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200, 861 }, { 862 .subvendor = 0x107d, 863 .subdevice = 0x6f39, 864 .card = CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000, 865 }, { 866 .subvendor = 0x185b, 867 .subdevice = 0xe800, 868 .card = CX23885_BOARD_COMPRO_VIDEOMATE_E650F, 869 }, { 870 .subvendor = 0x6920, 871 .subdevice = 0x8888, 872 .card = CX23885_BOARD_TBS_6920, 873 }, { 874 .subvendor = 0x6980, 875 .subdevice = 0x8888, 876 .card = CX23885_BOARD_TBS_6980, 877 }, { 878 .subvendor = 0x6981, 879 .subdevice = 0x8888, 880 .card = CX23885_BOARD_TBS_6981, 881 }, { 882 .subvendor = 0xd470, 883 .subdevice = 0x9022, 884 .card = CX23885_BOARD_TEVII_S470, 885 }, { 886 .subvendor = 0x0001, 887 .subdevice = 0x2005, 888 .card = CX23885_BOARD_DVBWORLD_2005, 889 }, { 890 .subvendor = 0x1b55, 891 .subdevice = 0x2a2c, 892 .card = CX23885_BOARD_NETUP_DUAL_DVBS2_CI, 893 }, { 894 .subvendor = 0x0070, 895 .subdevice = 0x2211, 896 .card = CX23885_BOARD_HAUPPAUGE_HVR1270, 897 }, { 898 .subvendor = 0x0070, 899 .subdevice = 0x2215, 900 .card = CX23885_BOARD_HAUPPAUGE_HVR1275, 901 }, { 902 .subvendor = 0x0070, 903 .subdevice = 0x221d, 904 .card = CX23885_BOARD_HAUPPAUGE_HVR1275, 905 }, { 906 .subvendor = 0x0070, 907 .subdevice = 0x2251, 908 .card = CX23885_BOARD_HAUPPAUGE_HVR1255, 909 }, { 910 .subvendor = 0x0070, 911 .subdevice = 0x2259, 912 .card = CX23885_BOARD_HAUPPAUGE_HVR1255_22111, 913 }, { 914 .subvendor = 0x0070, 915 .subdevice = 0x2291, 916 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, 917 }, { 918 .subvendor = 0x0070, 919 .subdevice = 0x2295, 920 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, 921 }, { 922 .subvendor = 0x0070, 923 .subdevice = 0x2299, 924 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, 925 }, { 926 .subvendor = 0x0070, 927 .subdevice = 0x229d, 928 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */ 929 }, { 930 .subvendor = 0x0070, 931 .subdevice = 0x22f0, 932 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, 933 }, { 934 .subvendor = 0x0070, 935 .subdevice = 0x22f1, 936 .card = CX23885_BOARD_HAUPPAUGE_HVR1255, 937 }, { 938 .subvendor = 0x0070, 939 .subdevice = 0x22f2, 940 .card = CX23885_BOARD_HAUPPAUGE_HVR1275, 941 }, { 942 .subvendor = 0x0070, 943 .subdevice = 0x22f3, 944 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */ 945 }, { 946 .subvendor = 0x0070, 947 .subdevice = 0x22f4, 948 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, 949 }, { 950 .subvendor = 0x0070, 951 .subdevice = 0x22f5, 952 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */ 953 }, { 954 .subvendor = 0x14f1, 955 .subdevice = 0x8651, 956 .card = CX23885_BOARD_MYGICA_X8506, 957 }, { 958 .subvendor = 0x14f1, 959 .subdevice = 0x8657, 960 .card = CX23885_BOARD_MAGICPRO_PROHDTVE2, 961 }, { 962 .subvendor = 0x0070, 963 .subdevice = 0x8541, 964 .card = CX23885_BOARD_HAUPPAUGE_HVR1850, 965 }, { 966 .subvendor = 0x1858, 967 .subdevice = 0xe800, 968 .card = CX23885_BOARD_COMPRO_VIDEOMATE_E800, 969 }, { 970 .subvendor = 0x0070, 971 .subdevice = 0x8551, 972 .card = CX23885_BOARD_HAUPPAUGE_HVR1290, 973 }, { 974 .subvendor = 0x14f1, 975 .subdevice = 0x8578, 976 .card = CX23885_BOARD_MYGICA_X8558PRO, 977 }, { 978 .subvendor = 0x107d, 979 .subdevice = 0x6f22, 980 .card = CX23885_BOARD_LEADTEK_WINFAST_PXTV1200, 981 }, { 982 .subvendor = 0x5654, 983 .subdevice = 0x2390, 984 .card = CX23885_BOARD_GOTVIEW_X5_3D_HYBRID, 985 }, { 986 .subvendor = 0x1b55, 987 .subdevice = 0xe2e4, 988 .card = CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF, 989 }, { 990 .subvendor = 0x14f1, 991 .subdevice = 0x8502, 992 .card = CX23885_BOARD_MYGICA_X8507, 993 }, { 994 .subvendor = 0x153b, 995 .subdevice = 0x117e, 996 .card = CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL, 997 }, { 998 .subvendor = 0xd471, 999 .subdevice = 0x9022, 1000 .card = CX23885_BOARD_TEVII_S471, 1001 }, { 1002 .subvendor = 0x8000, 1003 .subdevice = 0x3034, 1004 .card = CX23885_BOARD_PROF_8000, 1005 }, { 1006 .subvendor = 0x0070, 1007 .subdevice = 0xc108, 1008 .card = CX23885_BOARD_HAUPPAUGE_HVR4400, /* Hauppauge WinTV HVR-4400 (Model 121xxx, Hybrid DVB-T/S2, IR) */ 1009 }, { 1010 .subvendor = 0x0070, 1011 .subdevice = 0xc138, 1012 .card = CX23885_BOARD_HAUPPAUGE_HVR4400, /* Hauppauge WinTV HVR-5500 (Model 121xxx, Hybrid DVB-T/C/S2, IR) */ 1013 }, { 1014 .subvendor = 0x0070, 1015 .subdevice = 0xc12a, 1016 .card = CX23885_BOARD_HAUPPAUGE_STARBURST, /* Hauppauge WinTV Starburst (Model 121x00, DVB-S2, IR) */ 1017 }, { 1018 .subvendor = 0x0070, 1019 .subdevice = 0xc1f8, 1020 .card = CX23885_BOARD_HAUPPAUGE_HVR4400, /* Hauppauge WinTV HVR-5500 (Model 121xxx, Hybrid DVB-T/C/S2, IR) */ 1021 }, { 1022 .subvendor = 0x1461, 1023 .subdevice = 0xd939, 1024 .card = CX23885_BOARD_AVERMEDIA_HC81R, 1025 }, { 1026 .subvendor = 0x0070, 1027 .subdevice = 0x7133, 1028 .card = CX23885_BOARD_HAUPPAUGE_IMPACTVCBE, 1029 }, { 1030 .subvendor = 0x18ac, 1031 .subdevice = 0xdb98, 1032 .card = CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2, 1033 }, { 1034 .subvendor = 0x4254, 1035 .subdevice = 0x9580, 1036 .card = CX23885_BOARD_DVBSKY_T9580, 1037 }, { 1038 .subvendor = 0x4254, 1039 .subdevice = 0x980c, 1040 .card = CX23885_BOARD_DVBSKY_T980C, 1041 }, { 1042 .subvendor = 0x4254, 1043 .subdevice = 0x950c, 1044 .card = CX23885_BOARD_DVBSKY_S950C, 1045 }, { 1046 .subvendor = 0x13c2, 1047 .subdevice = 0x3013, 1048 .card = CX23885_BOARD_TT_CT2_4500_CI, 1049 }, { 1050 .subvendor = 0x4254, 1051 .subdevice = 0x0950, 1052 .card = CX23885_BOARD_DVBSKY_S950, 1053 }, { 1054 .subvendor = 0x4254, 1055 .subdevice = 0x0952, 1056 .card = CX23885_BOARD_DVBSKY_S952, 1057 }, { 1058 .subvendor = 0x4254, 1059 .subdevice = 0x0982, 1060 .card = CX23885_BOARD_DVBSKY_T982, 1061 }, { 1062 .subvendor = 0x0070, 1063 .subdevice = 0xf038, 1064 .card = CX23885_BOARD_HAUPPAUGE_HVR5525, 1065 }, { 1066 .subvendor = 0x1576, 1067 .subdevice = 0x0260, 1068 .card = CX23885_BOARD_VIEWCAST_260E, 1069 }, { 1070 .subvendor = 0x1576, 1071 .subdevice = 0x0460, 1072 .card = CX23885_BOARD_VIEWCAST_460E, 1073 }, { 1074 .subvendor = 0x0070, 1075 .subdevice = 0x6a28, 1076 .card = CX23885_BOARD_HAUPPAUGE_QUADHD_DVB, /* Tuner Pair 1 */ 1077 }, { 1078 .subvendor = 0x0070, 1079 .subdevice = 0x6b28, 1080 .card = CX23885_BOARD_HAUPPAUGE_QUADHD_DVB, /* Tuner Pair 2 */ 1081 }, { 1082 .subvendor = 0x0070, 1083 .subdevice = 0x6a18, 1084 .card = CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC, /* Tuner Pair 1 */ 1085 }, { 1086 .subvendor = 0x0070, 1087 .subdevice = 0x6b18, 1088 .card = CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC, /* Tuner Pair 2 */ 1089 }, 1090 }; 1091 const unsigned int cx23885_idcount = ARRAY_SIZE(cx23885_subids); 1092 1093 void cx23885_card_list(struct cx23885_dev *dev) 1094 { 1095 int i; 1096 1097 if (0 == dev->pci->subsystem_vendor && 1098 0 == dev->pci->subsystem_device) { 1099 printk(KERN_INFO 1100 "%s: Board has no valid PCIe Subsystem ID and can't\n" 1101 "%s: be autodetected. Pass card=<n> insmod option\n" 1102 "%s: to workaround that. Redirect complaints to the\n" 1103 "%s: vendor of the TV card. Best regards,\n" 1104 "%s: -- tux\n", 1105 dev->name, dev->name, dev->name, dev->name, dev->name); 1106 } else { 1107 printk(KERN_INFO 1108 "%s: Your board isn't known (yet) to the driver.\n" 1109 "%s: Try to pick one of the existing card configs via\n" 1110 "%s: card=<n> insmod option. Updating to the latest\n" 1111 "%s: version might help as well.\n", 1112 dev->name, dev->name, dev->name, dev->name); 1113 } 1114 printk(KERN_INFO "%s: Here is a list of valid choices for the card=<n> insmod option:\n", 1115 dev->name); 1116 for (i = 0; i < cx23885_bcount; i++) 1117 printk(KERN_INFO "%s: card=%d -> %s\n", 1118 dev->name, i, cx23885_boards[i].name); 1119 } 1120 1121 static void viewcast_eeprom(struct cx23885_dev *dev, u8 *eeprom_data) 1122 { 1123 u32 sn; 1124 1125 /* The serial number record begins with tag 0x59 */ 1126 if (*(eeprom_data + 0x00) != 0x59) { 1127 pr_info("%s() eeprom records are undefined, no serial number\n", 1128 __func__); 1129 return; 1130 } 1131 1132 sn = (*(eeprom_data + 0x06) << 24) | 1133 (*(eeprom_data + 0x05) << 16) | 1134 (*(eeprom_data + 0x04) << 8) | 1135 (*(eeprom_data + 0x03)); 1136 1137 pr_info("%s: card '%s' sn# MM%d\n", 1138 dev->name, 1139 cx23885_boards[dev->board].name, 1140 sn); 1141 } 1142 1143 static void hauppauge_eeprom(struct cx23885_dev *dev, u8 *eeprom_data) 1144 { 1145 struct tveeprom tv; 1146 1147 tveeprom_hauppauge_analog(&dev->i2c_bus[0].i2c_client, &tv, 1148 eeprom_data); 1149 1150 /* Make sure we support the board model */ 1151 switch (tv.model) { 1152 case 22001: 1153 /* WinTV-HVR1270 (PCIe, Retail, half height) 1154 * ATSC/QAM and basic analog, IR Blast */ 1155 case 22009: 1156 /* WinTV-HVR1210 (PCIe, Retail, half height) 1157 * DVB-T and basic analog, IR Blast */ 1158 case 22011: 1159 /* WinTV-HVR1270 (PCIe, Retail, half height) 1160 * ATSC/QAM and basic analog, IR Recv */ 1161 case 22019: 1162 /* WinTV-HVR1210 (PCIe, Retail, half height) 1163 * DVB-T and basic analog, IR Recv */ 1164 case 22021: 1165 /* WinTV-HVR1275 (PCIe, Retail, half height) 1166 * ATSC/QAM and basic analog, IR Recv */ 1167 case 22029: 1168 /* WinTV-HVR1210 (PCIe, Retail, half height) 1169 * DVB-T and basic analog, IR Recv */ 1170 case 22101: 1171 /* WinTV-HVR1270 (PCIe, Retail, full height) 1172 * ATSC/QAM and basic analog, IR Blast */ 1173 case 22109: 1174 /* WinTV-HVR1210 (PCIe, Retail, full height) 1175 * DVB-T and basic analog, IR Blast */ 1176 case 22111: 1177 /* WinTV-HVR1270 (PCIe, Retail, full height) 1178 * ATSC/QAM and basic analog, IR Recv */ 1179 case 22119: 1180 /* WinTV-HVR1210 (PCIe, Retail, full height) 1181 * DVB-T and basic analog, IR Recv */ 1182 case 22121: 1183 /* WinTV-HVR1275 (PCIe, Retail, full height) 1184 * ATSC/QAM and basic analog, IR Recv */ 1185 case 22129: 1186 /* WinTV-HVR1210 (PCIe, Retail, full height) 1187 * DVB-T and basic analog, IR Recv */ 1188 case 71009: 1189 /* WinTV-HVR1200 (PCIe, Retail, full height) 1190 * DVB-T and basic analog */ 1191 case 71100: 1192 /* WinTV-ImpactVCB-e (PCIe, Retail, half height) 1193 * Basic analog */ 1194 case 71359: 1195 /* WinTV-HVR1200 (PCIe, OEM, half height) 1196 * DVB-T and basic analog */ 1197 case 71439: 1198 /* WinTV-HVR1200 (PCIe, OEM, half height) 1199 * DVB-T and basic analog */ 1200 case 71449: 1201 /* WinTV-HVR1200 (PCIe, OEM, full height) 1202 * DVB-T and basic analog */ 1203 case 71939: 1204 /* WinTV-HVR1200 (PCIe, OEM, half height) 1205 * DVB-T and basic analog */ 1206 case 71949: 1207 /* WinTV-HVR1200 (PCIe, OEM, full height) 1208 * DVB-T and basic analog */ 1209 case 71959: 1210 /* WinTV-HVR1200 (PCIe, OEM, full height) 1211 * DVB-T and basic analog */ 1212 case 71979: 1213 /* WinTV-HVR1200 (PCIe, OEM, half height) 1214 * DVB-T and basic analog */ 1215 case 71999: 1216 /* WinTV-HVR1200 (PCIe, OEM, full height) 1217 * DVB-T and basic analog */ 1218 case 76601: 1219 /* WinTV-HVR1800lp (PCIe, Retail, No IR, Dual 1220 channel ATSC and MPEG2 HW Encoder */ 1221 case 77001: 1222 /* WinTV-HVR1500 (Express Card, OEM, No IR, ATSC 1223 and Basic analog */ 1224 case 77011: 1225 /* WinTV-HVR1500 (Express Card, Retail, No IR, ATSC 1226 and Basic analog */ 1227 case 77041: 1228 /* WinTV-HVR1500Q (Express Card, OEM, No IR, ATSC/QAM 1229 and Basic analog */ 1230 case 77051: 1231 /* WinTV-HVR1500Q (Express Card, Retail, No IR, ATSC/QAM 1232 and Basic analog */ 1233 case 78011: 1234 /* WinTV-HVR1800 (PCIe, Retail, 3.5mm in, IR, No FM, 1235 Dual channel ATSC and MPEG2 HW Encoder */ 1236 case 78501: 1237 /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM, 1238 Dual channel ATSC and MPEG2 HW Encoder */ 1239 case 78521: 1240 /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM, 1241 Dual channel ATSC and MPEG2 HW Encoder */ 1242 case 78531: 1243 /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, No FM, 1244 Dual channel ATSC and MPEG2 HW Encoder */ 1245 case 78631: 1246 /* WinTV-HVR1800 (PCIe, OEM, No IR, No FM, 1247 Dual channel ATSC and MPEG2 HW Encoder */ 1248 case 79001: 1249 /* WinTV-HVR1250 (PCIe, Retail, IR, full height, 1250 ATSC and Basic analog */ 1251 case 79101: 1252 /* WinTV-HVR1250 (PCIe, Retail, IR, half height, 1253 ATSC and Basic analog */ 1254 case 79501: 1255 /* WinTV-HVR1250 (PCIe, No IR, half height, 1256 ATSC [at least] and Basic analog) */ 1257 case 79561: 1258 /* WinTV-HVR1250 (PCIe, OEM, No IR, half height, 1259 ATSC and Basic analog */ 1260 case 79571: 1261 /* WinTV-HVR1250 (PCIe, OEM, No IR, full height, 1262 ATSC and Basic analog */ 1263 case 79671: 1264 /* WinTV-HVR1250 (PCIe, OEM, No IR, half height, 1265 ATSC and Basic analog */ 1266 case 80019: 1267 /* WinTV-HVR1400 (Express Card, Retail, IR, 1268 * DVB-T and Basic analog */ 1269 case 81509: 1270 /* WinTV-HVR1700 (PCIe, OEM, No IR, half height) 1271 * DVB-T and MPEG2 HW Encoder */ 1272 case 81519: 1273 /* WinTV-HVR1700 (PCIe, OEM, No IR, full height) 1274 * DVB-T and MPEG2 HW Encoder */ 1275 break; 1276 case 85021: 1277 /* WinTV-HVR1850 (PCIe, Retail, 3.5mm in, IR, FM, 1278 Dual channel ATSC and MPEG2 HW Encoder */ 1279 break; 1280 case 85721: 1281 /* WinTV-HVR1290 (PCIe, OEM, RCA in, IR, 1282 Dual channel ATSC and Basic analog */ 1283 case 150329: 1284 /* WinTV-HVR5525 (PCIe, DVB-S/S2, DVB-T/T2/C) */ 1285 break; 1286 case 166100: 1287 /* WinTV-QuadHD (DVB) Tuner Pair 1 (PCIe, IR, half height, 1288 DVB-T/T2/C, DVB-T/T2/C */ 1289 break; 1290 case 166101: 1291 /* WinTV-QuadHD (DVB) Tuner Pair 2 (PCIe, IR, half height, 1292 DVB-T/T2/C, DVB-T/T2/C */ 1293 break; 1294 case 165100: 1295 /* 1296 * WinTV-QuadHD (ATSC) Tuner Pair 1 (PCIe, IR, half height, 1297 * ATSC, ATSC 1298 */ 1299 break; 1300 case 165101: 1301 /* 1302 * WinTV-QuadHD (DVB) Tuner Pair 2 (PCIe, IR, half height, 1303 * ATSC, ATSC 1304 */ 1305 break; 1306 default: 1307 printk(KERN_WARNING "%s: warning: unknown hauppauge model #%d\n", 1308 dev->name, tv.model); 1309 break; 1310 } 1311 1312 printk(KERN_INFO "%s: hauppauge eeprom: model=%d\n", 1313 dev->name, tv.model); 1314 } 1315 1316 /* Some TBS cards require initing a chip using a bitbanged SPI attached 1317 to the cx23885 gpio's. If this chip doesn't get init'ed the demod 1318 doesn't respond to any command. */ 1319 static void tbs_card_init(struct cx23885_dev *dev) 1320 { 1321 int i; 1322 const u8 buf[] = { 1323 0xe0, 0x06, 0x66, 0x33, 0x65, 1324 0x01, 0x17, 0x06, 0xde}; 1325 1326 switch (dev->board) { 1327 case CX23885_BOARD_TBS_6980: 1328 case CX23885_BOARD_TBS_6981: 1329 cx_set(GP0_IO, 0x00070007); 1330 usleep_range(1000, 10000); 1331 cx_clear(GP0_IO, 2); 1332 usleep_range(1000, 10000); 1333 for (i = 0; i < 9 * 8; i++) { 1334 cx_clear(GP0_IO, 7); 1335 usleep_range(1000, 10000); 1336 cx_set(GP0_IO, 1337 ((buf[i >> 3] >> (7 - (i & 7))) & 1) | 4); 1338 usleep_range(1000, 10000); 1339 } 1340 cx_set(GP0_IO, 7); 1341 break; 1342 } 1343 } 1344 1345 int cx23885_tuner_callback(void *priv, int component, int command, int arg) 1346 { 1347 struct cx23885_tsport *port = priv; 1348 struct cx23885_dev *dev = port->dev; 1349 u32 bitmask = 0; 1350 1351 if ((command == XC2028_RESET_CLK) || (command == XC2028_I2C_FLUSH)) 1352 return 0; 1353 1354 if (command != 0) { 1355 printk(KERN_ERR "%s(): Unknown command 0x%x.\n", 1356 __func__, command); 1357 return -EINVAL; 1358 } 1359 1360 switch (dev->board) { 1361 case CX23885_BOARD_HAUPPAUGE_HVR1400: 1362 case CX23885_BOARD_HAUPPAUGE_HVR1500: 1363 case CX23885_BOARD_HAUPPAUGE_HVR1500Q: 1364 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H: 1365 case CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200: 1366 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000: 1367 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F: 1368 case CX23885_BOARD_COMPRO_VIDEOMATE_E800: 1369 case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200: 1370 /* Tuner Reset Command */ 1371 bitmask = 0x04; 1372 break; 1373 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP: 1374 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: 1375 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2: 1376 /* Two identical tuners on two different i2c buses, 1377 * we need to reset the correct gpio. */ 1378 if (port->nr == 1) 1379 bitmask = 0x01; 1380 else if (port->nr == 2) 1381 bitmask = 0x04; 1382 break; 1383 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID: 1384 /* Tuner Reset Command */ 1385 bitmask = 0x02; 1386 break; 1387 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: 1388 altera_ci_tuner_reset(dev, port->nr); 1389 break; 1390 case CX23885_BOARD_AVERMEDIA_HC81R: 1391 /* XC3028L Reset Command */ 1392 bitmask = 1 << 2; 1393 break; 1394 } 1395 1396 if (bitmask) { 1397 /* Drive the tuner into reset and back out */ 1398 cx_clear(GP0_IO, bitmask); 1399 mdelay(200); 1400 cx_set(GP0_IO, bitmask); 1401 } 1402 1403 return 0; 1404 } 1405 1406 void cx23885_gpio_setup(struct cx23885_dev *dev) 1407 { 1408 switch (dev->board) { 1409 case CX23885_BOARD_HAUPPAUGE_HVR1250: 1410 /* GPIO-0 cx24227 demodulator reset */ 1411 cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */ 1412 break; 1413 case CX23885_BOARD_HAUPPAUGE_HVR1500: 1414 /* GPIO-0 cx24227 demodulator */ 1415 /* GPIO-2 xc3028 tuner */ 1416 1417 /* Put the parts into reset */ 1418 cx_set(GP0_IO, 0x00050000); 1419 cx_clear(GP0_IO, 0x00000005); 1420 msleep(5); 1421 1422 /* Bring the parts out of reset */ 1423 cx_set(GP0_IO, 0x00050005); 1424 break; 1425 case CX23885_BOARD_HAUPPAUGE_HVR1500Q: 1426 /* GPIO-0 cx24227 demodulator reset */ 1427 /* GPIO-2 xc5000 tuner reset */ 1428 cx_set(GP0_IO, 0x00050005); /* Bring the part out of reset */ 1429 break; 1430 case CX23885_BOARD_HAUPPAUGE_HVR1800: 1431 /* GPIO-0 656_CLK */ 1432 /* GPIO-1 656_D0 */ 1433 /* GPIO-2 8295A Reset */ 1434 /* GPIO-3-10 cx23417 data0-7 */ 1435 /* GPIO-11-14 cx23417 addr0-3 */ 1436 /* GPIO-15-18 cx23417 READY, CS, RD, WR */ 1437 /* GPIO-19 IR_RX */ 1438 1439 /* CX23417 GPIO's */ 1440 /* EIO15 Zilog Reset */ 1441 /* EIO14 S5H1409/CX24227 Reset */ 1442 mc417_gpio_enable(dev, GPIO_15 | GPIO_14, 1); 1443 1444 /* Put the demod into reset and protect the eeprom */ 1445 mc417_gpio_clear(dev, GPIO_15 | GPIO_14); 1446 mdelay(100); 1447 1448 /* Bring the demod and blaster out of reset */ 1449 mc417_gpio_set(dev, GPIO_15 | GPIO_14); 1450 mdelay(100); 1451 1452 /* Force the TDA8295A into reset and back */ 1453 cx23885_gpio_enable(dev, GPIO_2, 1); 1454 cx23885_gpio_set(dev, GPIO_2); 1455 mdelay(20); 1456 cx23885_gpio_clear(dev, GPIO_2); 1457 mdelay(20); 1458 cx23885_gpio_set(dev, GPIO_2); 1459 mdelay(20); 1460 break; 1461 case CX23885_BOARD_HAUPPAUGE_HVR1200: 1462 /* GPIO-0 tda10048 demodulator reset */ 1463 /* GPIO-2 tda18271 tuner reset */ 1464 1465 /* Put the parts into reset and back */ 1466 cx_set(GP0_IO, 0x00050000); 1467 mdelay(20); 1468 cx_clear(GP0_IO, 0x00000005); 1469 mdelay(20); 1470 cx_set(GP0_IO, 0x00050005); 1471 break; 1472 case CX23885_BOARD_HAUPPAUGE_HVR1700: 1473 /* GPIO-0 TDA10048 demodulator reset */ 1474 /* GPIO-2 TDA8295A Reset */ 1475 /* GPIO-3-10 cx23417 data0-7 */ 1476 /* GPIO-11-14 cx23417 addr0-3 */ 1477 /* GPIO-15-18 cx23417 READY, CS, RD, WR */ 1478 1479 /* The following GPIO's are on the interna AVCore (cx25840) */ 1480 /* GPIO-19 IR_RX */ 1481 /* GPIO-20 IR_TX 416/DVBT Select */ 1482 /* GPIO-21 IIS DAT */ 1483 /* GPIO-22 IIS WCLK */ 1484 /* GPIO-23 IIS BCLK */ 1485 1486 /* Put the parts into reset and back */ 1487 cx_set(GP0_IO, 0x00050000); 1488 mdelay(20); 1489 cx_clear(GP0_IO, 0x00000005); 1490 mdelay(20); 1491 cx_set(GP0_IO, 0x00050005); 1492 break; 1493 case CX23885_BOARD_HAUPPAUGE_HVR1400: 1494 /* GPIO-0 Dibcom7000p demodulator reset */ 1495 /* GPIO-2 xc3028L tuner reset */ 1496 /* GPIO-13 LED */ 1497 1498 /* Put the parts into reset and back */ 1499 cx_set(GP0_IO, 0x00050000); 1500 mdelay(20); 1501 cx_clear(GP0_IO, 0x00000005); 1502 mdelay(20); 1503 cx_set(GP0_IO, 0x00050005); 1504 break; 1505 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP: 1506 /* GPIO-0 xc5000 tuner reset i2c bus 0 */ 1507 /* GPIO-1 s5h1409 demod reset i2c bus 0 */ 1508 /* GPIO-2 xc5000 tuner reset i2c bus 1 */ 1509 /* GPIO-3 s5h1409 demod reset i2c bus 0 */ 1510 1511 /* Put the parts into reset and back */ 1512 cx_set(GP0_IO, 0x000f0000); 1513 mdelay(20); 1514 cx_clear(GP0_IO, 0x0000000f); 1515 mdelay(20); 1516 cx_set(GP0_IO, 0x000f000f); 1517 break; 1518 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: 1519 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2: 1520 /* GPIO-0 portb xc3028 reset */ 1521 /* GPIO-1 portb zl10353 reset */ 1522 /* GPIO-2 portc xc3028 reset */ 1523 /* GPIO-3 portc zl10353 reset */ 1524 1525 /* Put the parts into reset and back */ 1526 cx_set(GP0_IO, 0x000f0000); 1527 mdelay(20); 1528 cx_clear(GP0_IO, 0x0000000f); 1529 mdelay(20); 1530 cx_set(GP0_IO, 0x000f000f); 1531 break; 1532 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H: 1533 case CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200: 1534 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000: 1535 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F: 1536 case CX23885_BOARD_COMPRO_VIDEOMATE_E800: 1537 case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200: 1538 /* GPIO-2 xc3028 tuner reset */ 1539 1540 /* The following GPIO's are on the internal AVCore (cx25840) */ 1541 /* GPIO-? zl10353 demod reset */ 1542 1543 /* Put the parts into reset and back */ 1544 cx_set(GP0_IO, 0x00040000); 1545 mdelay(20); 1546 cx_clear(GP0_IO, 0x00000004); 1547 mdelay(20); 1548 cx_set(GP0_IO, 0x00040004); 1549 break; 1550 case CX23885_BOARD_TBS_6920: 1551 case CX23885_BOARD_TBS_6980: 1552 case CX23885_BOARD_TBS_6981: 1553 case CX23885_BOARD_PROF_8000: 1554 cx_write(MC417_CTL, 0x00000036); 1555 cx_write(MC417_OEN, 0x00001000); 1556 cx_set(MC417_RWD, 0x00000002); 1557 mdelay(200); 1558 cx_clear(MC417_RWD, 0x00000800); 1559 mdelay(200); 1560 cx_set(MC417_RWD, 0x00000800); 1561 mdelay(200); 1562 break; 1563 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: 1564 /* GPIO-0 INTA from CiMax1 1565 GPIO-1 INTB from CiMax2 1566 GPIO-2 reset chips 1567 GPIO-3 to GPIO-10 data/addr for CA 1568 GPIO-11 ~CS0 to CiMax1 1569 GPIO-12 ~CS1 to CiMax2 1570 GPIO-13 ADL0 load LSB addr 1571 GPIO-14 ADL1 load MSB addr 1572 GPIO-15 ~RDY from CiMax 1573 GPIO-17 ~RD to CiMax 1574 GPIO-18 ~WR to CiMax 1575 */ 1576 cx_set(GP0_IO, 0x00040000); /* GPIO as out */ 1577 /* GPIO1 and GPIO2 as INTA and INTB from CiMaxes, reset low */ 1578 cx_clear(GP0_IO, 0x00030004); 1579 mdelay(100);/* reset delay */ 1580 cx_set(GP0_IO, 0x00040004); /* GPIO as out, reset high */ 1581 cx_write(MC417_CTL, 0x00000037);/* enable GPIO3-18 pins */ 1582 /* GPIO-15 IN as ~ACK, rest as OUT */ 1583 cx_write(MC417_OEN, 0x00001000); 1584 /* ~RD, ~WR high; ADL0, ADL1 low; ~CS0, ~CS1 high */ 1585 cx_write(MC417_RWD, 0x0000c300); 1586 /* enable irq */ 1587 cx_write(GPIO_ISM, 0x00000000);/* INTERRUPTS active low*/ 1588 break; 1589 case CX23885_BOARD_HAUPPAUGE_HVR1270: 1590 case CX23885_BOARD_HAUPPAUGE_HVR1275: 1591 case CX23885_BOARD_HAUPPAUGE_HVR1255: 1592 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111: 1593 case CX23885_BOARD_HAUPPAUGE_HVR1210: 1594 /* GPIO-5 RF Control: 0 = RF1 Terrestrial, 1 = RF2 Cable */ 1595 /* GPIO-6 I2C Gate which can isolate the demod from the bus */ 1596 /* GPIO-9 Demod reset */ 1597 1598 /* Put the parts into reset and back */ 1599 cx23885_gpio_enable(dev, GPIO_9 | GPIO_6 | GPIO_5, 1); 1600 cx23885_gpio_set(dev, GPIO_9 | GPIO_6 | GPIO_5); 1601 cx23885_gpio_clear(dev, GPIO_9); 1602 mdelay(20); 1603 cx23885_gpio_set(dev, GPIO_9); 1604 break; 1605 case CX23885_BOARD_MYGICA_X8506: 1606 case CX23885_BOARD_MAGICPRO_PROHDTVE2: 1607 case CX23885_BOARD_MYGICA_X8507: 1608 /* GPIO-0 (0)Analog / (1)Digital TV */ 1609 /* GPIO-1 reset XC5000 */ 1610 /* GPIO-2 demod reset */ 1611 cx23885_gpio_enable(dev, GPIO_0 | GPIO_1 | GPIO_2, 1); 1612 cx23885_gpio_clear(dev, GPIO_1 | GPIO_2); 1613 mdelay(100); 1614 cx23885_gpio_set(dev, GPIO_0 | GPIO_1 | GPIO_2); 1615 mdelay(100); 1616 break; 1617 case CX23885_BOARD_MYGICA_X8558PRO: 1618 /* GPIO-0 reset first ATBM8830 */ 1619 /* GPIO-1 reset second ATBM8830 */ 1620 cx23885_gpio_enable(dev, GPIO_0 | GPIO_1, 1); 1621 cx23885_gpio_clear(dev, GPIO_0 | GPIO_1); 1622 mdelay(100); 1623 cx23885_gpio_set(dev, GPIO_0 | GPIO_1); 1624 mdelay(100); 1625 break; 1626 case CX23885_BOARD_HAUPPAUGE_HVR1850: 1627 case CX23885_BOARD_HAUPPAUGE_HVR1290: 1628 /* GPIO-0 656_CLK */ 1629 /* GPIO-1 656_D0 */ 1630 /* GPIO-2 Wake# */ 1631 /* GPIO-3-10 cx23417 data0-7 */ 1632 /* GPIO-11-14 cx23417 addr0-3 */ 1633 /* GPIO-15-18 cx23417 READY, CS, RD, WR */ 1634 /* GPIO-19 IR_RX */ 1635 /* GPIO-20 C_IR_TX */ 1636 /* GPIO-21 I2S DAT */ 1637 /* GPIO-22 I2S WCLK */ 1638 /* GPIO-23 I2S BCLK */ 1639 /* ALT GPIO: EXP GPIO LATCH */ 1640 1641 /* CX23417 GPIO's */ 1642 /* GPIO-14 S5H1411/CX24228 Reset */ 1643 /* GPIO-13 EEPROM write protect */ 1644 mc417_gpio_enable(dev, GPIO_14 | GPIO_13, 1); 1645 1646 /* Put the demod into reset and protect the eeprom */ 1647 mc417_gpio_clear(dev, GPIO_14 | GPIO_13); 1648 mdelay(100); 1649 1650 /* Bring the demod out of reset */ 1651 mc417_gpio_set(dev, GPIO_14); 1652 mdelay(100); 1653 1654 /* CX24228 GPIO */ 1655 /* Connected to IF / Mux */ 1656 break; 1657 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID: 1658 cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */ 1659 break; 1660 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: 1661 /* GPIO-0 ~INT in 1662 GPIO-1 TMS out 1663 GPIO-2 ~reset chips out 1664 GPIO-3 to GPIO-10 data/addr for CA in/out 1665 GPIO-11 ~CS out 1666 GPIO-12 ADDR out 1667 GPIO-13 ~WR out 1668 GPIO-14 ~RD out 1669 GPIO-15 ~RDY in 1670 GPIO-16 TCK out 1671 GPIO-17 TDO in 1672 GPIO-18 TDI out 1673 */ 1674 cx_set(GP0_IO, 0x00060000); /* GPIO-1,2 as out */ 1675 /* GPIO-0 as INT, reset & TMS low */ 1676 cx_clear(GP0_IO, 0x00010006); 1677 mdelay(100);/* reset delay */ 1678 cx_set(GP0_IO, 0x00000004); /* reset high */ 1679 cx_write(MC417_CTL, 0x00000037);/* enable GPIO-3..18 pins */ 1680 /* GPIO-17 is TDO in, GPIO-15 is ~RDY in, rest is out */ 1681 cx_write(MC417_OEN, 0x00005000); 1682 /* ~RD, ~WR high; ADDR low; ~CS high */ 1683 cx_write(MC417_RWD, 0x00000d00); 1684 /* enable irq */ 1685 cx_write(GPIO_ISM, 0x00000000);/* INTERRUPTS active low*/ 1686 break; 1687 case CX23885_BOARD_HAUPPAUGE_HVR4400: 1688 case CX23885_BOARD_HAUPPAUGE_STARBURST: 1689 /* GPIO-8 tda10071 demod reset */ 1690 /* GPIO-9 si2165 demod reset (only HVR4400/HVR5500)*/ 1691 1692 /* Put the parts into reset and back */ 1693 cx23885_gpio_enable(dev, GPIO_8 | GPIO_9, 1); 1694 1695 cx23885_gpio_clear(dev, GPIO_8 | GPIO_9); 1696 mdelay(100); 1697 cx23885_gpio_set(dev, GPIO_8 | GPIO_9); 1698 mdelay(100); 1699 1700 break; 1701 case CX23885_BOARD_AVERMEDIA_HC81R: 1702 cx_clear(MC417_CTL, 1); 1703 /* GPIO-0,1,2 setup direction as output */ 1704 cx_set(GP0_IO, 0x00070000); 1705 mdelay(10); 1706 /* AF9013 demod reset */ 1707 cx_set(GP0_IO, 0x00010001); 1708 mdelay(10); 1709 cx_clear(GP0_IO, 0x00010001); 1710 mdelay(10); 1711 cx_set(GP0_IO, 0x00010001); 1712 mdelay(10); 1713 /* demod tune? */ 1714 cx_clear(GP0_IO, 0x00030003); 1715 mdelay(10); 1716 cx_set(GP0_IO, 0x00020002); 1717 mdelay(10); 1718 cx_set(GP0_IO, 0x00010001); 1719 mdelay(10); 1720 cx_clear(GP0_IO, 0x00020002); 1721 /* XC3028L tuner reset */ 1722 cx_set(GP0_IO, 0x00040004); 1723 cx_clear(GP0_IO, 0x00040004); 1724 cx_set(GP0_IO, 0x00040004); 1725 mdelay(60); 1726 break; 1727 case CX23885_BOARD_DVBSKY_T9580: 1728 case CX23885_BOARD_DVBSKY_S952: 1729 case CX23885_BOARD_DVBSKY_T982: 1730 /* enable GPIO3-18 pins */ 1731 cx_write(MC417_CTL, 0x00000037); 1732 cx23885_gpio_enable(dev, GPIO_2 | GPIO_11, 1); 1733 cx23885_gpio_clear(dev, GPIO_2 | GPIO_11); 1734 mdelay(100); 1735 cx23885_gpio_set(dev, GPIO_2 | GPIO_11); 1736 break; 1737 case CX23885_BOARD_DVBSKY_T980C: 1738 case CX23885_BOARD_DVBSKY_S950C: 1739 case CX23885_BOARD_TT_CT2_4500_CI: 1740 /* 1741 * GPIO-0 INTA from CiMax, input 1742 * GPIO-1 reset CiMax, output, high active 1743 * GPIO-2 reset demod, output, low active 1744 * GPIO-3 to GPIO-10 data/addr for CAM 1745 * GPIO-11 ~CS0 to CiMax1 1746 * GPIO-12 ~CS1 to CiMax2 1747 * GPIO-13 ADL0 load LSB addr 1748 * GPIO-14 ADL1 load MSB addr 1749 * GPIO-15 ~RDY from CiMax 1750 * GPIO-17 ~RD to CiMax 1751 * GPIO-18 ~WR to CiMax 1752 */ 1753 1754 cx_set(GP0_IO, 0x00060002); /* GPIO 1/2 as output */ 1755 cx_clear(GP0_IO, 0x00010004); /* GPIO 0 as input */ 1756 mdelay(100); /* reset delay */ 1757 cx_set(GP0_IO, 0x00060004); /* GPIO as out, reset high */ 1758 cx_clear(GP0_IO, 0x00010002); 1759 cx_write(MC417_CTL, 0x00000037); /* enable GPIO3-18 pins */ 1760 1761 /* GPIO-15 IN as ~ACK, rest as OUT */ 1762 cx_write(MC417_OEN, 0x00001000); 1763 1764 /* ~RD, ~WR high; ADL0, ADL1 low; ~CS0, ~CS1 high */ 1765 cx_write(MC417_RWD, 0x0000c300); 1766 1767 /* enable irq */ 1768 cx_write(GPIO_ISM, 0x00000000); /* INTERRUPTS active low */ 1769 break; 1770 case CX23885_BOARD_DVBSKY_S950: 1771 cx23885_gpio_enable(dev, GPIO_2, 1); 1772 cx23885_gpio_clear(dev, GPIO_2); 1773 msleep(100); 1774 cx23885_gpio_set(dev, GPIO_2); 1775 break; 1776 case CX23885_BOARD_HAUPPAUGE_HVR5525: 1777 case CX23885_BOARD_HAUPPAUGE_QUADHD_DVB: 1778 case CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC: 1779 /* 1780 * HVR5525 GPIO Details: 1781 * GPIO-00 IR_WIDE 1782 * GPIO-02 wake# 1783 * GPIO-03 VAUX Pres. 1784 * GPIO-07 PROG# 1785 * GPIO-08 SAT_RESN 1786 * GPIO-09 TER_RESN 1787 * GPIO-10 B2_SENSE 1788 * GPIO-11 B1_SENSE 1789 * GPIO-15 IR_LED_STATUS 1790 * GPIO-19 IR_NARROW 1791 * GPIO-20 Blauster1 1792 * ALTGPIO VAUX_SWITCH 1793 * AUX_PLL_CLK : Blaster2 1794 */ 1795 /* Put the parts into reset and back */ 1796 cx23885_gpio_enable(dev, GPIO_8 | GPIO_9, 1); 1797 cx23885_gpio_clear(dev, GPIO_8 | GPIO_9); 1798 msleep(100); 1799 cx23885_gpio_set(dev, GPIO_8 | GPIO_9); 1800 msleep(100); 1801 break; 1802 case CX23885_BOARD_VIEWCAST_260E: 1803 case CX23885_BOARD_VIEWCAST_460E: 1804 /* For documentation purposes, it's worth noting that this 1805 * card does not have any GPIO's connected to subcomponents. 1806 */ 1807 break; 1808 } 1809 } 1810 1811 int cx23885_ir_init(struct cx23885_dev *dev) 1812 { 1813 static struct v4l2_subdev_io_pin_config ir_rxtx_pin_cfg[] = { 1814 { 1815 .flags = V4L2_SUBDEV_IO_PIN_INPUT, 1816 .pin = CX23885_PIN_IR_RX_GPIO19, 1817 .function = CX23885_PAD_IR_RX, 1818 .value = 0, 1819 .strength = CX25840_PIN_DRIVE_MEDIUM, 1820 }, { 1821 .flags = V4L2_SUBDEV_IO_PIN_OUTPUT, 1822 .pin = CX23885_PIN_IR_TX_GPIO20, 1823 .function = CX23885_PAD_IR_TX, 1824 .value = 0, 1825 .strength = CX25840_PIN_DRIVE_MEDIUM, 1826 } 1827 }; 1828 const size_t ir_rxtx_pin_cfg_count = ARRAY_SIZE(ir_rxtx_pin_cfg); 1829 1830 static struct v4l2_subdev_io_pin_config ir_rx_pin_cfg[] = { 1831 { 1832 .flags = V4L2_SUBDEV_IO_PIN_INPUT, 1833 .pin = CX23885_PIN_IR_RX_GPIO19, 1834 .function = CX23885_PAD_IR_RX, 1835 .value = 0, 1836 .strength = CX25840_PIN_DRIVE_MEDIUM, 1837 } 1838 }; 1839 const size_t ir_rx_pin_cfg_count = ARRAY_SIZE(ir_rx_pin_cfg); 1840 1841 struct v4l2_subdev_ir_parameters params; 1842 int ret = 0; 1843 switch (dev->board) { 1844 case CX23885_BOARD_HAUPPAUGE_HVR1500: 1845 case CX23885_BOARD_HAUPPAUGE_HVR1500Q: 1846 case CX23885_BOARD_HAUPPAUGE_HVR1800: 1847 case CX23885_BOARD_HAUPPAUGE_HVR1200: 1848 case CX23885_BOARD_HAUPPAUGE_HVR1400: 1849 case CX23885_BOARD_HAUPPAUGE_HVR1275: 1850 case CX23885_BOARD_HAUPPAUGE_HVR1255: 1851 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111: 1852 case CX23885_BOARD_HAUPPAUGE_HVR1210: 1853 case CX23885_BOARD_HAUPPAUGE_QUADHD_DVB: 1854 case CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC: 1855 /* FIXME: Implement me */ 1856 break; 1857 case CX23885_BOARD_HAUPPAUGE_HVR1270: 1858 ret = cx23888_ir_probe(dev); 1859 if (ret) 1860 break; 1861 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_888_IR); 1862 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config, 1863 ir_rx_pin_cfg_count, ir_rx_pin_cfg); 1864 break; 1865 case CX23885_BOARD_HAUPPAUGE_HVR1850: 1866 case CX23885_BOARD_HAUPPAUGE_HVR1290: 1867 ret = cx23888_ir_probe(dev); 1868 if (ret) 1869 break; 1870 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_888_IR); 1871 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config, 1872 ir_rxtx_pin_cfg_count, ir_rxtx_pin_cfg); 1873 /* 1874 * For these boards we need to invert the Tx output via the 1875 * IR controller to have the LED off while idle 1876 */ 1877 v4l2_subdev_call(dev->sd_ir, ir, tx_g_parameters, ¶ms); 1878 params.enable = false; 1879 params.shutdown = false; 1880 params.invert_level = true; 1881 v4l2_subdev_call(dev->sd_ir, ir, tx_s_parameters, ¶ms); 1882 params.shutdown = true; 1883 v4l2_subdev_call(dev->sd_ir, ir, tx_s_parameters, ¶ms); 1884 break; 1885 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL: 1886 case CX23885_BOARD_TEVII_S470: 1887 case CX23885_BOARD_MYGICA_X8507: 1888 case CX23885_BOARD_TBS_6980: 1889 case CX23885_BOARD_TBS_6981: 1890 case CX23885_BOARD_DVBSKY_T9580: 1891 case CX23885_BOARD_DVBSKY_T980C: 1892 case CX23885_BOARD_DVBSKY_S950C: 1893 case CX23885_BOARD_TT_CT2_4500_CI: 1894 case CX23885_BOARD_DVBSKY_S950: 1895 case CX23885_BOARD_DVBSKY_S952: 1896 case CX23885_BOARD_DVBSKY_T982: 1897 if (!enable_885_ir) 1898 break; 1899 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_AV_CORE); 1900 if (dev->sd_ir == NULL) { 1901 ret = -ENODEV; 1902 break; 1903 } 1904 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config, 1905 ir_rx_pin_cfg_count, ir_rx_pin_cfg); 1906 break; 1907 case CX23885_BOARD_HAUPPAUGE_HVR1250: 1908 if (!enable_885_ir) 1909 break; 1910 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_AV_CORE); 1911 if (dev->sd_ir == NULL) { 1912 ret = -ENODEV; 1913 break; 1914 } 1915 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config, 1916 ir_rxtx_pin_cfg_count, ir_rxtx_pin_cfg); 1917 break; 1918 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: 1919 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2: 1920 request_module("ir-kbd-i2c"); 1921 break; 1922 } 1923 1924 return ret; 1925 } 1926 1927 void cx23885_ir_fini(struct cx23885_dev *dev) 1928 { 1929 switch (dev->board) { 1930 case CX23885_BOARD_HAUPPAUGE_HVR1270: 1931 case CX23885_BOARD_HAUPPAUGE_HVR1850: 1932 case CX23885_BOARD_HAUPPAUGE_HVR1290: 1933 cx23885_irq_remove(dev, PCI_MSK_IR); 1934 cx23888_ir_remove(dev); 1935 dev->sd_ir = NULL; 1936 break; 1937 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL: 1938 case CX23885_BOARD_TEVII_S470: 1939 case CX23885_BOARD_HAUPPAUGE_HVR1250: 1940 case CX23885_BOARD_MYGICA_X8507: 1941 case CX23885_BOARD_TBS_6980: 1942 case CX23885_BOARD_TBS_6981: 1943 case CX23885_BOARD_DVBSKY_T9580: 1944 case CX23885_BOARD_DVBSKY_T980C: 1945 case CX23885_BOARD_DVBSKY_S950C: 1946 case CX23885_BOARD_TT_CT2_4500_CI: 1947 case CX23885_BOARD_DVBSKY_S950: 1948 case CX23885_BOARD_DVBSKY_S952: 1949 case CX23885_BOARD_DVBSKY_T982: 1950 cx23885_irq_remove(dev, PCI_MSK_AV_CORE); 1951 /* sd_ir is a duplicate pointer to the AV Core, just clear it */ 1952 dev->sd_ir = NULL; 1953 break; 1954 } 1955 } 1956 1957 static int netup_jtag_io(void *device, int tms, int tdi, int read_tdo) 1958 { 1959 int data; 1960 int tdo = 0; 1961 struct cx23885_dev *dev = (struct cx23885_dev *)device; 1962 /*TMS*/ 1963 data = ((cx_read(GP0_IO)) & (~0x00000002)); 1964 data |= (tms ? 0x00020002 : 0x00020000); 1965 cx_write(GP0_IO, data); 1966 1967 /*TDI*/ 1968 data = ((cx_read(MC417_RWD)) & (~0x0000a000)); 1969 data |= (tdi ? 0x00008000 : 0); 1970 cx_write(MC417_RWD, data); 1971 if (read_tdo) 1972 tdo = (data & 0x00004000) ? 1 : 0; /*TDO*/ 1973 1974 cx_write(MC417_RWD, data | 0x00002000); 1975 udelay(1); 1976 /*TCK*/ 1977 cx_write(MC417_RWD, data); 1978 1979 return tdo; 1980 } 1981 1982 void cx23885_ir_pci_int_enable(struct cx23885_dev *dev) 1983 { 1984 switch (dev->board) { 1985 case CX23885_BOARD_HAUPPAUGE_HVR1270: 1986 case CX23885_BOARD_HAUPPAUGE_HVR1850: 1987 case CX23885_BOARD_HAUPPAUGE_HVR1290: 1988 if (dev->sd_ir) 1989 cx23885_irq_add_enable(dev, PCI_MSK_IR); 1990 break; 1991 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL: 1992 case CX23885_BOARD_TEVII_S470: 1993 case CX23885_BOARD_HAUPPAUGE_HVR1250: 1994 case CX23885_BOARD_MYGICA_X8507: 1995 case CX23885_BOARD_TBS_6980: 1996 case CX23885_BOARD_TBS_6981: 1997 case CX23885_BOARD_DVBSKY_T9580: 1998 case CX23885_BOARD_DVBSKY_T980C: 1999 case CX23885_BOARD_DVBSKY_S950C: 2000 case CX23885_BOARD_TT_CT2_4500_CI: 2001 case CX23885_BOARD_DVBSKY_S950: 2002 case CX23885_BOARD_DVBSKY_S952: 2003 case CX23885_BOARD_DVBSKY_T982: 2004 if (dev->sd_ir) 2005 cx23885_irq_add_enable(dev, PCI_MSK_AV_CORE); 2006 break; 2007 } 2008 } 2009 2010 void cx23885_card_setup(struct cx23885_dev *dev) 2011 { 2012 struct cx23885_tsport *ts1 = &dev->ts1; 2013 struct cx23885_tsport *ts2 = &dev->ts2; 2014 2015 static u8 eeprom[256]; 2016 2017 if (dev->i2c_bus[0].i2c_rc == 0) { 2018 dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1; 2019 tveeprom_read(&dev->i2c_bus[0].i2c_client, 2020 eeprom, sizeof(eeprom)); 2021 } 2022 2023 switch (dev->board) { 2024 case CX23885_BOARD_HAUPPAUGE_HVR1250: 2025 if (dev->i2c_bus[0].i2c_rc == 0) { 2026 if (eeprom[0x80] != 0x84) 2027 hauppauge_eeprom(dev, eeprom+0xc0); 2028 else 2029 hauppauge_eeprom(dev, eeprom+0x80); 2030 } 2031 break; 2032 case CX23885_BOARD_HAUPPAUGE_HVR1500: 2033 case CX23885_BOARD_HAUPPAUGE_HVR1500Q: 2034 case CX23885_BOARD_HAUPPAUGE_HVR1400: 2035 if (dev->i2c_bus[0].i2c_rc == 0) 2036 hauppauge_eeprom(dev, eeprom+0x80); 2037 break; 2038 case CX23885_BOARD_HAUPPAUGE_HVR1800: 2039 case CX23885_BOARD_HAUPPAUGE_HVR1800lp: 2040 case CX23885_BOARD_HAUPPAUGE_HVR1200: 2041 case CX23885_BOARD_HAUPPAUGE_HVR1700: 2042 case CX23885_BOARD_HAUPPAUGE_HVR1270: 2043 case CX23885_BOARD_HAUPPAUGE_HVR1275: 2044 case CX23885_BOARD_HAUPPAUGE_HVR1255: 2045 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111: 2046 case CX23885_BOARD_HAUPPAUGE_HVR1210: 2047 case CX23885_BOARD_HAUPPAUGE_HVR1850: 2048 case CX23885_BOARD_HAUPPAUGE_HVR1290: 2049 case CX23885_BOARD_HAUPPAUGE_HVR4400: 2050 case CX23885_BOARD_HAUPPAUGE_STARBURST: 2051 case CX23885_BOARD_HAUPPAUGE_IMPACTVCBE: 2052 case CX23885_BOARD_HAUPPAUGE_HVR5525: 2053 case CX23885_BOARD_HAUPPAUGE_QUADHD_DVB: 2054 case CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC: 2055 if (dev->i2c_bus[0].i2c_rc == 0) 2056 hauppauge_eeprom(dev, eeprom+0xc0); 2057 break; 2058 case CX23885_BOARD_VIEWCAST_260E: 2059 case CX23885_BOARD_VIEWCAST_460E: 2060 dev->i2c_bus[1].i2c_client.addr = 0xa0 >> 1; 2061 tveeprom_read(&dev->i2c_bus[1].i2c_client, 2062 eeprom, sizeof(eeprom)); 2063 if (dev->i2c_bus[0].i2c_rc == 0) 2064 viewcast_eeprom(dev, eeprom); 2065 break; 2066 } 2067 2068 switch (dev->board) { 2069 case CX23885_BOARD_AVERMEDIA_HC81R: 2070 /* Defaults for VID B */ 2071 ts1->gen_ctrl_val = 0x4; /* Parallel */ 2072 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2073 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2074 /* Defaults for VID C */ 2075 /* DREQ_POL, SMODE, PUNC_CLK, MCLK_POL Serial bus + punc clk */ 2076 ts2->gen_ctrl_val = 0x10e; 2077 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2078 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2079 break; 2080 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP: 2081 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: 2082 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2: 2083 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 2084 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2085 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2086 /* break omitted intentionally */ 2087 case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP: 2088 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 2089 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2090 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2091 break; 2092 case CX23885_BOARD_HAUPPAUGE_HVR1850: 2093 case CX23885_BOARD_HAUPPAUGE_HVR1800: 2094 /* Defaults for VID B - Analog encoder */ 2095 /* DREQ_POL, SMODE, PUNC_CLK, MCLK_POL Serial bus + punc clk */ 2096 ts1->gen_ctrl_val = 0x10e; 2097 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2098 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2099 2100 /* APB_TSVALERR_POL (active low)*/ 2101 ts1->vld_misc_val = 0x2000; 2102 ts1->hw_sop_ctrl_val = (0x47 << 16 | 188 << 4 | 0xc); 2103 cx_write(0x130184, 0xc); 2104 2105 /* Defaults for VID C */ 2106 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 2107 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2108 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2109 break; 2110 case CX23885_BOARD_TBS_6920: 2111 ts1->gen_ctrl_val = 0x4; /* Parallel */ 2112 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2113 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2114 break; 2115 case CX23885_BOARD_TEVII_S470: 2116 case CX23885_BOARD_TEVII_S471: 2117 case CX23885_BOARD_DVBWORLD_2005: 2118 case CX23885_BOARD_PROF_8000: 2119 case CX23885_BOARD_DVBSKY_T980C: 2120 case CX23885_BOARD_DVBSKY_S950C: 2121 case CX23885_BOARD_TT_CT2_4500_CI: 2122 case CX23885_BOARD_DVBSKY_S950: 2123 ts1->gen_ctrl_val = 0x5; /* Parallel */ 2124 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2125 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2126 break; 2127 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: 2128 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: 2129 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL: 2130 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 2131 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2132 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2133 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 2134 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2135 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2136 break; 2137 case CX23885_BOARD_TBS_6980: 2138 case CX23885_BOARD_TBS_6981: 2139 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 2140 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2141 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2142 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 2143 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2144 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2145 tbs_card_init(dev); 2146 break; 2147 case CX23885_BOARD_MYGICA_X8506: 2148 case CX23885_BOARD_MAGICPRO_PROHDTVE2: 2149 case CX23885_BOARD_MYGICA_X8507: 2150 ts1->gen_ctrl_val = 0x5; /* Parallel */ 2151 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2152 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2153 break; 2154 case CX23885_BOARD_MYGICA_X8558PRO: 2155 ts1->gen_ctrl_val = 0x5; /* Parallel */ 2156 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2157 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2158 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 2159 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2160 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2161 break; 2162 case CX23885_BOARD_HAUPPAUGE_HVR4400: 2163 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 2164 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2165 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2166 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 2167 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2168 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2169 break; 2170 case CX23885_BOARD_HAUPPAUGE_STARBURST: 2171 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 2172 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2173 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2174 break; 2175 case CX23885_BOARD_DVBSKY_T9580: 2176 case CX23885_BOARD_DVBSKY_T982: 2177 ts1->gen_ctrl_val = 0x5; /* Parallel */ 2178 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2179 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2180 ts2->gen_ctrl_val = 0x8; /* Serial bus */ 2181 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2182 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2183 break; 2184 case CX23885_BOARD_DVBSKY_S952: 2185 ts1->gen_ctrl_val = 0x5; /* Parallel */ 2186 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2187 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2188 ts2->gen_ctrl_val = 0xe; /* Serial bus */ 2189 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2190 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2191 break; 2192 case CX23885_BOARD_HAUPPAUGE_HVR5525: 2193 ts1->gen_ctrl_val = 0x5; /* Parallel */ 2194 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2195 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2196 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 2197 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2198 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2199 break; 2200 case CX23885_BOARD_HAUPPAUGE_QUADHD_DVB: 2201 case CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC: 2202 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 2203 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2204 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2205 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 2206 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2207 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2208 break; 2209 case CX23885_BOARD_HAUPPAUGE_HVR1250: 2210 case CX23885_BOARD_HAUPPAUGE_HVR1500: 2211 case CX23885_BOARD_HAUPPAUGE_HVR1500Q: 2212 case CX23885_BOARD_HAUPPAUGE_HVR1800lp: 2213 case CX23885_BOARD_HAUPPAUGE_HVR1200: 2214 case CX23885_BOARD_HAUPPAUGE_HVR1700: 2215 case CX23885_BOARD_HAUPPAUGE_HVR1400: 2216 case CX23885_BOARD_HAUPPAUGE_IMPACTVCBE: 2217 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H: 2218 case CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200: 2219 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000: 2220 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F: 2221 case CX23885_BOARD_HAUPPAUGE_HVR1270: 2222 case CX23885_BOARD_HAUPPAUGE_HVR1275: 2223 case CX23885_BOARD_HAUPPAUGE_HVR1255: 2224 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111: 2225 case CX23885_BOARD_HAUPPAUGE_HVR1210: 2226 case CX23885_BOARD_COMPRO_VIDEOMATE_E800: 2227 case CX23885_BOARD_HAUPPAUGE_HVR1290: 2228 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID: 2229 default: 2230 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 2231 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2232 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2233 } 2234 2235 /* Certain boards support analog, or require the avcore to be 2236 * loaded, ensure this happens. 2237 */ 2238 switch (dev->board) { 2239 case CX23885_BOARD_TEVII_S470: 2240 /* Currently only enabled for the integrated IR controller */ 2241 if (!enable_885_ir) 2242 break; 2243 case CX23885_BOARD_HAUPPAUGE_HVR1250: 2244 case CX23885_BOARD_HAUPPAUGE_HVR1800: 2245 case CX23885_BOARD_HAUPPAUGE_IMPACTVCBE: 2246 case CX23885_BOARD_HAUPPAUGE_HVR1800lp: 2247 case CX23885_BOARD_HAUPPAUGE_HVR1700: 2248 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H: 2249 case CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200: 2250 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000: 2251 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F: 2252 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: 2253 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: 2254 case CX23885_BOARD_COMPRO_VIDEOMATE_E800: 2255 case CX23885_BOARD_HAUPPAUGE_HVR1255: 2256 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111: 2257 case CX23885_BOARD_HAUPPAUGE_HVR1270: 2258 case CX23885_BOARD_HAUPPAUGE_HVR1850: 2259 case CX23885_BOARD_MYGICA_X8506: 2260 case CX23885_BOARD_MAGICPRO_PROHDTVE2: 2261 case CX23885_BOARD_HAUPPAUGE_HVR1290: 2262 case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200: 2263 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID: 2264 case CX23885_BOARD_HAUPPAUGE_HVR1500: 2265 case CX23885_BOARD_MPX885: 2266 case CX23885_BOARD_MYGICA_X8507: 2267 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL: 2268 case CX23885_BOARD_AVERMEDIA_HC81R: 2269 case CX23885_BOARD_TBS_6980: 2270 case CX23885_BOARD_TBS_6981: 2271 case CX23885_BOARD_DVBSKY_T9580: 2272 case CX23885_BOARD_DVBSKY_T980C: 2273 case CX23885_BOARD_DVBSKY_S950C: 2274 case CX23885_BOARD_TT_CT2_4500_CI: 2275 case CX23885_BOARD_DVBSKY_S950: 2276 case CX23885_BOARD_DVBSKY_S952: 2277 case CX23885_BOARD_DVBSKY_T982: 2278 case CX23885_BOARD_VIEWCAST_260E: 2279 case CX23885_BOARD_VIEWCAST_460E: 2280 dev->sd_cx25840 = v4l2_i2c_new_subdev(&dev->v4l2_dev, 2281 &dev->i2c_bus[2].i2c_adap, 2282 "cx25840", 0x88 >> 1, NULL); 2283 if (dev->sd_cx25840) { 2284 dev->sd_cx25840->grp_id = CX23885_HW_AV_CORE; 2285 v4l2_subdev_call(dev->sd_cx25840, core, load_fw); 2286 } 2287 break; 2288 } 2289 2290 switch (dev->board) { 2291 case CX23885_BOARD_VIEWCAST_260E: 2292 v4l2_i2c_new_subdev(&dev->v4l2_dev, 2293 &dev->i2c_bus[0].i2c_adap, 2294 "cs3308", 0x82 >> 1, NULL); 2295 break; 2296 case CX23885_BOARD_VIEWCAST_460E: 2297 /* This cs3308 controls the audio from the breakout cable */ 2298 v4l2_i2c_new_subdev(&dev->v4l2_dev, 2299 &dev->i2c_bus[0].i2c_adap, 2300 "cs3308", 0x80 >> 1, NULL); 2301 /* This cs3308 controls the audio from the onboard header */ 2302 v4l2_i2c_new_subdev(&dev->v4l2_dev, 2303 &dev->i2c_bus[0].i2c_adap, 2304 "cs3308", 0x82 >> 1, NULL); 2305 break; 2306 } 2307 2308 /* AUX-PLL 27MHz CLK */ 2309 switch (dev->board) { 2310 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: 2311 netup_initialize(dev); 2312 break; 2313 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: { 2314 int ret; 2315 const struct firmware *fw; 2316 const char *filename = "dvb-netup-altera-01.fw"; 2317 char *action = "configure"; 2318 static struct netup_card_info cinfo; 2319 struct altera_config netup_config = { 2320 .dev = dev, 2321 .action = action, 2322 .jtag_io = netup_jtag_io, 2323 }; 2324 2325 netup_initialize(dev); 2326 2327 netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo); 2328 if (netup_card_rev) 2329 cinfo.rev = netup_card_rev; 2330 2331 switch (cinfo.rev) { 2332 case 0x4: 2333 filename = "dvb-netup-altera-04.fw"; 2334 break; 2335 default: 2336 filename = "dvb-netup-altera-01.fw"; 2337 break; 2338 } 2339 printk(KERN_INFO "NetUP card rev=0x%x fw_filename=%s\n", 2340 cinfo.rev, filename); 2341 2342 ret = request_firmware(&fw, filename, &dev->pci->dev); 2343 if (ret != 0) 2344 printk(KERN_ERR "did not find the firmware file. (%s) Please see linux/Documentation/dvb/ for more details on firmware-problems.", 2345 filename); 2346 else 2347 altera_init(&netup_config, fw); 2348 2349 release_firmware(fw); 2350 break; 2351 } 2352 } 2353 } 2354