1 /* 2 * Driver for the Conexant CX23885 PCIe bridge 3 * 4 * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * 15 * GNU General Public License for more details. 16 */ 17 18 #include <linux/init.h> 19 #include <linux/module.h> 20 #include <linux/pci.h> 21 #include <linux/delay.h> 22 #include <media/cx25840.h> 23 #include <linux/firmware.h> 24 #include <misc/altera.h> 25 26 #include "cx23885.h" 27 #include "tuner-xc2028.h" 28 #include "netup-eeprom.h" 29 #include "netup-init.h" 30 #include "altera-ci.h" 31 #include "xc4000.h" 32 #include "xc5000.h" 33 #include "cx23888-ir.h" 34 35 static unsigned int netup_card_rev = 4; 36 module_param(netup_card_rev, int, 0644); 37 MODULE_PARM_DESC(netup_card_rev, 38 "NetUP Dual DVB-T/C CI card revision"); 39 static unsigned int enable_885_ir; 40 module_param(enable_885_ir, int, 0644); 41 MODULE_PARM_DESC(enable_885_ir, 42 "Enable integrated IR controller for supported\n" 43 "\t\t CX2388[57] boards that are wired for it:\n" 44 "\t\t\tHVR-1250 (reported safe)\n" 45 "\t\t\tTerraTec Cinergy T PCIe Dual (not well tested, appears to be safe)\n" 46 "\t\t\tTeVii S470 (reported unsafe)\n" 47 "\t\t This can cause an interrupt storm with some cards.\n" 48 "\t\t Default: 0 [Disabled]"); 49 50 /* ------------------------------------------------------------------ */ 51 /* board config info */ 52 53 struct cx23885_board cx23885_boards[] = { 54 [CX23885_BOARD_UNKNOWN] = { 55 .name = "UNKNOWN/GENERIC", 56 /* Ensure safe default for unknown boards */ 57 .clk_freq = 0, 58 .input = {{ 59 .type = CX23885_VMUX_COMPOSITE1, 60 .vmux = 0, 61 }, { 62 .type = CX23885_VMUX_COMPOSITE2, 63 .vmux = 1, 64 }, { 65 .type = CX23885_VMUX_COMPOSITE3, 66 .vmux = 2, 67 }, { 68 .type = CX23885_VMUX_COMPOSITE4, 69 .vmux = 3, 70 } }, 71 }, 72 [CX23885_BOARD_HAUPPAUGE_HVR1800lp] = { 73 .name = "Hauppauge WinTV-HVR1800lp", 74 .portc = CX23885_MPEG_DVB, 75 .input = {{ 76 .type = CX23885_VMUX_TELEVISION, 77 .vmux = 0, 78 .gpio0 = 0xff00, 79 }, { 80 .type = CX23885_VMUX_DEBUG, 81 .vmux = 0, 82 .gpio0 = 0xff01, 83 }, { 84 .type = CX23885_VMUX_COMPOSITE1, 85 .vmux = 1, 86 .gpio0 = 0xff02, 87 }, { 88 .type = CX23885_VMUX_SVIDEO, 89 .vmux = 2, 90 .gpio0 = 0xff02, 91 } }, 92 }, 93 [CX23885_BOARD_HAUPPAUGE_HVR1800] = { 94 .name = "Hauppauge WinTV-HVR1800", 95 .porta = CX23885_ANALOG_VIDEO, 96 .portb = CX23885_MPEG_ENCODER, 97 .portc = CX23885_MPEG_DVB, 98 .tuner_type = TUNER_PHILIPS_TDA8290, 99 .tuner_addr = 0x42, /* 0x84 >> 1 */ 100 .tuner_bus = 1, 101 .input = {{ 102 .type = CX23885_VMUX_TELEVISION, 103 .vmux = CX25840_VIN7_CH3 | 104 CX25840_VIN5_CH2 | 105 CX25840_VIN2_CH1, 106 .amux = CX25840_AUDIO8, 107 .gpio0 = 0, 108 }, { 109 .type = CX23885_VMUX_COMPOSITE1, 110 .vmux = CX25840_VIN7_CH3 | 111 CX25840_VIN4_CH2 | 112 CX25840_VIN6_CH1, 113 .amux = CX25840_AUDIO7, 114 .gpio0 = 0, 115 }, { 116 .type = CX23885_VMUX_SVIDEO, 117 .vmux = CX25840_VIN7_CH3 | 118 CX25840_VIN4_CH2 | 119 CX25840_VIN8_CH1 | 120 CX25840_SVIDEO_ON, 121 .amux = CX25840_AUDIO7, 122 .gpio0 = 0, 123 } }, 124 }, 125 [CX23885_BOARD_HAUPPAUGE_HVR1250] = { 126 .name = "Hauppauge WinTV-HVR1250", 127 .porta = CX23885_ANALOG_VIDEO, 128 .portc = CX23885_MPEG_DVB, 129 #ifdef MT2131_NO_ANALOG_SUPPORT_YET 130 .tuner_type = TUNER_PHILIPS_TDA8290, 131 .tuner_addr = 0x42, /* 0x84 >> 1 */ 132 .tuner_bus = 1, 133 #endif 134 .force_bff = 1, 135 .input = {{ 136 #ifdef MT2131_NO_ANALOG_SUPPORT_YET 137 .type = CX23885_VMUX_TELEVISION, 138 .vmux = CX25840_VIN7_CH3 | 139 CX25840_VIN5_CH2 | 140 CX25840_VIN2_CH1, 141 .amux = CX25840_AUDIO8, 142 .gpio0 = 0xff00, 143 }, { 144 #endif 145 .type = CX23885_VMUX_COMPOSITE1, 146 .vmux = CX25840_VIN7_CH3 | 147 CX25840_VIN4_CH2 | 148 CX25840_VIN6_CH1, 149 .amux = CX25840_AUDIO7, 150 .gpio0 = 0xff02, 151 }, { 152 .type = CX23885_VMUX_SVIDEO, 153 .vmux = CX25840_VIN7_CH3 | 154 CX25840_VIN4_CH2 | 155 CX25840_VIN8_CH1 | 156 CX25840_SVIDEO_ON, 157 .amux = CX25840_AUDIO7, 158 .gpio0 = 0xff02, 159 } }, 160 }, 161 [CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP] = { 162 .name = "DViCO FusionHDTV5 Express", 163 .portb = CX23885_MPEG_DVB, 164 }, 165 [CX23885_BOARD_HAUPPAUGE_HVR1500Q] = { 166 .name = "Hauppauge WinTV-HVR1500Q", 167 .portc = CX23885_MPEG_DVB, 168 }, 169 [CX23885_BOARD_HAUPPAUGE_HVR1500] = { 170 .name = "Hauppauge WinTV-HVR1500", 171 .porta = CX23885_ANALOG_VIDEO, 172 .portc = CX23885_MPEG_DVB, 173 .tuner_type = TUNER_XC2028, 174 .tuner_addr = 0x61, /* 0xc2 >> 1 */ 175 .input = {{ 176 .type = CX23885_VMUX_TELEVISION, 177 .vmux = CX25840_VIN7_CH3 | 178 CX25840_VIN5_CH2 | 179 CX25840_VIN2_CH1, 180 .gpio0 = 0, 181 }, { 182 .type = CX23885_VMUX_COMPOSITE1, 183 .vmux = CX25840_VIN7_CH3 | 184 CX25840_VIN4_CH2 | 185 CX25840_VIN6_CH1, 186 .gpio0 = 0, 187 }, { 188 .type = CX23885_VMUX_SVIDEO, 189 .vmux = CX25840_VIN7_CH3 | 190 CX25840_VIN4_CH2 | 191 CX25840_VIN8_CH1 | 192 CX25840_SVIDEO_ON, 193 .gpio0 = 0, 194 } }, 195 }, 196 [CX23885_BOARD_HAUPPAUGE_HVR1200] = { 197 .name = "Hauppauge WinTV-HVR1200", 198 .portc = CX23885_MPEG_DVB, 199 }, 200 [CX23885_BOARD_HAUPPAUGE_HVR1700] = { 201 .name = "Hauppauge WinTV-HVR1700", 202 .portc = CX23885_MPEG_DVB, 203 }, 204 [CX23885_BOARD_HAUPPAUGE_HVR1400] = { 205 .name = "Hauppauge WinTV-HVR1400", 206 .portc = CX23885_MPEG_DVB, 207 }, 208 [CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP] = { 209 .name = "DViCO FusionHDTV7 Dual Express", 210 .portb = CX23885_MPEG_DVB, 211 .portc = CX23885_MPEG_DVB, 212 }, 213 [CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP] = { 214 .name = "DViCO FusionHDTV DVB-T Dual Express", 215 .portb = CX23885_MPEG_DVB, 216 .portc = CX23885_MPEG_DVB, 217 }, 218 [CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H] = { 219 .name = "Leadtek Winfast PxDVR3200 H", 220 .portc = CX23885_MPEG_DVB, 221 }, 222 [CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200] = { 223 .name = "Leadtek Winfast PxPVR2200", 224 .porta = CX23885_ANALOG_VIDEO, 225 .tuner_type = TUNER_XC2028, 226 .tuner_addr = 0x61, 227 .tuner_bus = 1, 228 .input = {{ 229 .type = CX23885_VMUX_TELEVISION, 230 .vmux = CX25840_VIN2_CH1 | 231 CX25840_VIN5_CH2, 232 .amux = CX25840_AUDIO8, 233 .gpio0 = 0x704040, 234 }, { 235 .type = CX23885_VMUX_COMPOSITE1, 236 .vmux = CX25840_COMPOSITE1, 237 .amux = CX25840_AUDIO7, 238 .gpio0 = 0x704040, 239 }, { 240 .type = CX23885_VMUX_SVIDEO, 241 .vmux = CX25840_SVIDEO_LUMA3 | 242 CX25840_SVIDEO_CHROMA4, 243 .amux = CX25840_AUDIO7, 244 .gpio0 = 0x704040, 245 }, { 246 .type = CX23885_VMUX_COMPONENT, 247 .vmux = CX25840_VIN7_CH1 | 248 CX25840_VIN6_CH2 | 249 CX25840_VIN8_CH3 | 250 CX25840_COMPONENT_ON, 251 .amux = CX25840_AUDIO7, 252 .gpio0 = 0x704040, 253 } }, 254 }, 255 [CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000] = { 256 .name = "Leadtek Winfast PxDVR3200 H XC4000", 257 .porta = CX23885_ANALOG_VIDEO, 258 .portc = CX23885_MPEG_DVB, 259 .tuner_type = TUNER_XC4000, 260 .tuner_addr = 0x61, 261 .radio_type = UNSET, 262 .radio_addr = ADDR_UNSET, 263 .input = {{ 264 .type = CX23885_VMUX_TELEVISION, 265 .vmux = CX25840_VIN2_CH1 | 266 CX25840_VIN5_CH2 | 267 CX25840_NONE0_CH3, 268 }, { 269 .type = CX23885_VMUX_COMPOSITE1, 270 .vmux = CX25840_COMPOSITE1, 271 }, { 272 .type = CX23885_VMUX_SVIDEO, 273 .vmux = CX25840_SVIDEO_LUMA3 | 274 CX25840_SVIDEO_CHROMA4, 275 }, { 276 .type = CX23885_VMUX_COMPONENT, 277 .vmux = CX25840_VIN7_CH1 | 278 CX25840_VIN6_CH2 | 279 CX25840_VIN8_CH3 | 280 CX25840_COMPONENT_ON, 281 } }, 282 }, 283 [CX23885_BOARD_COMPRO_VIDEOMATE_E650F] = { 284 .name = "Compro VideoMate E650F", 285 .portc = CX23885_MPEG_DVB, 286 }, 287 [CX23885_BOARD_TBS_6920] = { 288 .name = "TurboSight TBS 6920", 289 .portb = CX23885_MPEG_DVB, 290 }, 291 [CX23885_BOARD_TBS_6980] = { 292 .name = "TurboSight TBS 6980", 293 .portb = CX23885_MPEG_DVB, 294 .portc = CX23885_MPEG_DVB, 295 }, 296 [CX23885_BOARD_TBS_6981] = { 297 .name = "TurboSight TBS 6981", 298 .portb = CX23885_MPEG_DVB, 299 .portc = CX23885_MPEG_DVB, 300 }, 301 [CX23885_BOARD_TEVII_S470] = { 302 .name = "TeVii S470", 303 .portb = CX23885_MPEG_DVB, 304 }, 305 [CX23885_BOARD_DVBWORLD_2005] = { 306 .name = "DVBWorld DVB-S2 2005", 307 .portb = CX23885_MPEG_DVB, 308 }, 309 [CX23885_BOARD_NETUP_DUAL_DVBS2_CI] = { 310 .ci_type = 1, 311 .name = "NetUP Dual DVB-S2 CI", 312 .portb = CX23885_MPEG_DVB, 313 .portc = CX23885_MPEG_DVB, 314 }, 315 [CX23885_BOARD_HAUPPAUGE_HVR1270] = { 316 .name = "Hauppauge WinTV-HVR1270", 317 .portc = CX23885_MPEG_DVB, 318 }, 319 [CX23885_BOARD_HAUPPAUGE_HVR1275] = { 320 .name = "Hauppauge WinTV-HVR1275", 321 .portc = CX23885_MPEG_DVB, 322 }, 323 [CX23885_BOARD_HAUPPAUGE_HVR1255] = { 324 .name = "Hauppauge WinTV-HVR1255", 325 .porta = CX23885_ANALOG_VIDEO, 326 .portc = CX23885_MPEG_DVB, 327 .tuner_type = TUNER_ABSENT, 328 .tuner_addr = 0x42, /* 0x84 >> 1 */ 329 .force_bff = 1, 330 .input = {{ 331 .type = CX23885_VMUX_TELEVISION, 332 .vmux = CX25840_VIN7_CH3 | 333 CX25840_VIN5_CH2 | 334 CX25840_VIN2_CH1 | 335 CX25840_DIF_ON, 336 .amux = CX25840_AUDIO8, 337 }, { 338 .type = CX23885_VMUX_COMPOSITE1, 339 .vmux = CX25840_VIN7_CH3 | 340 CX25840_VIN4_CH2 | 341 CX25840_VIN6_CH1, 342 .amux = CX25840_AUDIO7, 343 }, { 344 .type = CX23885_VMUX_SVIDEO, 345 .vmux = CX25840_VIN7_CH3 | 346 CX25840_VIN4_CH2 | 347 CX25840_VIN8_CH1 | 348 CX25840_SVIDEO_ON, 349 .amux = CX25840_AUDIO7, 350 } }, 351 }, 352 [CX23885_BOARD_HAUPPAUGE_HVR1255_22111] = { 353 .name = "Hauppauge WinTV-HVR1255", 354 .porta = CX23885_ANALOG_VIDEO, 355 .portc = CX23885_MPEG_DVB, 356 .tuner_type = TUNER_ABSENT, 357 .tuner_addr = 0x42, /* 0x84 >> 1 */ 358 .force_bff = 1, 359 .input = {{ 360 .type = CX23885_VMUX_TELEVISION, 361 .vmux = CX25840_VIN7_CH3 | 362 CX25840_VIN5_CH2 | 363 CX25840_VIN2_CH1 | 364 CX25840_DIF_ON, 365 .amux = CX25840_AUDIO8, 366 }, { 367 .type = CX23885_VMUX_SVIDEO, 368 .vmux = CX25840_VIN7_CH3 | 369 CX25840_VIN4_CH2 | 370 CX25840_VIN8_CH1 | 371 CX25840_SVIDEO_ON, 372 .amux = CX25840_AUDIO7, 373 } }, 374 }, 375 [CX23885_BOARD_HAUPPAUGE_HVR1210] = { 376 .name = "Hauppauge WinTV-HVR1210", 377 .portc = CX23885_MPEG_DVB, 378 }, 379 [CX23885_BOARD_MYGICA_X8506] = { 380 .name = "Mygica X8506 DMB-TH", 381 .tuner_type = TUNER_XC5000, 382 .tuner_addr = 0x61, 383 .tuner_bus = 1, 384 .porta = CX23885_ANALOG_VIDEO, 385 .portb = CX23885_MPEG_DVB, 386 .input = { 387 { 388 .type = CX23885_VMUX_TELEVISION, 389 .vmux = CX25840_COMPOSITE2, 390 }, 391 { 392 .type = CX23885_VMUX_COMPOSITE1, 393 .vmux = CX25840_COMPOSITE8, 394 }, 395 { 396 .type = CX23885_VMUX_SVIDEO, 397 .vmux = CX25840_SVIDEO_LUMA3 | 398 CX25840_SVIDEO_CHROMA4, 399 }, 400 { 401 .type = CX23885_VMUX_COMPONENT, 402 .vmux = CX25840_COMPONENT_ON | 403 CX25840_VIN1_CH1 | 404 CX25840_VIN6_CH2 | 405 CX25840_VIN7_CH3, 406 }, 407 }, 408 }, 409 [CX23885_BOARD_MAGICPRO_PROHDTVE2] = { 410 .name = "Magic-Pro ProHDTV Extreme 2", 411 .tuner_type = TUNER_XC5000, 412 .tuner_addr = 0x61, 413 .tuner_bus = 1, 414 .porta = CX23885_ANALOG_VIDEO, 415 .portb = CX23885_MPEG_DVB, 416 .input = { 417 { 418 .type = CX23885_VMUX_TELEVISION, 419 .vmux = CX25840_COMPOSITE2, 420 }, 421 { 422 .type = CX23885_VMUX_COMPOSITE1, 423 .vmux = CX25840_COMPOSITE8, 424 }, 425 { 426 .type = CX23885_VMUX_SVIDEO, 427 .vmux = CX25840_SVIDEO_LUMA3 | 428 CX25840_SVIDEO_CHROMA4, 429 }, 430 { 431 .type = CX23885_VMUX_COMPONENT, 432 .vmux = CX25840_COMPONENT_ON | 433 CX25840_VIN1_CH1 | 434 CX25840_VIN6_CH2 | 435 CX25840_VIN7_CH3, 436 }, 437 }, 438 }, 439 [CX23885_BOARD_HAUPPAUGE_HVR1850] = { 440 .name = "Hauppauge WinTV-HVR1850", 441 .porta = CX23885_ANALOG_VIDEO, 442 .portb = CX23885_MPEG_ENCODER, 443 .portc = CX23885_MPEG_DVB, 444 .tuner_type = TUNER_ABSENT, 445 .tuner_addr = 0x42, /* 0x84 >> 1 */ 446 .force_bff = 1, 447 .input = {{ 448 .type = CX23885_VMUX_TELEVISION, 449 .vmux = CX25840_VIN7_CH3 | 450 CX25840_VIN5_CH2 | 451 CX25840_VIN2_CH1 | 452 CX25840_DIF_ON, 453 .amux = CX25840_AUDIO8, 454 }, { 455 .type = CX23885_VMUX_COMPOSITE1, 456 .vmux = CX25840_VIN7_CH3 | 457 CX25840_VIN4_CH2 | 458 CX25840_VIN6_CH1, 459 .amux = CX25840_AUDIO7, 460 }, { 461 .type = CX23885_VMUX_SVIDEO, 462 .vmux = CX25840_VIN7_CH3 | 463 CX25840_VIN4_CH2 | 464 CX25840_VIN8_CH1 | 465 CX25840_SVIDEO_ON, 466 .amux = CX25840_AUDIO7, 467 } }, 468 }, 469 [CX23885_BOARD_COMPRO_VIDEOMATE_E800] = { 470 .name = "Compro VideoMate E800", 471 .portc = CX23885_MPEG_DVB, 472 }, 473 [CX23885_BOARD_HAUPPAUGE_HVR1290] = { 474 .name = "Hauppauge WinTV-HVR1290", 475 .portc = CX23885_MPEG_DVB, 476 }, 477 [CX23885_BOARD_MYGICA_X8558PRO] = { 478 .name = "Mygica X8558 PRO DMB-TH", 479 .portb = CX23885_MPEG_DVB, 480 .portc = CX23885_MPEG_DVB, 481 }, 482 [CX23885_BOARD_LEADTEK_WINFAST_PXTV1200] = { 483 .name = "LEADTEK WinFast PxTV1200", 484 .porta = CX23885_ANALOG_VIDEO, 485 .tuner_type = TUNER_XC2028, 486 .tuner_addr = 0x61, 487 .tuner_bus = 1, 488 .input = {{ 489 .type = CX23885_VMUX_TELEVISION, 490 .vmux = CX25840_VIN2_CH1 | 491 CX25840_VIN5_CH2 | 492 CX25840_NONE0_CH3, 493 }, { 494 .type = CX23885_VMUX_COMPOSITE1, 495 .vmux = CX25840_COMPOSITE1, 496 }, { 497 .type = CX23885_VMUX_SVIDEO, 498 .vmux = CX25840_SVIDEO_LUMA3 | 499 CX25840_SVIDEO_CHROMA4, 500 }, { 501 .type = CX23885_VMUX_COMPONENT, 502 .vmux = CX25840_VIN7_CH1 | 503 CX25840_VIN6_CH2 | 504 CX25840_VIN8_CH3 | 505 CX25840_COMPONENT_ON, 506 } }, 507 }, 508 [CX23885_BOARD_GOTVIEW_X5_3D_HYBRID] = { 509 .name = "GoTView X5 3D Hybrid", 510 .tuner_type = TUNER_XC5000, 511 .tuner_addr = 0x64, 512 .tuner_bus = 1, 513 .porta = CX23885_ANALOG_VIDEO, 514 .portb = CX23885_MPEG_DVB, 515 .input = {{ 516 .type = CX23885_VMUX_TELEVISION, 517 .vmux = CX25840_VIN2_CH1 | 518 CX25840_VIN5_CH2, 519 .gpio0 = 0x02, 520 }, { 521 .type = CX23885_VMUX_COMPOSITE1, 522 .vmux = CX23885_VMUX_COMPOSITE1, 523 }, { 524 .type = CX23885_VMUX_SVIDEO, 525 .vmux = CX25840_SVIDEO_LUMA3 | 526 CX25840_SVIDEO_CHROMA4, 527 } }, 528 }, 529 [CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF] = { 530 .ci_type = 2, 531 .name = "NetUP Dual DVB-T/C-CI RF", 532 .porta = CX23885_ANALOG_VIDEO, 533 .portb = CX23885_MPEG_DVB, 534 .portc = CX23885_MPEG_DVB, 535 .num_fds_portb = 2, 536 .num_fds_portc = 2, 537 .tuner_type = TUNER_XC5000, 538 .tuner_addr = 0x64, 539 .input = { { 540 .type = CX23885_VMUX_TELEVISION, 541 .vmux = CX25840_COMPOSITE1, 542 } }, 543 }, 544 [CX23885_BOARD_MPX885] = { 545 .name = "MPX-885", 546 .porta = CX23885_ANALOG_VIDEO, 547 .input = {{ 548 .type = CX23885_VMUX_COMPOSITE1, 549 .vmux = CX25840_COMPOSITE1, 550 .amux = CX25840_AUDIO6, 551 .gpio0 = 0, 552 }, { 553 .type = CX23885_VMUX_COMPOSITE2, 554 .vmux = CX25840_COMPOSITE2, 555 .amux = CX25840_AUDIO6, 556 .gpio0 = 0, 557 }, { 558 .type = CX23885_VMUX_COMPOSITE3, 559 .vmux = CX25840_COMPOSITE3, 560 .amux = CX25840_AUDIO7, 561 .gpio0 = 0, 562 }, { 563 .type = CX23885_VMUX_COMPOSITE4, 564 .vmux = CX25840_COMPOSITE4, 565 .amux = CX25840_AUDIO7, 566 .gpio0 = 0, 567 } }, 568 }, 569 [CX23885_BOARD_MYGICA_X8507] = { 570 .name = "Mygica X8502/X8507 ISDB-T", 571 .tuner_type = TUNER_XC5000, 572 .tuner_addr = 0x61, 573 .tuner_bus = 1, 574 .porta = CX23885_ANALOG_VIDEO, 575 .portb = CX23885_MPEG_DVB, 576 .input = { 577 { 578 .type = CX23885_VMUX_TELEVISION, 579 .vmux = CX25840_COMPOSITE2, 580 .amux = CX25840_AUDIO8, 581 }, 582 { 583 .type = CX23885_VMUX_COMPOSITE1, 584 .vmux = CX25840_COMPOSITE8, 585 .amux = CX25840_AUDIO7, 586 }, 587 { 588 .type = CX23885_VMUX_SVIDEO, 589 .vmux = CX25840_SVIDEO_LUMA3 | 590 CX25840_SVIDEO_CHROMA4, 591 .amux = CX25840_AUDIO7, 592 }, 593 { 594 .type = CX23885_VMUX_COMPONENT, 595 .vmux = CX25840_COMPONENT_ON | 596 CX25840_VIN1_CH1 | 597 CX25840_VIN6_CH2 | 598 CX25840_VIN7_CH3, 599 .amux = CX25840_AUDIO7, 600 }, 601 }, 602 }, 603 [CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL] = { 604 .name = "TerraTec Cinergy T PCIe Dual", 605 .portb = CX23885_MPEG_DVB, 606 .portc = CX23885_MPEG_DVB, 607 }, 608 [CX23885_BOARD_TEVII_S471] = { 609 .name = "TeVii S471", 610 .portb = CX23885_MPEG_DVB, 611 }, 612 [CX23885_BOARD_PROF_8000] = { 613 .name = "Prof Revolution DVB-S2 8000", 614 .portb = CX23885_MPEG_DVB, 615 }, 616 [CX23885_BOARD_HAUPPAUGE_HVR4400] = { 617 .name = "Hauppauge WinTV-HVR4400", 618 .porta = CX23885_ANALOG_VIDEO, 619 .portb = CX23885_MPEG_DVB, 620 .portc = CX23885_MPEG_DVB, 621 .tuner_type = TUNER_NXP_TDA18271, 622 .tuner_addr = 0x60, /* 0xc0 >> 1 */ 623 .tuner_bus = 1, 624 }, 625 [CX23885_BOARD_AVERMEDIA_HC81R] = { 626 .name = "AVerTV Hybrid Express Slim HC81R", 627 .tuner_type = TUNER_XC2028, 628 .tuner_addr = 0x61, /* 0xc2 >> 1 */ 629 .tuner_bus = 1, 630 .porta = CX23885_ANALOG_VIDEO, 631 .input = {{ 632 .type = CX23885_VMUX_TELEVISION, 633 .vmux = CX25840_VIN2_CH1 | 634 CX25840_VIN5_CH2 | 635 CX25840_NONE0_CH3 | 636 CX25840_NONE1_CH3, 637 .amux = CX25840_AUDIO8, 638 }, { 639 .type = CX23885_VMUX_SVIDEO, 640 .vmux = CX25840_VIN8_CH1 | 641 CX25840_NONE_CH2 | 642 CX25840_VIN7_CH3 | 643 CX25840_SVIDEO_ON, 644 .amux = CX25840_AUDIO6, 645 }, { 646 .type = CX23885_VMUX_COMPONENT, 647 .vmux = CX25840_VIN1_CH1 | 648 CX25840_NONE_CH2 | 649 CX25840_NONE0_CH3 | 650 CX25840_NONE1_CH3, 651 .amux = CX25840_AUDIO6, 652 } }, 653 }, 654 [CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2] = { 655 .name = "DViCO FusionHDTV DVB-T Dual Express2", 656 .portb = CX23885_MPEG_DVB, 657 .portc = CX23885_MPEG_DVB, 658 }, 659 [CX23885_BOARD_HAUPPAUGE_IMPACTVCBE] = { 660 .name = "Hauppauge ImpactVCB-e", 661 .tuner_type = TUNER_ABSENT, 662 .porta = CX23885_ANALOG_VIDEO, 663 .input = {{ 664 .type = CX23885_VMUX_COMPOSITE1, 665 .vmux = CX25840_VIN7_CH3 | 666 CX25840_VIN4_CH2 | 667 CX25840_VIN6_CH1, 668 .amux = CX25840_AUDIO7, 669 }, { 670 .type = CX23885_VMUX_SVIDEO, 671 .vmux = CX25840_VIN7_CH3 | 672 CX25840_VIN4_CH2 | 673 CX25840_VIN8_CH1 | 674 CX25840_SVIDEO_ON, 675 .amux = CX25840_AUDIO7, 676 } }, 677 }, 678 [CX23885_BOARD_DVBSKY_T9580] = { 679 .name = "DVBSky T9580", 680 .portb = CX23885_MPEG_DVB, 681 .portc = CX23885_MPEG_DVB, 682 }, 683 }; 684 const unsigned int cx23885_bcount = ARRAY_SIZE(cx23885_boards); 685 686 /* ------------------------------------------------------------------ */ 687 /* PCI subsystem IDs */ 688 689 struct cx23885_subid cx23885_subids[] = { 690 { 691 .subvendor = 0x0070, 692 .subdevice = 0x3400, 693 .card = CX23885_BOARD_UNKNOWN, 694 }, { 695 .subvendor = 0x0070, 696 .subdevice = 0x7600, 697 .card = CX23885_BOARD_HAUPPAUGE_HVR1800lp, 698 }, { 699 .subvendor = 0x0070, 700 .subdevice = 0x7800, 701 .card = CX23885_BOARD_HAUPPAUGE_HVR1800, 702 }, { 703 .subvendor = 0x0070, 704 .subdevice = 0x7801, 705 .card = CX23885_BOARD_HAUPPAUGE_HVR1800, 706 }, { 707 .subvendor = 0x0070, 708 .subdevice = 0x7809, 709 .card = CX23885_BOARD_HAUPPAUGE_HVR1800, 710 }, { 711 .subvendor = 0x0070, 712 .subdevice = 0x7911, 713 .card = CX23885_BOARD_HAUPPAUGE_HVR1250, 714 }, { 715 .subvendor = 0x18ac, 716 .subdevice = 0xd500, 717 .card = CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP, 718 }, { 719 .subvendor = 0x0070, 720 .subdevice = 0x7790, 721 .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q, 722 }, { 723 .subvendor = 0x0070, 724 .subdevice = 0x7797, 725 .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q, 726 }, { 727 .subvendor = 0x0070, 728 .subdevice = 0x7710, 729 .card = CX23885_BOARD_HAUPPAUGE_HVR1500, 730 }, { 731 .subvendor = 0x0070, 732 .subdevice = 0x7717, 733 .card = CX23885_BOARD_HAUPPAUGE_HVR1500, 734 }, { 735 .subvendor = 0x0070, 736 .subdevice = 0x71d1, 737 .card = CX23885_BOARD_HAUPPAUGE_HVR1200, 738 }, { 739 .subvendor = 0x0070, 740 .subdevice = 0x71d3, 741 .card = CX23885_BOARD_HAUPPAUGE_HVR1200, 742 }, { 743 .subvendor = 0x0070, 744 .subdevice = 0x8101, 745 .card = CX23885_BOARD_HAUPPAUGE_HVR1700, 746 }, { 747 .subvendor = 0x0070, 748 .subdevice = 0x8010, 749 .card = CX23885_BOARD_HAUPPAUGE_HVR1400, 750 }, { 751 .subvendor = 0x18ac, 752 .subdevice = 0xd618, 753 .card = CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP, 754 }, { 755 .subvendor = 0x18ac, 756 .subdevice = 0xdb78, 757 .card = CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP, 758 }, { 759 .subvendor = 0x107d, 760 .subdevice = 0x6681, 761 .card = CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H, 762 }, { 763 .subvendor = 0x107d, 764 .subdevice = 0x6f21, 765 .card = CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200, 766 }, { 767 .subvendor = 0x107d, 768 .subdevice = 0x6f39, 769 .card = CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000, 770 }, { 771 .subvendor = 0x185b, 772 .subdevice = 0xe800, 773 .card = CX23885_BOARD_COMPRO_VIDEOMATE_E650F, 774 }, { 775 .subvendor = 0x6920, 776 .subdevice = 0x8888, 777 .card = CX23885_BOARD_TBS_6920, 778 }, { 779 .subvendor = 0x6980, 780 .subdevice = 0x8888, 781 .card = CX23885_BOARD_TBS_6980, 782 }, { 783 .subvendor = 0x6981, 784 .subdevice = 0x8888, 785 .card = CX23885_BOARD_TBS_6981, 786 }, { 787 .subvendor = 0xd470, 788 .subdevice = 0x9022, 789 .card = CX23885_BOARD_TEVII_S470, 790 }, { 791 .subvendor = 0x0001, 792 .subdevice = 0x2005, 793 .card = CX23885_BOARD_DVBWORLD_2005, 794 }, { 795 .subvendor = 0x1b55, 796 .subdevice = 0x2a2c, 797 .card = CX23885_BOARD_NETUP_DUAL_DVBS2_CI, 798 }, { 799 .subvendor = 0x0070, 800 .subdevice = 0x2211, 801 .card = CX23885_BOARD_HAUPPAUGE_HVR1270, 802 }, { 803 .subvendor = 0x0070, 804 .subdevice = 0x2215, 805 .card = CX23885_BOARD_HAUPPAUGE_HVR1275, 806 }, { 807 .subvendor = 0x0070, 808 .subdevice = 0x221d, 809 .card = CX23885_BOARD_HAUPPAUGE_HVR1275, 810 }, { 811 .subvendor = 0x0070, 812 .subdevice = 0x2251, 813 .card = CX23885_BOARD_HAUPPAUGE_HVR1255, 814 }, { 815 .subvendor = 0x0070, 816 .subdevice = 0x2259, 817 .card = CX23885_BOARD_HAUPPAUGE_HVR1255_22111, 818 }, { 819 .subvendor = 0x0070, 820 .subdevice = 0x2291, 821 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, 822 }, { 823 .subvendor = 0x0070, 824 .subdevice = 0x2295, 825 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, 826 }, { 827 .subvendor = 0x0070, 828 .subdevice = 0x2299, 829 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, 830 }, { 831 .subvendor = 0x0070, 832 .subdevice = 0x229d, 833 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */ 834 }, { 835 .subvendor = 0x0070, 836 .subdevice = 0x22f0, 837 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, 838 }, { 839 .subvendor = 0x0070, 840 .subdevice = 0x22f1, 841 .card = CX23885_BOARD_HAUPPAUGE_HVR1255, 842 }, { 843 .subvendor = 0x0070, 844 .subdevice = 0x22f2, 845 .card = CX23885_BOARD_HAUPPAUGE_HVR1275, 846 }, { 847 .subvendor = 0x0070, 848 .subdevice = 0x22f3, 849 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */ 850 }, { 851 .subvendor = 0x0070, 852 .subdevice = 0x22f4, 853 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, 854 }, { 855 .subvendor = 0x0070, 856 .subdevice = 0x22f5, 857 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */ 858 }, { 859 .subvendor = 0x14f1, 860 .subdevice = 0x8651, 861 .card = CX23885_BOARD_MYGICA_X8506, 862 }, { 863 .subvendor = 0x14f1, 864 .subdevice = 0x8657, 865 .card = CX23885_BOARD_MAGICPRO_PROHDTVE2, 866 }, { 867 .subvendor = 0x0070, 868 .subdevice = 0x8541, 869 .card = CX23885_BOARD_HAUPPAUGE_HVR1850, 870 }, { 871 .subvendor = 0x1858, 872 .subdevice = 0xe800, 873 .card = CX23885_BOARD_COMPRO_VIDEOMATE_E800, 874 }, { 875 .subvendor = 0x0070, 876 .subdevice = 0x8551, 877 .card = CX23885_BOARD_HAUPPAUGE_HVR1290, 878 }, { 879 .subvendor = 0x14f1, 880 .subdevice = 0x8578, 881 .card = CX23885_BOARD_MYGICA_X8558PRO, 882 }, { 883 .subvendor = 0x107d, 884 .subdevice = 0x6f22, 885 .card = CX23885_BOARD_LEADTEK_WINFAST_PXTV1200, 886 }, { 887 .subvendor = 0x5654, 888 .subdevice = 0x2390, 889 .card = CX23885_BOARD_GOTVIEW_X5_3D_HYBRID, 890 }, { 891 .subvendor = 0x1b55, 892 .subdevice = 0xe2e4, 893 .card = CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF, 894 }, { 895 .subvendor = 0x14f1, 896 .subdevice = 0x8502, 897 .card = CX23885_BOARD_MYGICA_X8507, 898 }, { 899 .subvendor = 0x153b, 900 .subdevice = 0x117e, 901 .card = CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL, 902 }, { 903 .subvendor = 0xd471, 904 .subdevice = 0x9022, 905 .card = CX23885_BOARD_TEVII_S471, 906 }, { 907 .subvendor = 0x8000, 908 .subdevice = 0x3034, 909 .card = CX23885_BOARD_PROF_8000, 910 }, { 911 .subvendor = 0x0070, 912 .subdevice = 0xc108, 913 .card = CX23885_BOARD_HAUPPAUGE_HVR4400, 914 }, { 915 .subvendor = 0x0070, 916 .subdevice = 0xc138, 917 .card = CX23885_BOARD_HAUPPAUGE_HVR4400, 918 }, { 919 .subvendor = 0x0070, 920 .subdevice = 0xc12a, 921 .card = CX23885_BOARD_HAUPPAUGE_HVR4400, 922 }, { 923 .subvendor = 0x0070, 924 .subdevice = 0xc1f8, 925 .card = CX23885_BOARD_HAUPPAUGE_HVR4400, 926 }, { 927 .subvendor = 0x1461, 928 .subdevice = 0xd939, 929 .card = CX23885_BOARD_AVERMEDIA_HC81R, 930 }, { 931 .subvendor = 0x0070, 932 .subdevice = 0x7133, 933 .card = CX23885_BOARD_HAUPPAUGE_IMPACTVCBE, 934 }, { 935 .subvendor = 0x18ac, 936 .subdevice = 0xdb98, 937 .card = CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2, 938 }, { 939 .subvendor = 0x4254, 940 .subdevice = 0x9580, 941 .card = CX23885_BOARD_DVBSKY_T9580, 942 }, 943 }; 944 const unsigned int cx23885_idcount = ARRAY_SIZE(cx23885_subids); 945 946 void cx23885_card_list(struct cx23885_dev *dev) 947 { 948 int i; 949 950 if (0 == dev->pci->subsystem_vendor && 951 0 == dev->pci->subsystem_device) { 952 printk(KERN_INFO 953 "%s: Board has no valid PCIe Subsystem ID and can't\n" 954 "%s: be autodetected. Pass card=<n> insmod option\n" 955 "%s: to workaround that. Redirect complaints to the\n" 956 "%s: vendor of the TV card. Best regards,\n" 957 "%s: -- tux\n", 958 dev->name, dev->name, dev->name, dev->name, dev->name); 959 } else { 960 printk(KERN_INFO 961 "%s: Your board isn't known (yet) to the driver.\n" 962 "%s: Try to pick one of the existing card configs via\n" 963 "%s: card=<n> insmod option. Updating to the latest\n" 964 "%s: version might help as well.\n", 965 dev->name, dev->name, dev->name, dev->name); 966 } 967 printk(KERN_INFO "%s: Here is a list of valid choices for the card=<n> insmod option:\n", 968 dev->name); 969 for (i = 0; i < cx23885_bcount; i++) 970 printk(KERN_INFO "%s: card=%d -> %s\n", 971 dev->name, i, cx23885_boards[i].name); 972 } 973 974 static void hauppauge_eeprom(struct cx23885_dev *dev, u8 *eeprom_data) 975 { 976 struct tveeprom tv; 977 978 tveeprom_hauppauge_analog(&dev->i2c_bus[0].i2c_client, &tv, 979 eeprom_data); 980 981 /* Make sure we support the board model */ 982 switch (tv.model) { 983 case 22001: 984 /* WinTV-HVR1270 (PCIe, Retail, half height) 985 * ATSC/QAM and basic analog, IR Blast */ 986 case 22009: 987 /* WinTV-HVR1210 (PCIe, Retail, half height) 988 * DVB-T and basic analog, IR Blast */ 989 case 22011: 990 /* WinTV-HVR1270 (PCIe, Retail, half height) 991 * ATSC/QAM and basic analog, IR Recv */ 992 case 22019: 993 /* WinTV-HVR1210 (PCIe, Retail, half height) 994 * DVB-T and basic analog, IR Recv */ 995 case 22021: 996 /* WinTV-HVR1275 (PCIe, Retail, half height) 997 * ATSC/QAM and basic analog, IR Recv */ 998 case 22029: 999 /* WinTV-HVR1210 (PCIe, Retail, half height) 1000 * DVB-T and basic analog, IR Recv */ 1001 case 22101: 1002 /* WinTV-HVR1270 (PCIe, Retail, full height) 1003 * ATSC/QAM and basic analog, IR Blast */ 1004 case 22109: 1005 /* WinTV-HVR1210 (PCIe, Retail, full height) 1006 * DVB-T and basic analog, IR Blast */ 1007 case 22111: 1008 /* WinTV-HVR1270 (PCIe, Retail, full height) 1009 * ATSC/QAM and basic analog, IR Recv */ 1010 case 22119: 1011 /* WinTV-HVR1210 (PCIe, Retail, full height) 1012 * DVB-T and basic analog, IR Recv */ 1013 case 22121: 1014 /* WinTV-HVR1275 (PCIe, Retail, full height) 1015 * ATSC/QAM and basic analog, IR Recv */ 1016 case 22129: 1017 /* WinTV-HVR1210 (PCIe, Retail, full height) 1018 * DVB-T and basic analog, IR Recv */ 1019 case 71009: 1020 /* WinTV-HVR1200 (PCIe, Retail, full height) 1021 * DVB-T and basic analog */ 1022 case 71100: 1023 /* WinTV-ImpactVCB-e (PCIe, Retail, half height) 1024 * Basic analog */ 1025 case 71359: 1026 /* WinTV-HVR1200 (PCIe, OEM, half height) 1027 * DVB-T and basic analog */ 1028 case 71439: 1029 /* WinTV-HVR1200 (PCIe, OEM, half height) 1030 * DVB-T and basic analog */ 1031 case 71449: 1032 /* WinTV-HVR1200 (PCIe, OEM, full height) 1033 * DVB-T and basic analog */ 1034 case 71939: 1035 /* WinTV-HVR1200 (PCIe, OEM, half height) 1036 * DVB-T and basic analog */ 1037 case 71949: 1038 /* WinTV-HVR1200 (PCIe, OEM, full height) 1039 * DVB-T and basic analog */ 1040 case 71959: 1041 /* WinTV-HVR1200 (PCIe, OEM, full height) 1042 * DVB-T and basic analog */ 1043 case 71979: 1044 /* WinTV-HVR1200 (PCIe, OEM, half height) 1045 * DVB-T and basic analog */ 1046 case 71999: 1047 /* WinTV-HVR1200 (PCIe, OEM, full height) 1048 * DVB-T and basic analog */ 1049 case 76601: 1050 /* WinTV-HVR1800lp (PCIe, Retail, No IR, Dual 1051 channel ATSC and MPEG2 HW Encoder */ 1052 case 77001: 1053 /* WinTV-HVR1500 (Express Card, OEM, No IR, ATSC 1054 and Basic analog */ 1055 case 77011: 1056 /* WinTV-HVR1500 (Express Card, Retail, No IR, ATSC 1057 and Basic analog */ 1058 case 77041: 1059 /* WinTV-HVR1500Q (Express Card, OEM, No IR, ATSC/QAM 1060 and Basic analog */ 1061 case 77051: 1062 /* WinTV-HVR1500Q (Express Card, Retail, No IR, ATSC/QAM 1063 and Basic analog */ 1064 case 78011: 1065 /* WinTV-HVR1800 (PCIe, Retail, 3.5mm in, IR, No FM, 1066 Dual channel ATSC and MPEG2 HW Encoder */ 1067 case 78501: 1068 /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM, 1069 Dual channel ATSC and MPEG2 HW Encoder */ 1070 case 78521: 1071 /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM, 1072 Dual channel ATSC and MPEG2 HW Encoder */ 1073 case 78531: 1074 /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, No FM, 1075 Dual channel ATSC and MPEG2 HW Encoder */ 1076 case 78631: 1077 /* WinTV-HVR1800 (PCIe, OEM, No IR, No FM, 1078 Dual channel ATSC and MPEG2 HW Encoder */ 1079 case 79001: 1080 /* WinTV-HVR1250 (PCIe, Retail, IR, full height, 1081 ATSC and Basic analog */ 1082 case 79101: 1083 /* WinTV-HVR1250 (PCIe, Retail, IR, half height, 1084 ATSC and Basic analog */ 1085 case 79501: 1086 /* WinTV-HVR1250 (PCIe, No IR, half height, 1087 ATSC [at least] and Basic analog) */ 1088 case 79561: 1089 /* WinTV-HVR1250 (PCIe, OEM, No IR, half height, 1090 ATSC and Basic analog */ 1091 case 79571: 1092 /* WinTV-HVR1250 (PCIe, OEM, No IR, full height, 1093 ATSC and Basic analog */ 1094 case 79671: 1095 /* WinTV-HVR1250 (PCIe, OEM, No IR, half height, 1096 ATSC and Basic analog */ 1097 case 80019: 1098 /* WinTV-HVR1400 (Express Card, Retail, IR, 1099 * DVB-T and Basic analog */ 1100 case 81509: 1101 /* WinTV-HVR1700 (PCIe, OEM, No IR, half height) 1102 * DVB-T and MPEG2 HW Encoder */ 1103 case 81519: 1104 /* WinTV-HVR1700 (PCIe, OEM, No IR, full height) 1105 * DVB-T and MPEG2 HW Encoder */ 1106 break; 1107 case 85021: 1108 /* WinTV-HVR1850 (PCIe, Retail, 3.5mm in, IR, FM, 1109 Dual channel ATSC and MPEG2 HW Encoder */ 1110 break; 1111 case 85721: 1112 /* WinTV-HVR1290 (PCIe, OEM, RCA in, IR, 1113 Dual channel ATSC and Basic analog */ 1114 break; 1115 default: 1116 printk(KERN_WARNING "%s: warning: " 1117 "unknown hauppauge model #%d\n", 1118 dev->name, tv.model); 1119 break; 1120 } 1121 1122 printk(KERN_INFO "%s: hauppauge eeprom: model=%d\n", 1123 dev->name, tv.model); 1124 } 1125 1126 /* Some TBS cards require initing a chip using a bitbanged SPI attached 1127 to the cx23885 gpio's. If this chip doesn't get init'ed the demod 1128 doesn't respond to any command. */ 1129 static void tbs_card_init(struct cx23885_dev *dev) 1130 { 1131 int i; 1132 const u8 buf[] = { 1133 0xe0, 0x06, 0x66, 0x33, 0x65, 1134 0x01, 0x17, 0x06, 0xde}; 1135 1136 switch (dev->board) { 1137 case CX23885_BOARD_TBS_6980: 1138 case CX23885_BOARD_TBS_6981: 1139 cx_set(GP0_IO, 0x00070007); 1140 usleep_range(1000, 10000); 1141 cx_clear(GP0_IO, 2); 1142 usleep_range(1000, 10000); 1143 for (i = 0; i < 9 * 8; i++) { 1144 cx_clear(GP0_IO, 7); 1145 usleep_range(1000, 10000); 1146 cx_set(GP0_IO, 1147 ((buf[i >> 3] >> (7 - (i & 7))) & 1) | 4); 1148 usleep_range(1000, 10000); 1149 } 1150 cx_set(GP0_IO, 7); 1151 break; 1152 } 1153 } 1154 1155 int cx23885_tuner_callback(void *priv, int component, int command, int arg) 1156 { 1157 struct cx23885_tsport *port = priv; 1158 struct cx23885_dev *dev = port->dev; 1159 u32 bitmask = 0; 1160 1161 if ((command == XC2028_RESET_CLK) || (command == XC2028_I2C_FLUSH)) 1162 return 0; 1163 1164 if (command != 0) { 1165 printk(KERN_ERR "%s(): Unknown command 0x%x.\n", 1166 __func__, command); 1167 return -EINVAL; 1168 } 1169 1170 switch (dev->board) { 1171 case CX23885_BOARD_HAUPPAUGE_HVR1400: 1172 case CX23885_BOARD_HAUPPAUGE_HVR1500: 1173 case CX23885_BOARD_HAUPPAUGE_HVR1500Q: 1174 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H: 1175 case CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200: 1176 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000: 1177 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F: 1178 case CX23885_BOARD_COMPRO_VIDEOMATE_E800: 1179 case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200: 1180 /* Tuner Reset Command */ 1181 bitmask = 0x04; 1182 break; 1183 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP: 1184 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: 1185 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2: 1186 /* Two identical tuners on two different i2c buses, 1187 * we need to reset the correct gpio. */ 1188 if (port->nr == 1) 1189 bitmask = 0x01; 1190 else if (port->nr == 2) 1191 bitmask = 0x04; 1192 break; 1193 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID: 1194 /* Tuner Reset Command */ 1195 bitmask = 0x02; 1196 break; 1197 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: 1198 altera_ci_tuner_reset(dev, port->nr); 1199 break; 1200 case CX23885_BOARD_AVERMEDIA_HC81R: 1201 /* XC3028L Reset Command */ 1202 bitmask = 1 << 2; 1203 break; 1204 } 1205 1206 if (bitmask) { 1207 /* Drive the tuner into reset and back out */ 1208 cx_clear(GP0_IO, bitmask); 1209 mdelay(200); 1210 cx_set(GP0_IO, bitmask); 1211 } 1212 1213 return 0; 1214 } 1215 1216 void cx23885_gpio_setup(struct cx23885_dev *dev) 1217 { 1218 switch (dev->board) { 1219 case CX23885_BOARD_HAUPPAUGE_HVR1250: 1220 /* GPIO-0 cx24227 demodulator reset */ 1221 cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */ 1222 break; 1223 case CX23885_BOARD_HAUPPAUGE_HVR1500: 1224 /* GPIO-0 cx24227 demodulator */ 1225 /* GPIO-2 xc3028 tuner */ 1226 1227 /* Put the parts into reset */ 1228 cx_set(GP0_IO, 0x00050000); 1229 cx_clear(GP0_IO, 0x00000005); 1230 msleep(5); 1231 1232 /* Bring the parts out of reset */ 1233 cx_set(GP0_IO, 0x00050005); 1234 break; 1235 case CX23885_BOARD_HAUPPAUGE_HVR1500Q: 1236 /* GPIO-0 cx24227 demodulator reset */ 1237 /* GPIO-2 xc5000 tuner reset */ 1238 cx_set(GP0_IO, 0x00050005); /* Bring the part out of reset */ 1239 break; 1240 case CX23885_BOARD_HAUPPAUGE_HVR1800: 1241 /* GPIO-0 656_CLK */ 1242 /* GPIO-1 656_D0 */ 1243 /* GPIO-2 8295A Reset */ 1244 /* GPIO-3-10 cx23417 data0-7 */ 1245 /* GPIO-11-14 cx23417 addr0-3 */ 1246 /* GPIO-15-18 cx23417 READY, CS, RD, WR */ 1247 /* GPIO-19 IR_RX */ 1248 1249 /* CX23417 GPIO's */ 1250 /* EIO15 Zilog Reset */ 1251 /* EIO14 S5H1409/CX24227 Reset */ 1252 mc417_gpio_enable(dev, GPIO_15 | GPIO_14, 1); 1253 1254 /* Put the demod into reset and protect the eeprom */ 1255 mc417_gpio_clear(dev, GPIO_15 | GPIO_14); 1256 mdelay(100); 1257 1258 /* Bring the demod and blaster out of reset */ 1259 mc417_gpio_set(dev, GPIO_15 | GPIO_14); 1260 mdelay(100); 1261 1262 /* Force the TDA8295A into reset and back */ 1263 cx23885_gpio_enable(dev, GPIO_2, 1); 1264 cx23885_gpio_set(dev, GPIO_2); 1265 mdelay(20); 1266 cx23885_gpio_clear(dev, GPIO_2); 1267 mdelay(20); 1268 cx23885_gpio_set(dev, GPIO_2); 1269 mdelay(20); 1270 break; 1271 case CX23885_BOARD_HAUPPAUGE_HVR1200: 1272 /* GPIO-0 tda10048 demodulator reset */ 1273 /* GPIO-2 tda18271 tuner reset */ 1274 1275 /* Put the parts into reset and back */ 1276 cx_set(GP0_IO, 0x00050000); 1277 mdelay(20); 1278 cx_clear(GP0_IO, 0x00000005); 1279 mdelay(20); 1280 cx_set(GP0_IO, 0x00050005); 1281 break; 1282 case CX23885_BOARD_HAUPPAUGE_HVR1700: 1283 /* GPIO-0 TDA10048 demodulator reset */ 1284 /* GPIO-2 TDA8295A Reset */ 1285 /* GPIO-3-10 cx23417 data0-7 */ 1286 /* GPIO-11-14 cx23417 addr0-3 */ 1287 /* GPIO-15-18 cx23417 READY, CS, RD, WR */ 1288 1289 /* The following GPIO's are on the interna AVCore (cx25840) */ 1290 /* GPIO-19 IR_RX */ 1291 /* GPIO-20 IR_TX 416/DVBT Select */ 1292 /* GPIO-21 IIS DAT */ 1293 /* GPIO-22 IIS WCLK */ 1294 /* GPIO-23 IIS BCLK */ 1295 1296 /* Put the parts into reset and back */ 1297 cx_set(GP0_IO, 0x00050000); 1298 mdelay(20); 1299 cx_clear(GP0_IO, 0x00000005); 1300 mdelay(20); 1301 cx_set(GP0_IO, 0x00050005); 1302 break; 1303 case CX23885_BOARD_HAUPPAUGE_HVR1400: 1304 /* GPIO-0 Dibcom7000p demodulator reset */ 1305 /* GPIO-2 xc3028L tuner reset */ 1306 /* GPIO-13 LED */ 1307 1308 /* Put the parts into reset and back */ 1309 cx_set(GP0_IO, 0x00050000); 1310 mdelay(20); 1311 cx_clear(GP0_IO, 0x00000005); 1312 mdelay(20); 1313 cx_set(GP0_IO, 0x00050005); 1314 break; 1315 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP: 1316 /* GPIO-0 xc5000 tuner reset i2c bus 0 */ 1317 /* GPIO-1 s5h1409 demod reset i2c bus 0 */ 1318 /* GPIO-2 xc5000 tuner reset i2c bus 1 */ 1319 /* GPIO-3 s5h1409 demod reset i2c bus 0 */ 1320 1321 /* Put the parts into reset and back */ 1322 cx_set(GP0_IO, 0x000f0000); 1323 mdelay(20); 1324 cx_clear(GP0_IO, 0x0000000f); 1325 mdelay(20); 1326 cx_set(GP0_IO, 0x000f000f); 1327 break; 1328 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: 1329 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2: 1330 /* GPIO-0 portb xc3028 reset */ 1331 /* GPIO-1 portb zl10353 reset */ 1332 /* GPIO-2 portc xc3028 reset */ 1333 /* GPIO-3 portc zl10353 reset */ 1334 1335 /* Put the parts into reset and back */ 1336 cx_set(GP0_IO, 0x000f0000); 1337 mdelay(20); 1338 cx_clear(GP0_IO, 0x0000000f); 1339 mdelay(20); 1340 cx_set(GP0_IO, 0x000f000f); 1341 break; 1342 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H: 1343 case CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200: 1344 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000: 1345 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F: 1346 case CX23885_BOARD_COMPRO_VIDEOMATE_E800: 1347 case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200: 1348 /* GPIO-2 xc3028 tuner reset */ 1349 1350 /* The following GPIO's are on the internal AVCore (cx25840) */ 1351 /* GPIO-? zl10353 demod reset */ 1352 1353 /* Put the parts into reset and back */ 1354 cx_set(GP0_IO, 0x00040000); 1355 mdelay(20); 1356 cx_clear(GP0_IO, 0x00000004); 1357 mdelay(20); 1358 cx_set(GP0_IO, 0x00040004); 1359 break; 1360 case CX23885_BOARD_TBS_6920: 1361 case CX23885_BOARD_TBS_6980: 1362 case CX23885_BOARD_TBS_6981: 1363 case CX23885_BOARD_PROF_8000: 1364 cx_write(MC417_CTL, 0x00000036); 1365 cx_write(MC417_OEN, 0x00001000); 1366 cx_set(MC417_RWD, 0x00000002); 1367 mdelay(200); 1368 cx_clear(MC417_RWD, 0x00000800); 1369 mdelay(200); 1370 cx_set(MC417_RWD, 0x00000800); 1371 mdelay(200); 1372 break; 1373 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: 1374 /* GPIO-0 INTA from CiMax1 1375 GPIO-1 INTB from CiMax2 1376 GPIO-2 reset chips 1377 GPIO-3 to GPIO-10 data/addr for CA 1378 GPIO-11 ~CS0 to CiMax1 1379 GPIO-12 ~CS1 to CiMax2 1380 GPIO-13 ADL0 load LSB addr 1381 GPIO-14 ADL1 load MSB addr 1382 GPIO-15 ~RDY from CiMax 1383 GPIO-17 ~RD to CiMax 1384 GPIO-18 ~WR to CiMax 1385 */ 1386 cx_set(GP0_IO, 0x00040000); /* GPIO as out */ 1387 /* GPIO1 and GPIO2 as INTA and INTB from CiMaxes, reset low */ 1388 cx_clear(GP0_IO, 0x00030004); 1389 mdelay(100);/* reset delay */ 1390 cx_set(GP0_IO, 0x00040004); /* GPIO as out, reset high */ 1391 cx_write(MC417_CTL, 0x00000037);/* enable GPIO3-18 pins */ 1392 /* GPIO-15 IN as ~ACK, rest as OUT */ 1393 cx_write(MC417_OEN, 0x00001000); 1394 /* ~RD, ~WR high; ADL0, ADL1 low; ~CS0, ~CS1 high */ 1395 cx_write(MC417_RWD, 0x0000c300); 1396 /* enable irq */ 1397 cx_write(GPIO_ISM, 0x00000000);/* INTERRUPTS active low*/ 1398 break; 1399 case CX23885_BOARD_HAUPPAUGE_HVR1270: 1400 case CX23885_BOARD_HAUPPAUGE_HVR1275: 1401 case CX23885_BOARD_HAUPPAUGE_HVR1255: 1402 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111: 1403 case CX23885_BOARD_HAUPPAUGE_HVR1210: 1404 /* GPIO-5 RF Control: 0 = RF1 Terrestrial, 1 = RF2 Cable */ 1405 /* GPIO-6 I2C Gate which can isolate the demod from the bus */ 1406 /* GPIO-9 Demod reset */ 1407 1408 /* Put the parts into reset and back */ 1409 cx23885_gpio_enable(dev, GPIO_9 | GPIO_6 | GPIO_5, 1); 1410 cx23885_gpio_set(dev, GPIO_9 | GPIO_6 | GPIO_5); 1411 cx23885_gpio_clear(dev, GPIO_9); 1412 mdelay(20); 1413 cx23885_gpio_set(dev, GPIO_9); 1414 break; 1415 case CX23885_BOARD_MYGICA_X8506: 1416 case CX23885_BOARD_MAGICPRO_PROHDTVE2: 1417 case CX23885_BOARD_MYGICA_X8507: 1418 /* GPIO-0 (0)Analog / (1)Digital TV */ 1419 /* GPIO-1 reset XC5000 */ 1420 /* GPIO-2 demod reset */ 1421 cx23885_gpio_enable(dev, GPIO_0 | GPIO_1 | GPIO_2, 1); 1422 cx23885_gpio_clear(dev, GPIO_1 | GPIO_2); 1423 mdelay(100); 1424 cx23885_gpio_set(dev, GPIO_0 | GPIO_1 | GPIO_2); 1425 mdelay(100); 1426 break; 1427 case CX23885_BOARD_MYGICA_X8558PRO: 1428 /* GPIO-0 reset first ATBM8830 */ 1429 /* GPIO-1 reset second ATBM8830 */ 1430 cx23885_gpio_enable(dev, GPIO_0 | GPIO_1, 1); 1431 cx23885_gpio_clear(dev, GPIO_0 | GPIO_1); 1432 mdelay(100); 1433 cx23885_gpio_set(dev, GPIO_0 | GPIO_1); 1434 mdelay(100); 1435 break; 1436 case CX23885_BOARD_HAUPPAUGE_HVR1850: 1437 case CX23885_BOARD_HAUPPAUGE_HVR1290: 1438 /* GPIO-0 656_CLK */ 1439 /* GPIO-1 656_D0 */ 1440 /* GPIO-2 Wake# */ 1441 /* GPIO-3-10 cx23417 data0-7 */ 1442 /* GPIO-11-14 cx23417 addr0-3 */ 1443 /* GPIO-15-18 cx23417 READY, CS, RD, WR */ 1444 /* GPIO-19 IR_RX */ 1445 /* GPIO-20 C_IR_TX */ 1446 /* GPIO-21 I2S DAT */ 1447 /* GPIO-22 I2S WCLK */ 1448 /* GPIO-23 I2S BCLK */ 1449 /* ALT GPIO: EXP GPIO LATCH */ 1450 1451 /* CX23417 GPIO's */ 1452 /* GPIO-14 S5H1411/CX24228 Reset */ 1453 /* GPIO-13 EEPROM write protect */ 1454 mc417_gpio_enable(dev, GPIO_14 | GPIO_13, 1); 1455 1456 /* Put the demod into reset and protect the eeprom */ 1457 mc417_gpio_clear(dev, GPIO_14 | GPIO_13); 1458 mdelay(100); 1459 1460 /* Bring the demod out of reset */ 1461 mc417_gpio_set(dev, GPIO_14); 1462 mdelay(100); 1463 1464 /* CX24228 GPIO */ 1465 /* Connected to IF / Mux */ 1466 break; 1467 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID: 1468 cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */ 1469 break; 1470 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: 1471 /* GPIO-0 ~INT in 1472 GPIO-1 TMS out 1473 GPIO-2 ~reset chips out 1474 GPIO-3 to GPIO-10 data/addr for CA in/out 1475 GPIO-11 ~CS out 1476 GPIO-12 ADDR out 1477 GPIO-13 ~WR out 1478 GPIO-14 ~RD out 1479 GPIO-15 ~RDY in 1480 GPIO-16 TCK out 1481 GPIO-17 TDO in 1482 GPIO-18 TDI out 1483 */ 1484 cx_set(GP0_IO, 0x00060000); /* GPIO-1,2 as out */ 1485 /* GPIO-0 as INT, reset & TMS low */ 1486 cx_clear(GP0_IO, 0x00010006); 1487 mdelay(100);/* reset delay */ 1488 cx_set(GP0_IO, 0x00000004); /* reset high */ 1489 cx_write(MC417_CTL, 0x00000037);/* enable GPIO-3..18 pins */ 1490 /* GPIO-17 is TDO in, GPIO-15 is ~RDY in, rest is out */ 1491 cx_write(MC417_OEN, 0x00005000); 1492 /* ~RD, ~WR high; ADDR low; ~CS high */ 1493 cx_write(MC417_RWD, 0x00000d00); 1494 /* enable irq */ 1495 cx_write(GPIO_ISM, 0x00000000);/* INTERRUPTS active low*/ 1496 break; 1497 case CX23885_BOARD_HAUPPAUGE_HVR4400: 1498 /* GPIO-8 tda10071 demod reset */ 1499 /* GPIO-9 si2165 demod reset */ 1500 1501 /* Put the parts into reset and back */ 1502 cx23885_gpio_enable(dev, GPIO_8 | GPIO_9, 1); 1503 1504 cx23885_gpio_clear(dev, GPIO_8 | GPIO_9); 1505 mdelay(100); 1506 cx23885_gpio_set(dev, GPIO_8 | GPIO_9); 1507 mdelay(100); 1508 1509 break; 1510 case CX23885_BOARD_AVERMEDIA_HC81R: 1511 cx_clear(MC417_CTL, 1); 1512 /* GPIO-0,1,2 setup direction as output */ 1513 cx_set(GP0_IO, 0x00070000); 1514 mdelay(10); 1515 /* AF9013 demod reset */ 1516 cx_set(GP0_IO, 0x00010001); 1517 mdelay(10); 1518 cx_clear(GP0_IO, 0x00010001); 1519 mdelay(10); 1520 cx_set(GP0_IO, 0x00010001); 1521 mdelay(10); 1522 /* demod tune? */ 1523 cx_clear(GP0_IO, 0x00030003); 1524 mdelay(10); 1525 cx_set(GP0_IO, 0x00020002); 1526 mdelay(10); 1527 cx_set(GP0_IO, 0x00010001); 1528 mdelay(10); 1529 cx_clear(GP0_IO, 0x00020002); 1530 /* XC3028L tuner reset */ 1531 cx_set(GP0_IO, 0x00040004); 1532 cx_clear(GP0_IO, 0x00040004); 1533 cx_set(GP0_IO, 0x00040004); 1534 mdelay(60); 1535 break; 1536 case CX23885_BOARD_DVBSKY_T9580: 1537 /* enable GPIO3-18 pins */ 1538 cx_write(MC417_CTL, 0x00000037); 1539 cx23885_gpio_enable(dev, GPIO_2 | GPIO_11, 1); 1540 cx23885_gpio_clear(dev, GPIO_2 | GPIO_11); 1541 mdelay(100); 1542 cx23885_gpio_set(dev, GPIO_2 | GPIO_11); 1543 break; 1544 } 1545 } 1546 1547 int cx23885_ir_init(struct cx23885_dev *dev) 1548 { 1549 static struct v4l2_subdev_io_pin_config ir_rxtx_pin_cfg[] = { 1550 { 1551 .flags = V4L2_SUBDEV_IO_PIN_INPUT, 1552 .pin = CX23885_PIN_IR_RX_GPIO19, 1553 .function = CX23885_PAD_IR_RX, 1554 .value = 0, 1555 .strength = CX25840_PIN_DRIVE_MEDIUM, 1556 }, { 1557 .flags = V4L2_SUBDEV_IO_PIN_OUTPUT, 1558 .pin = CX23885_PIN_IR_TX_GPIO20, 1559 .function = CX23885_PAD_IR_TX, 1560 .value = 0, 1561 .strength = CX25840_PIN_DRIVE_MEDIUM, 1562 } 1563 }; 1564 const size_t ir_rxtx_pin_cfg_count = ARRAY_SIZE(ir_rxtx_pin_cfg); 1565 1566 static struct v4l2_subdev_io_pin_config ir_rx_pin_cfg[] = { 1567 { 1568 .flags = V4L2_SUBDEV_IO_PIN_INPUT, 1569 .pin = CX23885_PIN_IR_RX_GPIO19, 1570 .function = CX23885_PAD_IR_RX, 1571 .value = 0, 1572 .strength = CX25840_PIN_DRIVE_MEDIUM, 1573 } 1574 }; 1575 const size_t ir_rx_pin_cfg_count = ARRAY_SIZE(ir_rx_pin_cfg); 1576 1577 struct v4l2_subdev_ir_parameters params; 1578 int ret = 0; 1579 switch (dev->board) { 1580 case CX23885_BOARD_HAUPPAUGE_HVR1500: 1581 case CX23885_BOARD_HAUPPAUGE_HVR1500Q: 1582 case CX23885_BOARD_HAUPPAUGE_HVR1800: 1583 case CX23885_BOARD_HAUPPAUGE_HVR1200: 1584 case CX23885_BOARD_HAUPPAUGE_HVR1400: 1585 case CX23885_BOARD_HAUPPAUGE_HVR1275: 1586 case CX23885_BOARD_HAUPPAUGE_HVR1255: 1587 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111: 1588 case CX23885_BOARD_HAUPPAUGE_HVR1210: 1589 /* FIXME: Implement me */ 1590 break; 1591 case CX23885_BOARD_HAUPPAUGE_HVR1270: 1592 ret = cx23888_ir_probe(dev); 1593 if (ret) 1594 break; 1595 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_888_IR); 1596 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config, 1597 ir_rx_pin_cfg_count, ir_rx_pin_cfg); 1598 break; 1599 case CX23885_BOARD_HAUPPAUGE_HVR1850: 1600 case CX23885_BOARD_HAUPPAUGE_HVR1290: 1601 ret = cx23888_ir_probe(dev); 1602 if (ret) 1603 break; 1604 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_888_IR); 1605 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config, 1606 ir_rxtx_pin_cfg_count, ir_rxtx_pin_cfg); 1607 /* 1608 * For these boards we need to invert the Tx output via the 1609 * IR controller to have the LED off while idle 1610 */ 1611 v4l2_subdev_call(dev->sd_ir, ir, tx_g_parameters, ¶ms); 1612 params.enable = false; 1613 params.shutdown = false; 1614 params.invert_level = true; 1615 v4l2_subdev_call(dev->sd_ir, ir, tx_s_parameters, ¶ms); 1616 params.shutdown = true; 1617 v4l2_subdev_call(dev->sd_ir, ir, tx_s_parameters, ¶ms); 1618 break; 1619 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL: 1620 case CX23885_BOARD_TEVII_S470: 1621 case CX23885_BOARD_MYGICA_X8507: 1622 case CX23885_BOARD_TBS_6980: 1623 case CX23885_BOARD_TBS_6981: 1624 if (!enable_885_ir) 1625 break; 1626 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_AV_CORE); 1627 if (dev->sd_ir == NULL) { 1628 ret = -ENODEV; 1629 break; 1630 } 1631 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config, 1632 ir_rx_pin_cfg_count, ir_rx_pin_cfg); 1633 break; 1634 case CX23885_BOARD_HAUPPAUGE_HVR1250: 1635 if (!enable_885_ir) 1636 break; 1637 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_AV_CORE); 1638 if (dev->sd_ir == NULL) { 1639 ret = -ENODEV; 1640 break; 1641 } 1642 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config, 1643 ir_rxtx_pin_cfg_count, ir_rxtx_pin_cfg); 1644 break; 1645 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: 1646 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2: 1647 request_module("ir-kbd-i2c"); 1648 break; 1649 } 1650 1651 return ret; 1652 } 1653 1654 void cx23885_ir_fini(struct cx23885_dev *dev) 1655 { 1656 switch (dev->board) { 1657 case CX23885_BOARD_HAUPPAUGE_HVR1270: 1658 case CX23885_BOARD_HAUPPAUGE_HVR1850: 1659 case CX23885_BOARD_HAUPPAUGE_HVR1290: 1660 cx23885_irq_remove(dev, PCI_MSK_IR); 1661 cx23888_ir_remove(dev); 1662 dev->sd_ir = NULL; 1663 break; 1664 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL: 1665 case CX23885_BOARD_TEVII_S470: 1666 case CX23885_BOARD_HAUPPAUGE_HVR1250: 1667 case CX23885_BOARD_MYGICA_X8507: 1668 case CX23885_BOARD_TBS_6980: 1669 case CX23885_BOARD_TBS_6981: 1670 cx23885_irq_remove(dev, PCI_MSK_AV_CORE); 1671 /* sd_ir is a duplicate pointer to the AV Core, just clear it */ 1672 dev->sd_ir = NULL; 1673 break; 1674 } 1675 } 1676 1677 static int netup_jtag_io(void *device, int tms, int tdi, int read_tdo) 1678 { 1679 int data; 1680 int tdo = 0; 1681 struct cx23885_dev *dev = (struct cx23885_dev *)device; 1682 /*TMS*/ 1683 data = ((cx_read(GP0_IO)) & (~0x00000002)); 1684 data |= (tms ? 0x00020002 : 0x00020000); 1685 cx_write(GP0_IO, data); 1686 1687 /*TDI*/ 1688 data = ((cx_read(MC417_RWD)) & (~0x0000a000)); 1689 data |= (tdi ? 0x00008000 : 0); 1690 cx_write(MC417_RWD, data); 1691 if (read_tdo) 1692 tdo = (data & 0x00004000) ? 1 : 0; /*TDO*/ 1693 1694 cx_write(MC417_RWD, data | 0x00002000); 1695 udelay(1); 1696 /*TCK*/ 1697 cx_write(MC417_RWD, data); 1698 1699 return tdo; 1700 } 1701 1702 void cx23885_ir_pci_int_enable(struct cx23885_dev *dev) 1703 { 1704 switch (dev->board) { 1705 case CX23885_BOARD_HAUPPAUGE_HVR1270: 1706 case CX23885_BOARD_HAUPPAUGE_HVR1850: 1707 case CX23885_BOARD_HAUPPAUGE_HVR1290: 1708 if (dev->sd_ir) 1709 cx23885_irq_add_enable(dev, PCI_MSK_IR); 1710 break; 1711 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL: 1712 case CX23885_BOARD_TEVII_S470: 1713 case CX23885_BOARD_HAUPPAUGE_HVR1250: 1714 case CX23885_BOARD_MYGICA_X8507: 1715 case CX23885_BOARD_TBS_6980: 1716 case CX23885_BOARD_TBS_6981: 1717 if (dev->sd_ir) 1718 cx23885_irq_add_enable(dev, PCI_MSK_AV_CORE); 1719 break; 1720 } 1721 } 1722 1723 void cx23885_card_setup(struct cx23885_dev *dev) 1724 { 1725 struct cx23885_tsport *ts1 = &dev->ts1; 1726 struct cx23885_tsport *ts2 = &dev->ts2; 1727 1728 static u8 eeprom[256]; 1729 1730 if (dev->i2c_bus[0].i2c_rc == 0) { 1731 dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1; 1732 tveeprom_read(&dev->i2c_bus[0].i2c_client, 1733 eeprom, sizeof(eeprom)); 1734 } 1735 1736 switch (dev->board) { 1737 case CX23885_BOARD_HAUPPAUGE_HVR1250: 1738 if (dev->i2c_bus[0].i2c_rc == 0) { 1739 if (eeprom[0x80] != 0x84) 1740 hauppauge_eeprom(dev, eeprom+0xc0); 1741 else 1742 hauppauge_eeprom(dev, eeprom+0x80); 1743 } 1744 break; 1745 case CX23885_BOARD_HAUPPAUGE_HVR1500: 1746 case CX23885_BOARD_HAUPPAUGE_HVR1500Q: 1747 case CX23885_BOARD_HAUPPAUGE_HVR1400: 1748 if (dev->i2c_bus[0].i2c_rc == 0) 1749 hauppauge_eeprom(dev, eeprom+0x80); 1750 break; 1751 case CX23885_BOARD_HAUPPAUGE_HVR1800: 1752 case CX23885_BOARD_HAUPPAUGE_HVR1800lp: 1753 case CX23885_BOARD_HAUPPAUGE_HVR1200: 1754 case CX23885_BOARD_HAUPPAUGE_HVR1700: 1755 case CX23885_BOARD_HAUPPAUGE_HVR1270: 1756 case CX23885_BOARD_HAUPPAUGE_HVR1275: 1757 case CX23885_BOARD_HAUPPAUGE_HVR1255: 1758 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111: 1759 case CX23885_BOARD_HAUPPAUGE_HVR1210: 1760 case CX23885_BOARD_HAUPPAUGE_HVR1850: 1761 case CX23885_BOARD_HAUPPAUGE_HVR1290: 1762 case CX23885_BOARD_HAUPPAUGE_HVR4400: 1763 case CX23885_BOARD_HAUPPAUGE_IMPACTVCBE: 1764 if (dev->i2c_bus[0].i2c_rc == 0) 1765 hauppauge_eeprom(dev, eeprom+0xc0); 1766 break; 1767 } 1768 1769 switch (dev->board) { 1770 case CX23885_BOARD_AVERMEDIA_HC81R: 1771 /* Defaults for VID B */ 1772 ts1->gen_ctrl_val = 0x4; /* Parallel */ 1773 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1774 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1775 /* Defaults for VID C */ 1776 /* DREQ_POL, SMODE, PUNC_CLK, MCLK_POL Serial bus + punc clk */ 1777 ts2->gen_ctrl_val = 0x10e; 1778 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1779 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1780 break; 1781 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP: 1782 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: 1783 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2: 1784 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 1785 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1786 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1787 /* break omitted intentionally */ 1788 case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP: 1789 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 1790 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1791 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1792 break; 1793 case CX23885_BOARD_HAUPPAUGE_HVR1850: 1794 case CX23885_BOARD_HAUPPAUGE_HVR1800: 1795 /* Defaults for VID B - Analog encoder */ 1796 /* DREQ_POL, SMODE, PUNC_CLK, MCLK_POL Serial bus + punc clk */ 1797 ts1->gen_ctrl_val = 0x10e; 1798 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1799 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1800 1801 /* APB_TSVALERR_POL (active low)*/ 1802 ts1->vld_misc_val = 0x2000; 1803 ts1->hw_sop_ctrl_val = (0x47 << 16 | 188 << 4 | 0xc); 1804 cx_write(0x130184, 0xc); 1805 1806 /* Defaults for VID C */ 1807 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 1808 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1809 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1810 break; 1811 case CX23885_BOARD_TBS_6920: 1812 ts1->gen_ctrl_val = 0x4; /* Parallel */ 1813 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1814 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1815 break; 1816 case CX23885_BOARD_TEVII_S470: 1817 case CX23885_BOARD_TEVII_S471: 1818 case CX23885_BOARD_DVBWORLD_2005: 1819 case CX23885_BOARD_PROF_8000: 1820 ts1->gen_ctrl_val = 0x5; /* Parallel */ 1821 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1822 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1823 break; 1824 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: 1825 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: 1826 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL: 1827 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 1828 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1829 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1830 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 1831 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1832 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1833 break; 1834 case CX23885_BOARD_TBS_6980: 1835 case CX23885_BOARD_TBS_6981: 1836 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 1837 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1838 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1839 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 1840 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1841 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1842 tbs_card_init(dev); 1843 break; 1844 case CX23885_BOARD_MYGICA_X8506: 1845 case CX23885_BOARD_MAGICPRO_PROHDTVE2: 1846 case CX23885_BOARD_MYGICA_X8507: 1847 ts1->gen_ctrl_val = 0x5; /* Parallel */ 1848 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1849 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1850 break; 1851 case CX23885_BOARD_MYGICA_X8558PRO: 1852 ts1->gen_ctrl_val = 0x5; /* Parallel */ 1853 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1854 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1855 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 1856 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1857 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1858 break; 1859 case CX23885_BOARD_HAUPPAUGE_HVR4400: 1860 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 1861 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1862 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1863 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 1864 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1865 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1866 break; 1867 case CX23885_BOARD_DVBSKY_T9580: 1868 ts1->gen_ctrl_val = 0x5; /* Parallel */ 1869 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1870 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1871 ts2->gen_ctrl_val = 0x8; /* Serial bus */ 1872 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1873 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1874 break; 1875 case CX23885_BOARD_HAUPPAUGE_HVR1250: 1876 case CX23885_BOARD_HAUPPAUGE_HVR1500: 1877 case CX23885_BOARD_HAUPPAUGE_HVR1500Q: 1878 case CX23885_BOARD_HAUPPAUGE_HVR1800lp: 1879 case CX23885_BOARD_HAUPPAUGE_HVR1200: 1880 case CX23885_BOARD_HAUPPAUGE_HVR1700: 1881 case CX23885_BOARD_HAUPPAUGE_HVR1400: 1882 case CX23885_BOARD_HAUPPAUGE_IMPACTVCBE: 1883 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H: 1884 case CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200: 1885 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000: 1886 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F: 1887 case CX23885_BOARD_HAUPPAUGE_HVR1270: 1888 case CX23885_BOARD_HAUPPAUGE_HVR1275: 1889 case CX23885_BOARD_HAUPPAUGE_HVR1255: 1890 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111: 1891 case CX23885_BOARD_HAUPPAUGE_HVR1210: 1892 case CX23885_BOARD_COMPRO_VIDEOMATE_E800: 1893 case CX23885_BOARD_HAUPPAUGE_HVR1290: 1894 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID: 1895 default: 1896 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 1897 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1898 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1899 } 1900 1901 /* Certain boards support analog, or require the avcore to be 1902 * loaded, ensure this happens. 1903 */ 1904 switch (dev->board) { 1905 case CX23885_BOARD_TEVII_S470: 1906 /* Currently only enabled for the integrated IR controller */ 1907 if (!enable_885_ir) 1908 break; 1909 case CX23885_BOARD_HAUPPAUGE_HVR1250: 1910 case CX23885_BOARD_HAUPPAUGE_HVR1800: 1911 case CX23885_BOARD_HAUPPAUGE_IMPACTVCBE: 1912 case CX23885_BOARD_HAUPPAUGE_HVR1800lp: 1913 case CX23885_BOARD_HAUPPAUGE_HVR1700: 1914 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H: 1915 case CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200: 1916 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000: 1917 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F: 1918 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: 1919 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: 1920 case CX23885_BOARD_COMPRO_VIDEOMATE_E800: 1921 case CX23885_BOARD_HAUPPAUGE_HVR1255: 1922 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111: 1923 case CX23885_BOARD_HAUPPAUGE_HVR1270: 1924 case CX23885_BOARD_HAUPPAUGE_HVR1850: 1925 case CX23885_BOARD_MYGICA_X8506: 1926 case CX23885_BOARD_MAGICPRO_PROHDTVE2: 1927 case CX23885_BOARD_HAUPPAUGE_HVR1290: 1928 case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200: 1929 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID: 1930 case CX23885_BOARD_HAUPPAUGE_HVR1500: 1931 case CX23885_BOARD_MPX885: 1932 case CX23885_BOARD_MYGICA_X8507: 1933 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL: 1934 case CX23885_BOARD_AVERMEDIA_HC81R: 1935 case CX23885_BOARD_TBS_6980: 1936 case CX23885_BOARD_TBS_6981: 1937 case CX23885_BOARD_DVBSKY_T9580: 1938 dev->sd_cx25840 = v4l2_i2c_new_subdev(&dev->v4l2_dev, 1939 &dev->i2c_bus[2].i2c_adap, 1940 "cx25840", 0x88 >> 1, NULL); 1941 if (dev->sd_cx25840) { 1942 dev->sd_cx25840->grp_id = CX23885_HW_AV_CORE; 1943 v4l2_subdev_call(dev->sd_cx25840, core, load_fw); 1944 } 1945 break; 1946 } 1947 1948 /* AUX-PLL 27MHz CLK */ 1949 switch (dev->board) { 1950 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: 1951 netup_initialize(dev); 1952 break; 1953 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: { 1954 int ret; 1955 const struct firmware *fw; 1956 const char *filename = "dvb-netup-altera-01.fw"; 1957 char *action = "configure"; 1958 static struct netup_card_info cinfo; 1959 struct altera_config netup_config = { 1960 .dev = dev, 1961 .action = action, 1962 .jtag_io = netup_jtag_io, 1963 }; 1964 1965 netup_initialize(dev); 1966 1967 netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo); 1968 if (netup_card_rev) 1969 cinfo.rev = netup_card_rev; 1970 1971 switch (cinfo.rev) { 1972 case 0x4: 1973 filename = "dvb-netup-altera-04.fw"; 1974 break; 1975 default: 1976 filename = "dvb-netup-altera-01.fw"; 1977 break; 1978 } 1979 printk(KERN_INFO "NetUP card rev=0x%x fw_filename=%s\n", 1980 cinfo.rev, filename); 1981 1982 ret = request_firmware(&fw, filename, &dev->pci->dev); 1983 if (ret != 0) 1984 printk(KERN_ERR "did not find the firmware file. (%s) " 1985 "Please see linux/Documentation/dvb/ for more details " 1986 "on firmware-problems.", filename); 1987 else 1988 altera_init(&netup_config, fw); 1989 1990 release_firmware(fw); 1991 break; 1992 } 1993 } 1994 } 1995