1 /* 2 * Driver for the Conexant CX23885 PCIe bridge 3 * 4 * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * 15 * GNU General Public License for more details. 16 */ 17 18 #include "cx23885.h" 19 20 #include <linux/init.h> 21 #include <linux/module.h> 22 #include <linux/pci.h> 23 #include <linux/delay.h> 24 #include <media/drv-intf/cx25840.h> 25 #include <linux/firmware.h> 26 #include <misc/altera.h> 27 28 #include "tuner-xc2028.h" 29 #include "netup-eeprom.h" 30 #include "netup-init.h" 31 #include "altera-ci.h" 32 #include "xc4000.h" 33 #include "xc5000.h" 34 #include "cx23888-ir.h" 35 36 static unsigned int netup_card_rev = 4; 37 module_param(netup_card_rev, int, 0644); 38 MODULE_PARM_DESC(netup_card_rev, 39 "NetUP Dual DVB-T/C CI card revision"); 40 static unsigned int enable_885_ir; 41 module_param(enable_885_ir, int, 0644); 42 MODULE_PARM_DESC(enable_885_ir, 43 "Enable integrated IR controller for supported\n" 44 "\t\t CX2388[57] boards that are wired for it:\n" 45 "\t\t\tHVR-1250 (reported safe)\n" 46 "\t\t\tTerraTec Cinergy T PCIe Dual (not well tested, appears to be safe)\n" 47 "\t\t\tTeVii S470 (reported unsafe)\n" 48 "\t\t This can cause an interrupt storm with some cards.\n" 49 "\t\t Default: 0 [Disabled]"); 50 51 /* ------------------------------------------------------------------ */ 52 /* board config info */ 53 54 struct cx23885_board cx23885_boards[] = { 55 [CX23885_BOARD_UNKNOWN] = { 56 .name = "UNKNOWN/GENERIC", 57 /* Ensure safe default for unknown boards */ 58 .clk_freq = 0, 59 .input = {{ 60 .type = CX23885_VMUX_COMPOSITE1, 61 .vmux = 0, 62 }, { 63 .type = CX23885_VMUX_COMPOSITE2, 64 .vmux = 1, 65 }, { 66 .type = CX23885_VMUX_COMPOSITE3, 67 .vmux = 2, 68 }, { 69 .type = CX23885_VMUX_COMPOSITE4, 70 .vmux = 3, 71 } }, 72 }, 73 [CX23885_BOARD_HAUPPAUGE_HVR1800lp] = { 74 .name = "Hauppauge WinTV-HVR1800lp", 75 .portc = CX23885_MPEG_DVB, 76 .input = {{ 77 .type = CX23885_VMUX_TELEVISION, 78 .vmux = 0, 79 .gpio0 = 0xff00, 80 }, { 81 .type = CX23885_VMUX_DEBUG, 82 .vmux = 0, 83 .gpio0 = 0xff01, 84 }, { 85 .type = CX23885_VMUX_COMPOSITE1, 86 .vmux = 1, 87 .gpio0 = 0xff02, 88 }, { 89 .type = CX23885_VMUX_SVIDEO, 90 .vmux = 2, 91 .gpio0 = 0xff02, 92 } }, 93 }, 94 [CX23885_BOARD_HAUPPAUGE_HVR1800] = { 95 .name = "Hauppauge WinTV-HVR1800", 96 .porta = CX23885_ANALOG_VIDEO, 97 .portb = CX23885_MPEG_ENCODER, 98 .portc = CX23885_MPEG_DVB, 99 .tuner_type = TUNER_PHILIPS_TDA8290, 100 .tuner_addr = 0x42, /* 0x84 >> 1 */ 101 .tuner_bus = 1, 102 .input = {{ 103 .type = CX23885_VMUX_TELEVISION, 104 .vmux = CX25840_VIN7_CH3 | 105 CX25840_VIN5_CH2 | 106 CX25840_VIN2_CH1, 107 .amux = CX25840_AUDIO8, 108 .gpio0 = 0, 109 }, { 110 .type = CX23885_VMUX_COMPOSITE1, 111 .vmux = CX25840_VIN7_CH3 | 112 CX25840_VIN4_CH2 | 113 CX25840_VIN6_CH1, 114 .amux = CX25840_AUDIO7, 115 .gpio0 = 0, 116 }, { 117 .type = CX23885_VMUX_SVIDEO, 118 .vmux = CX25840_VIN7_CH3 | 119 CX25840_VIN4_CH2 | 120 CX25840_VIN8_CH1 | 121 CX25840_SVIDEO_ON, 122 .amux = CX25840_AUDIO7, 123 .gpio0 = 0, 124 } }, 125 }, 126 [CX23885_BOARD_HAUPPAUGE_HVR1250] = { 127 .name = "Hauppauge WinTV-HVR1250", 128 .porta = CX23885_ANALOG_VIDEO, 129 .portc = CX23885_MPEG_DVB, 130 #ifdef MT2131_NO_ANALOG_SUPPORT_YET 131 .tuner_type = TUNER_PHILIPS_TDA8290, 132 .tuner_addr = 0x42, /* 0x84 >> 1 */ 133 .tuner_bus = 1, 134 #endif 135 .force_bff = 1, 136 .input = {{ 137 #ifdef MT2131_NO_ANALOG_SUPPORT_YET 138 .type = CX23885_VMUX_TELEVISION, 139 .vmux = CX25840_VIN7_CH3 | 140 CX25840_VIN5_CH2 | 141 CX25840_VIN2_CH1, 142 .amux = CX25840_AUDIO8, 143 .gpio0 = 0xff00, 144 }, { 145 #endif 146 .type = CX23885_VMUX_COMPOSITE1, 147 .vmux = CX25840_VIN7_CH3 | 148 CX25840_VIN4_CH2 | 149 CX25840_VIN6_CH1, 150 .amux = CX25840_AUDIO7, 151 .gpio0 = 0xff02, 152 }, { 153 .type = CX23885_VMUX_SVIDEO, 154 .vmux = CX25840_VIN7_CH3 | 155 CX25840_VIN4_CH2 | 156 CX25840_VIN8_CH1 | 157 CX25840_SVIDEO_ON, 158 .amux = CX25840_AUDIO7, 159 .gpio0 = 0xff02, 160 } }, 161 }, 162 [CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP] = { 163 .name = "DViCO FusionHDTV5 Express", 164 .portb = CX23885_MPEG_DVB, 165 }, 166 [CX23885_BOARD_HAUPPAUGE_HVR1500Q] = { 167 .name = "Hauppauge WinTV-HVR1500Q", 168 .portc = CX23885_MPEG_DVB, 169 }, 170 [CX23885_BOARD_HAUPPAUGE_HVR1500] = { 171 .name = "Hauppauge WinTV-HVR1500", 172 .porta = CX23885_ANALOG_VIDEO, 173 .portc = CX23885_MPEG_DVB, 174 .tuner_type = TUNER_XC2028, 175 .tuner_addr = 0x61, /* 0xc2 >> 1 */ 176 .input = {{ 177 .type = CX23885_VMUX_TELEVISION, 178 .vmux = CX25840_VIN7_CH3 | 179 CX25840_VIN5_CH2 | 180 CX25840_VIN2_CH1, 181 .gpio0 = 0, 182 }, { 183 .type = CX23885_VMUX_COMPOSITE1, 184 .vmux = CX25840_VIN7_CH3 | 185 CX25840_VIN4_CH2 | 186 CX25840_VIN6_CH1, 187 .gpio0 = 0, 188 }, { 189 .type = CX23885_VMUX_SVIDEO, 190 .vmux = CX25840_VIN7_CH3 | 191 CX25840_VIN4_CH2 | 192 CX25840_VIN8_CH1 | 193 CX25840_SVIDEO_ON, 194 .gpio0 = 0, 195 } }, 196 }, 197 [CX23885_BOARD_HAUPPAUGE_HVR1200] = { 198 .name = "Hauppauge WinTV-HVR1200", 199 .portc = CX23885_MPEG_DVB, 200 }, 201 [CX23885_BOARD_HAUPPAUGE_HVR1700] = { 202 .name = "Hauppauge WinTV-HVR1700", 203 .portc = CX23885_MPEG_DVB, 204 }, 205 [CX23885_BOARD_HAUPPAUGE_HVR1400] = { 206 .name = "Hauppauge WinTV-HVR1400", 207 .portc = CX23885_MPEG_DVB, 208 }, 209 [CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP] = { 210 .name = "DViCO FusionHDTV7 Dual Express", 211 .portb = CX23885_MPEG_DVB, 212 .portc = CX23885_MPEG_DVB, 213 }, 214 [CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP] = { 215 .name = "DViCO FusionHDTV DVB-T Dual Express", 216 .portb = CX23885_MPEG_DVB, 217 .portc = CX23885_MPEG_DVB, 218 }, 219 [CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H] = { 220 .name = "Leadtek Winfast PxDVR3200 H", 221 .portc = CX23885_MPEG_DVB, 222 }, 223 [CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200] = { 224 .name = "Leadtek Winfast PxPVR2200", 225 .porta = CX23885_ANALOG_VIDEO, 226 .tuner_type = TUNER_XC2028, 227 .tuner_addr = 0x61, 228 .tuner_bus = 1, 229 .input = {{ 230 .type = CX23885_VMUX_TELEVISION, 231 .vmux = CX25840_VIN2_CH1 | 232 CX25840_VIN5_CH2, 233 .amux = CX25840_AUDIO8, 234 .gpio0 = 0x704040, 235 }, { 236 .type = CX23885_VMUX_COMPOSITE1, 237 .vmux = CX25840_COMPOSITE1, 238 .amux = CX25840_AUDIO7, 239 .gpio0 = 0x704040, 240 }, { 241 .type = CX23885_VMUX_SVIDEO, 242 .vmux = CX25840_SVIDEO_LUMA3 | 243 CX25840_SVIDEO_CHROMA4, 244 .amux = CX25840_AUDIO7, 245 .gpio0 = 0x704040, 246 }, { 247 .type = CX23885_VMUX_COMPONENT, 248 .vmux = CX25840_VIN7_CH1 | 249 CX25840_VIN6_CH2 | 250 CX25840_VIN8_CH3 | 251 CX25840_COMPONENT_ON, 252 .amux = CX25840_AUDIO7, 253 .gpio0 = 0x704040, 254 } }, 255 }, 256 [CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000] = { 257 .name = "Leadtek Winfast PxDVR3200 H XC4000", 258 .porta = CX23885_ANALOG_VIDEO, 259 .portc = CX23885_MPEG_DVB, 260 .tuner_type = TUNER_XC4000, 261 .tuner_addr = 0x61, 262 .radio_type = UNSET, 263 .radio_addr = ADDR_UNSET, 264 .input = {{ 265 .type = CX23885_VMUX_TELEVISION, 266 .vmux = CX25840_VIN2_CH1 | 267 CX25840_VIN5_CH2 | 268 CX25840_NONE0_CH3, 269 }, { 270 .type = CX23885_VMUX_COMPOSITE1, 271 .vmux = CX25840_COMPOSITE1, 272 }, { 273 .type = CX23885_VMUX_SVIDEO, 274 .vmux = CX25840_SVIDEO_LUMA3 | 275 CX25840_SVIDEO_CHROMA4, 276 }, { 277 .type = CX23885_VMUX_COMPONENT, 278 .vmux = CX25840_VIN7_CH1 | 279 CX25840_VIN6_CH2 | 280 CX25840_VIN8_CH3 | 281 CX25840_COMPONENT_ON, 282 } }, 283 }, 284 [CX23885_BOARD_COMPRO_VIDEOMATE_E650F] = { 285 .name = "Compro VideoMate E650F", 286 .portc = CX23885_MPEG_DVB, 287 }, 288 [CX23885_BOARD_TBS_6920] = { 289 .name = "TurboSight TBS 6920", 290 .portb = CX23885_MPEG_DVB, 291 }, 292 [CX23885_BOARD_TBS_6980] = { 293 .name = "TurboSight TBS 6980", 294 .portb = CX23885_MPEG_DVB, 295 .portc = CX23885_MPEG_DVB, 296 }, 297 [CX23885_BOARD_TBS_6981] = { 298 .name = "TurboSight TBS 6981", 299 .portb = CX23885_MPEG_DVB, 300 .portc = CX23885_MPEG_DVB, 301 }, 302 [CX23885_BOARD_TEVII_S470] = { 303 .name = "TeVii S470", 304 .portb = CX23885_MPEG_DVB, 305 }, 306 [CX23885_BOARD_DVBWORLD_2005] = { 307 .name = "DVBWorld DVB-S2 2005", 308 .portb = CX23885_MPEG_DVB, 309 }, 310 [CX23885_BOARD_NETUP_DUAL_DVBS2_CI] = { 311 .ci_type = 1, 312 .name = "NetUP Dual DVB-S2 CI", 313 .portb = CX23885_MPEG_DVB, 314 .portc = CX23885_MPEG_DVB, 315 }, 316 [CX23885_BOARD_HAUPPAUGE_HVR1270] = { 317 .name = "Hauppauge WinTV-HVR1270", 318 .portc = CX23885_MPEG_DVB, 319 }, 320 [CX23885_BOARD_HAUPPAUGE_HVR1275] = { 321 .name = "Hauppauge WinTV-HVR1275", 322 .portc = CX23885_MPEG_DVB, 323 }, 324 [CX23885_BOARD_HAUPPAUGE_HVR1255] = { 325 .name = "Hauppauge WinTV-HVR1255", 326 .porta = CX23885_ANALOG_VIDEO, 327 .portc = CX23885_MPEG_DVB, 328 .tuner_type = TUNER_ABSENT, 329 .tuner_addr = 0x42, /* 0x84 >> 1 */ 330 .force_bff = 1, 331 .input = {{ 332 .type = CX23885_VMUX_TELEVISION, 333 .vmux = CX25840_VIN7_CH3 | 334 CX25840_VIN5_CH2 | 335 CX25840_VIN2_CH1 | 336 CX25840_DIF_ON, 337 .amux = CX25840_AUDIO8, 338 }, { 339 .type = CX23885_VMUX_COMPOSITE1, 340 .vmux = CX25840_VIN7_CH3 | 341 CX25840_VIN4_CH2 | 342 CX25840_VIN6_CH1, 343 .amux = CX25840_AUDIO7, 344 }, { 345 .type = CX23885_VMUX_SVIDEO, 346 .vmux = CX25840_VIN7_CH3 | 347 CX25840_VIN4_CH2 | 348 CX25840_VIN8_CH1 | 349 CX25840_SVIDEO_ON, 350 .amux = CX25840_AUDIO7, 351 } }, 352 }, 353 [CX23885_BOARD_HAUPPAUGE_HVR1255_22111] = { 354 .name = "Hauppauge WinTV-HVR1255", 355 .porta = CX23885_ANALOG_VIDEO, 356 .portc = CX23885_MPEG_DVB, 357 .tuner_type = TUNER_ABSENT, 358 .tuner_addr = 0x42, /* 0x84 >> 1 */ 359 .force_bff = 1, 360 .input = {{ 361 .type = CX23885_VMUX_TELEVISION, 362 .vmux = CX25840_VIN7_CH3 | 363 CX25840_VIN5_CH2 | 364 CX25840_VIN2_CH1 | 365 CX25840_DIF_ON, 366 .amux = CX25840_AUDIO8, 367 }, { 368 .type = CX23885_VMUX_SVIDEO, 369 .vmux = CX25840_VIN7_CH3 | 370 CX25840_VIN4_CH2 | 371 CX25840_VIN8_CH1 | 372 CX25840_SVIDEO_ON, 373 .amux = CX25840_AUDIO7, 374 } }, 375 }, 376 [CX23885_BOARD_HAUPPAUGE_HVR1210] = { 377 .name = "Hauppauge WinTV-HVR1210", 378 .portc = CX23885_MPEG_DVB, 379 }, 380 [CX23885_BOARD_MYGICA_X8506] = { 381 .name = "Mygica X8506 DMB-TH", 382 .tuner_type = TUNER_XC5000, 383 .tuner_addr = 0x61, 384 .tuner_bus = 1, 385 .porta = CX23885_ANALOG_VIDEO, 386 .portb = CX23885_MPEG_DVB, 387 .input = { 388 { 389 .type = CX23885_VMUX_TELEVISION, 390 .vmux = CX25840_COMPOSITE2, 391 }, 392 { 393 .type = CX23885_VMUX_COMPOSITE1, 394 .vmux = CX25840_COMPOSITE8, 395 }, 396 { 397 .type = CX23885_VMUX_SVIDEO, 398 .vmux = CX25840_SVIDEO_LUMA3 | 399 CX25840_SVIDEO_CHROMA4, 400 }, 401 { 402 .type = CX23885_VMUX_COMPONENT, 403 .vmux = CX25840_COMPONENT_ON | 404 CX25840_VIN1_CH1 | 405 CX25840_VIN6_CH2 | 406 CX25840_VIN7_CH3, 407 }, 408 }, 409 }, 410 [CX23885_BOARD_MAGICPRO_PROHDTVE2] = { 411 .name = "Magic-Pro ProHDTV Extreme 2", 412 .tuner_type = TUNER_XC5000, 413 .tuner_addr = 0x61, 414 .tuner_bus = 1, 415 .porta = CX23885_ANALOG_VIDEO, 416 .portb = CX23885_MPEG_DVB, 417 .input = { 418 { 419 .type = CX23885_VMUX_TELEVISION, 420 .vmux = CX25840_COMPOSITE2, 421 }, 422 { 423 .type = CX23885_VMUX_COMPOSITE1, 424 .vmux = CX25840_COMPOSITE8, 425 }, 426 { 427 .type = CX23885_VMUX_SVIDEO, 428 .vmux = CX25840_SVIDEO_LUMA3 | 429 CX25840_SVIDEO_CHROMA4, 430 }, 431 { 432 .type = CX23885_VMUX_COMPONENT, 433 .vmux = CX25840_COMPONENT_ON | 434 CX25840_VIN1_CH1 | 435 CX25840_VIN6_CH2 | 436 CX25840_VIN7_CH3, 437 }, 438 }, 439 }, 440 [CX23885_BOARD_HAUPPAUGE_HVR1850] = { 441 .name = "Hauppauge WinTV-HVR1850", 442 .porta = CX23885_ANALOG_VIDEO, 443 .portb = CX23885_MPEG_ENCODER, 444 .portc = CX23885_MPEG_DVB, 445 .tuner_type = TUNER_ABSENT, 446 .tuner_addr = 0x42, /* 0x84 >> 1 */ 447 .force_bff = 1, 448 .input = {{ 449 .type = CX23885_VMUX_TELEVISION, 450 .vmux = CX25840_VIN7_CH3 | 451 CX25840_VIN5_CH2 | 452 CX25840_VIN2_CH1 | 453 CX25840_DIF_ON, 454 .amux = CX25840_AUDIO8, 455 }, { 456 .type = CX23885_VMUX_COMPOSITE1, 457 .vmux = CX25840_VIN7_CH3 | 458 CX25840_VIN4_CH2 | 459 CX25840_VIN6_CH1, 460 .amux = CX25840_AUDIO7, 461 }, { 462 .type = CX23885_VMUX_SVIDEO, 463 .vmux = CX25840_VIN7_CH3 | 464 CX25840_VIN4_CH2 | 465 CX25840_VIN8_CH1 | 466 CX25840_SVIDEO_ON, 467 .amux = CX25840_AUDIO7, 468 } }, 469 }, 470 [CX23885_BOARD_COMPRO_VIDEOMATE_E800] = { 471 .name = "Compro VideoMate E800", 472 .portc = CX23885_MPEG_DVB, 473 }, 474 [CX23885_BOARD_HAUPPAUGE_HVR1290] = { 475 .name = "Hauppauge WinTV-HVR1290", 476 .portc = CX23885_MPEG_DVB, 477 }, 478 [CX23885_BOARD_MYGICA_X8558PRO] = { 479 .name = "Mygica X8558 PRO DMB-TH", 480 .portb = CX23885_MPEG_DVB, 481 .portc = CX23885_MPEG_DVB, 482 }, 483 [CX23885_BOARD_LEADTEK_WINFAST_PXTV1200] = { 484 .name = "LEADTEK WinFast PxTV1200", 485 .porta = CX23885_ANALOG_VIDEO, 486 .tuner_type = TUNER_XC2028, 487 .tuner_addr = 0x61, 488 .tuner_bus = 1, 489 .input = {{ 490 .type = CX23885_VMUX_TELEVISION, 491 .vmux = CX25840_VIN2_CH1 | 492 CX25840_VIN5_CH2 | 493 CX25840_NONE0_CH3, 494 }, { 495 .type = CX23885_VMUX_COMPOSITE1, 496 .vmux = CX25840_COMPOSITE1, 497 }, { 498 .type = CX23885_VMUX_SVIDEO, 499 .vmux = CX25840_SVIDEO_LUMA3 | 500 CX25840_SVIDEO_CHROMA4, 501 }, { 502 .type = CX23885_VMUX_COMPONENT, 503 .vmux = CX25840_VIN7_CH1 | 504 CX25840_VIN6_CH2 | 505 CX25840_VIN8_CH3 | 506 CX25840_COMPONENT_ON, 507 } }, 508 }, 509 [CX23885_BOARD_GOTVIEW_X5_3D_HYBRID] = { 510 .name = "GoTView X5 3D Hybrid", 511 .tuner_type = TUNER_XC5000, 512 .tuner_addr = 0x64, 513 .tuner_bus = 1, 514 .porta = CX23885_ANALOG_VIDEO, 515 .portb = CX23885_MPEG_DVB, 516 .input = {{ 517 .type = CX23885_VMUX_TELEVISION, 518 .vmux = CX25840_VIN2_CH1 | 519 CX25840_VIN5_CH2, 520 .gpio0 = 0x02, 521 }, { 522 .type = CX23885_VMUX_COMPOSITE1, 523 .vmux = CX23885_VMUX_COMPOSITE1, 524 }, { 525 .type = CX23885_VMUX_SVIDEO, 526 .vmux = CX25840_SVIDEO_LUMA3 | 527 CX25840_SVIDEO_CHROMA4, 528 } }, 529 }, 530 [CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF] = { 531 .ci_type = 2, 532 .name = "NetUP Dual DVB-T/C-CI RF", 533 .porta = CX23885_ANALOG_VIDEO, 534 .portb = CX23885_MPEG_DVB, 535 .portc = CX23885_MPEG_DVB, 536 .num_fds_portb = 2, 537 .num_fds_portc = 2, 538 .tuner_type = TUNER_XC5000, 539 .tuner_addr = 0x64, 540 .input = { { 541 .type = CX23885_VMUX_TELEVISION, 542 .vmux = CX25840_COMPOSITE1, 543 } }, 544 }, 545 [CX23885_BOARD_MPX885] = { 546 .name = "MPX-885", 547 .porta = CX23885_ANALOG_VIDEO, 548 .input = {{ 549 .type = CX23885_VMUX_COMPOSITE1, 550 .vmux = CX25840_COMPOSITE1, 551 .amux = CX25840_AUDIO6, 552 .gpio0 = 0, 553 }, { 554 .type = CX23885_VMUX_COMPOSITE2, 555 .vmux = CX25840_COMPOSITE2, 556 .amux = CX25840_AUDIO6, 557 .gpio0 = 0, 558 }, { 559 .type = CX23885_VMUX_COMPOSITE3, 560 .vmux = CX25840_COMPOSITE3, 561 .amux = CX25840_AUDIO7, 562 .gpio0 = 0, 563 }, { 564 .type = CX23885_VMUX_COMPOSITE4, 565 .vmux = CX25840_COMPOSITE4, 566 .amux = CX25840_AUDIO7, 567 .gpio0 = 0, 568 } }, 569 }, 570 [CX23885_BOARD_MYGICA_X8507] = { 571 .name = "Mygica X8502/X8507 ISDB-T", 572 .tuner_type = TUNER_XC5000, 573 .tuner_addr = 0x61, 574 .tuner_bus = 1, 575 .porta = CX23885_ANALOG_VIDEO, 576 .portb = CX23885_MPEG_DVB, 577 .input = { 578 { 579 .type = CX23885_VMUX_TELEVISION, 580 .vmux = CX25840_COMPOSITE2, 581 .amux = CX25840_AUDIO8, 582 }, 583 { 584 .type = CX23885_VMUX_COMPOSITE1, 585 .vmux = CX25840_COMPOSITE8, 586 .amux = CX25840_AUDIO7, 587 }, 588 { 589 .type = CX23885_VMUX_SVIDEO, 590 .vmux = CX25840_SVIDEO_LUMA3 | 591 CX25840_SVIDEO_CHROMA4, 592 .amux = CX25840_AUDIO7, 593 }, 594 { 595 .type = CX23885_VMUX_COMPONENT, 596 .vmux = CX25840_COMPONENT_ON | 597 CX25840_VIN1_CH1 | 598 CX25840_VIN6_CH2 | 599 CX25840_VIN7_CH3, 600 .amux = CX25840_AUDIO7, 601 }, 602 }, 603 }, 604 [CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL] = { 605 .name = "TerraTec Cinergy T PCIe Dual", 606 .portb = CX23885_MPEG_DVB, 607 .portc = CX23885_MPEG_DVB, 608 }, 609 [CX23885_BOARD_TEVII_S471] = { 610 .name = "TeVii S471", 611 .portb = CX23885_MPEG_DVB, 612 }, 613 [CX23885_BOARD_PROF_8000] = { 614 .name = "Prof Revolution DVB-S2 8000", 615 .portb = CX23885_MPEG_DVB, 616 }, 617 [CX23885_BOARD_HAUPPAUGE_HVR4400] = { 618 .name = "Hauppauge WinTV-HVR4400/HVR5500", 619 .porta = CX23885_ANALOG_VIDEO, 620 .portb = CX23885_MPEG_DVB, 621 .portc = CX23885_MPEG_DVB, 622 .tuner_type = TUNER_NXP_TDA18271, 623 .tuner_addr = 0x60, /* 0xc0 >> 1 */ 624 .tuner_bus = 1, 625 }, 626 [CX23885_BOARD_HAUPPAUGE_STARBURST] = { 627 .name = "Hauppauge WinTV Starburst", 628 .portb = CX23885_MPEG_DVB, 629 }, 630 [CX23885_BOARD_AVERMEDIA_HC81R] = { 631 .name = "AVerTV Hybrid Express Slim HC81R", 632 .tuner_type = TUNER_XC2028, 633 .tuner_addr = 0x61, /* 0xc2 >> 1 */ 634 .tuner_bus = 1, 635 .porta = CX23885_ANALOG_VIDEO, 636 .input = {{ 637 .type = CX23885_VMUX_TELEVISION, 638 .vmux = CX25840_VIN2_CH1 | 639 CX25840_VIN5_CH2 | 640 CX25840_NONE0_CH3 | 641 CX25840_NONE1_CH3, 642 .amux = CX25840_AUDIO8, 643 }, { 644 .type = CX23885_VMUX_SVIDEO, 645 .vmux = CX25840_VIN8_CH1 | 646 CX25840_NONE_CH2 | 647 CX25840_VIN7_CH3 | 648 CX25840_SVIDEO_ON, 649 .amux = CX25840_AUDIO6, 650 }, { 651 .type = CX23885_VMUX_COMPONENT, 652 .vmux = CX25840_VIN1_CH1 | 653 CX25840_NONE_CH2 | 654 CX25840_NONE0_CH3 | 655 CX25840_NONE1_CH3, 656 .amux = CX25840_AUDIO6, 657 } }, 658 }, 659 [CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2] = { 660 .name = "DViCO FusionHDTV DVB-T Dual Express2", 661 .portb = CX23885_MPEG_DVB, 662 .portc = CX23885_MPEG_DVB, 663 }, 664 [CX23885_BOARD_HAUPPAUGE_IMPACTVCBE] = { 665 .name = "Hauppauge ImpactVCB-e", 666 .tuner_type = TUNER_ABSENT, 667 .porta = CX23885_ANALOG_VIDEO, 668 .input = {{ 669 .type = CX23885_VMUX_COMPOSITE1, 670 .vmux = CX25840_VIN7_CH3 | 671 CX25840_VIN4_CH2 | 672 CX25840_VIN6_CH1, 673 .amux = CX25840_AUDIO7, 674 }, { 675 .type = CX23885_VMUX_SVIDEO, 676 .vmux = CX25840_VIN7_CH3 | 677 CX25840_VIN4_CH2 | 678 CX25840_VIN8_CH1 | 679 CX25840_SVIDEO_ON, 680 .amux = CX25840_AUDIO7, 681 } }, 682 }, 683 [CX23885_BOARD_DVBSKY_T9580] = { 684 .name = "DVBSky T9580", 685 .portb = CX23885_MPEG_DVB, 686 .portc = CX23885_MPEG_DVB, 687 }, 688 [CX23885_BOARD_DVBSKY_T980C] = { 689 .name = "DVBSky T980C", 690 .portb = CX23885_MPEG_DVB, 691 }, 692 [CX23885_BOARD_DVBSKY_S950C] = { 693 .name = "DVBSky S950C", 694 .portb = CX23885_MPEG_DVB, 695 }, 696 [CX23885_BOARD_TT_CT2_4500_CI] = { 697 .name = "Technotrend TT-budget CT2-4500 CI", 698 .portb = CX23885_MPEG_DVB, 699 }, 700 [CX23885_BOARD_DVBSKY_S950] = { 701 .name = "DVBSky S950", 702 .portb = CX23885_MPEG_DVB, 703 }, 704 [CX23885_BOARD_DVBSKY_S952] = { 705 .name = "DVBSky S952", 706 .portb = CX23885_MPEG_DVB, 707 .portc = CX23885_MPEG_DVB, 708 }, 709 [CX23885_BOARD_DVBSKY_T982] = { 710 .name = "DVBSky T982", 711 .portb = CX23885_MPEG_DVB, 712 .portc = CX23885_MPEG_DVB, 713 }, 714 [CX23885_BOARD_HAUPPAUGE_HVR5525] = { 715 .name = "Hauppauge WinTV-HVR5525", 716 .portb = CX23885_MPEG_DVB, 717 .portc = CX23885_MPEG_DVB, 718 }, 719 [CX23885_BOARD_VIEWCAST_260E] = { 720 .name = "ViewCast 260e", 721 .porta = CX23885_ANALOG_VIDEO, 722 .force_bff = 1, 723 .input = {{ 724 .type = CX23885_VMUX_COMPOSITE1, 725 .vmux = CX25840_VIN6_CH1, 726 .amux = CX25840_AUDIO7, 727 }, { 728 .type = CX23885_VMUX_SVIDEO, 729 .vmux = CX25840_VIN7_CH3 | 730 CX25840_VIN5_CH1 | 731 CX25840_SVIDEO_ON, 732 .amux = CX25840_AUDIO7, 733 }, { 734 .type = CX23885_VMUX_COMPONENT, 735 .vmux = CX25840_VIN7_CH3 | 736 CX25840_VIN6_CH2 | 737 CX25840_VIN5_CH1 | 738 CX25840_COMPONENT_ON, 739 .amux = CX25840_AUDIO7, 740 } }, 741 }, 742 [CX23885_BOARD_VIEWCAST_460E] = { 743 .name = "ViewCast 460e", 744 .porta = CX23885_ANALOG_VIDEO, 745 .force_bff = 1, 746 .input = {{ 747 .type = CX23885_VMUX_COMPOSITE1, 748 .vmux = CX25840_VIN4_CH1, 749 .amux = CX25840_AUDIO7, 750 }, { 751 .type = CX23885_VMUX_SVIDEO, 752 .vmux = CX25840_VIN7_CH3 | 753 CX25840_VIN6_CH1 | 754 CX25840_SVIDEO_ON, 755 .amux = CX25840_AUDIO7, 756 }, { 757 .type = CX23885_VMUX_COMPONENT, 758 .vmux = CX25840_VIN7_CH3 | 759 CX25840_VIN6_CH1 | 760 CX25840_VIN5_CH2 | 761 CX25840_COMPONENT_ON, 762 .amux = CX25840_AUDIO7, 763 }, { 764 .type = CX23885_VMUX_COMPOSITE2, 765 .vmux = CX25840_VIN6_CH1, 766 .amux = CX25840_AUDIO7, 767 } }, 768 }, 769 [CX23885_BOARD_HAUPPAUGE_QUADHD_DVB] = { 770 .name = "Hauppauge WinTV-QuadHD-DVB", 771 .portb = CX23885_MPEG_DVB, 772 .portc = CX23885_MPEG_DVB, 773 }, 774 [CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC] = { 775 .name = "Hauppauge WinTV-QuadHD-ATSC", 776 .portb = CX23885_MPEG_DVB, 777 .portc = CX23885_MPEG_DVB, 778 }, 779 }; 780 const unsigned int cx23885_bcount = ARRAY_SIZE(cx23885_boards); 781 782 /* ------------------------------------------------------------------ */ 783 /* PCI subsystem IDs */ 784 785 struct cx23885_subid cx23885_subids[] = { 786 { 787 .subvendor = 0x0070, 788 .subdevice = 0x3400, 789 .card = CX23885_BOARD_UNKNOWN, 790 }, { 791 .subvendor = 0x0070, 792 .subdevice = 0x7600, 793 .card = CX23885_BOARD_HAUPPAUGE_HVR1800lp, 794 }, { 795 .subvendor = 0x0070, 796 .subdevice = 0x7800, 797 .card = CX23885_BOARD_HAUPPAUGE_HVR1800, 798 }, { 799 .subvendor = 0x0070, 800 .subdevice = 0x7801, 801 .card = CX23885_BOARD_HAUPPAUGE_HVR1800, 802 }, { 803 .subvendor = 0x0070, 804 .subdevice = 0x7809, 805 .card = CX23885_BOARD_HAUPPAUGE_HVR1800, 806 }, { 807 .subvendor = 0x0070, 808 .subdevice = 0x7911, 809 .card = CX23885_BOARD_HAUPPAUGE_HVR1250, 810 }, { 811 .subvendor = 0x18ac, 812 .subdevice = 0xd500, 813 .card = CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP, 814 }, { 815 .subvendor = 0x0070, 816 .subdevice = 0x7790, 817 .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q, 818 }, { 819 .subvendor = 0x0070, 820 .subdevice = 0x7797, 821 .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q, 822 }, { 823 .subvendor = 0x0070, 824 .subdevice = 0x7710, 825 .card = CX23885_BOARD_HAUPPAUGE_HVR1500, 826 }, { 827 .subvendor = 0x0070, 828 .subdevice = 0x7717, 829 .card = CX23885_BOARD_HAUPPAUGE_HVR1500, 830 }, { 831 .subvendor = 0x0070, 832 .subdevice = 0x71d1, 833 .card = CX23885_BOARD_HAUPPAUGE_HVR1200, 834 }, { 835 .subvendor = 0x0070, 836 .subdevice = 0x71d3, 837 .card = CX23885_BOARD_HAUPPAUGE_HVR1200, 838 }, { 839 .subvendor = 0x0070, 840 .subdevice = 0x8101, 841 .card = CX23885_BOARD_HAUPPAUGE_HVR1700, 842 }, { 843 .subvendor = 0x0070, 844 .subdevice = 0x8010, 845 .card = CX23885_BOARD_HAUPPAUGE_HVR1400, 846 }, { 847 .subvendor = 0x18ac, 848 .subdevice = 0xd618, 849 .card = CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP, 850 }, { 851 .subvendor = 0x18ac, 852 .subdevice = 0xdb78, 853 .card = CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP, 854 }, { 855 .subvendor = 0x107d, 856 .subdevice = 0x6681, 857 .card = CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H, 858 }, { 859 .subvendor = 0x107d, 860 .subdevice = 0x6f21, 861 .card = CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200, 862 }, { 863 .subvendor = 0x107d, 864 .subdevice = 0x6f39, 865 .card = CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000, 866 }, { 867 .subvendor = 0x185b, 868 .subdevice = 0xe800, 869 .card = CX23885_BOARD_COMPRO_VIDEOMATE_E650F, 870 }, { 871 .subvendor = 0x6920, 872 .subdevice = 0x8888, 873 .card = CX23885_BOARD_TBS_6920, 874 }, { 875 .subvendor = 0x6980, 876 .subdevice = 0x8888, 877 .card = CX23885_BOARD_TBS_6980, 878 }, { 879 .subvendor = 0x6981, 880 .subdevice = 0x8888, 881 .card = CX23885_BOARD_TBS_6981, 882 }, { 883 .subvendor = 0xd470, 884 .subdevice = 0x9022, 885 .card = CX23885_BOARD_TEVII_S470, 886 }, { 887 .subvendor = 0x0001, 888 .subdevice = 0x2005, 889 .card = CX23885_BOARD_DVBWORLD_2005, 890 }, { 891 .subvendor = 0x1b55, 892 .subdevice = 0x2a2c, 893 .card = CX23885_BOARD_NETUP_DUAL_DVBS2_CI, 894 }, { 895 .subvendor = 0x0070, 896 .subdevice = 0x2211, 897 .card = CX23885_BOARD_HAUPPAUGE_HVR1270, 898 }, { 899 .subvendor = 0x0070, 900 .subdevice = 0x2215, 901 .card = CX23885_BOARD_HAUPPAUGE_HVR1275, 902 }, { 903 .subvendor = 0x0070, 904 .subdevice = 0x221d, 905 .card = CX23885_BOARD_HAUPPAUGE_HVR1275, 906 }, { 907 .subvendor = 0x0070, 908 .subdevice = 0x2251, 909 .card = CX23885_BOARD_HAUPPAUGE_HVR1255, 910 }, { 911 .subvendor = 0x0070, 912 .subdevice = 0x2259, 913 .card = CX23885_BOARD_HAUPPAUGE_HVR1255_22111, 914 }, { 915 .subvendor = 0x0070, 916 .subdevice = 0x2291, 917 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, 918 }, { 919 .subvendor = 0x0070, 920 .subdevice = 0x2295, 921 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, 922 }, { 923 .subvendor = 0x0070, 924 .subdevice = 0x2299, 925 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, 926 }, { 927 .subvendor = 0x0070, 928 .subdevice = 0x229d, 929 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */ 930 }, { 931 .subvendor = 0x0070, 932 .subdevice = 0x22f0, 933 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, 934 }, { 935 .subvendor = 0x0070, 936 .subdevice = 0x22f1, 937 .card = CX23885_BOARD_HAUPPAUGE_HVR1255, 938 }, { 939 .subvendor = 0x0070, 940 .subdevice = 0x22f2, 941 .card = CX23885_BOARD_HAUPPAUGE_HVR1275, 942 }, { 943 .subvendor = 0x0070, 944 .subdevice = 0x22f3, 945 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */ 946 }, { 947 .subvendor = 0x0070, 948 .subdevice = 0x22f4, 949 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, 950 }, { 951 .subvendor = 0x0070, 952 .subdevice = 0x22f5, 953 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */ 954 }, { 955 .subvendor = 0x14f1, 956 .subdevice = 0x8651, 957 .card = CX23885_BOARD_MYGICA_X8506, 958 }, { 959 .subvendor = 0x14f1, 960 .subdevice = 0x8657, 961 .card = CX23885_BOARD_MAGICPRO_PROHDTVE2, 962 }, { 963 .subvendor = 0x0070, 964 .subdevice = 0x8541, 965 .card = CX23885_BOARD_HAUPPAUGE_HVR1850, 966 }, { 967 .subvendor = 0x1858, 968 .subdevice = 0xe800, 969 .card = CX23885_BOARD_COMPRO_VIDEOMATE_E800, 970 }, { 971 .subvendor = 0x0070, 972 .subdevice = 0x8551, 973 .card = CX23885_BOARD_HAUPPAUGE_HVR1290, 974 }, { 975 .subvendor = 0x14f1, 976 .subdevice = 0x8578, 977 .card = CX23885_BOARD_MYGICA_X8558PRO, 978 }, { 979 .subvendor = 0x107d, 980 .subdevice = 0x6f22, 981 .card = CX23885_BOARD_LEADTEK_WINFAST_PXTV1200, 982 }, { 983 .subvendor = 0x5654, 984 .subdevice = 0x2390, 985 .card = CX23885_BOARD_GOTVIEW_X5_3D_HYBRID, 986 }, { 987 .subvendor = 0x1b55, 988 .subdevice = 0xe2e4, 989 .card = CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF, 990 }, { 991 .subvendor = 0x14f1, 992 .subdevice = 0x8502, 993 .card = CX23885_BOARD_MYGICA_X8507, 994 }, { 995 .subvendor = 0x153b, 996 .subdevice = 0x117e, 997 .card = CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL, 998 }, { 999 .subvendor = 0xd471, 1000 .subdevice = 0x9022, 1001 .card = CX23885_BOARD_TEVII_S471, 1002 }, { 1003 .subvendor = 0x8000, 1004 .subdevice = 0x3034, 1005 .card = CX23885_BOARD_PROF_8000, 1006 }, { 1007 .subvendor = 0x0070, 1008 .subdevice = 0xc108, 1009 .card = CX23885_BOARD_HAUPPAUGE_HVR4400, /* Hauppauge WinTV HVR-4400 (Model 121xxx, Hybrid DVB-T/S2, IR) */ 1010 }, { 1011 .subvendor = 0x0070, 1012 .subdevice = 0xc138, 1013 .card = CX23885_BOARD_HAUPPAUGE_HVR4400, /* Hauppauge WinTV HVR-5500 (Model 121xxx, Hybrid DVB-T/C/S2, IR) */ 1014 }, { 1015 .subvendor = 0x0070, 1016 .subdevice = 0xc12a, 1017 .card = CX23885_BOARD_HAUPPAUGE_STARBURST, /* Hauppauge WinTV Starburst (Model 121x00, DVB-S2, IR) */ 1018 }, { 1019 .subvendor = 0x0070, 1020 .subdevice = 0xc1f8, 1021 .card = CX23885_BOARD_HAUPPAUGE_HVR4400, /* Hauppauge WinTV HVR-5500 (Model 121xxx, Hybrid DVB-T/C/S2, IR) */ 1022 }, { 1023 .subvendor = 0x1461, 1024 .subdevice = 0xd939, 1025 .card = CX23885_BOARD_AVERMEDIA_HC81R, 1026 }, { 1027 .subvendor = 0x0070, 1028 .subdevice = 0x7133, 1029 .card = CX23885_BOARD_HAUPPAUGE_IMPACTVCBE, 1030 }, { 1031 .subvendor = 0x18ac, 1032 .subdevice = 0xdb98, 1033 .card = CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2, 1034 }, { 1035 .subvendor = 0x4254, 1036 .subdevice = 0x9580, 1037 .card = CX23885_BOARD_DVBSKY_T9580, 1038 }, { 1039 .subvendor = 0x4254, 1040 .subdevice = 0x980c, 1041 .card = CX23885_BOARD_DVBSKY_T980C, 1042 }, { 1043 .subvendor = 0x4254, 1044 .subdevice = 0x950c, 1045 .card = CX23885_BOARD_DVBSKY_S950C, 1046 }, { 1047 .subvendor = 0x13c2, 1048 .subdevice = 0x3013, 1049 .card = CX23885_BOARD_TT_CT2_4500_CI, 1050 }, { 1051 .subvendor = 0x4254, 1052 .subdevice = 0x0950, 1053 .card = CX23885_BOARD_DVBSKY_S950, 1054 }, { 1055 .subvendor = 0x4254, 1056 .subdevice = 0x0952, 1057 .card = CX23885_BOARD_DVBSKY_S952, 1058 }, { 1059 .subvendor = 0x4254, 1060 .subdevice = 0x0982, 1061 .card = CX23885_BOARD_DVBSKY_T982, 1062 }, { 1063 .subvendor = 0x0070, 1064 .subdevice = 0xf038, 1065 .card = CX23885_BOARD_HAUPPAUGE_HVR5525, 1066 }, { 1067 .subvendor = 0x1576, 1068 .subdevice = 0x0260, 1069 .card = CX23885_BOARD_VIEWCAST_260E, 1070 }, { 1071 .subvendor = 0x1576, 1072 .subdevice = 0x0460, 1073 .card = CX23885_BOARD_VIEWCAST_460E, 1074 }, { 1075 .subvendor = 0x0070, 1076 .subdevice = 0x6a28, 1077 .card = CX23885_BOARD_HAUPPAUGE_QUADHD_DVB, /* Tuner Pair 1 */ 1078 }, { 1079 .subvendor = 0x0070, 1080 .subdevice = 0x6b28, 1081 .card = CX23885_BOARD_HAUPPAUGE_QUADHD_DVB, /* Tuner Pair 2 */ 1082 }, { 1083 .subvendor = 0x0070, 1084 .subdevice = 0x6a18, 1085 .card = CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC, /* Tuner Pair 1 */ 1086 }, { 1087 .subvendor = 0x0070, 1088 .subdevice = 0x6b18, 1089 .card = CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC, /* Tuner Pair 2 */ 1090 }, 1091 }; 1092 const unsigned int cx23885_idcount = ARRAY_SIZE(cx23885_subids); 1093 1094 void cx23885_card_list(struct cx23885_dev *dev) 1095 { 1096 int i; 1097 1098 if (0 == dev->pci->subsystem_vendor && 1099 0 == dev->pci->subsystem_device) { 1100 pr_info("%s: Board has no valid PCIe Subsystem ID and can't\n" 1101 "%s: be autodetected. Pass card=<n> insmod option\n" 1102 "%s: to workaround that. Redirect complaints to the\n" 1103 "%s: vendor of the TV card. Best regards,\n" 1104 "%s: -- tux\n", 1105 dev->name, dev->name, dev->name, dev->name, dev->name); 1106 } else { 1107 pr_info("%s: Your board isn't known (yet) to the driver.\n" 1108 "%s: Try to pick one of the existing card configs via\n" 1109 "%s: card=<n> insmod option. Updating to the latest\n" 1110 "%s: version might help as well.\n", 1111 dev->name, dev->name, dev->name, dev->name); 1112 } 1113 pr_info("%s: Here is a list of valid choices for the card=<n> insmod option:\n", 1114 dev->name); 1115 for (i = 0; i < cx23885_bcount; i++) 1116 pr_info("%s: card=%d -> %s\n", 1117 dev->name, i, cx23885_boards[i].name); 1118 } 1119 1120 static void viewcast_eeprom(struct cx23885_dev *dev, u8 *eeprom_data) 1121 { 1122 u32 sn; 1123 1124 /* The serial number record begins with tag 0x59 */ 1125 if (*(eeprom_data + 0x00) != 0x59) { 1126 pr_info("%s() eeprom records are undefined, no serial number\n", 1127 __func__); 1128 return; 1129 } 1130 1131 sn = (*(eeprom_data + 0x06) << 24) | 1132 (*(eeprom_data + 0x05) << 16) | 1133 (*(eeprom_data + 0x04) << 8) | 1134 (*(eeprom_data + 0x03)); 1135 1136 pr_info("%s: card '%s' sn# MM%d\n", 1137 dev->name, 1138 cx23885_boards[dev->board].name, 1139 sn); 1140 } 1141 1142 static void hauppauge_eeprom(struct cx23885_dev *dev, u8 *eeprom_data) 1143 { 1144 struct tveeprom tv; 1145 1146 tveeprom_hauppauge_analog(&tv, eeprom_data); 1147 1148 /* Make sure we support the board model */ 1149 switch (tv.model) { 1150 case 22001: 1151 /* WinTV-HVR1270 (PCIe, Retail, half height) 1152 * ATSC/QAM and basic analog, IR Blast */ 1153 case 22009: 1154 /* WinTV-HVR1210 (PCIe, Retail, half height) 1155 * DVB-T and basic analog, IR Blast */ 1156 case 22011: 1157 /* WinTV-HVR1270 (PCIe, Retail, half height) 1158 * ATSC/QAM and basic analog, IR Recv */ 1159 case 22019: 1160 /* WinTV-HVR1210 (PCIe, Retail, half height) 1161 * DVB-T and basic analog, IR Recv */ 1162 case 22021: 1163 /* WinTV-HVR1275 (PCIe, Retail, half height) 1164 * ATSC/QAM and basic analog, IR Recv */ 1165 case 22029: 1166 /* WinTV-HVR1210 (PCIe, Retail, half height) 1167 * DVB-T and basic analog, IR Recv */ 1168 case 22101: 1169 /* WinTV-HVR1270 (PCIe, Retail, full height) 1170 * ATSC/QAM and basic analog, IR Blast */ 1171 case 22109: 1172 /* WinTV-HVR1210 (PCIe, Retail, full height) 1173 * DVB-T and basic analog, IR Blast */ 1174 case 22111: 1175 /* WinTV-HVR1270 (PCIe, Retail, full height) 1176 * ATSC/QAM and basic analog, IR Recv */ 1177 case 22119: 1178 /* WinTV-HVR1210 (PCIe, Retail, full height) 1179 * DVB-T and basic analog, IR Recv */ 1180 case 22121: 1181 /* WinTV-HVR1275 (PCIe, Retail, full height) 1182 * ATSC/QAM and basic analog, IR Recv */ 1183 case 22129: 1184 /* WinTV-HVR1210 (PCIe, Retail, full height) 1185 * DVB-T and basic analog, IR Recv */ 1186 case 71009: 1187 /* WinTV-HVR1200 (PCIe, Retail, full height) 1188 * DVB-T and basic analog */ 1189 case 71100: 1190 /* WinTV-ImpactVCB-e (PCIe, Retail, half height) 1191 * Basic analog */ 1192 case 71359: 1193 /* WinTV-HVR1200 (PCIe, OEM, half height) 1194 * DVB-T and basic analog */ 1195 case 71439: 1196 /* WinTV-HVR1200 (PCIe, OEM, half height) 1197 * DVB-T and basic analog */ 1198 case 71449: 1199 /* WinTV-HVR1200 (PCIe, OEM, full height) 1200 * DVB-T and basic analog */ 1201 case 71939: 1202 /* WinTV-HVR1200 (PCIe, OEM, half height) 1203 * DVB-T and basic analog */ 1204 case 71949: 1205 /* WinTV-HVR1200 (PCIe, OEM, full height) 1206 * DVB-T and basic analog */ 1207 case 71959: 1208 /* WinTV-HVR1200 (PCIe, OEM, full height) 1209 * DVB-T and basic analog */ 1210 case 71979: 1211 /* WinTV-HVR1200 (PCIe, OEM, half height) 1212 * DVB-T and basic analog */ 1213 case 71999: 1214 /* WinTV-HVR1200 (PCIe, OEM, full height) 1215 * DVB-T and basic analog */ 1216 case 76601: 1217 /* WinTV-HVR1800lp (PCIe, Retail, No IR, Dual 1218 channel ATSC and MPEG2 HW Encoder */ 1219 case 77001: 1220 /* WinTV-HVR1500 (Express Card, OEM, No IR, ATSC 1221 and Basic analog */ 1222 case 77011: 1223 /* WinTV-HVR1500 (Express Card, Retail, No IR, ATSC 1224 and Basic analog */ 1225 case 77041: 1226 /* WinTV-HVR1500Q (Express Card, OEM, No IR, ATSC/QAM 1227 and Basic analog */ 1228 case 77051: 1229 /* WinTV-HVR1500Q (Express Card, Retail, No IR, ATSC/QAM 1230 and Basic analog */ 1231 case 78011: 1232 /* WinTV-HVR1800 (PCIe, Retail, 3.5mm in, IR, No FM, 1233 Dual channel ATSC and MPEG2 HW Encoder */ 1234 case 78501: 1235 /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM, 1236 Dual channel ATSC and MPEG2 HW Encoder */ 1237 case 78521: 1238 /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM, 1239 Dual channel ATSC and MPEG2 HW Encoder */ 1240 case 78531: 1241 /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, No FM, 1242 Dual channel ATSC and MPEG2 HW Encoder */ 1243 case 78631: 1244 /* WinTV-HVR1800 (PCIe, OEM, No IR, No FM, 1245 Dual channel ATSC and MPEG2 HW Encoder */ 1246 case 79001: 1247 /* WinTV-HVR1250 (PCIe, Retail, IR, full height, 1248 ATSC and Basic analog */ 1249 case 79101: 1250 /* WinTV-HVR1250 (PCIe, Retail, IR, half height, 1251 ATSC and Basic analog */ 1252 case 79501: 1253 /* WinTV-HVR1250 (PCIe, No IR, half height, 1254 ATSC [at least] and Basic analog) */ 1255 case 79561: 1256 /* WinTV-HVR1250 (PCIe, OEM, No IR, half height, 1257 ATSC and Basic analog */ 1258 case 79571: 1259 /* WinTV-HVR1250 (PCIe, OEM, No IR, full height, 1260 ATSC and Basic analog */ 1261 case 79671: 1262 /* WinTV-HVR1250 (PCIe, OEM, No IR, half height, 1263 ATSC and Basic analog */ 1264 case 80019: 1265 /* WinTV-HVR1400 (Express Card, Retail, IR, 1266 * DVB-T and Basic analog */ 1267 case 81509: 1268 /* WinTV-HVR1700 (PCIe, OEM, No IR, half height) 1269 * DVB-T and MPEG2 HW Encoder */ 1270 case 81519: 1271 /* WinTV-HVR1700 (PCIe, OEM, No IR, full height) 1272 * DVB-T and MPEG2 HW Encoder */ 1273 break; 1274 case 85021: 1275 /* WinTV-HVR1850 (PCIe, Retail, 3.5mm in, IR, FM, 1276 Dual channel ATSC and MPEG2 HW Encoder */ 1277 break; 1278 case 85721: 1279 /* WinTV-HVR1290 (PCIe, OEM, RCA in, IR, 1280 Dual channel ATSC and Basic analog */ 1281 case 121019: 1282 /* WinTV-HVR4400 (PCIe, DVB-S2, DVB-C/T) */ 1283 break; 1284 case 121029: 1285 /* WinTV-HVR5500 (PCIe, DVB-S2, DVB-C/T) */ 1286 break; 1287 case 150329: 1288 /* WinTV-HVR5525 (PCIe, DVB-S/S2, DVB-T/T2/C) */ 1289 break; 1290 case 166100: 1291 /* WinTV-QuadHD (DVB) Tuner Pair 1 (PCIe, IR, half height, 1292 DVB-T/T2/C, DVB-T/T2/C */ 1293 break; 1294 case 166101: 1295 /* WinTV-QuadHD (DVB) Tuner Pair 2 (PCIe, IR, half height, 1296 DVB-T/T2/C, DVB-T/T2/C */ 1297 break; 1298 case 165100: 1299 /* 1300 * WinTV-QuadHD (ATSC) Tuner Pair 1 (PCIe, IR, half height, 1301 * ATSC, ATSC 1302 */ 1303 break; 1304 case 165101: 1305 /* 1306 * WinTV-QuadHD (DVB) Tuner Pair 2 (PCIe, IR, half height, 1307 * ATSC, ATSC 1308 */ 1309 break; 1310 default: 1311 pr_warn("%s: warning: unknown hauppauge model #%d\n", 1312 dev->name, tv.model); 1313 break; 1314 } 1315 1316 pr_info("%s: hauppauge eeprom: model=%d\n", 1317 dev->name, tv.model); 1318 } 1319 1320 /* Some TBS cards require initing a chip using a bitbanged SPI attached 1321 to the cx23885 gpio's. If this chip doesn't get init'ed the demod 1322 doesn't respond to any command. */ 1323 static void tbs_card_init(struct cx23885_dev *dev) 1324 { 1325 int i; 1326 static const u8 buf[] = { 1327 0xe0, 0x06, 0x66, 0x33, 0x65, 1328 0x01, 0x17, 0x06, 0xde}; 1329 1330 switch (dev->board) { 1331 case CX23885_BOARD_TBS_6980: 1332 case CX23885_BOARD_TBS_6981: 1333 cx_set(GP0_IO, 0x00070007); 1334 usleep_range(1000, 10000); 1335 cx_clear(GP0_IO, 2); 1336 usleep_range(1000, 10000); 1337 for (i = 0; i < 9 * 8; i++) { 1338 cx_clear(GP0_IO, 7); 1339 usleep_range(1000, 10000); 1340 cx_set(GP0_IO, 1341 ((buf[i >> 3] >> (7 - (i & 7))) & 1) | 4); 1342 usleep_range(1000, 10000); 1343 } 1344 cx_set(GP0_IO, 7); 1345 break; 1346 } 1347 } 1348 1349 int cx23885_tuner_callback(void *priv, int component, int command, int arg) 1350 { 1351 struct cx23885_tsport *port = priv; 1352 struct cx23885_dev *dev = port->dev; 1353 u32 bitmask = 0; 1354 1355 if ((command == XC2028_RESET_CLK) || (command == XC2028_I2C_FLUSH)) 1356 return 0; 1357 1358 if (command != 0) { 1359 pr_err("%s(): Unknown command 0x%x.\n", 1360 __func__, command); 1361 return -EINVAL; 1362 } 1363 1364 switch (dev->board) { 1365 case CX23885_BOARD_HAUPPAUGE_HVR1400: 1366 case CX23885_BOARD_HAUPPAUGE_HVR1500: 1367 case CX23885_BOARD_HAUPPAUGE_HVR1500Q: 1368 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H: 1369 case CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200: 1370 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000: 1371 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F: 1372 case CX23885_BOARD_COMPRO_VIDEOMATE_E800: 1373 case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200: 1374 /* Tuner Reset Command */ 1375 bitmask = 0x04; 1376 break; 1377 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP: 1378 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: 1379 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2: 1380 /* Two identical tuners on two different i2c buses, 1381 * we need to reset the correct gpio. */ 1382 if (port->nr == 1) 1383 bitmask = 0x01; 1384 else if (port->nr == 2) 1385 bitmask = 0x04; 1386 break; 1387 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID: 1388 /* Tuner Reset Command */ 1389 bitmask = 0x02; 1390 break; 1391 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: 1392 altera_ci_tuner_reset(dev, port->nr); 1393 break; 1394 case CX23885_BOARD_AVERMEDIA_HC81R: 1395 /* XC3028L Reset Command */ 1396 bitmask = 1 << 2; 1397 break; 1398 } 1399 1400 if (bitmask) { 1401 /* Drive the tuner into reset and back out */ 1402 cx_clear(GP0_IO, bitmask); 1403 mdelay(200); 1404 cx_set(GP0_IO, bitmask); 1405 } 1406 1407 return 0; 1408 } 1409 1410 void cx23885_gpio_setup(struct cx23885_dev *dev) 1411 { 1412 switch (dev->board) { 1413 case CX23885_BOARD_HAUPPAUGE_HVR1250: 1414 /* GPIO-0 cx24227 demodulator reset */ 1415 cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */ 1416 break; 1417 case CX23885_BOARD_HAUPPAUGE_HVR1500: 1418 /* GPIO-0 cx24227 demodulator */ 1419 /* GPIO-2 xc3028 tuner */ 1420 1421 /* Put the parts into reset */ 1422 cx_set(GP0_IO, 0x00050000); 1423 cx_clear(GP0_IO, 0x00000005); 1424 msleep(5); 1425 1426 /* Bring the parts out of reset */ 1427 cx_set(GP0_IO, 0x00050005); 1428 break; 1429 case CX23885_BOARD_HAUPPAUGE_HVR1500Q: 1430 /* GPIO-0 cx24227 demodulator reset */ 1431 /* GPIO-2 xc5000 tuner reset */ 1432 cx_set(GP0_IO, 0x00050005); /* Bring the part out of reset */ 1433 break; 1434 case CX23885_BOARD_HAUPPAUGE_HVR1800: 1435 /* GPIO-0 656_CLK */ 1436 /* GPIO-1 656_D0 */ 1437 /* GPIO-2 8295A Reset */ 1438 /* GPIO-3-10 cx23417 data0-7 */ 1439 /* GPIO-11-14 cx23417 addr0-3 */ 1440 /* GPIO-15-18 cx23417 READY, CS, RD, WR */ 1441 /* GPIO-19 IR_RX */ 1442 1443 /* CX23417 GPIO's */ 1444 /* EIO15 Zilog Reset */ 1445 /* EIO14 S5H1409/CX24227 Reset */ 1446 mc417_gpio_enable(dev, GPIO_15 | GPIO_14, 1); 1447 1448 /* Put the demod into reset and protect the eeprom */ 1449 mc417_gpio_clear(dev, GPIO_15 | GPIO_14); 1450 mdelay(100); 1451 1452 /* Bring the demod and blaster out of reset */ 1453 mc417_gpio_set(dev, GPIO_15 | GPIO_14); 1454 mdelay(100); 1455 1456 /* Force the TDA8295A into reset and back */ 1457 cx23885_gpio_enable(dev, GPIO_2, 1); 1458 cx23885_gpio_set(dev, GPIO_2); 1459 mdelay(20); 1460 cx23885_gpio_clear(dev, GPIO_2); 1461 mdelay(20); 1462 cx23885_gpio_set(dev, GPIO_2); 1463 mdelay(20); 1464 break; 1465 case CX23885_BOARD_HAUPPAUGE_HVR1200: 1466 /* GPIO-0 tda10048 demodulator reset */ 1467 /* GPIO-2 tda18271 tuner reset */ 1468 1469 /* Put the parts into reset and back */ 1470 cx_set(GP0_IO, 0x00050000); 1471 mdelay(20); 1472 cx_clear(GP0_IO, 0x00000005); 1473 mdelay(20); 1474 cx_set(GP0_IO, 0x00050005); 1475 break; 1476 case CX23885_BOARD_HAUPPAUGE_HVR1700: 1477 /* GPIO-0 TDA10048 demodulator reset */ 1478 /* GPIO-2 TDA8295A Reset */ 1479 /* GPIO-3-10 cx23417 data0-7 */ 1480 /* GPIO-11-14 cx23417 addr0-3 */ 1481 /* GPIO-15-18 cx23417 READY, CS, RD, WR */ 1482 1483 /* The following GPIO's are on the interna AVCore (cx25840) */ 1484 /* GPIO-19 IR_RX */ 1485 /* GPIO-20 IR_TX 416/DVBT Select */ 1486 /* GPIO-21 IIS DAT */ 1487 /* GPIO-22 IIS WCLK */ 1488 /* GPIO-23 IIS BCLK */ 1489 1490 /* Put the parts into reset and back */ 1491 cx_set(GP0_IO, 0x00050000); 1492 mdelay(20); 1493 cx_clear(GP0_IO, 0x00000005); 1494 mdelay(20); 1495 cx_set(GP0_IO, 0x00050005); 1496 break; 1497 case CX23885_BOARD_HAUPPAUGE_HVR1400: 1498 /* GPIO-0 Dibcom7000p demodulator reset */ 1499 /* GPIO-2 xc3028L tuner reset */ 1500 /* GPIO-13 LED */ 1501 1502 /* Put the parts into reset and back */ 1503 cx_set(GP0_IO, 0x00050000); 1504 mdelay(20); 1505 cx_clear(GP0_IO, 0x00000005); 1506 mdelay(20); 1507 cx_set(GP0_IO, 0x00050005); 1508 break; 1509 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP: 1510 /* GPIO-0 xc5000 tuner reset i2c bus 0 */ 1511 /* GPIO-1 s5h1409 demod reset i2c bus 0 */ 1512 /* GPIO-2 xc5000 tuner reset i2c bus 1 */ 1513 /* GPIO-3 s5h1409 demod reset i2c bus 0 */ 1514 1515 /* Put the parts into reset and back */ 1516 cx_set(GP0_IO, 0x000f0000); 1517 mdelay(20); 1518 cx_clear(GP0_IO, 0x0000000f); 1519 mdelay(20); 1520 cx_set(GP0_IO, 0x000f000f); 1521 break; 1522 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: 1523 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2: 1524 /* GPIO-0 portb xc3028 reset */ 1525 /* GPIO-1 portb zl10353 reset */ 1526 /* GPIO-2 portc xc3028 reset */ 1527 /* GPIO-3 portc zl10353 reset */ 1528 1529 /* Put the parts into reset and back */ 1530 cx_set(GP0_IO, 0x000f0000); 1531 mdelay(20); 1532 cx_clear(GP0_IO, 0x0000000f); 1533 mdelay(20); 1534 cx_set(GP0_IO, 0x000f000f); 1535 break; 1536 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H: 1537 case CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200: 1538 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000: 1539 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F: 1540 case CX23885_BOARD_COMPRO_VIDEOMATE_E800: 1541 case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200: 1542 /* GPIO-2 xc3028 tuner reset */ 1543 1544 /* The following GPIO's are on the internal AVCore (cx25840) */ 1545 /* GPIO-? zl10353 demod reset */ 1546 1547 /* Put the parts into reset and back */ 1548 cx_set(GP0_IO, 0x00040000); 1549 mdelay(20); 1550 cx_clear(GP0_IO, 0x00000004); 1551 mdelay(20); 1552 cx_set(GP0_IO, 0x00040004); 1553 break; 1554 case CX23885_BOARD_TBS_6920: 1555 case CX23885_BOARD_TBS_6980: 1556 case CX23885_BOARD_TBS_6981: 1557 case CX23885_BOARD_PROF_8000: 1558 cx_write(MC417_CTL, 0x00000036); 1559 cx_write(MC417_OEN, 0x00001000); 1560 cx_set(MC417_RWD, 0x00000002); 1561 mdelay(200); 1562 cx_clear(MC417_RWD, 0x00000800); 1563 mdelay(200); 1564 cx_set(MC417_RWD, 0x00000800); 1565 mdelay(200); 1566 break; 1567 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: 1568 /* GPIO-0 INTA from CiMax1 1569 GPIO-1 INTB from CiMax2 1570 GPIO-2 reset chips 1571 GPIO-3 to GPIO-10 data/addr for CA 1572 GPIO-11 ~CS0 to CiMax1 1573 GPIO-12 ~CS1 to CiMax2 1574 GPIO-13 ADL0 load LSB addr 1575 GPIO-14 ADL1 load MSB addr 1576 GPIO-15 ~RDY from CiMax 1577 GPIO-17 ~RD to CiMax 1578 GPIO-18 ~WR to CiMax 1579 */ 1580 cx_set(GP0_IO, 0x00040000); /* GPIO as out */ 1581 /* GPIO1 and GPIO2 as INTA and INTB from CiMaxes, reset low */ 1582 cx_clear(GP0_IO, 0x00030004); 1583 mdelay(100);/* reset delay */ 1584 cx_set(GP0_IO, 0x00040004); /* GPIO as out, reset high */ 1585 cx_write(MC417_CTL, 0x00000037);/* enable GPIO3-18 pins */ 1586 /* GPIO-15 IN as ~ACK, rest as OUT */ 1587 cx_write(MC417_OEN, 0x00001000); 1588 /* ~RD, ~WR high; ADL0, ADL1 low; ~CS0, ~CS1 high */ 1589 cx_write(MC417_RWD, 0x0000c300); 1590 /* enable irq */ 1591 cx_write(GPIO_ISM, 0x00000000);/* INTERRUPTS active low*/ 1592 break; 1593 case CX23885_BOARD_HAUPPAUGE_HVR1270: 1594 case CX23885_BOARD_HAUPPAUGE_HVR1275: 1595 case CX23885_BOARD_HAUPPAUGE_HVR1255: 1596 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111: 1597 case CX23885_BOARD_HAUPPAUGE_HVR1210: 1598 /* GPIO-5 RF Control: 0 = RF1 Terrestrial, 1 = RF2 Cable */ 1599 /* GPIO-6 I2C Gate which can isolate the demod from the bus */ 1600 /* GPIO-9 Demod reset */ 1601 1602 /* Put the parts into reset and back */ 1603 cx23885_gpio_enable(dev, GPIO_9 | GPIO_6 | GPIO_5, 1); 1604 cx23885_gpio_set(dev, GPIO_9 | GPIO_6 | GPIO_5); 1605 cx23885_gpio_clear(dev, GPIO_9); 1606 mdelay(20); 1607 cx23885_gpio_set(dev, GPIO_9); 1608 break; 1609 case CX23885_BOARD_MYGICA_X8506: 1610 case CX23885_BOARD_MAGICPRO_PROHDTVE2: 1611 case CX23885_BOARD_MYGICA_X8507: 1612 /* GPIO-0 (0)Analog / (1)Digital TV */ 1613 /* GPIO-1 reset XC5000 */ 1614 /* GPIO-2 demod reset */ 1615 cx23885_gpio_enable(dev, GPIO_0 | GPIO_1 | GPIO_2, 1); 1616 cx23885_gpio_clear(dev, GPIO_1 | GPIO_2); 1617 mdelay(100); 1618 cx23885_gpio_set(dev, GPIO_0 | GPIO_1 | GPIO_2); 1619 mdelay(100); 1620 break; 1621 case CX23885_BOARD_MYGICA_X8558PRO: 1622 /* GPIO-0 reset first ATBM8830 */ 1623 /* GPIO-1 reset second ATBM8830 */ 1624 cx23885_gpio_enable(dev, GPIO_0 | GPIO_1, 1); 1625 cx23885_gpio_clear(dev, GPIO_0 | GPIO_1); 1626 mdelay(100); 1627 cx23885_gpio_set(dev, GPIO_0 | GPIO_1); 1628 mdelay(100); 1629 break; 1630 case CX23885_BOARD_HAUPPAUGE_HVR1850: 1631 case CX23885_BOARD_HAUPPAUGE_HVR1290: 1632 /* GPIO-0 656_CLK */ 1633 /* GPIO-1 656_D0 */ 1634 /* GPIO-2 Wake# */ 1635 /* GPIO-3-10 cx23417 data0-7 */ 1636 /* GPIO-11-14 cx23417 addr0-3 */ 1637 /* GPIO-15-18 cx23417 READY, CS, RD, WR */ 1638 /* GPIO-19 IR_RX */ 1639 /* GPIO-20 C_IR_TX */ 1640 /* GPIO-21 I2S DAT */ 1641 /* GPIO-22 I2S WCLK */ 1642 /* GPIO-23 I2S BCLK */ 1643 /* ALT GPIO: EXP GPIO LATCH */ 1644 1645 /* CX23417 GPIO's */ 1646 /* GPIO-14 S5H1411/CX24228 Reset */ 1647 /* GPIO-13 EEPROM write protect */ 1648 mc417_gpio_enable(dev, GPIO_14 | GPIO_13, 1); 1649 1650 /* Put the demod into reset and protect the eeprom */ 1651 mc417_gpio_clear(dev, GPIO_14 | GPIO_13); 1652 mdelay(100); 1653 1654 /* Bring the demod out of reset */ 1655 mc417_gpio_set(dev, GPIO_14); 1656 mdelay(100); 1657 1658 /* CX24228 GPIO */ 1659 /* Connected to IF / Mux */ 1660 break; 1661 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID: 1662 cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */ 1663 break; 1664 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: 1665 /* GPIO-0 ~INT in 1666 GPIO-1 TMS out 1667 GPIO-2 ~reset chips out 1668 GPIO-3 to GPIO-10 data/addr for CA in/out 1669 GPIO-11 ~CS out 1670 GPIO-12 ADDR out 1671 GPIO-13 ~WR out 1672 GPIO-14 ~RD out 1673 GPIO-15 ~RDY in 1674 GPIO-16 TCK out 1675 GPIO-17 TDO in 1676 GPIO-18 TDI out 1677 */ 1678 cx_set(GP0_IO, 0x00060000); /* GPIO-1,2 as out */ 1679 /* GPIO-0 as INT, reset & TMS low */ 1680 cx_clear(GP0_IO, 0x00010006); 1681 mdelay(100);/* reset delay */ 1682 cx_set(GP0_IO, 0x00000004); /* reset high */ 1683 cx_write(MC417_CTL, 0x00000037);/* enable GPIO-3..18 pins */ 1684 /* GPIO-17 is TDO in, GPIO-15 is ~RDY in, rest is out */ 1685 cx_write(MC417_OEN, 0x00005000); 1686 /* ~RD, ~WR high; ADDR low; ~CS high */ 1687 cx_write(MC417_RWD, 0x00000d00); 1688 /* enable irq */ 1689 cx_write(GPIO_ISM, 0x00000000);/* INTERRUPTS active low*/ 1690 break; 1691 case CX23885_BOARD_HAUPPAUGE_HVR4400: 1692 case CX23885_BOARD_HAUPPAUGE_STARBURST: 1693 /* GPIO-8 tda10071 demod reset */ 1694 /* GPIO-9 si2165 demod reset (only HVR4400/HVR5500)*/ 1695 1696 /* Put the parts into reset and back */ 1697 cx23885_gpio_enable(dev, GPIO_8 | GPIO_9, 1); 1698 1699 cx23885_gpio_clear(dev, GPIO_8 | GPIO_9); 1700 mdelay(100); 1701 cx23885_gpio_set(dev, GPIO_8 | GPIO_9); 1702 mdelay(100); 1703 1704 break; 1705 case CX23885_BOARD_AVERMEDIA_HC81R: 1706 cx_clear(MC417_CTL, 1); 1707 /* GPIO-0,1,2 setup direction as output */ 1708 cx_set(GP0_IO, 0x00070000); 1709 mdelay(10); 1710 /* AF9013 demod reset */ 1711 cx_set(GP0_IO, 0x00010001); 1712 mdelay(10); 1713 cx_clear(GP0_IO, 0x00010001); 1714 mdelay(10); 1715 cx_set(GP0_IO, 0x00010001); 1716 mdelay(10); 1717 /* demod tune? */ 1718 cx_clear(GP0_IO, 0x00030003); 1719 mdelay(10); 1720 cx_set(GP0_IO, 0x00020002); 1721 mdelay(10); 1722 cx_set(GP0_IO, 0x00010001); 1723 mdelay(10); 1724 cx_clear(GP0_IO, 0x00020002); 1725 /* XC3028L tuner reset */ 1726 cx_set(GP0_IO, 0x00040004); 1727 cx_clear(GP0_IO, 0x00040004); 1728 cx_set(GP0_IO, 0x00040004); 1729 mdelay(60); 1730 break; 1731 case CX23885_BOARD_DVBSKY_T9580: 1732 case CX23885_BOARD_DVBSKY_S952: 1733 case CX23885_BOARD_DVBSKY_T982: 1734 /* enable GPIO3-18 pins */ 1735 cx_write(MC417_CTL, 0x00000037); 1736 cx23885_gpio_enable(dev, GPIO_2 | GPIO_11, 1); 1737 cx23885_gpio_clear(dev, GPIO_2 | GPIO_11); 1738 mdelay(100); 1739 cx23885_gpio_set(dev, GPIO_2 | GPIO_11); 1740 break; 1741 case CX23885_BOARD_DVBSKY_T980C: 1742 case CX23885_BOARD_DVBSKY_S950C: 1743 case CX23885_BOARD_TT_CT2_4500_CI: 1744 /* 1745 * GPIO-0 INTA from CiMax, input 1746 * GPIO-1 reset CiMax, output, high active 1747 * GPIO-2 reset demod, output, low active 1748 * GPIO-3 to GPIO-10 data/addr for CAM 1749 * GPIO-11 ~CS0 to CiMax1 1750 * GPIO-12 ~CS1 to CiMax2 1751 * GPIO-13 ADL0 load LSB addr 1752 * GPIO-14 ADL1 load MSB addr 1753 * GPIO-15 ~RDY from CiMax 1754 * GPIO-17 ~RD to CiMax 1755 * GPIO-18 ~WR to CiMax 1756 */ 1757 1758 cx_set(GP0_IO, 0x00060002); /* GPIO 1/2 as output */ 1759 cx_clear(GP0_IO, 0x00010004); /* GPIO 0 as input */ 1760 mdelay(100); /* reset delay */ 1761 cx_set(GP0_IO, 0x00060004); /* GPIO as out, reset high */ 1762 cx_clear(GP0_IO, 0x00010002); 1763 cx_write(MC417_CTL, 0x00000037); /* enable GPIO3-18 pins */ 1764 1765 /* GPIO-15 IN as ~ACK, rest as OUT */ 1766 cx_write(MC417_OEN, 0x00001000); 1767 1768 /* ~RD, ~WR high; ADL0, ADL1 low; ~CS0, ~CS1 high */ 1769 cx_write(MC417_RWD, 0x0000c300); 1770 1771 /* enable irq */ 1772 cx_write(GPIO_ISM, 0x00000000); /* INTERRUPTS active low */ 1773 break; 1774 case CX23885_BOARD_DVBSKY_S950: 1775 cx23885_gpio_enable(dev, GPIO_2, 1); 1776 cx23885_gpio_clear(dev, GPIO_2); 1777 msleep(100); 1778 cx23885_gpio_set(dev, GPIO_2); 1779 break; 1780 case CX23885_BOARD_HAUPPAUGE_HVR5525: 1781 case CX23885_BOARD_HAUPPAUGE_QUADHD_DVB: 1782 case CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC: 1783 /* 1784 * HVR5525 GPIO Details: 1785 * GPIO-00 IR_WIDE 1786 * GPIO-02 wake# 1787 * GPIO-03 VAUX Pres. 1788 * GPIO-07 PROG# 1789 * GPIO-08 SAT_RESN 1790 * GPIO-09 TER_RESN 1791 * GPIO-10 B2_SENSE 1792 * GPIO-11 B1_SENSE 1793 * GPIO-15 IR_LED_STATUS 1794 * GPIO-19 IR_NARROW 1795 * GPIO-20 Blauster1 1796 * ALTGPIO VAUX_SWITCH 1797 * AUX_PLL_CLK : Blaster2 1798 */ 1799 /* Put the parts into reset and back */ 1800 cx23885_gpio_enable(dev, GPIO_8 | GPIO_9, 1); 1801 cx23885_gpio_clear(dev, GPIO_8 | GPIO_9); 1802 msleep(100); 1803 cx23885_gpio_set(dev, GPIO_8 | GPIO_9); 1804 msleep(100); 1805 break; 1806 case CX23885_BOARD_VIEWCAST_260E: 1807 case CX23885_BOARD_VIEWCAST_460E: 1808 /* For documentation purposes, it's worth noting that this 1809 * card does not have any GPIO's connected to subcomponents. 1810 */ 1811 break; 1812 } 1813 } 1814 1815 int cx23885_ir_init(struct cx23885_dev *dev) 1816 { 1817 static struct v4l2_subdev_io_pin_config ir_rxtx_pin_cfg[] = { 1818 { 1819 .flags = BIT(V4L2_SUBDEV_IO_PIN_INPUT), 1820 .pin = CX23885_PIN_IR_RX_GPIO19, 1821 .function = CX23885_PAD_IR_RX, 1822 .value = 0, 1823 .strength = CX25840_PIN_DRIVE_MEDIUM, 1824 }, { 1825 .flags = BIT(V4L2_SUBDEV_IO_PIN_OUTPUT), 1826 .pin = CX23885_PIN_IR_TX_GPIO20, 1827 .function = CX23885_PAD_IR_TX, 1828 .value = 0, 1829 .strength = CX25840_PIN_DRIVE_MEDIUM, 1830 } 1831 }; 1832 const size_t ir_rxtx_pin_cfg_count = ARRAY_SIZE(ir_rxtx_pin_cfg); 1833 1834 static struct v4l2_subdev_io_pin_config ir_rx_pin_cfg[] = { 1835 { 1836 .flags = BIT(V4L2_SUBDEV_IO_PIN_INPUT), 1837 .pin = CX23885_PIN_IR_RX_GPIO19, 1838 .function = CX23885_PAD_IR_RX, 1839 .value = 0, 1840 .strength = CX25840_PIN_DRIVE_MEDIUM, 1841 } 1842 }; 1843 const size_t ir_rx_pin_cfg_count = ARRAY_SIZE(ir_rx_pin_cfg); 1844 1845 struct v4l2_subdev_ir_parameters params; 1846 int ret = 0; 1847 switch (dev->board) { 1848 case CX23885_BOARD_HAUPPAUGE_HVR1500: 1849 case CX23885_BOARD_HAUPPAUGE_HVR1500Q: 1850 case CX23885_BOARD_HAUPPAUGE_HVR1800: 1851 case CX23885_BOARD_HAUPPAUGE_HVR1200: 1852 case CX23885_BOARD_HAUPPAUGE_HVR1400: 1853 case CX23885_BOARD_HAUPPAUGE_HVR1275: 1854 case CX23885_BOARD_HAUPPAUGE_HVR1255: 1855 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111: 1856 case CX23885_BOARD_HAUPPAUGE_HVR1210: 1857 case CX23885_BOARD_HAUPPAUGE_QUADHD_DVB: 1858 case CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC: 1859 /* FIXME: Implement me */ 1860 break; 1861 case CX23885_BOARD_HAUPPAUGE_HVR1270: 1862 ret = cx23888_ir_probe(dev); 1863 if (ret) 1864 break; 1865 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_888_IR); 1866 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config, 1867 ir_rx_pin_cfg_count, ir_rx_pin_cfg); 1868 break; 1869 case CX23885_BOARD_HAUPPAUGE_HVR1850: 1870 case CX23885_BOARD_HAUPPAUGE_HVR1290: 1871 ret = cx23888_ir_probe(dev); 1872 if (ret) 1873 break; 1874 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_888_IR); 1875 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config, 1876 ir_rxtx_pin_cfg_count, ir_rxtx_pin_cfg); 1877 /* 1878 * For these boards we need to invert the Tx output via the 1879 * IR controller to have the LED off while idle 1880 */ 1881 v4l2_subdev_call(dev->sd_ir, ir, tx_g_parameters, ¶ms); 1882 params.enable = false; 1883 params.shutdown = false; 1884 params.invert_level = true; 1885 v4l2_subdev_call(dev->sd_ir, ir, tx_s_parameters, ¶ms); 1886 params.shutdown = true; 1887 v4l2_subdev_call(dev->sd_ir, ir, tx_s_parameters, ¶ms); 1888 break; 1889 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL: 1890 case CX23885_BOARD_TEVII_S470: 1891 case CX23885_BOARD_MYGICA_X8507: 1892 case CX23885_BOARD_TBS_6980: 1893 case CX23885_BOARD_TBS_6981: 1894 case CX23885_BOARD_DVBSKY_T9580: 1895 case CX23885_BOARD_DVBSKY_T980C: 1896 case CX23885_BOARD_DVBSKY_S950C: 1897 case CX23885_BOARD_TT_CT2_4500_CI: 1898 case CX23885_BOARD_DVBSKY_S950: 1899 case CX23885_BOARD_DVBSKY_S952: 1900 case CX23885_BOARD_DVBSKY_T982: 1901 if (!enable_885_ir) 1902 break; 1903 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_AV_CORE); 1904 if (dev->sd_ir == NULL) { 1905 ret = -ENODEV; 1906 break; 1907 } 1908 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config, 1909 ir_rx_pin_cfg_count, ir_rx_pin_cfg); 1910 break; 1911 case CX23885_BOARD_HAUPPAUGE_HVR1250: 1912 if (!enable_885_ir) 1913 break; 1914 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_AV_CORE); 1915 if (dev->sd_ir == NULL) { 1916 ret = -ENODEV; 1917 break; 1918 } 1919 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config, 1920 ir_rxtx_pin_cfg_count, ir_rxtx_pin_cfg); 1921 break; 1922 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: 1923 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2: 1924 request_module("ir-kbd-i2c"); 1925 break; 1926 } 1927 1928 return ret; 1929 } 1930 1931 void cx23885_ir_fini(struct cx23885_dev *dev) 1932 { 1933 switch (dev->board) { 1934 case CX23885_BOARD_HAUPPAUGE_HVR1270: 1935 case CX23885_BOARD_HAUPPAUGE_HVR1850: 1936 case CX23885_BOARD_HAUPPAUGE_HVR1290: 1937 cx23885_irq_remove(dev, PCI_MSK_IR); 1938 cx23888_ir_remove(dev); 1939 dev->sd_ir = NULL; 1940 break; 1941 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL: 1942 case CX23885_BOARD_TEVII_S470: 1943 case CX23885_BOARD_HAUPPAUGE_HVR1250: 1944 case CX23885_BOARD_MYGICA_X8507: 1945 case CX23885_BOARD_TBS_6980: 1946 case CX23885_BOARD_TBS_6981: 1947 case CX23885_BOARD_DVBSKY_T9580: 1948 case CX23885_BOARD_DVBSKY_T980C: 1949 case CX23885_BOARD_DVBSKY_S950C: 1950 case CX23885_BOARD_TT_CT2_4500_CI: 1951 case CX23885_BOARD_DVBSKY_S950: 1952 case CX23885_BOARD_DVBSKY_S952: 1953 case CX23885_BOARD_DVBSKY_T982: 1954 cx23885_irq_remove(dev, PCI_MSK_AV_CORE); 1955 /* sd_ir is a duplicate pointer to the AV Core, just clear it */ 1956 dev->sd_ir = NULL; 1957 break; 1958 } 1959 } 1960 1961 static int netup_jtag_io(void *device, int tms, int tdi, int read_tdo) 1962 { 1963 int data; 1964 int tdo = 0; 1965 struct cx23885_dev *dev = (struct cx23885_dev *)device; 1966 /*TMS*/ 1967 data = ((cx_read(GP0_IO)) & (~0x00000002)); 1968 data |= (tms ? 0x00020002 : 0x00020000); 1969 cx_write(GP0_IO, data); 1970 1971 /*TDI*/ 1972 data = ((cx_read(MC417_RWD)) & (~0x0000a000)); 1973 data |= (tdi ? 0x00008000 : 0); 1974 cx_write(MC417_RWD, data); 1975 if (read_tdo) 1976 tdo = (data & 0x00004000) ? 1 : 0; /*TDO*/ 1977 1978 cx_write(MC417_RWD, data | 0x00002000); 1979 udelay(1); 1980 /*TCK*/ 1981 cx_write(MC417_RWD, data); 1982 1983 return tdo; 1984 } 1985 1986 void cx23885_ir_pci_int_enable(struct cx23885_dev *dev) 1987 { 1988 switch (dev->board) { 1989 case CX23885_BOARD_HAUPPAUGE_HVR1270: 1990 case CX23885_BOARD_HAUPPAUGE_HVR1850: 1991 case CX23885_BOARD_HAUPPAUGE_HVR1290: 1992 if (dev->sd_ir) 1993 cx23885_irq_add_enable(dev, PCI_MSK_IR); 1994 break; 1995 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL: 1996 case CX23885_BOARD_TEVII_S470: 1997 case CX23885_BOARD_HAUPPAUGE_HVR1250: 1998 case CX23885_BOARD_MYGICA_X8507: 1999 case CX23885_BOARD_TBS_6980: 2000 case CX23885_BOARD_TBS_6981: 2001 case CX23885_BOARD_DVBSKY_T9580: 2002 case CX23885_BOARD_DVBSKY_T980C: 2003 case CX23885_BOARD_DVBSKY_S950C: 2004 case CX23885_BOARD_TT_CT2_4500_CI: 2005 case CX23885_BOARD_DVBSKY_S950: 2006 case CX23885_BOARD_DVBSKY_S952: 2007 case CX23885_BOARD_DVBSKY_T982: 2008 if (dev->sd_ir) 2009 cx23885_irq_add_enable(dev, PCI_MSK_AV_CORE); 2010 break; 2011 } 2012 } 2013 2014 void cx23885_card_setup(struct cx23885_dev *dev) 2015 { 2016 struct cx23885_tsport *ts1 = &dev->ts1; 2017 struct cx23885_tsport *ts2 = &dev->ts2; 2018 2019 static u8 eeprom[256]; 2020 2021 if (dev->i2c_bus[0].i2c_rc == 0) { 2022 dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1; 2023 tveeprom_read(&dev->i2c_bus[0].i2c_client, 2024 eeprom, sizeof(eeprom)); 2025 } 2026 2027 switch (dev->board) { 2028 case CX23885_BOARD_HAUPPAUGE_HVR1250: 2029 if (dev->i2c_bus[0].i2c_rc == 0) { 2030 if (eeprom[0x80] != 0x84) 2031 hauppauge_eeprom(dev, eeprom+0xc0); 2032 else 2033 hauppauge_eeprom(dev, eeprom+0x80); 2034 } 2035 break; 2036 case CX23885_BOARD_HAUPPAUGE_HVR1500: 2037 case CX23885_BOARD_HAUPPAUGE_HVR1500Q: 2038 case CX23885_BOARD_HAUPPAUGE_HVR1400: 2039 if (dev->i2c_bus[0].i2c_rc == 0) 2040 hauppauge_eeprom(dev, eeprom+0x80); 2041 break; 2042 case CX23885_BOARD_HAUPPAUGE_HVR1800: 2043 case CX23885_BOARD_HAUPPAUGE_HVR1800lp: 2044 case CX23885_BOARD_HAUPPAUGE_HVR1200: 2045 case CX23885_BOARD_HAUPPAUGE_HVR1700: 2046 case CX23885_BOARD_HAUPPAUGE_HVR1270: 2047 case CX23885_BOARD_HAUPPAUGE_HVR1275: 2048 case CX23885_BOARD_HAUPPAUGE_HVR1255: 2049 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111: 2050 case CX23885_BOARD_HAUPPAUGE_HVR1210: 2051 case CX23885_BOARD_HAUPPAUGE_HVR1850: 2052 case CX23885_BOARD_HAUPPAUGE_HVR1290: 2053 case CX23885_BOARD_HAUPPAUGE_HVR4400: 2054 case CX23885_BOARD_HAUPPAUGE_STARBURST: 2055 case CX23885_BOARD_HAUPPAUGE_IMPACTVCBE: 2056 case CX23885_BOARD_HAUPPAUGE_HVR5525: 2057 case CX23885_BOARD_HAUPPAUGE_QUADHD_DVB: 2058 case CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC: 2059 if (dev->i2c_bus[0].i2c_rc == 0) 2060 hauppauge_eeprom(dev, eeprom+0xc0); 2061 break; 2062 case CX23885_BOARD_VIEWCAST_260E: 2063 case CX23885_BOARD_VIEWCAST_460E: 2064 dev->i2c_bus[1].i2c_client.addr = 0xa0 >> 1; 2065 tveeprom_read(&dev->i2c_bus[1].i2c_client, 2066 eeprom, sizeof(eeprom)); 2067 if (dev->i2c_bus[0].i2c_rc == 0) 2068 viewcast_eeprom(dev, eeprom); 2069 break; 2070 } 2071 2072 switch (dev->board) { 2073 case CX23885_BOARD_AVERMEDIA_HC81R: 2074 /* Defaults for VID B */ 2075 ts1->gen_ctrl_val = 0x4; /* Parallel */ 2076 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2077 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2078 /* Defaults for VID C */ 2079 /* DREQ_POL, SMODE, PUNC_CLK, MCLK_POL Serial bus + punc clk */ 2080 ts2->gen_ctrl_val = 0x10e; 2081 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2082 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2083 break; 2084 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP: 2085 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: 2086 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2: 2087 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 2088 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2089 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2090 /* fall-through */ 2091 case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP: 2092 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 2093 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2094 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2095 break; 2096 case CX23885_BOARD_HAUPPAUGE_HVR1850: 2097 case CX23885_BOARD_HAUPPAUGE_HVR1800: 2098 /* Defaults for VID B - Analog encoder */ 2099 /* DREQ_POL, SMODE, PUNC_CLK, MCLK_POL Serial bus + punc clk */ 2100 ts1->gen_ctrl_val = 0x10e; 2101 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2102 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2103 2104 /* APB_TSVALERR_POL (active low)*/ 2105 ts1->vld_misc_val = 0x2000; 2106 ts1->hw_sop_ctrl_val = (0x47 << 16 | 188 << 4 | 0xc); 2107 cx_write(0x130184, 0xc); 2108 2109 /* Defaults for VID C */ 2110 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 2111 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2112 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2113 break; 2114 case CX23885_BOARD_TBS_6920: 2115 ts1->gen_ctrl_val = 0x4; /* Parallel */ 2116 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2117 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2118 break; 2119 case CX23885_BOARD_TEVII_S470: 2120 case CX23885_BOARD_TEVII_S471: 2121 case CX23885_BOARD_DVBWORLD_2005: 2122 case CX23885_BOARD_PROF_8000: 2123 case CX23885_BOARD_DVBSKY_T980C: 2124 case CX23885_BOARD_DVBSKY_S950C: 2125 case CX23885_BOARD_TT_CT2_4500_CI: 2126 case CX23885_BOARD_DVBSKY_S950: 2127 ts1->gen_ctrl_val = 0x5; /* Parallel */ 2128 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2129 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2130 break; 2131 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: 2132 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: 2133 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL: 2134 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 2135 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2136 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2137 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 2138 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2139 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2140 break; 2141 case CX23885_BOARD_TBS_6980: 2142 case CX23885_BOARD_TBS_6981: 2143 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 2144 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2145 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2146 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 2147 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2148 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2149 tbs_card_init(dev); 2150 break; 2151 case CX23885_BOARD_MYGICA_X8506: 2152 case CX23885_BOARD_MAGICPRO_PROHDTVE2: 2153 case CX23885_BOARD_MYGICA_X8507: 2154 ts1->gen_ctrl_val = 0x5; /* Parallel */ 2155 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2156 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2157 break; 2158 case CX23885_BOARD_MYGICA_X8558PRO: 2159 ts1->gen_ctrl_val = 0x5; /* Parallel */ 2160 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2161 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2162 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 2163 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2164 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2165 break; 2166 case CX23885_BOARD_HAUPPAUGE_HVR4400: 2167 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 2168 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2169 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2170 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 2171 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2172 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2173 break; 2174 case CX23885_BOARD_HAUPPAUGE_STARBURST: 2175 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 2176 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2177 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2178 break; 2179 case CX23885_BOARD_DVBSKY_T9580: 2180 case CX23885_BOARD_DVBSKY_T982: 2181 ts1->gen_ctrl_val = 0x5; /* Parallel */ 2182 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2183 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2184 ts2->gen_ctrl_val = 0x8; /* Serial bus */ 2185 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2186 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2187 break; 2188 case CX23885_BOARD_DVBSKY_S952: 2189 ts1->gen_ctrl_val = 0x5; /* Parallel */ 2190 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2191 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2192 ts2->gen_ctrl_val = 0xe; /* Serial bus */ 2193 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2194 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2195 break; 2196 case CX23885_BOARD_HAUPPAUGE_HVR5525: 2197 ts1->gen_ctrl_val = 0x5; /* Parallel */ 2198 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2199 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2200 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 2201 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2202 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2203 break; 2204 case CX23885_BOARD_HAUPPAUGE_QUADHD_DVB: 2205 case CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC: 2206 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 2207 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2208 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2209 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 2210 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2211 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2212 break; 2213 case CX23885_BOARD_HAUPPAUGE_HVR1250: 2214 case CX23885_BOARD_HAUPPAUGE_HVR1500: 2215 case CX23885_BOARD_HAUPPAUGE_HVR1500Q: 2216 case CX23885_BOARD_HAUPPAUGE_HVR1800lp: 2217 case CX23885_BOARD_HAUPPAUGE_HVR1200: 2218 case CX23885_BOARD_HAUPPAUGE_HVR1700: 2219 case CX23885_BOARD_HAUPPAUGE_HVR1400: 2220 case CX23885_BOARD_HAUPPAUGE_IMPACTVCBE: 2221 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H: 2222 case CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200: 2223 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000: 2224 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F: 2225 case CX23885_BOARD_HAUPPAUGE_HVR1270: 2226 case CX23885_BOARD_HAUPPAUGE_HVR1275: 2227 case CX23885_BOARD_HAUPPAUGE_HVR1255: 2228 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111: 2229 case CX23885_BOARD_HAUPPAUGE_HVR1210: 2230 case CX23885_BOARD_COMPRO_VIDEOMATE_E800: 2231 case CX23885_BOARD_HAUPPAUGE_HVR1290: 2232 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID: 2233 default: 2234 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 2235 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2236 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2237 } 2238 2239 /* Certain boards support analog, or require the avcore to be 2240 * loaded, ensure this happens. 2241 */ 2242 switch (dev->board) { 2243 case CX23885_BOARD_TEVII_S470: 2244 /* Currently only enabled for the integrated IR controller */ 2245 if (!enable_885_ir) 2246 break; 2247 /* fall-through */ 2248 case CX23885_BOARD_HAUPPAUGE_HVR1250: 2249 case CX23885_BOARD_HAUPPAUGE_HVR1800: 2250 case CX23885_BOARD_HAUPPAUGE_IMPACTVCBE: 2251 case CX23885_BOARD_HAUPPAUGE_HVR1800lp: 2252 case CX23885_BOARD_HAUPPAUGE_HVR1700: 2253 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H: 2254 case CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200: 2255 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000: 2256 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F: 2257 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: 2258 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: 2259 case CX23885_BOARD_COMPRO_VIDEOMATE_E800: 2260 case CX23885_BOARD_HAUPPAUGE_HVR1255: 2261 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111: 2262 case CX23885_BOARD_HAUPPAUGE_HVR1270: 2263 case CX23885_BOARD_HAUPPAUGE_HVR1850: 2264 case CX23885_BOARD_MYGICA_X8506: 2265 case CX23885_BOARD_MAGICPRO_PROHDTVE2: 2266 case CX23885_BOARD_HAUPPAUGE_HVR1290: 2267 case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200: 2268 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID: 2269 case CX23885_BOARD_HAUPPAUGE_HVR1500: 2270 case CX23885_BOARD_MPX885: 2271 case CX23885_BOARD_MYGICA_X8507: 2272 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL: 2273 case CX23885_BOARD_AVERMEDIA_HC81R: 2274 case CX23885_BOARD_TBS_6980: 2275 case CX23885_BOARD_TBS_6981: 2276 case CX23885_BOARD_DVBSKY_T9580: 2277 case CX23885_BOARD_DVBSKY_T980C: 2278 case CX23885_BOARD_DVBSKY_S950C: 2279 case CX23885_BOARD_TT_CT2_4500_CI: 2280 case CX23885_BOARD_DVBSKY_S950: 2281 case CX23885_BOARD_DVBSKY_S952: 2282 case CX23885_BOARD_DVBSKY_T982: 2283 case CX23885_BOARD_VIEWCAST_260E: 2284 case CX23885_BOARD_VIEWCAST_460E: 2285 dev->sd_cx25840 = v4l2_i2c_new_subdev(&dev->v4l2_dev, 2286 &dev->i2c_bus[2].i2c_adap, 2287 "cx25840", 0x88 >> 1, NULL); 2288 if (dev->sd_cx25840) { 2289 dev->sd_cx25840->grp_id = CX23885_HW_AV_CORE; 2290 v4l2_subdev_call(dev->sd_cx25840, core, load_fw); 2291 } 2292 break; 2293 } 2294 2295 switch (dev->board) { 2296 case CX23885_BOARD_VIEWCAST_260E: 2297 v4l2_i2c_new_subdev(&dev->v4l2_dev, 2298 &dev->i2c_bus[0].i2c_adap, 2299 "cs3308", 0x82 >> 1, NULL); 2300 break; 2301 case CX23885_BOARD_VIEWCAST_460E: 2302 /* This cs3308 controls the audio from the breakout cable */ 2303 v4l2_i2c_new_subdev(&dev->v4l2_dev, 2304 &dev->i2c_bus[0].i2c_adap, 2305 "cs3308", 0x80 >> 1, NULL); 2306 /* This cs3308 controls the audio from the onboard header */ 2307 v4l2_i2c_new_subdev(&dev->v4l2_dev, 2308 &dev->i2c_bus[0].i2c_adap, 2309 "cs3308", 0x82 >> 1, NULL); 2310 break; 2311 } 2312 2313 /* AUX-PLL 27MHz CLK */ 2314 switch (dev->board) { 2315 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: 2316 netup_initialize(dev); 2317 break; 2318 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: { 2319 int ret; 2320 const struct firmware *fw; 2321 const char *filename = "dvb-netup-altera-01.fw"; 2322 char *action = "configure"; 2323 static struct netup_card_info cinfo; 2324 struct altera_config netup_config = { 2325 .dev = dev, 2326 .action = action, 2327 .jtag_io = netup_jtag_io, 2328 }; 2329 2330 netup_initialize(dev); 2331 2332 netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo); 2333 if (netup_card_rev) 2334 cinfo.rev = netup_card_rev; 2335 2336 switch (cinfo.rev) { 2337 case 0x4: 2338 filename = "dvb-netup-altera-04.fw"; 2339 break; 2340 default: 2341 filename = "dvb-netup-altera-01.fw"; 2342 break; 2343 } 2344 pr_info("NetUP card rev=0x%x fw_filename=%s\n", 2345 cinfo.rev, filename); 2346 2347 ret = request_firmware(&fw, filename, &dev->pci->dev); 2348 if (ret != 0) 2349 pr_err("did not find the firmware file. (%s) Please see linux/Documentation/dvb/ for more details on firmware-problems.", 2350 filename); 2351 else 2352 altera_init(&netup_config, fw); 2353 2354 release_firmware(fw); 2355 break; 2356 } 2357 } 2358 } 2359