1 /* 2 * Driver for the Conexant CX23885 PCIe bridge 3 * 4 * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 20 */ 21 22 #include <linux/init.h> 23 #include <linux/module.h> 24 #include <linux/pci.h> 25 #include <linux/delay.h> 26 #include <media/cx25840.h> 27 #include <linux/firmware.h> 28 #include <misc/altera.h> 29 30 #include "cx23885.h" 31 #include "tuner-xc2028.h" 32 #include "netup-eeprom.h" 33 #include "netup-init.h" 34 #include "altera-ci.h" 35 #include "xc4000.h" 36 #include "xc5000.h" 37 #include "cx23888-ir.h" 38 39 static unsigned int netup_card_rev = 4; 40 module_param(netup_card_rev, int, 0644); 41 MODULE_PARM_DESC(netup_card_rev, 42 "NetUP Dual DVB-T/C CI card revision"); 43 static unsigned int enable_885_ir; 44 module_param(enable_885_ir, int, 0644); 45 MODULE_PARM_DESC(enable_885_ir, 46 "Enable integrated IR controller for supported\n" 47 "\t\t CX2388[57] boards that are wired for it:\n" 48 "\t\t\tHVR-1250 (reported safe)\n" 49 "\t\t\tTerraTec Cinergy T PCIe Dual (not well tested, appears to be safe)\n" 50 "\t\t\tTeVii S470 (reported unsafe)\n" 51 "\t\t This can cause an interrupt storm with some cards.\n" 52 "\t\t Default: 0 [Disabled]"); 53 54 /* ------------------------------------------------------------------ */ 55 /* board config info */ 56 57 struct cx23885_board cx23885_boards[] = { 58 [CX23885_BOARD_UNKNOWN] = { 59 .name = "UNKNOWN/GENERIC", 60 /* Ensure safe default for unknown boards */ 61 .clk_freq = 0, 62 .input = {{ 63 .type = CX23885_VMUX_COMPOSITE1, 64 .vmux = 0, 65 }, { 66 .type = CX23885_VMUX_COMPOSITE2, 67 .vmux = 1, 68 }, { 69 .type = CX23885_VMUX_COMPOSITE3, 70 .vmux = 2, 71 }, { 72 .type = CX23885_VMUX_COMPOSITE4, 73 .vmux = 3, 74 } }, 75 }, 76 [CX23885_BOARD_HAUPPAUGE_HVR1800lp] = { 77 .name = "Hauppauge WinTV-HVR1800lp", 78 .portc = CX23885_MPEG_DVB, 79 .input = {{ 80 .type = CX23885_VMUX_TELEVISION, 81 .vmux = 0, 82 .gpio0 = 0xff00, 83 }, { 84 .type = CX23885_VMUX_DEBUG, 85 .vmux = 0, 86 .gpio0 = 0xff01, 87 }, { 88 .type = CX23885_VMUX_COMPOSITE1, 89 .vmux = 1, 90 .gpio0 = 0xff02, 91 }, { 92 .type = CX23885_VMUX_SVIDEO, 93 .vmux = 2, 94 .gpio0 = 0xff02, 95 } }, 96 }, 97 [CX23885_BOARD_HAUPPAUGE_HVR1800] = { 98 .name = "Hauppauge WinTV-HVR1800", 99 .porta = CX23885_ANALOG_VIDEO, 100 .portb = CX23885_MPEG_ENCODER, 101 .portc = CX23885_MPEG_DVB, 102 .tuner_type = TUNER_PHILIPS_TDA8290, 103 .tuner_addr = 0x42, /* 0x84 >> 1 */ 104 .tuner_bus = 1, 105 .input = {{ 106 .type = CX23885_VMUX_TELEVISION, 107 .vmux = CX25840_VIN7_CH3 | 108 CX25840_VIN5_CH2 | 109 CX25840_VIN2_CH1, 110 .amux = CX25840_AUDIO8, 111 .gpio0 = 0, 112 }, { 113 .type = CX23885_VMUX_COMPOSITE1, 114 .vmux = CX25840_VIN7_CH3 | 115 CX25840_VIN4_CH2 | 116 CX25840_VIN6_CH1, 117 .amux = CX25840_AUDIO7, 118 .gpio0 = 0, 119 }, { 120 .type = CX23885_VMUX_SVIDEO, 121 .vmux = CX25840_VIN7_CH3 | 122 CX25840_VIN4_CH2 | 123 CX25840_VIN8_CH1 | 124 CX25840_SVIDEO_ON, 125 .amux = CX25840_AUDIO7, 126 .gpio0 = 0, 127 } }, 128 }, 129 [CX23885_BOARD_HAUPPAUGE_HVR1250] = { 130 .name = "Hauppauge WinTV-HVR1250", 131 .porta = CX23885_ANALOG_VIDEO, 132 .portc = CX23885_MPEG_DVB, 133 #ifdef MT2131_NO_ANALOG_SUPPORT_YET 134 .tuner_type = TUNER_PHILIPS_TDA8290, 135 .tuner_addr = 0x42, /* 0x84 >> 1 */ 136 .tuner_bus = 1, 137 #endif 138 .force_bff = 1, 139 .input = {{ 140 #ifdef MT2131_NO_ANALOG_SUPPORT_YET 141 .type = CX23885_VMUX_TELEVISION, 142 .vmux = CX25840_VIN7_CH3 | 143 CX25840_VIN5_CH2 | 144 CX25840_VIN2_CH1, 145 .amux = CX25840_AUDIO8, 146 .gpio0 = 0xff00, 147 }, { 148 #endif 149 .type = CX23885_VMUX_COMPOSITE1, 150 .vmux = CX25840_VIN7_CH3 | 151 CX25840_VIN4_CH2 | 152 CX25840_VIN6_CH1, 153 .amux = CX25840_AUDIO7, 154 .gpio0 = 0xff02, 155 }, { 156 .type = CX23885_VMUX_SVIDEO, 157 .vmux = CX25840_VIN7_CH3 | 158 CX25840_VIN4_CH2 | 159 CX25840_VIN8_CH1 | 160 CX25840_SVIDEO_ON, 161 .amux = CX25840_AUDIO7, 162 .gpio0 = 0xff02, 163 } }, 164 }, 165 [CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP] = { 166 .name = "DViCO FusionHDTV5 Express", 167 .portb = CX23885_MPEG_DVB, 168 }, 169 [CX23885_BOARD_HAUPPAUGE_HVR1500Q] = { 170 .name = "Hauppauge WinTV-HVR1500Q", 171 .portc = CX23885_MPEG_DVB, 172 }, 173 [CX23885_BOARD_HAUPPAUGE_HVR1500] = { 174 .name = "Hauppauge WinTV-HVR1500", 175 .porta = CX23885_ANALOG_VIDEO, 176 .portc = CX23885_MPEG_DVB, 177 .tuner_type = TUNER_XC2028, 178 .tuner_addr = 0x61, /* 0xc2 >> 1 */ 179 .input = {{ 180 .type = CX23885_VMUX_TELEVISION, 181 .vmux = CX25840_VIN7_CH3 | 182 CX25840_VIN5_CH2 | 183 CX25840_VIN2_CH1, 184 .gpio0 = 0, 185 }, { 186 .type = CX23885_VMUX_COMPOSITE1, 187 .vmux = CX25840_VIN7_CH3 | 188 CX25840_VIN4_CH2 | 189 CX25840_VIN6_CH1, 190 .gpio0 = 0, 191 }, { 192 .type = CX23885_VMUX_SVIDEO, 193 .vmux = CX25840_VIN7_CH3 | 194 CX25840_VIN4_CH2 | 195 CX25840_VIN8_CH1 | 196 CX25840_SVIDEO_ON, 197 .gpio0 = 0, 198 } }, 199 }, 200 [CX23885_BOARD_HAUPPAUGE_HVR1200] = { 201 .name = "Hauppauge WinTV-HVR1200", 202 .portc = CX23885_MPEG_DVB, 203 }, 204 [CX23885_BOARD_HAUPPAUGE_HVR1700] = { 205 .name = "Hauppauge WinTV-HVR1700", 206 .portc = CX23885_MPEG_DVB, 207 }, 208 [CX23885_BOARD_HAUPPAUGE_HVR1400] = { 209 .name = "Hauppauge WinTV-HVR1400", 210 .portc = CX23885_MPEG_DVB, 211 }, 212 [CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP] = { 213 .name = "DViCO FusionHDTV7 Dual Express", 214 .portb = CX23885_MPEG_DVB, 215 .portc = CX23885_MPEG_DVB, 216 }, 217 [CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP] = { 218 .name = "DViCO FusionHDTV DVB-T Dual Express", 219 .portb = CX23885_MPEG_DVB, 220 .portc = CX23885_MPEG_DVB, 221 }, 222 [CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H] = { 223 .name = "Leadtek Winfast PxDVR3200 H", 224 .portc = CX23885_MPEG_DVB, 225 }, 226 [CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200] = { 227 .name = "Leadtek Winfast PxPVR2200", 228 .porta = CX23885_ANALOG_VIDEO, 229 .tuner_type = TUNER_XC2028, 230 .tuner_addr = 0x61, 231 .tuner_bus = 1, 232 .input = {{ 233 .type = CX23885_VMUX_TELEVISION, 234 .vmux = CX25840_VIN2_CH1 | 235 CX25840_VIN5_CH2, 236 .amux = CX25840_AUDIO8, 237 .gpio0 = 0x704040, 238 }, { 239 .type = CX23885_VMUX_COMPOSITE1, 240 .vmux = CX25840_COMPOSITE1, 241 .amux = CX25840_AUDIO7, 242 .gpio0 = 0x704040, 243 }, { 244 .type = CX23885_VMUX_SVIDEO, 245 .vmux = CX25840_SVIDEO_LUMA3 | 246 CX25840_SVIDEO_CHROMA4, 247 .amux = CX25840_AUDIO7, 248 .gpio0 = 0x704040, 249 }, { 250 .type = CX23885_VMUX_COMPONENT, 251 .vmux = CX25840_VIN7_CH1 | 252 CX25840_VIN6_CH2 | 253 CX25840_VIN8_CH3 | 254 CX25840_COMPONENT_ON, 255 .amux = CX25840_AUDIO7, 256 .gpio0 = 0x704040, 257 } }, 258 }, 259 [CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000] = { 260 .name = "Leadtek Winfast PxDVR3200 H XC4000", 261 .porta = CX23885_ANALOG_VIDEO, 262 .portc = CX23885_MPEG_DVB, 263 .tuner_type = TUNER_XC4000, 264 .tuner_addr = 0x61, 265 .radio_type = UNSET, 266 .radio_addr = ADDR_UNSET, 267 .input = {{ 268 .type = CX23885_VMUX_TELEVISION, 269 .vmux = CX25840_VIN2_CH1 | 270 CX25840_VIN5_CH2 | 271 CX25840_NONE0_CH3, 272 }, { 273 .type = CX23885_VMUX_COMPOSITE1, 274 .vmux = CX25840_COMPOSITE1, 275 }, { 276 .type = CX23885_VMUX_SVIDEO, 277 .vmux = CX25840_SVIDEO_LUMA3 | 278 CX25840_SVIDEO_CHROMA4, 279 }, { 280 .type = CX23885_VMUX_COMPONENT, 281 .vmux = CX25840_VIN7_CH1 | 282 CX25840_VIN6_CH2 | 283 CX25840_VIN8_CH3 | 284 CX25840_COMPONENT_ON, 285 } }, 286 }, 287 [CX23885_BOARD_COMPRO_VIDEOMATE_E650F] = { 288 .name = "Compro VideoMate E650F", 289 .portc = CX23885_MPEG_DVB, 290 }, 291 [CX23885_BOARD_TBS_6920] = { 292 .name = "TurboSight TBS 6920", 293 .portb = CX23885_MPEG_DVB, 294 }, 295 [CX23885_BOARD_TBS_6980] = { 296 .name = "TurboSight TBS 6980", 297 .portb = CX23885_MPEG_DVB, 298 .portc = CX23885_MPEG_DVB, 299 }, 300 [CX23885_BOARD_TBS_6981] = { 301 .name = "TurboSight TBS 6981", 302 .portb = CX23885_MPEG_DVB, 303 .portc = CX23885_MPEG_DVB, 304 }, 305 [CX23885_BOARD_TEVII_S470] = { 306 .name = "TeVii S470", 307 .portb = CX23885_MPEG_DVB, 308 }, 309 [CX23885_BOARD_DVBWORLD_2005] = { 310 .name = "DVBWorld DVB-S2 2005", 311 .portb = CX23885_MPEG_DVB, 312 }, 313 [CX23885_BOARD_NETUP_DUAL_DVBS2_CI] = { 314 .ci_type = 1, 315 .name = "NetUP Dual DVB-S2 CI", 316 .portb = CX23885_MPEG_DVB, 317 .portc = CX23885_MPEG_DVB, 318 }, 319 [CX23885_BOARD_HAUPPAUGE_HVR1270] = { 320 .name = "Hauppauge WinTV-HVR1270", 321 .portc = CX23885_MPEG_DVB, 322 }, 323 [CX23885_BOARD_HAUPPAUGE_HVR1275] = { 324 .name = "Hauppauge WinTV-HVR1275", 325 .portc = CX23885_MPEG_DVB, 326 }, 327 [CX23885_BOARD_HAUPPAUGE_HVR1255] = { 328 .name = "Hauppauge WinTV-HVR1255", 329 .porta = CX23885_ANALOG_VIDEO, 330 .portc = CX23885_MPEG_DVB, 331 .tuner_type = TUNER_ABSENT, 332 .tuner_addr = 0x42, /* 0x84 >> 1 */ 333 .force_bff = 1, 334 .input = {{ 335 .type = CX23885_VMUX_TELEVISION, 336 .vmux = CX25840_VIN7_CH3 | 337 CX25840_VIN5_CH2 | 338 CX25840_VIN2_CH1 | 339 CX25840_DIF_ON, 340 .amux = CX25840_AUDIO8, 341 }, { 342 .type = CX23885_VMUX_COMPOSITE1, 343 .vmux = CX25840_VIN7_CH3 | 344 CX25840_VIN4_CH2 | 345 CX25840_VIN6_CH1, 346 .amux = CX25840_AUDIO7, 347 }, { 348 .type = CX23885_VMUX_SVIDEO, 349 .vmux = CX25840_VIN7_CH3 | 350 CX25840_VIN4_CH2 | 351 CX25840_VIN8_CH1 | 352 CX25840_SVIDEO_ON, 353 .amux = CX25840_AUDIO7, 354 } }, 355 }, 356 [CX23885_BOARD_HAUPPAUGE_HVR1255_22111] = { 357 .name = "Hauppauge WinTV-HVR1255", 358 .porta = CX23885_ANALOG_VIDEO, 359 .portc = CX23885_MPEG_DVB, 360 .tuner_type = TUNER_ABSENT, 361 .tuner_addr = 0x42, /* 0x84 >> 1 */ 362 .force_bff = 1, 363 .input = {{ 364 .type = CX23885_VMUX_TELEVISION, 365 .vmux = CX25840_VIN7_CH3 | 366 CX25840_VIN5_CH2 | 367 CX25840_VIN2_CH1 | 368 CX25840_DIF_ON, 369 .amux = CX25840_AUDIO8, 370 }, { 371 .type = CX23885_VMUX_SVIDEO, 372 .vmux = CX25840_VIN7_CH3 | 373 CX25840_VIN4_CH2 | 374 CX25840_VIN8_CH1 | 375 CX25840_SVIDEO_ON, 376 .amux = CX25840_AUDIO7, 377 } }, 378 }, 379 [CX23885_BOARD_HAUPPAUGE_HVR1210] = { 380 .name = "Hauppauge WinTV-HVR1210", 381 .portc = CX23885_MPEG_DVB, 382 }, 383 [CX23885_BOARD_MYGICA_X8506] = { 384 .name = "Mygica X8506 DMB-TH", 385 .tuner_type = TUNER_XC5000, 386 .tuner_addr = 0x61, 387 .tuner_bus = 1, 388 .porta = CX23885_ANALOG_VIDEO, 389 .portb = CX23885_MPEG_DVB, 390 .input = { 391 { 392 .type = CX23885_VMUX_TELEVISION, 393 .vmux = CX25840_COMPOSITE2, 394 }, 395 { 396 .type = CX23885_VMUX_COMPOSITE1, 397 .vmux = CX25840_COMPOSITE8, 398 }, 399 { 400 .type = CX23885_VMUX_SVIDEO, 401 .vmux = CX25840_SVIDEO_LUMA3 | 402 CX25840_SVIDEO_CHROMA4, 403 }, 404 { 405 .type = CX23885_VMUX_COMPONENT, 406 .vmux = CX25840_COMPONENT_ON | 407 CX25840_VIN1_CH1 | 408 CX25840_VIN6_CH2 | 409 CX25840_VIN7_CH3, 410 }, 411 }, 412 }, 413 [CX23885_BOARD_MAGICPRO_PROHDTVE2] = { 414 .name = "Magic-Pro ProHDTV Extreme 2", 415 .tuner_type = TUNER_XC5000, 416 .tuner_addr = 0x61, 417 .tuner_bus = 1, 418 .porta = CX23885_ANALOG_VIDEO, 419 .portb = CX23885_MPEG_DVB, 420 .input = { 421 { 422 .type = CX23885_VMUX_TELEVISION, 423 .vmux = CX25840_COMPOSITE2, 424 }, 425 { 426 .type = CX23885_VMUX_COMPOSITE1, 427 .vmux = CX25840_COMPOSITE8, 428 }, 429 { 430 .type = CX23885_VMUX_SVIDEO, 431 .vmux = CX25840_SVIDEO_LUMA3 | 432 CX25840_SVIDEO_CHROMA4, 433 }, 434 { 435 .type = CX23885_VMUX_COMPONENT, 436 .vmux = CX25840_COMPONENT_ON | 437 CX25840_VIN1_CH1 | 438 CX25840_VIN6_CH2 | 439 CX25840_VIN7_CH3, 440 }, 441 }, 442 }, 443 [CX23885_BOARD_HAUPPAUGE_HVR1850] = { 444 .name = "Hauppauge WinTV-HVR1850", 445 .porta = CX23885_ANALOG_VIDEO, 446 .portb = CX23885_MPEG_ENCODER, 447 .portc = CX23885_MPEG_DVB, 448 .tuner_type = TUNER_ABSENT, 449 .tuner_addr = 0x42, /* 0x84 >> 1 */ 450 .force_bff = 1, 451 .input = {{ 452 .type = CX23885_VMUX_TELEVISION, 453 .vmux = CX25840_VIN7_CH3 | 454 CX25840_VIN5_CH2 | 455 CX25840_VIN2_CH1 | 456 CX25840_DIF_ON, 457 .amux = CX25840_AUDIO8, 458 }, { 459 .type = CX23885_VMUX_COMPOSITE1, 460 .vmux = CX25840_VIN7_CH3 | 461 CX25840_VIN4_CH2 | 462 CX25840_VIN6_CH1, 463 .amux = CX25840_AUDIO7, 464 }, { 465 .type = CX23885_VMUX_SVIDEO, 466 .vmux = CX25840_VIN7_CH3 | 467 CX25840_VIN4_CH2 | 468 CX25840_VIN8_CH1 | 469 CX25840_SVIDEO_ON, 470 .amux = CX25840_AUDIO7, 471 } }, 472 }, 473 [CX23885_BOARD_COMPRO_VIDEOMATE_E800] = { 474 .name = "Compro VideoMate E800", 475 .portc = CX23885_MPEG_DVB, 476 }, 477 [CX23885_BOARD_HAUPPAUGE_HVR1290] = { 478 .name = "Hauppauge WinTV-HVR1290", 479 .portc = CX23885_MPEG_DVB, 480 }, 481 [CX23885_BOARD_MYGICA_X8558PRO] = { 482 .name = "Mygica X8558 PRO DMB-TH", 483 .portb = CX23885_MPEG_DVB, 484 .portc = CX23885_MPEG_DVB, 485 }, 486 [CX23885_BOARD_LEADTEK_WINFAST_PXTV1200] = { 487 .name = "LEADTEK WinFast PxTV1200", 488 .porta = CX23885_ANALOG_VIDEO, 489 .tuner_type = TUNER_XC2028, 490 .tuner_addr = 0x61, 491 .tuner_bus = 1, 492 .input = {{ 493 .type = CX23885_VMUX_TELEVISION, 494 .vmux = CX25840_VIN2_CH1 | 495 CX25840_VIN5_CH2 | 496 CX25840_NONE0_CH3, 497 }, { 498 .type = CX23885_VMUX_COMPOSITE1, 499 .vmux = CX25840_COMPOSITE1, 500 }, { 501 .type = CX23885_VMUX_SVIDEO, 502 .vmux = CX25840_SVIDEO_LUMA3 | 503 CX25840_SVIDEO_CHROMA4, 504 }, { 505 .type = CX23885_VMUX_COMPONENT, 506 .vmux = CX25840_VIN7_CH1 | 507 CX25840_VIN6_CH2 | 508 CX25840_VIN8_CH3 | 509 CX25840_COMPONENT_ON, 510 } }, 511 }, 512 [CX23885_BOARD_GOTVIEW_X5_3D_HYBRID] = { 513 .name = "GoTView X5 3D Hybrid", 514 .tuner_type = TUNER_XC5000, 515 .tuner_addr = 0x64, 516 .tuner_bus = 1, 517 .porta = CX23885_ANALOG_VIDEO, 518 .portb = CX23885_MPEG_DVB, 519 .input = {{ 520 .type = CX23885_VMUX_TELEVISION, 521 .vmux = CX25840_VIN2_CH1 | 522 CX25840_VIN5_CH2, 523 .gpio0 = 0x02, 524 }, { 525 .type = CX23885_VMUX_COMPOSITE1, 526 .vmux = CX23885_VMUX_COMPOSITE1, 527 }, { 528 .type = CX23885_VMUX_SVIDEO, 529 .vmux = CX25840_SVIDEO_LUMA3 | 530 CX25840_SVIDEO_CHROMA4, 531 } }, 532 }, 533 [CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF] = { 534 .ci_type = 2, 535 .name = "NetUP Dual DVB-T/C-CI RF", 536 .porta = CX23885_ANALOG_VIDEO, 537 .portb = CX23885_MPEG_DVB, 538 .portc = CX23885_MPEG_DVB, 539 .num_fds_portb = 2, 540 .num_fds_portc = 2, 541 .tuner_type = TUNER_XC5000, 542 .tuner_addr = 0x64, 543 .input = { { 544 .type = CX23885_VMUX_TELEVISION, 545 .vmux = CX25840_COMPOSITE1, 546 } }, 547 }, 548 [CX23885_BOARD_MPX885] = { 549 .name = "MPX-885", 550 .porta = CX23885_ANALOG_VIDEO, 551 .input = {{ 552 .type = CX23885_VMUX_COMPOSITE1, 553 .vmux = CX25840_COMPOSITE1, 554 .amux = CX25840_AUDIO6, 555 .gpio0 = 0, 556 }, { 557 .type = CX23885_VMUX_COMPOSITE2, 558 .vmux = CX25840_COMPOSITE2, 559 .amux = CX25840_AUDIO6, 560 .gpio0 = 0, 561 }, { 562 .type = CX23885_VMUX_COMPOSITE3, 563 .vmux = CX25840_COMPOSITE3, 564 .amux = CX25840_AUDIO7, 565 .gpio0 = 0, 566 }, { 567 .type = CX23885_VMUX_COMPOSITE4, 568 .vmux = CX25840_COMPOSITE4, 569 .amux = CX25840_AUDIO7, 570 .gpio0 = 0, 571 } }, 572 }, 573 [CX23885_BOARD_MYGICA_X8507] = { 574 .name = "Mygica X8502/X8507 ISDB-T", 575 .tuner_type = TUNER_XC5000, 576 .tuner_addr = 0x61, 577 .tuner_bus = 1, 578 .porta = CX23885_ANALOG_VIDEO, 579 .portb = CX23885_MPEG_DVB, 580 .input = { 581 { 582 .type = CX23885_VMUX_TELEVISION, 583 .vmux = CX25840_COMPOSITE2, 584 .amux = CX25840_AUDIO8, 585 }, 586 { 587 .type = CX23885_VMUX_COMPOSITE1, 588 .vmux = CX25840_COMPOSITE8, 589 .amux = CX25840_AUDIO7, 590 }, 591 { 592 .type = CX23885_VMUX_SVIDEO, 593 .vmux = CX25840_SVIDEO_LUMA3 | 594 CX25840_SVIDEO_CHROMA4, 595 .amux = CX25840_AUDIO7, 596 }, 597 { 598 .type = CX23885_VMUX_COMPONENT, 599 .vmux = CX25840_COMPONENT_ON | 600 CX25840_VIN1_CH1 | 601 CX25840_VIN6_CH2 | 602 CX25840_VIN7_CH3, 603 .amux = CX25840_AUDIO7, 604 }, 605 }, 606 }, 607 [CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL] = { 608 .name = "TerraTec Cinergy T PCIe Dual", 609 .portb = CX23885_MPEG_DVB, 610 .portc = CX23885_MPEG_DVB, 611 }, 612 [CX23885_BOARD_TEVII_S471] = { 613 .name = "TeVii S471", 614 .portb = CX23885_MPEG_DVB, 615 }, 616 [CX23885_BOARD_PROF_8000] = { 617 .name = "Prof Revolution DVB-S2 8000", 618 .portb = CX23885_MPEG_DVB, 619 }, 620 [CX23885_BOARD_HAUPPAUGE_HVR4400] = { 621 .name = "Hauppauge WinTV-HVR4400", 622 .porta = CX23885_ANALOG_VIDEO, 623 .portb = CX23885_MPEG_DVB, 624 .portc = CX23885_MPEG_DVB, 625 .tuner_type = TUNER_NXP_TDA18271, 626 .tuner_addr = 0x60, /* 0xc0 >> 1 */ 627 .tuner_bus = 1, 628 }, 629 [CX23885_BOARD_AVERMEDIA_HC81R] = { 630 .name = "AVerTV Hybrid Express Slim HC81R", 631 .tuner_type = TUNER_XC2028, 632 .tuner_addr = 0x61, /* 0xc2 >> 1 */ 633 .tuner_bus = 1, 634 .porta = CX23885_ANALOG_VIDEO, 635 .input = {{ 636 .type = CX23885_VMUX_TELEVISION, 637 .vmux = CX25840_VIN2_CH1 | 638 CX25840_VIN5_CH2 | 639 CX25840_NONE0_CH3 | 640 CX25840_NONE1_CH3, 641 .amux = CX25840_AUDIO8, 642 }, { 643 .type = CX23885_VMUX_SVIDEO, 644 .vmux = CX25840_VIN8_CH1 | 645 CX25840_NONE_CH2 | 646 CX25840_VIN7_CH3 | 647 CX25840_SVIDEO_ON, 648 .amux = CX25840_AUDIO6, 649 }, { 650 .type = CX23885_VMUX_COMPONENT, 651 .vmux = CX25840_VIN1_CH1 | 652 CX25840_NONE_CH2 | 653 CX25840_NONE0_CH3 | 654 CX25840_NONE1_CH3, 655 .amux = CX25840_AUDIO6, 656 } }, 657 }, 658 [CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2] = { 659 .name = "DViCO FusionHDTV DVB-T Dual Express2", 660 .portb = CX23885_MPEG_DVB, 661 .portc = CX23885_MPEG_DVB, 662 }, 663 [CX23885_BOARD_HAUPPAUGE_IMPACTVCBE] = { 664 .name = "Hauppauge ImpactVCB-e", 665 .tuner_type = TUNER_ABSENT, 666 .porta = CX23885_ANALOG_VIDEO, 667 .input = {{ 668 .type = CX23885_VMUX_COMPOSITE1, 669 .vmux = CX25840_VIN7_CH3 | 670 CX25840_VIN4_CH2 | 671 CX25840_VIN6_CH1, 672 .amux = CX25840_AUDIO7, 673 }, { 674 .type = CX23885_VMUX_SVIDEO, 675 .vmux = CX25840_VIN7_CH3 | 676 CX25840_VIN4_CH2 | 677 CX25840_VIN8_CH1 | 678 CX25840_SVIDEO_ON, 679 .amux = CX25840_AUDIO7, 680 } }, 681 }, 682 }; 683 const unsigned int cx23885_bcount = ARRAY_SIZE(cx23885_boards); 684 685 /* ------------------------------------------------------------------ */ 686 /* PCI subsystem IDs */ 687 688 struct cx23885_subid cx23885_subids[] = { 689 { 690 .subvendor = 0x0070, 691 .subdevice = 0x3400, 692 .card = CX23885_BOARD_UNKNOWN, 693 }, { 694 .subvendor = 0x0070, 695 .subdevice = 0x7600, 696 .card = CX23885_BOARD_HAUPPAUGE_HVR1800lp, 697 }, { 698 .subvendor = 0x0070, 699 .subdevice = 0x7800, 700 .card = CX23885_BOARD_HAUPPAUGE_HVR1800, 701 }, { 702 .subvendor = 0x0070, 703 .subdevice = 0x7801, 704 .card = CX23885_BOARD_HAUPPAUGE_HVR1800, 705 }, { 706 .subvendor = 0x0070, 707 .subdevice = 0x7809, 708 .card = CX23885_BOARD_HAUPPAUGE_HVR1800, 709 }, { 710 .subvendor = 0x0070, 711 .subdevice = 0x7911, 712 .card = CX23885_BOARD_HAUPPAUGE_HVR1250, 713 }, { 714 .subvendor = 0x18ac, 715 .subdevice = 0xd500, 716 .card = CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP, 717 }, { 718 .subvendor = 0x0070, 719 .subdevice = 0x7790, 720 .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q, 721 }, { 722 .subvendor = 0x0070, 723 .subdevice = 0x7797, 724 .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q, 725 }, { 726 .subvendor = 0x0070, 727 .subdevice = 0x7710, 728 .card = CX23885_BOARD_HAUPPAUGE_HVR1500, 729 }, { 730 .subvendor = 0x0070, 731 .subdevice = 0x7717, 732 .card = CX23885_BOARD_HAUPPAUGE_HVR1500, 733 }, { 734 .subvendor = 0x0070, 735 .subdevice = 0x71d1, 736 .card = CX23885_BOARD_HAUPPAUGE_HVR1200, 737 }, { 738 .subvendor = 0x0070, 739 .subdevice = 0x71d3, 740 .card = CX23885_BOARD_HAUPPAUGE_HVR1200, 741 }, { 742 .subvendor = 0x0070, 743 .subdevice = 0x8101, 744 .card = CX23885_BOARD_HAUPPAUGE_HVR1700, 745 }, { 746 .subvendor = 0x0070, 747 .subdevice = 0x8010, 748 .card = CX23885_BOARD_HAUPPAUGE_HVR1400, 749 }, { 750 .subvendor = 0x18ac, 751 .subdevice = 0xd618, 752 .card = CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP, 753 }, { 754 .subvendor = 0x18ac, 755 .subdevice = 0xdb78, 756 .card = CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP, 757 }, { 758 .subvendor = 0x107d, 759 .subdevice = 0x6681, 760 .card = CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H, 761 }, { 762 .subvendor = 0x107d, 763 .subdevice = 0x6f21, 764 .card = CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200, 765 }, { 766 .subvendor = 0x107d, 767 .subdevice = 0x6f39, 768 .card = CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000, 769 }, { 770 .subvendor = 0x185b, 771 .subdevice = 0xe800, 772 .card = CX23885_BOARD_COMPRO_VIDEOMATE_E650F, 773 }, { 774 .subvendor = 0x6920, 775 .subdevice = 0x8888, 776 .card = CX23885_BOARD_TBS_6920, 777 }, { 778 .subvendor = 0x6980, 779 .subdevice = 0x8888, 780 .card = CX23885_BOARD_TBS_6980, 781 }, { 782 .subvendor = 0x6981, 783 .subdevice = 0x8888, 784 .card = CX23885_BOARD_TBS_6981, 785 }, { 786 .subvendor = 0xd470, 787 .subdevice = 0x9022, 788 .card = CX23885_BOARD_TEVII_S470, 789 }, { 790 .subvendor = 0x0001, 791 .subdevice = 0x2005, 792 .card = CX23885_BOARD_DVBWORLD_2005, 793 }, { 794 .subvendor = 0x1b55, 795 .subdevice = 0x2a2c, 796 .card = CX23885_BOARD_NETUP_DUAL_DVBS2_CI, 797 }, { 798 .subvendor = 0x0070, 799 .subdevice = 0x2211, 800 .card = CX23885_BOARD_HAUPPAUGE_HVR1270, 801 }, { 802 .subvendor = 0x0070, 803 .subdevice = 0x2215, 804 .card = CX23885_BOARD_HAUPPAUGE_HVR1275, 805 }, { 806 .subvendor = 0x0070, 807 .subdevice = 0x221d, 808 .card = CX23885_BOARD_HAUPPAUGE_HVR1275, 809 }, { 810 .subvendor = 0x0070, 811 .subdevice = 0x2251, 812 .card = CX23885_BOARD_HAUPPAUGE_HVR1255, 813 }, { 814 .subvendor = 0x0070, 815 .subdevice = 0x2259, 816 .card = CX23885_BOARD_HAUPPAUGE_HVR1255_22111, 817 }, { 818 .subvendor = 0x0070, 819 .subdevice = 0x2291, 820 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, 821 }, { 822 .subvendor = 0x0070, 823 .subdevice = 0x2295, 824 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, 825 }, { 826 .subvendor = 0x0070, 827 .subdevice = 0x2299, 828 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, 829 }, { 830 .subvendor = 0x0070, 831 .subdevice = 0x229d, 832 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */ 833 }, { 834 .subvendor = 0x0070, 835 .subdevice = 0x22f0, 836 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, 837 }, { 838 .subvendor = 0x0070, 839 .subdevice = 0x22f1, 840 .card = CX23885_BOARD_HAUPPAUGE_HVR1255, 841 }, { 842 .subvendor = 0x0070, 843 .subdevice = 0x22f2, 844 .card = CX23885_BOARD_HAUPPAUGE_HVR1275, 845 }, { 846 .subvendor = 0x0070, 847 .subdevice = 0x22f3, 848 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */ 849 }, { 850 .subvendor = 0x0070, 851 .subdevice = 0x22f4, 852 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, 853 }, { 854 .subvendor = 0x0070, 855 .subdevice = 0x22f5, 856 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */ 857 }, { 858 .subvendor = 0x14f1, 859 .subdevice = 0x8651, 860 .card = CX23885_BOARD_MYGICA_X8506, 861 }, { 862 .subvendor = 0x14f1, 863 .subdevice = 0x8657, 864 .card = CX23885_BOARD_MAGICPRO_PROHDTVE2, 865 }, { 866 .subvendor = 0x0070, 867 .subdevice = 0x8541, 868 .card = CX23885_BOARD_HAUPPAUGE_HVR1850, 869 }, { 870 .subvendor = 0x1858, 871 .subdevice = 0xe800, 872 .card = CX23885_BOARD_COMPRO_VIDEOMATE_E800, 873 }, { 874 .subvendor = 0x0070, 875 .subdevice = 0x8551, 876 .card = CX23885_BOARD_HAUPPAUGE_HVR1290, 877 }, { 878 .subvendor = 0x14f1, 879 .subdevice = 0x8578, 880 .card = CX23885_BOARD_MYGICA_X8558PRO, 881 }, { 882 .subvendor = 0x107d, 883 .subdevice = 0x6f22, 884 .card = CX23885_BOARD_LEADTEK_WINFAST_PXTV1200, 885 }, { 886 .subvendor = 0x5654, 887 .subdevice = 0x2390, 888 .card = CX23885_BOARD_GOTVIEW_X5_3D_HYBRID, 889 }, { 890 .subvendor = 0x1b55, 891 .subdevice = 0xe2e4, 892 .card = CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF, 893 }, { 894 .subvendor = 0x14f1, 895 .subdevice = 0x8502, 896 .card = CX23885_BOARD_MYGICA_X8507, 897 }, { 898 .subvendor = 0x153b, 899 .subdevice = 0x117e, 900 .card = CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL, 901 }, { 902 .subvendor = 0xd471, 903 .subdevice = 0x9022, 904 .card = CX23885_BOARD_TEVII_S471, 905 }, { 906 .subvendor = 0x8000, 907 .subdevice = 0x3034, 908 .card = CX23885_BOARD_PROF_8000, 909 }, { 910 .subvendor = 0x0070, 911 .subdevice = 0xc108, 912 .card = CX23885_BOARD_HAUPPAUGE_HVR4400, 913 }, { 914 .subvendor = 0x0070, 915 .subdevice = 0xc138, 916 .card = CX23885_BOARD_HAUPPAUGE_HVR4400, 917 }, { 918 .subvendor = 0x0070, 919 .subdevice = 0xc12a, 920 .card = CX23885_BOARD_HAUPPAUGE_HVR4400, 921 }, { 922 .subvendor = 0x0070, 923 .subdevice = 0xc1f8, 924 .card = CX23885_BOARD_HAUPPAUGE_HVR4400, 925 }, { 926 .subvendor = 0x1461, 927 .subdevice = 0xd939, 928 .card = CX23885_BOARD_AVERMEDIA_HC81R, 929 }, { 930 .subvendor = 0x0070, 931 .subdevice = 0x7133, 932 .card = CX23885_BOARD_HAUPPAUGE_IMPACTVCBE, 933 }, { 934 .subvendor = 0x18ac, 935 .subdevice = 0xdb98, 936 .card = CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2, 937 }, 938 }; 939 const unsigned int cx23885_idcount = ARRAY_SIZE(cx23885_subids); 940 941 void cx23885_card_list(struct cx23885_dev *dev) 942 { 943 int i; 944 945 if (0 == dev->pci->subsystem_vendor && 946 0 == dev->pci->subsystem_device) { 947 printk(KERN_INFO 948 "%s: Board has no valid PCIe Subsystem ID and can't\n" 949 "%s: be autodetected. Pass card=<n> insmod option\n" 950 "%s: to workaround that. Redirect complaints to the\n" 951 "%s: vendor of the TV card. Best regards,\n" 952 "%s: -- tux\n", 953 dev->name, dev->name, dev->name, dev->name, dev->name); 954 } else { 955 printk(KERN_INFO 956 "%s: Your board isn't known (yet) to the driver.\n" 957 "%s: Try to pick one of the existing card configs via\n" 958 "%s: card=<n> insmod option. Updating to the latest\n" 959 "%s: version might help as well.\n", 960 dev->name, dev->name, dev->name, dev->name); 961 } 962 printk(KERN_INFO "%s: Here is a list of valid choices for the card=<n> insmod option:\n", 963 dev->name); 964 for (i = 0; i < cx23885_bcount; i++) 965 printk(KERN_INFO "%s: card=%d -> %s\n", 966 dev->name, i, cx23885_boards[i].name); 967 } 968 969 static void hauppauge_eeprom(struct cx23885_dev *dev, u8 *eeprom_data) 970 { 971 struct tveeprom tv; 972 973 tveeprom_hauppauge_analog(&dev->i2c_bus[0].i2c_client, &tv, 974 eeprom_data); 975 976 /* Make sure we support the board model */ 977 switch (tv.model) { 978 case 22001: 979 /* WinTV-HVR1270 (PCIe, Retail, half height) 980 * ATSC/QAM and basic analog, IR Blast */ 981 case 22009: 982 /* WinTV-HVR1210 (PCIe, Retail, half height) 983 * DVB-T and basic analog, IR Blast */ 984 case 22011: 985 /* WinTV-HVR1270 (PCIe, Retail, half height) 986 * ATSC/QAM and basic analog, IR Recv */ 987 case 22019: 988 /* WinTV-HVR1210 (PCIe, Retail, half height) 989 * DVB-T and basic analog, IR Recv */ 990 case 22021: 991 /* WinTV-HVR1275 (PCIe, Retail, half height) 992 * ATSC/QAM and basic analog, IR Recv */ 993 case 22029: 994 /* WinTV-HVR1210 (PCIe, Retail, half height) 995 * DVB-T and basic analog, IR Recv */ 996 case 22101: 997 /* WinTV-HVR1270 (PCIe, Retail, full height) 998 * ATSC/QAM and basic analog, IR Blast */ 999 case 22109: 1000 /* WinTV-HVR1210 (PCIe, Retail, full height) 1001 * DVB-T and basic analog, IR Blast */ 1002 case 22111: 1003 /* WinTV-HVR1270 (PCIe, Retail, full height) 1004 * ATSC/QAM and basic analog, IR Recv */ 1005 case 22119: 1006 /* WinTV-HVR1210 (PCIe, Retail, full height) 1007 * DVB-T and basic analog, IR Recv */ 1008 case 22121: 1009 /* WinTV-HVR1275 (PCIe, Retail, full height) 1010 * ATSC/QAM and basic analog, IR Recv */ 1011 case 22129: 1012 /* WinTV-HVR1210 (PCIe, Retail, full height) 1013 * DVB-T and basic analog, IR Recv */ 1014 case 71009: 1015 /* WinTV-HVR1200 (PCIe, Retail, full height) 1016 * DVB-T and basic analog */ 1017 case 71100: 1018 /* WinTV-ImpactVCB-e (PCIe, Retail, half height) 1019 * Basic analog */ 1020 case 71359: 1021 /* WinTV-HVR1200 (PCIe, OEM, half height) 1022 * DVB-T and basic analog */ 1023 case 71439: 1024 /* WinTV-HVR1200 (PCIe, OEM, half height) 1025 * DVB-T and basic analog */ 1026 case 71449: 1027 /* WinTV-HVR1200 (PCIe, OEM, full height) 1028 * DVB-T and basic analog */ 1029 case 71939: 1030 /* WinTV-HVR1200 (PCIe, OEM, half height) 1031 * DVB-T and basic analog */ 1032 case 71949: 1033 /* WinTV-HVR1200 (PCIe, OEM, full height) 1034 * DVB-T and basic analog */ 1035 case 71959: 1036 /* WinTV-HVR1200 (PCIe, OEM, full height) 1037 * DVB-T and basic analog */ 1038 case 71979: 1039 /* WinTV-HVR1200 (PCIe, OEM, half height) 1040 * DVB-T and basic analog */ 1041 case 71999: 1042 /* WinTV-HVR1200 (PCIe, OEM, full height) 1043 * DVB-T and basic analog */ 1044 case 76601: 1045 /* WinTV-HVR1800lp (PCIe, Retail, No IR, Dual 1046 channel ATSC and MPEG2 HW Encoder */ 1047 case 77001: 1048 /* WinTV-HVR1500 (Express Card, OEM, No IR, ATSC 1049 and Basic analog */ 1050 case 77011: 1051 /* WinTV-HVR1500 (Express Card, Retail, No IR, ATSC 1052 and Basic analog */ 1053 case 77041: 1054 /* WinTV-HVR1500Q (Express Card, OEM, No IR, ATSC/QAM 1055 and Basic analog */ 1056 case 77051: 1057 /* WinTV-HVR1500Q (Express Card, Retail, No IR, ATSC/QAM 1058 and Basic analog */ 1059 case 78011: 1060 /* WinTV-HVR1800 (PCIe, Retail, 3.5mm in, IR, No FM, 1061 Dual channel ATSC and MPEG2 HW Encoder */ 1062 case 78501: 1063 /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM, 1064 Dual channel ATSC and MPEG2 HW Encoder */ 1065 case 78521: 1066 /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM, 1067 Dual channel ATSC and MPEG2 HW Encoder */ 1068 case 78531: 1069 /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, No FM, 1070 Dual channel ATSC and MPEG2 HW Encoder */ 1071 case 78631: 1072 /* WinTV-HVR1800 (PCIe, OEM, No IR, No FM, 1073 Dual channel ATSC and MPEG2 HW Encoder */ 1074 case 79001: 1075 /* WinTV-HVR1250 (PCIe, Retail, IR, full height, 1076 ATSC and Basic analog */ 1077 case 79101: 1078 /* WinTV-HVR1250 (PCIe, Retail, IR, half height, 1079 ATSC and Basic analog */ 1080 case 79501: 1081 /* WinTV-HVR1250 (PCIe, No IR, half height, 1082 ATSC [at least] and Basic analog) */ 1083 case 79561: 1084 /* WinTV-HVR1250 (PCIe, OEM, No IR, half height, 1085 ATSC and Basic analog */ 1086 case 79571: 1087 /* WinTV-HVR1250 (PCIe, OEM, No IR, full height, 1088 ATSC and Basic analog */ 1089 case 79671: 1090 /* WinTV-HVR1250 (PCIe, OEM, No IR, half height, 1091 ATSC and Basic analog */ 1092 case 80019: 1093 /* WinTV-HVR1400 (Express Card, Retail, IR, 1094 * DVB-T and Basic analog */ 1095 case 81509: 1096 /* WinTV-HVR1700 (PCIe, OEM, No IR, half height) 1097 * DVB-T and MPEG2 HW Encoder */ 1098 case 81519: 1099 /* WinTV-HVR1700 (PCIe, OEM, No IR, full height) 1100 * DVB-T and MPEG2 HW Encoder */ 1101 break; 1102 case 85021: 1103 /* WinTV-HVR1850 (PCIe, Retail, 3.5mm in, IR, FM, 1104 Dual channel ATSC and MPEG2 HW Encoder */ 1105 break; 1106 case 85721: 1107 /* WinTV-HVR1290 (PCIe, OEM, RCA in, IR, 1108 Dual channel ATSC and Basic analog */ 1109 break; 1110 default: 1111 printk(KERN_WARNING "%s: warning: " 1112 "unknown hauppauge model #%d\n", 1113 dev->name, tv.model); 1114 break; 1115 } 1116 1117 printk(KERN_INFO "%s: hauppauge eeprom: model=%d\n", 1118 dev->name, tv.model); 1119 } 1120 1121 /* Some TBS cards require initing a chip using a bitbanged SPI attached 1122 to the cx23885 gpio's. If this chip doesn't get init'ed the demod 1123 doesn't respond to any command. */ 1124 static void tbs_card_init(struct cx23885_dev *dev) 1125 { 1126 int i; 1127 const u8 buf[] = { 1128 0xe0, 0x06, 0x66, 0x33, 0x65, 1129 0x01, 0x17, 0x06, 0xde}; 1130 1131 switch (dev->board) { 1132 case CX23885_BOARD_TBS_6980: 1133 case CX23885_BOARD_TBS_6981: 1134 cx_set(GP0_IO, 0x00070007); 1135 usleep_range(1000, 10000); 1136 cx_clear(GP0_IO, 2); 1137 usleep_range(1000, 10000); 1138 for (i = 0; i < 9 * 8; i++) { 1139 cx_clear(GP0_IO, 7); 1140 usleep_range(1000, 10000); 1141 cx_set(GP0_IO, 1142 ((buf[i >> 3] >> (7 - (i & 7))) & 1) | 4); 1143 usleep_range(1000, 10000); 1144 } 1145 cx_set(GP0_IO, 7); 1146 break; 1147 } 1148 } 1149 1150 int cx23885_tuner_callback(void *priv, int component, int command, int arg) 1151 { 1152 struct cx23885_tsport *port = priv; 1153 struct cx23885_dev *dev = port->dev; 1154 u32 bitmask = 0; 1155 1156 if ((command == XC2028_RESET_CLK) || (command == XC2028_I2C_FLUSH)) 1157 return 0; 1158 1159 if (command != 0) { 1160 printk(KERN_ERR "%s(): Unknown command 0x%x.\n", 1161 __func__, command); 1162 return -EINVAL; 1163 } 1164 1165 switch (dev->board) { 1166 case CX23885_BOARD_HAUPPAUGE_HVR1400: 1167 case CX23885_BOARD_HAUPPAUGE_HVR1500: 1168 case CX23885_BOARD_HAUPPAUGE_HVR1500Q: 1169 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H: 1170 case CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200: 1171 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000: 1172 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F: 1173 case CX23885_BOARD_COMPRO_VIDEOMATE_E800: 1174 case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200: 1175 /* Tuner Reset Command */ 1176 bitmask = 0x04; 1177 break; 1178 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP: 1179 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: 1180 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2: 1181 /* Two identical tuners on two different i2c buses, 1182 * we need to reset the correct gpio. */ 1183 if (port->nr == 1) 1184 bitmask = 0x01; 1185 else if (port->nr == 2) 1186 bitmask = 0x04; 1187 break; 1188 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID: 1189 /* Tuner Reset Command */ 1190 bitmask = 0x02; 1191 break; 1192 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: 1193 altera_ci_tuner_reset(dev, port->nr); 1194 break; 1195 case CX23885_BOARD_AVERMEDIA_HC81R: 1196 /* XC3028L Reset Command */ 1197 bitmask = 1 << 2; 1198 break; 1199 } 1200 1201 if (bitmask) { 1202 /* Drive the tuner into reset and back out */ 1203 cx_clear(GP0_IO, bitmask); 1204 mdelay(200); 1205 cx_set(GP0_IO, bitmask); 1206 } 1207 1208 return 0; 1209 } 1210 1211 void cx23885_gpio_setup(struct cx23885_dev *dev) 1212 { 1213 switch (dev->board) { 1214 case CX23885_BOARD_HAUPPAUGE_HVR1250: 1215 /* GPIO-0 cx24227 demodulator reset */ 1216 cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */ 1217 break; 1218 case CX23885_BOARD_HAUPPAUGE_HVR1500: 1219 /* GPIO-0 cx24227 demodulator */ 1220 /* GPIO-2 xc3028 tuner */ 1221 1222 /* Put the parts into reset */ 1223 cx_set(GP0_IO, 0x00050000); 1224 cx_clear(GP0_IO, 0x00000005); 1225 msleep(5); 1226 1227 /* Bring the parts out of reset */ 1228 cx_set(GP0_IO, 0x00050005); 1229 break; 1230 case CX23885_BOARD_HAUPPAUGE_HVR1500Q: 1231 /* GPIO-0 cx24227 demodulator reset */ 1232 /* GPIO-2 xc5000 tuner reset */ 1233 cx_set(GP0_IO, 0x00050005); /* Bring the part out of reset */ 1234 break; 1235 case CX23885_BOARD_HAUPPAUGE_HVR1800: 1236 /* GPIO-0 656_CLK */ 1237 /* GPIO-1 656_D0 */ 1238 /* GPIO-2 8295A Reset */ 1239 /* GPIO-3-10 cx23417 data0-7 */ 1240 /* GPIO-11-14 cx23417 addr0-3 */ 1241 /* GPIO-15-18 cx23417 READY, CS, RD, WR */ 1242 /* GPIO-19 IR_RX */ 1243 1244 /* CX23417 GPIO's */ 1245 /* EIO15 Zilog Reset */ 1246 /* EIO14 S5H1409/CX24227 Reset */ 1247 mc417_gpio_enable(dev, GPIO_15 | GPIO_14, 1); 1248 1249 /* Put the demod into reset and protect the eeprom */ 1250 mc417_gpio_clear(dev, GPIO_15 | GPIO_14); 1251 mdelay(100); 1252 1253 /* Bring the demod and blaster out of reset */ 1254 mc417_gpio_set(dev, GPIO_15 | GPIO_14); 1255 mdelay(100); 1256 1257 /* Force the TDA8295A into reset and back */ 1258 cx23885_gpio_enable(dev, GPIO_2, 1); 1259 cx23885_gpio_set(dev, GPIO_2); 1260 mdelay(20); 1261 cx23885_gpio_clear(dev, GPIO_2); 1262 mdelay(20); 1263 cx23885_gpio_set(dev, GPIO_2); 1264 mdelay(20); 1265 break; 1266 case CX23885_BOARD_HAUPPAUGE_HVR1200: 1267 /* GPIO-0 tda10048 demodulator reset */ 1268 /* GPIO-2 tda18271 tuner reset */ 1269 1270 /* Put the parts into reset and back */ 1271 cx_set(GP0_IO, 0x00050000); 1272 mdelay(20); 1273 cx_clear(GP0_IO, 0x00000005); 1274 mdelay(20); 1275 cx_set(GP0_IO, 0x00050005); 1276 break; 1277 case CX23885_BOARD_HAUPPAUGE_HVR1700: 1278 /* GPIO-0 TDA10048 demodulator reset */ 1279 /* GPIO-2 TDA8295A Reset */ 1280 /* GPIO-3-10 cx23417 data0-7 */ 1281 /* GPIO-11-14 cx23417 addr0-3 */ 1282 /* GPIO-15-18 cx23417 READY, CS, RD, WR */ 1283 1284 /* The following GPIO's are on the interna AVCore (cx25840) */ 1285 /* GPIO-19 IR_RX */ 1286 /* GPIO-20 IR_TX 416/DVBT Select */ 1287 /* GPIO-21 IIS DAT */ 1288 /* GPIO-22 IIS WCLK */ 1289 /* GPIO-23 IIS BCLK */ 1290 1291 /* Put the parts into reset and back */ 1292 cx_set(GP0_IO, 0x00050000); 1293 mdelay(20); 1294 cx_clear(GP0_IO, 0x00000005); 1295 mdelay(20); 1296 cx_set(GP0_IO, 0x00050005); 1297 break; 1298 case CX23885_BOARD_HAUPPAUGE_HVR1400: 1299 /* GPIO-0 Dibcom7000p demodulator reset */ 1300 /* GPIO-2 xc3028L tuner reset */ 1301 /* GPIO-13 LED */ 1302 1303 /* Put the parts into reset and back */ 1304 cx_set(GP0_IO, 0x00050000); 1305 mdelay(20); 1306 cx_clear(GP0_IO, 0x00000005); 1307 mdelay(20); 1308 cx_set(GP0_IO, 0x00050005); 1309 break; 1310 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP: 1311 /* GPIO-0 xc5000 tuner reset i2c bus 0 */ 1312 /* GPIO-1 s5h1409 demod reset i2c bus 0 */ 1313 /* GPIO-2 xc5000 tuner reset i2c bus 1 */ 1314 /* GPIO-3 s5h1409 demod reset i2c bus 0 */ 1315 1316 /* Put the parts into reset and back */ 1317 cx_set(GP0_IO, 0x000f0000); 1318 mdelay(20); 1319 cx_clear(GP0_IO, 0x0000000f); 1320 mdelay(20); 1321 cx_set(GP0_IO, 0x000f000f); 1322 break; 1323 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: 1324 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2: 1325 /* GPIO-0 portb xc3028 reset */ 1326 /* GPIO-1 portb zl10353 reset */ 1327 /* GPIO-2 portc xc3028 reset */ 1328 /* GPIO-3 portc zl10353 reset */ 1329 1330 /* Put the parts into reset and back */ 1331 cx_set(GP0_IO, 0x000f0000); 1332 mdelay(20); 1333 cx_clear(GP0_IO, 0x0000000f); 1334 mdelay(20); 1335 cx_set(GP0_IO, 0x000f000f); 1336 break; 1337 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H: 1338 case CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200: 1339 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000: 1340 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F: 1341 case CX23885_BOARD_COMPRO_VIDEOMATE_E800: 1342 case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200: 1343 /* GPIO-2 xc3028 tuner reset */ 1344 1345 /* The following GPIO's are on the internal AVCore (cx25840) */ 1346 /* GPIO-? zl10353 demod reset */ 1347 1348 /* Put the parts into reset and back */ 1349 cx_set(GP0_IO, 0x00040000); 1350 mdelay(20); 1351 cx_clear(GP0_IO, 0x00000004); 1352 mdelay(20); 1353 cx_set(GP0_IO, 0x00040004); 1354 break; 1355 case CX23885_BOARD_TBS_6920: 1356 case CX23885_BOARD_TBS_6980: 1357 case CX23885_BOARD_TBS_6981: 1358 case CX23885_BOARD_PROF_8000: 1359 cx_write(MC417_CTL, 0x00000036); 1360 cx_write(MC417_OEN, 0x00001000); 1361 cx_set(MC417_RWD, 0x00000002); 1362 mdelay(200); 1363 cx_clear(MC417_RWD, 0x00000800); 1364 mdelay(200); 1365 cx_set(MC417_RWD, 0x00000800); 1366 mdelay(200); 1367 break; 1368 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: 1369 /* GPIO-0 INTA from CiMax1 1370 GPIO-1 INTB from CiMax2 1371 GPIO-2 reset chips 1372 GPIO-3 to GPIO-10 data/addr for CA 1373 GPIO-11 ~CS0 to CiMax1 1374 GPIO-12 ~CS1 to CiMax2 1375 GPIO-13 ADL0 load LSB addr 1376 GPIO-14 ADL1 load MSB addr 1377 GPIO-15 ~RDY from CiMax 1378 GPIO-17 ~RD to CiMax 1379 GPIO-18 ~WR to CiMax 1380 */ 1381 cx_set(GP0_IO, 0x00040000); /* GPIO as out */ 1382 /* GPIO1 and GPIO2 as INTA and INTB from CiMaxes, reset low */ 1383 cx_clear(GP0_IO, 0x00030004); 1384 mdelay(100);/* reset delay */ 1385 cx_set(GP0_IO, 0x00040004); /* GPIO as out, reset high */ 1386 cx_write(MC417_CTL, 0x00000037);/* enable GPIO3-18 pins */ 1387 /* GPIO-15 IN as ~ACK, rest as OUT */ 1388 cx_write(MC417_OEN, 0x00001000); 1389 /* ~RD, ~WR high; ADL0, ADL1 low; ~CS0, ~CS1 high */ 1390 cx_write(MC417_RWD, 0x0000c300); 1391 /* enable irq */ 1392 cx_write(GPIO_ISM, 0x00000000);/* INTERRUPTS active low*/ 1393 break; 1394 case CX23885_BOARD_HAUPPAUGE_HVR1270: 1395 case CX23885_BOARD_HAUPPAUGE_HVR1275: 1396 case CX23885_BOARD_HAUPPAUGE_HVR1255: 1397 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111: 1398 case CX23885_BOARD_HAUPPAUGE_HVR1210: 1399 /* GPIO-5 RF Control: 0 = RF1 Terrestrial, 1 = RF2 Cable */ 1400 /* GPIO-6 I2C Gate which can isolate the demod from the bus */ 1401 /* GPIO-9 Demod reset */ 1402 1403 /* Put the parts into reset and back */ 1404 cx23885_gpio_enable(dev, GPIO_9 | GPIO_6 | GPIO_5, 1); 1405 cx23885_gpio_set(dev, GPIO_9 | GPIO_6 | GPIO_5); 1406 cx23885_gpio_clear(dev, GPIO_9); 1407 mdelay(20); 1408 cx23885_gpio_set(dev, GPIO_9); 1409 break; 1410 case CX23885_BOARD_MYGICA_X8506: 1411 case CX23885_BOARD_MAGICPRO_PROHDTVE2: 1412 case CX23885_BOARD_MYGICA_X8507: 1413 /* GPIO-0 (0)Analog / (1)Digital TV */ 1414 /* GPIO-1 reset XC5000 */ 1415 /* GPIO-2 demod reset */ 1416 cx23885_gpio_enable(dev, GPIO_0 | GPIO_1 | GPIO_2, 1); 1417 cx23885_gpio_clear(dev, GPIO_1 | GPIO_2); 1418 mdelay(100); 1419 cx23885_gpio_set(dev, GPIO_0 | GPIO_1 | GPIO_2); 1420 mdelay(100); 1421 break; 1422 case CX23885_BOARD_MYGICA_X8558PRO: 1423 /* GPIO-0 reset first ATBM8830 */ 1424 /* GPIO-1 reset second ATBM8830 */ 1425 cx23885_gpio_enable(dev, GPIO_0 | GPIO_1, 1); 1426 cx23885_gpio_clear(dev, GPIO_0 | GPIO_1); 1427 mdelay(100); 1428 cx23885_gpio_set(dev, GPIO_0 | GPIO_1); 1429 mdelay(100); 1430 break; 1431 case CX23885_BOARD_HAUPPAUGE_HVR1850: 1432 case CX23885_BOARD_HAUPPAUGE_HVR1290: 1433 /* GPIO-0 656_CLK */ 1434 /* GPIO-1 656_D0 */ 1435 /* GPIO-2 Wake# */ 1436 /* GPIO-3-10 cx23417 data0-7 */ 1437 /* GPIO-11-14 cx23417 addr0-3 */ 1438 /* GPIO-15-18 cx23417 READY, CS, RD, WR */ 1439 /* GPIO-19 IR_RX */ 1440 /* GPIO-20 C_IR_TX */ 1441 /* GPIO-21 I2S DAT */ 1442 /* GPIO-22 I2S WCLK */ 1443 /* GPIO-23 I2S BCLK */ 1444 /* ALT GPIO: EXP GPIO LATCH */ 1445 1446 /* CX23417 GPIO's */ 1447 /* GPIO-14 S5H1411/CX24228 Reset */ 1448 /* GPIO-13 EEPROM write protect */ 1449 mc417_gpio_enable(dev, GPIO_14 | GPIO_13, 1); 1450 1451 /* Put the demod into reset and protect the eeprom */ 1452 mc417_gpio_clear(dev, GPIO_14 | GPIO_13); 1453 mdelay(100); 1454 1455 /* Bring the demod out of reset */ 1456 mc417_gpio_set(dev, GPIO_14); 1457 mdelay(100); 1458 1459 /* CX24228 GPIO */ 1460 /* Connected to IF / Mux */ 1461 break; 1462 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID: 1463 cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */ 1464 break; 1465 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: 1466 /* GPIO-0 ~INT in 1467 GPIO-1 TMS out 1468 GPIO-2 ~reset chips out 1469 GPIO-3 to GPIO-10 data/addr for CA in/out 1470 GPIO-11 ~CS out 1471 GPIO-12 ADDR out 1472 GPIO-13 ~WR out 1473 GPIO-14 ~RD out 1474 GPIO-15 ~RDY in 1475 GPIO-16 TCK out 1476 GPIO-17 TDO in 1477 GPIO-18 TDI out 1478 */ 1479 cx_set(GP0_IO, 0x00060000); /* GPIO-1,2 as out */ 1480 /* GPIO-0 as INT, reset & TMS low */ 1481 cx_clear(GP0_IO, 0x00010006); 1482 mdelay(100);/* reset delay */ 1483 cx_set(GP0_IO, 0x00000004); /* reset high */ 1484 cx_write(MC417_CTL, 0x00000037);/* enable GPIO-3..18 pins */ 1485 /* GPIO-17 is TDO in, GPIO-15 is ~RDY in, rest is out */ 1486 cx_write(MC417_OEN, 0x00005000); 1487 /* ~RD, ~WR high; ADDR low; ~CS high */ 1488 cx_write(MC417_RWD, 0x00000d00); 1489 /* enable irq */ 1490 cx_write(GPIO_ISM, 0x00000000);/* INTERRUPTS active low*/ 1491 break; 1492 case CX23885_BOARD_HAUPPAUGE_HVR4400: 1493 /* GPIO-8 tda10071 demod reset */ 1494 /* GPIO-9 si2165 demod reset */ 1495 1496 /* Put the parts into reset and back */ 1497 cx23885_gpio_enable(dev, GPIO_8 | GPIO_9, 1); 1498 1499 cx23885_gpio_clear(dev, GPIO_8 | GPIO_9); 1500 mdelay(100); 1501 cx23885_gpio_set(dev, GPIO_8 | GPIO_9); 1502 mdelay(100); 1503 1504 break; 1505 case CX23885_BOARD_AVERMEDIA_HC81R: 1506 cx_clear(MC417_CTL, 1); 1507 /* GPIO-0,1,2 setup direction as output */ 1508 cx_set(GP0_IO, 0x00070000); 1509 mdelay(10); 1510 /* AF9013 demod reset */ 1511 cx_set(GP0_IO, 0x00010001); 1512 mdelay(10); 1513 cx_clear(GP0_IO, 0x00010001); 1514 mdelay(10); 1515 cx_set(GP0_IO, 0x00010001); 1516 mdelay(10); 1517 /* demod tune? */ 1518 cx_clear(GP0_IO, 0x00030003); 1519 mdelay(10); 1520 cx_set(GP0_IO, 0x00020002); 1521 mdelay(10); 1522 cx_set(GP0_IO, 0x00010001); 1523 mdelay(10); 1524 cx_clear(GP0_IO, 0x00020002); 1525 /* XC3028L tuner reset */ 1526 cx_set(GP0_IO, 0x00040004); 1527 cx_clear(GP0_IO, 0x00040004); 1528 cx_set(GP0_IO, 0x00040004); 1529 mdelay(60); 1530 break; 1531 } 1532 } 1533 1534 int cx23885_ir_init(struct cx23885_dev *dev) 1535 { 1536 static struct v4l2_subdev_io_pin_config ir_rxtx_pin_cfg[] = { 1537 { 1538 .flags = V4L2_SUBDEV_IO_PIN_INPUT, 1539 .pin = CX23885_PIN_IR_RX_GPIO19, 1540 .function = CX23885_PAD_IR_RX, 1541 .value = 0, 1542 .strength = CX25840_PIN_DRIVE_MEDIUM, 1543 }, { 1544 .flags = V4L2_SUBDEV_IO_PIN_OUTPUT, 1545 .pin = CX23885_PIN_IR_TX_GPIO20, 1546 .function = CX23885_PAD_IR_TX, 1547 .value = 0, 1548 .strength = CX25840_PIN_DRIVE_MEDIUM, 1549 } 1550 }; 1551 const size_t ir_rxtx_pin_cfg_count = ARRAY_SIZE(ir_rxtx_pin_cfg); 1552 1553 static struct v4l2_subdev_io_pin_config ir_rx_pin_cfg[] = { 1554 { 1555 .flags = V4L2_SUBDEV_IO_PIN_INPUT, 1556 .pin = CX23885_PIN_IR_RX_GPIO19, 1557 .function = CX23885_PAD_IR_RX, 1558 .value = 0, 1559 .strength = CX25840_PIN_DRIVE_MEDIUM, 1560 } 1561 }; 1562 const size_t ir_rx_pin_cfg_count = ARRAY_SIZE(ir_rx_pin_cfg); 1563 1564 struct v4l2_subdev_ir_parameters params; 1565 int ret = 0; 1566 switch (dev->board) { 1567 case CX23885_BOARD_HAUPPAUGE_HVR1500: 1568 case CX23885_BOARD_HAUPPAUGE_HVR1500Q: 1569 case CX23885_BOARD_HAUPPAUGE_HVR1800: 1570 case CX23885_BOARD_HAUPPAUGE_HVR1200: 1571 case CX23885_BOARD_HAUPPAUGE_HVR1400: 1572 case CX23885_BOARD_HAUPPAUGE_HVR1275: 1573 case CX23885_BOARD_HAUPPAUGE_HVR1255: 1574 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111: 1575 case CX23885_BOARD_HAUPPAUGE_HVR1210: 1576 /* FIXME: Implement me */ 1577 break; 1578 case CX23885_BOARD_HAUPPAUGE_HVR1270: 1579 ret = cx23888_ir_probe(dev); 1580 if (ret) 1581 break; 1582 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_888_IR); 1583 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config, 1584 ir_rx_pin_cfg_count, ir_rx_pin_cfg); 1585 break; 1586 case CX23885_BOARD_HAUPPAUGE_HVR1850: 1587 case CX23885_BOARD_HAUPPAUGE_HVR1290: 1588 ret = cx23888_ir_probe(dev); 1589 if (ret) 1590 break; 1591 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_888_IR); 1592 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config, 1593 ir_rxtx_pin_cfg_count, ir_rxtx_pin_cfg); 1594 /* 1595 * For these boards we need to invert the Tx output via the 1596 * IR controller to have the LED off while idle 1597 */ 1598 v4l2_subdev_call(dev->sd_ir, ir, tx_g_parameters, ¶ms); 1599 params.enable = false; 1600 params.shutdown = false; 1601 params.invert_level = true; 1602 v4l2_subdev_call(dev->sd_ir, ir, tx_s_parameters, ¶ms); 1603 params.shutdown = true; 1604 v4l2_subdev_call(dev->sd_ir, ir, tx_s_parameters, ¶ms); 1605 break; 1606 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL: 1607 case CX23885_BOARD_TEVII_S470: 1608 case CX23885_BOARD_MYGICA_X8507: 1609 case CX23885_BOARD_TBS_6980: 1610 case CX23885_BOARD_TBS_6981: 1611 if (!enable_885_ir) 1612 break; 1613 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_AV_CORE); 1614 if (dev->sd_ir == NULL) { 1615 ret = -ENODEV; 1616 break; 1617 } 1618 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config, 1619 ir_rx_pin_cfg_count, ir_rx_pin_cfg); 1620 break; 1621 case CX23885_BOARD_HAUPPAUGE_HVR1250: 1622 if (!enable_885_ir) 1623 break; 1624 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_AV_CORE); 1625 if (dev->sd_ir == NULL) { 1626 ret = -ENODEV; 1627 break; 1628 } 1629 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config, 1630 ir_rxtx_pin_cfg_count, ir_rxtx_pin_cfg); 1631 break; 1632 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: 1633 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2: 1634 request_module("ir-kbd-i2c"); 1635 break; 1636 } 1637 1638 return ret; 1639 } 1640 1641 void cx23885_ir_fini(struct cx23885_dev *dev) 1642 { 1643 switch (dev->board) { 1644 case CX23885_BOARD_HAUPPAUGE_HVR1270: 1645 case CX23885_BOARD_HAUPPAUGE_HVR1850: 1646 case CX23885_BOARD_HAUPPAUGE_HVR1290: 1647 cx23885_irq_remove(dev, PCI_MSK_IR); 1648 cx23888_ir_remove(dev); 1649 dev->sd_ir = NULL; 1650 break; 1651 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL: 1652 case CX23885_BOARD_TEVII_S470: 1653 case CX23885_BOARD_HAUPPAUGE_HVR1250: 1654 case CX23885_BOARD_MYGICA_X8507: 1655 case CX23885_BOARD_TBS_6980: 1656 case CX23885_BOARD_TBS_6981: 1657 cx23885_irq_remove(dev, PCI_MSK_AV_CORE); 1658 /* sd_ir is a duplicate pointer to the AV Core, just clear it */ 1659 dev->sd_ir = NULL; 1660 break; 1661 } 1662 } 1663 1664 static int netup_jtag_io(void *device, int tms, int tdi, int read_tdo) 1665 { 1666 int data; 1667 int tdo = 0; 1668 struct cx23885_dev *dev = (struct cx23885_dev *)device; 1669 /*TMS*/ 1670 data = ((cx_read(GP0_IO)) & (~0x00000002)); 1671 data |= (tms ? 0x00020002 : 0x00020000); 1672 cx_write(GP0_IO, data); 1673 1674 /*TDI*/ 1675 data = ((cx_read(MC417_RWD)) & (~0x0000a000)); 1676 data |= (tdi ? 0x00008000 : 0); 1677 cx_write(MC417_RWD, data); 1678 if (read_tdo) 1679 tdo = (data & 0x00004000) ? 1 : 0; /*TDO*/ 1680 1681 cx_write(MC417_RWD, data | 0x00002000); 1682 udelay(1); 1683 /*TCK*/ 1684 cx_write(MC417_RWD, data); 1685 1686 return tdo; 1687 } 1688 1689 void cx23885_ir_pci_int_enable(struct cx23885_dev *dev) 1690 { 1691 switch (dev->board) { 1692 case CX23885_BOARD_HAUPPAUGE_HVR1270: 1693 case CX23885_BOARD_HAUPPAUGE_HVR1850: 1694 case CX23885_BOARD_HAUPPAUGE_HVR1290: 1695 if (dev->sd_ir) 1696 cx23885_irq_add_enable(dev, PCI_MSK_IR); 1697 break; 1698 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL: 1699 case CX23885_BOARD_TEVII_S470: 1700 case CX23885_BOARD_HAUPPAUGE_HVR1250: 1701 case CX23885_BOARD_MYGICA_X8507: 1702 case CX23885_BOARD_TBS_6980: 1703 case CX23885_BOARD_TBS_6981: 1704 if (dev->sd_ir) 1705 cx23885_irq_add_enable(dev, PCI_MSK_AV_CORE); 1706 break; 1707 } 1708 } 1709 1710 void cx23885_card_setup(struct cx23885_dev *dev) 1711 { 1712 struct cx23885_tsport *ts1 = &dev->ts1; 1713 struct cx23885_tsport *ts2 = &dev->ts2; 1714 1715 static u8 eeprom[256]; 1716 1717 if (dev->i2c_bus[0].i2c_rc == 0) { 1718 dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1; 1719 tveeprom_read(&dev->i2c_bus[0].i2c_client, 1720 eeprom, sizeof(eeprom)); 1721 } 1722 1723 switch (dev->board) { 1724 case CX23885_BOARD_HAUPPAUGE_HVR1250: 1725 if (dev->i2c_bus[0].i2c_rc == 0) { 1726 if (eeprom[0x80] != 0x84) 1727 hauppauge_eeprom(dev, eeprom+0xc0); 1728 else 1729 hauppauge_eeprom(dev, eeprom+0x80); 1730 } 1731 break; 1732 case CX23885_BOARD_HAUPPAUGE_HVR1500: 1733 case CX23885_BOARD_HAUPPAUGE_HVR1500Q: 1734 case CX23885_BOARD_HAUPPAUGE_HVR1400: 1735 if (dev->i2c_bus[0].i2c_rc == 0) 1736 hauppauge_eeprom(dev, eeprom+0x80); 1737 break; 1738 case CX23885_BOARD_HAUPPAUGE_HVR1800: 1739 case CX23885_BOARD_HAUPPAUGE_HVR1800lp: 1740 case CX23885_BOARD_HAUPPAUGE_HVR1200: 1741 case CX23885_BOARD_HAUPPAUGE_HVR1700: 1742 case CX23885_BOARD_HAUPPAUGE_HVR1270: 1743 case CX23885_BOARD_HAUPPAUGE_HVR1275: 1744 case CX23885_BOARD_HAUPPAUGE_HVR1255: 1745 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111: 1746 case CX23885_BOARD_HAUPPAUGE_HVR1210: 1747 case CX23885_BOARD_HAUPPAUGE_HVR1850: 1748 case CX23885_BOARD_HAUPPAUGE_HVR1290: 1749 case CX23885_BOARD_HAUPPAUGE_HVR4400: 1750 case CX23885_BOARD_HAUPPAUGE_IMPACTVCBE: 1751 if (dev->i2c_bus[0].i2c_rc == 0) 1752 hauppauge_eeprom(dev, eeprom+0xc0); 1753 break; 1754 } 1755 1756 switch (dev->board) { 1757 case CX23885_BOARD_AVERMEDIA_HC81R: 1758 /* Defaults for VID B */ 1759 ts1->gen_ctrl_val = 0x4; /* Parallel */ 1760 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1761 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1762 /* Defaults for VID C */ 1763 /* DREQ_POL, SMODE, PUNC_CLK, MCLK_POL Serial bus + punc clk */ 1764 ts2->gen_ctrl_val = 0x10e; 1765 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1766 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1767 break; 1768 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP: 1769 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: 1770 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2: 1771 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 1772 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1773 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1774 /* break omitted intentionally */ 1775 case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP: 1776 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 1777 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1778 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1779 break; 1780 case CX23885_BOARD_HAUPPAUGE_HVR1850: 1781 case CX23885_BOARD_HAUPPAUGE_HVR1800: 1782 /* Defaults for VID B - Analog encoder */ 1783 /* DREQ_POL, SMODE, PUNC_CLK, MCLK_POL Serial bus + punc clk */ 1784 ts1->gen_ctrl_val = 0x10e; 1785 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1786 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1787 1788 /* APB_TSVALERR_POL (active low)*/ 1789 ts1->vld_misc_val = 0x2000; 1790 ts1->hw_sop_ctrl_val = (0x47 << 16 | 188 << 4 | 0xc); 1791 cx_write(0x130184, 0xc); 1792 1793 /* Defaults for VID C */ 1794 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 1795 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1796 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1797 break; 1798 case CX23885_BOARD_TBS_6920: 1799 ts1->gen_ctrl_val = 0x4; /* Parallel */ 1800 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1801 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1802 break; 1803 case CX23885_BOARD_TEVII_S470: 1804 case CX23885_BOARD_TEVII_S471: 1805 case CX23885_BOARD_DVBWORLD_2005: 1806 case CX23885_BOARD_PROF_8000: 1807 ts1->gen_ctrl_val = 0x5; /* Parallel */ 1808 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1809 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1810 break; 1811 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: 1812 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: 1813 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL: 1814 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 1815 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1816 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1817 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 1818 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1819 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1820 break; 1821 case CX23885_BOARD_TBS_6980: 1822 case CX23885_BOARD_TBS_6981: 1823 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 1824 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1825 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1826 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 1827 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1828 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1829 tbs_card_init(dev); 1830 break; 1831 case CX23885_BOARD_MYGICA_X8506: 1832 case CX23885_BOARD_MAGICPRO_PROHDTVE2: 1833 case CX23885_BOARD_MYGICA_X8507: 1834 ts1->gen_ctrl_val = 0x5; /* Parallel */ 1835 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1836 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1837 break; 1838 case CX23885_BOARD_MYGICA_X8558PRO: 1839 ts1->gen_ctrl_val = 0x5; /* Parallel */ 1840 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1841 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1842 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 1843 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1844 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1845 break; 1846 case CX23885_BOARD_HAUPPAUGE_HVR4400: 1847 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 1848 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1849 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1850 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 1851 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1852 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1853 break; 1854 case CX23885_BOARD_HAUPPAUGE_HVR1250: 1855 case CX23885_BOARD_HAUPPAUGE_HVR1500: 1856 case CX23885_BOARD_HAUPPAUGE_HVR1500Q: 1857 case CX23885_BOARD_HAUPPAUGE_HVR1800lp: 1858 case CX23885_BOARD_HAUPPAUGE_HVR1200: 1859 case CX23885_BOARD_HAUPPAUGE_HVR1700: 1860 case CX23885_BOARD_HAUPPAUGE_HVR1400: 1861 case CX23885_BOARD_HAUPPAUGE_IMPACTVCBE: 1862 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H: 1863 case CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200: 1864 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000: 1865 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F: 1866 case CX23885_BOARD_HAUPPAUGE_HVR1270: 1867 case CX23885_BOARD_HAUPPAUGE_HVR1275: 1868 case CX23885_BOARD_HAUPPAUGE_HVR1255: 1869 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111: 1870 case CX23885_BOARD_HAUPPAUGE_HVR1210: 1871 case CX23885_BOARD_COMPRO_VIDEOMATE_E800: 1872 case CX23885_BOARD_HAUPPAUGE_HVR1290: 1873 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID: 1874 default: 1875 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 1876 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1877 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1878 } 1879 1880 /* Certain boards support analog, or require the avcore to be 1881 * loaded, ensure this happens. 1882 */ 1883 switch (dev->board) { 1884 case CX23885_BOARD_TEVII_S470: 1885 /* Currently only enabled for the integrated IR controller */ 1886 if (!enable_885_ir) 1887 break; 1888 case CX23885_BOARD_HAUPPAUGE_HVR1250: 1889 case CX23885_BOARD_HAUPPAUGE_HVR1800: 1890 case CX23885_BOARD_HAUPPAUGE_IMPACTVCBE: 1891 case CX23885_BOARD_HAUPPAUGE_HVR1800lp: 1892 case CX23885_BOARD_HAUPPAUGE_HVR1700: 1893 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H: 1894 case CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200: 1895 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000: 1896 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F: 1897 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: 1898 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: 1899 case CX23885_BOARD_COMPRO_VIDEOMATE_E800: 1900 case CX23885_BOARD_HAUPPAUGE_HVR1255: 1901 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111: 1902 case CX23885_BOARD_HAUPPAUGE_HVR1270: 1903 case CX23885_BOARD_HAUPPAUGE_HVR1850: 1904 case CX23885_BOARD_MYGICA_X8506: 1905 case CX23885_BOARD_MAGICPRO_PROHDTVE2: 1906 case CX23885_BOARD_HAUPPAUGE_HVR1290: 1907 case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200: 1908 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID: 1909 case CX23885_BOARD_HAUPPAUGE_HVR1500: 1910 case CX23885_BOARD_MPX885: 1911 case CX23885_BOARD_MYGICA_X8507: 1912 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL: 1913 case CX23885_BOARD_AVERMEDIA_HC81R: 1914 case CX23885_BOARD_TBS_6980: 1915 case CX23885_BOARD_TBS_6981: 1916 dev->sd_cx25840 = v4l2_i2c_new_subdev(&dev->v4l2_dev, 1917 &dev->i2c_bus[2].i2c_adap, 1918 "cx25840", 0x88 >> 1, NULL); 1919 if (dev->sd_cx25840) { 1920 dev->sd_cx25840->grp_id = CX23885_HW_AV_CORE; 1921 v4l2_subdev_call(dev->sd_cx25840, core, load_fw); 1922 } 1923 break; 1924 } 1925 1926 /* AUX-PLL 27MHz CLK */ 1927 switch (dev->board) { 1928 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: 1929 netup_initialize(dev); 1930 break; 1931 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: { 1932 int ret; 1933 const struct firmware *fw; 1934 const char *filename = "dvb-netup-altera-01.fw"; 1935 char *action = "configure"; 1936 static struct netup_card_info cinfo; 1937 struct altera_config netup_config = { 1938 .dev = dev, 1939 .action = action, 1940 .jtag_io = netup_jtag_io, 1941 }; 1942 1943 netup_initialize(dev); 1944 1945 netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo); 1946 if (netup_card_rev) 1947 cinfo.rev = netup_card_rev; 1948 1949 switch (cinfo.rev) { 1950 case 0x4: 1951 filename = "dvb-netup-altera-04.fw"; 1952 break; 1953 default: 1954 filename = "dvb-netup-altera-01.fw"; 1955 break; 1956 } 1957 printk(KERN_INFO "NetUP card rev=0x%x fw_filename=%s\n", 1958 cinfo.rev, filename); 1959 1960 ret = request_firmware(&fw, filename, &dev->pci->dev); 1961 if (ret != 0) 1962 printk(KERN_ERR "did not find the firmware file. (%s) " 1963 "Please see linux/Documentation/dvb/ for more details " 1964 "on firmware-problems.", filename); 1965 else 1966 altera_init(&netup_config, fw); 1967 1968 release_firmware(fw); 1969 break; 1970 } 1971 } 1972 } 1973 1974 /* ------------------------------------------------------------------ */ 1975